8 time_sync_period=200000000
9 time_sync_spin_threshold=200000
13 children=bridge clk_domain cpu cpu_clk_domain disk0 dvfs_handler hypervisor_desc intrctrl iobus membus nvram partition_desc physmem0 physmem1 rom t1000 voltage_domain
16 clk_domain=system.clk_domain
18 hypervisor_addr=1099243257856
19 hypervisor_bin=/scratch/nilay/GEM5/system/binaries/q_new.bin
20 hypervisor_desc=system.hypervisor_desc
21 hypervisor_desc_addr=133446500352
22 hypervisor_desc_bin=/scratch/nilay/GEM5/system/binaries/1up-hv.bin
25 kernel_addr_check=true
26 load_addr_mask=1099511627775
29 mem_ranges=1048576:68157439 2147483648:2415919103
30 memories=system.nvram system.physmem1 system.hypervisor_desc system.partition_desc system.physmem0 system.rom
33 nvram_addr=133429198848
34 nvram_bin=/scratch/nilay/GEM5/system/binaries/nvram1
35 openboot_addr=1099243716608
36 openboot_bin=/scratch/nilay/GEM5/system/binaries/openboot_new.bin
37 partition_desc=system.partition_desc
38 partition_desc_addr=133445976064
39 partition_desc_bin=/scratch/nilay/GEM5/system/binaries/1up-md.bin
40 readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
41 reset_addr=1099243192320
42 reset_bin=/scratch/nilay/GEM5/system/binaries/reset_new.bin
45 work_begin_ckpt_count=0
46 work_begin_cpu_id_exit=-1
47 work_begin_exit_count=0
48 work_cpus_ckpt_count=0
52 system_port=system.membus.slave[0]
56 clk_domain=system.clk_domain
59 ranges=133412421632:133412421639 134217728000:554050781183 644245094400:652835028991 725849473024:1095485095935 1099255955456:1099255955463
62 master=system.iobus.slave[0]
63 slave=system.membus.master[2]
71 voltage_domain=system.voltage_domain
75 children=dtb interrupts isa itb tracer
78 clk_domain=system.cpu_clk_domain
80 do_checkpoint_insts=true
82 do_statistics_insts=true
87 function_trace_start=0
88 interrupts=system.cpu.interrupts
91 max_insts_all_threads=0
92 max_insts_any_thread=0
93 max_loads_all_threads=0
94 max_loads_any_thread=0
99 simulate_data_stalls=false
100 simulate_inst_stalls=false
104 tracer=system.cpu.tracer
107 dcache_port=system.membus.slave[2]
108 icache_port=system.membus.slave[1]
115 [system.cpu.interrupts]
132 [system.cpu_clk_domain]
138 voltage_domain=system.voltage_domain
143 clk_domain=system.clk_domain
145 image=system.disk0.image
146 pio_addr=134217728000
149 pio=system.iobus.master[14]
154 child=system.disk0.image.child
160 [system.disk0.image.child]
163 image_file=/scratch/nilay/GEM5/system/disks/disk.s10hw2
166 [system.dvfs_handler]
171 sys_clk_domain=system.clk_domain
172 transition_latency=200000
174 [system.hypervisor_desc]
177 clk_domain=system.clk_domain
178 conf_table_reported=true
184 range=133446500352:133446508543
185 port=system.membus.master[5]
194 clk_domain=system.clk_domain
197 use_default_range=false
199 master=system.t1000.fake_clk.pio system.t1000.fake_membnks.pio system.t1000.fake_l2_1.pio system.t1000.fake_l2_2.pio system.t1000.fake_l2_3.pio system.t1000.fake_l2_4.pio system.t1000.fake_l2esr_1.pio system.t1000.fake_l2esr_2.pio system.t1000.fake_l2esr_3.pio system.t1000.fake_l2esr_4.pio system.t1000.fake_ssi.pio system.t1000.fake_jbi.pio system.t1000.puart0.pio system.t1000.hvuart.pio system.disk0.pio
200 slave=system.bridge.master
204 children=badaddr_responder
205 clk_domain=system.clk_domain
210 use_default_range=false
212 default=system.membus.badaddr_responder.pio
213 master=system.t1000.iob.pio system.t1000.htod.pio system.bridge.slave system.rom.port system.nvram.port system.hypervisor_desc.port system.partition_desc.port system.physmem0.port system.physmem1.port
214 slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
216 [system.membus.badaddr_responder]
218 clk_domain=system.clk_domain
226 ret_data32=4294967295
227 ret_data64=18446744073709551615
232 pio=system.membus.default
237 clk_domain=system.clk_domain
238 conf_table_reported=true
244 range=133429198848:133429207039
245 port=system.membus.master[4]
247 [system.partition_desc]
250 clk_domain=system.clk_domain
251 conf_table_reported=true
257 range=133445976064:133445984255
258 port=system.membus.master[6]
263 clk_domain=system.clk_domain
264 conf_table_reported=true
270 range=1048576:68157439
271 port=system.membus.master[7]
276 clk_domain=system.clk_domain
277 conf_table_reported=true
283 range=2147483648:2415919103
284 port=system.membus.master[8]
289 clk_domain=system.clk_domain
290 conf_table_reported=true
296 range=1099243192320:1099251580927
297 port=system.membus.master[3]
301 children=fake_clk fake_jbi fake_l2_1 fake_l2_2 fake_l2_3 fake_l2_4 fake_l2esr_1 fake_l2esr_2 fake_l2esr_3 fake_l2esr_4 fake_membnks fake_ssi hterm htod hvuart iob pterm puart0
303 intrctrl=system.intrctrl
306 [system.t1000.fake_clk]
308 clk_domain=system.clk_domain
311 pio_addr=644245094400
316 ret_data32=4294967295
317 ret_data64=18446744073709551615
322 pio=system.iobus.master[0]
324 [system.t1000.fake_jbi]
326 clk_domain=system.clk_domain
329 pio_addr=549755813888
334 ret_data32=4294967295
335 ret_data64=18446744073709551615
340 pio=system.iobus.master[11]
342 [system.t1000.fake_l2_1]
344 clk_domain=system.clk_domain
347 pio_addr=725849473024
352 ret_data32=4294967295
358 pio=system.iobus.master[2]
360 [system.t1000.fake_l2_2]
362 clk_domain=system.clk_domain
365 pio_addr=725849473088
370 ret_data32=4294967295
376 pio=system.iobus.master[3]
378 [system.t1000.fake_l2_3]
380 clk_domain=system.clk_domain
383 pio_addr=725849473152
388 ret_data32=4294967295
394 pio=system.iobus.master[4]
396 [system.t1000.fake_l2_4]
398 clk_domain=system.clk_domain
401 pio_addr=725849473216
406 ret_data32=4294967295
412 pio=system.iobus.master[5]
414 [system.t1000.fake_l2esr_1]
416 clk_domain=system.clk_domain
419 pio_addr=734439407616
424 ret_data32=4294967295
430 pio=system.iobus.master[6]
432 [system.t1000.fake_l2esr_2]
434 clk_domain=system.clk_domain
437 pio_addr=734439407680
442 ret_data32=4294967295
448 pio=system.iobus.master[7]
450 [system.t1000.fake_l2esr_3]
452 clk_domain=system.clk_domain
455 pio_addr=734439407744
460 ret_data32=4294967295
466 pio=system.iobus.master[8]
468 [system.t1000.fake_l2esr_4]
470 clk_domain=system.clk_domain
473 pio_addr=734439407808
478 ret_data32=4294967295
484 pio=system.iobus.master[9]
486 [system.t1000.fake_membnks]
488 clk_domain=system.clk_domain
491 pio_addr=648540061696
496 ret_data32=4294967295
502 pio=system.iobus.master[1]
504 [system.t1000.fake_ssi]
506 clk_domain=system.clk_domain
509 pio_addr=1095216660480
514 ret_data32=4294967295
515 ret_data64=18446744073709551615
520 pio=system.iobus.master[10]
525 intr_control=system.intrctrl
532 clk_domain=system.clk_domain
534 pio_addr=1099255906296
537 time=Thu Jan 1 00:00:00 2009
538 pio=system.membus.master[1]
540 [system.t1000.hvuart]
542 clk_domain=system.clk_domain
544 pio_addr=1099255955456
546 platform=system.t1000
548 terminal=system.t1000.hterm
549 pio=system.iobus.master[13]
553 clk_domain=system.clk_domain
556 platform=system.t1000
558 pio=system.membus.master[0]
563 intr_control=system.intrctrl
568 [system.t1000.puart0]
570 clk_domain=system.clk_domain
572 pio_addr=133412421632
574 platform=system.t1000
576 terminal=system.t1000.pterm
577 pio=system.iobus.master[12]
579 [system.voltage_domain]