6 "kernel_addr_check": true,
8 "range": "1099243192320:1099251580927",
12 "clk_domain": "system.clk_domain",
14 "bandwidth": "0.000000",
15 "conf_table_reported": true,
16 "cxx_class": "SimpleMemory",
19 "type": "SimpleMemory",
21 "peer": "system.membus.master[3]",
28 "133412421632:133412421639",
29 "134217728000:554050781183",
30 "644245094400:652835028991",
31 "725849473024:1095485095935",
32 "1099255955456:1099255955463"
35 "peer": "system.membus.master[2]",
40 "clk_domain": "system.clk_domain",
44 "peer": "system.iobus.slave[0]",
47 "cxx_class": "Bridge",
48 "path": "system.bridge",
55 "system.bridge.master"
60 "clk_domain": "system.clk_domain",
66 "system.t1000.fake_clk.pio",
67 "system.t1000.fake_membnks.pio",
68 "system.t1000.fake_l2_1.pio",
69 "system.t1000.fake_l2_2.pio",
70 "system.t1000.fake_l2_3.pio",
71 "system.t1000.fake_l2_4.pio",
72 "system.t1000.fake_l2esr_1.pio",
73 "system.t1000.fake_l2esr_2.pio",
74 "system.t1000.fake_l2esr_3.pio",
75 "system.t1000.fake_l2esr_4.pio",
76 "system.t1000.fake_ssi.pio",
77 "system.t1000.fake_jbi.pio",
78 "system.t1000.puart0.pio",
79 "system.t1000.hvuart.pio",
84 "cxx_class": "NoncoherentXBar",
85 "path": "system.iobus",
86 "type": "NoncoherentXBar",
87 "use_default_range": false
93 "peer": "system.membus.master[1]",
96 "time": "Thu Jan 1 00:00:00 2009",
98 "clk_domain": "system.clk_domain",
101 "cxx_class": "DumbTOD",
102 "path": "system.t1000.htod",
103 "pio_addr": 1099255906296,
109 "peer": "system.iobus.master[12]",
113 "clk_domain": "system.clk_domain",
115 "terminal": "system.t1000.pterm",
116 "platform": "system.t1000",
118 "cxx_class": "Uart8250",
119 "path": "system.t1000.puart0",
120 "pio_addr": 133412421632,
126 "name": "fake_membnks",
129 "peer": "system.iobus.master[1]",
132 "ret_bad_addr": false,
134 "clk_domain": "system.clk_domain",
137 "ret_data32": 4294967295,
139 "update_data": false,
141 "cxx_class": "IsaFake",
142 "path": "system.t1000.fake_membnks",
143 "pio_addr": 648540061696,
147 "cxx_class": "T1000",
154 "peer": "system.iobus.master[11]",
157 "ret_bad_addr": false,
159 "clk_domain": "system.clk_domain",
161 "pio_size": 4294967296,
162 "ret_data32": 4294967295,
164 "update_data": false,
165 "ret_data64": 18446744073709551615,
166 "cxx_class": "IsaFake",
167 "path": "system.t1000.fake_jbi",
168 "pio_addr": 549755813888,
172 "intrctrl": "system.intrctrl",
176 "name": "fake_l2esr_2",
179 "peer": "system.iobus.master[7]",
182 "ret_bad_addr": false,
184 "clk_domain": "system.clk_domain",
187 "ret_data32": 4294967295,
191 "cxx_class": "IsaFake",
192 "path": "system.t1000.fake_l2esr_2",
193 "pio_addr": 734439407680,
203 "intr_control": "system.intrctrl",
205 "cxx_class": "Terminal",
206 "path": "system.t1000.hterm",
217 "peer": "system.iobus.master[5]",
220 "ret_bad_addr": false,
222 "clk_domain": "system.clk_domain",
225 "ret_data32": 4294967295,
229 "cxx_class": "IsaFake",
230 "path": "system.t1000.fake_l2_4",
231 "pio_addr": 725849473216,
241 "peer": "system.iobus.master[2]",
244 "ret_bad_addr": false,
246 "clk_domain": "system.clk_domain",
249 "ret_data32": 4294967295,
253 "cxx_class": "IsaFake",
254 "path": "system.t1000.fake_l2_1",
255 "pio_addr": 725849473024,
265 "peer": "system.iobus.master[3]",
268 "ret_bad_addr": false,
270 "clk_domain": "system.clk_domain",
273 "ret_data32": 4294967295,
277 "cxx_class": "IsaFake",
278 "path": "system.t1000.fake_l2_2",
279 "pio_addr": 725849473088,
289 "peer": "system.iobus.master[4]",
292 "ret_bad_addr": false,
294 "clk_domain": "system.clk_domain",
297 "ret_data32": 4294967295,
301 "cxx_class": "IsaFake",
302 "path": "system.t1000.fake_l2_3",
303 "pio_addr": 725849473152,
311 "intr_control": "system.intrctrl",
313 "cxx_class": "Terminal",
314 "path": "system.t1000.pterm",
318 "path": "system.t1000",
322 "peer": "system.membus.master[0]",
326 "clk_domain": "system.clk_domain",
328 "platform": "system.t1000",
331 "path": "system.t1000.iob",
337 "peer": "system.iobus.master[13]",
341 "clk_domain": "system.clk_domain",
343 "terminal": "system.t1000.hterm",
344 "platform": "system.t1000",
346 "cxx_class": "Uart8250",
347 "path": "system.t1000.hvuart",
348 "pio_addr": 1099255955456,
355 "name": "fake_l2esr_3",
358 "peer": "system.iobus.master[8]",
361 "ret_bad_addr": false,
363 "clk_domain": "system.clk_domain",
366 "ret_data32": 4294967295,
370 "cxx_class": "IsaFake",
371 "path": "system.t1000.fake_l2esr_3",
372 "pio_addr": 734439407744,
382 "peer": "system.iobus.master[10]",
385 "ret_bad_addr": false,
387 "clk_domain": "system.clk_domain",
389 "pio_size": 268435456,
390 "ret_data32": 4294967295,
392 "update_data": false,
393 "ret_data64": 18446744073709551615,
394 "cxx_class": "IsaFake",
395 "path": "system.t1000.fake_ssi",
396 "pio_addr": 1095216660480,
403 "name": "fake_l2esr_1",
406 "peer": "system.iobus.master[6]",
409 "ret_bad_addr": false,
411 "clk_domain": "system.clk_domain",
414 "ret_data32": 4294967295,
418 "cxx_class": "IsaFake",
419 "path": "system.t1000.fake_l2esr_1",
420 "pio_addr": 734439407616,
427 "name": "fake_l2esr_4",
430 "peer": "system.iobus.master[9]",
433 "ret_bad_addr": false,
435 "clk_domain": "system.clk_domain",
438 "ret_data32": 4294967295,
442 "cxx_class": "IsaFake",
443 "path": "system.t1000.fake_l2esr_4",
444 "pio_addr": 734439407808,
454 "peer": "system.iobus.master[0]",
457 "ret_bad_addr": false,
459 "clk_domain": "system.clk_domain",
461 "pio_size": 4294967296,
462 "ret_data32": 4294967295,
464 "update_data": false,
465 "ret_data64": 18446744073709551615,
466 "cxx_class": "IsaFake",
467 "path": "system.t1000.fake_clk",
468 "pio_addr": 644245094400,
474 "readfile": "/z/stever/hg/gem5/tests/halt.sh",
475 "hypervisor_addr": 1099243257856,
478 "2147483648:2415919103"
480 "cxx_class": "SparcSystem",
482 "reset_bin": "/dist/m5/system/binaries/reset_new.bin",
483 "openboot_addr": 1099243716608,
484 "work_end_ckpt_count": 0,
485 "nvram_addr": 133429198848,
487 "system.hypervisor_desc",
489 "system.partition_desc",
494 "work_begin_ckpt_count": 0,
496 "range": "133445976064:133445984255",
498 "name": "partition_desc",
500 "clk_domain": "system.clk_domain",
502 "bandwidth": "0.000000",
503 "conf_table_reported": true,
504 "cxx_class": "SimpleMemory",
505 "path": "system.partition_desc",
507 "type": "SimpleMemory",
509 "peer": "system.membus.master[6]",
515 "name": "clk_domain",
519 "init_perf_level": 0,
520 "voltage_domain": "system.voltage_domain",
522 "cxx_class": "SrcClockDomain",
523 "path": "system.clk_domain",
524 "type": "SrcClockDomain",
528 "range": "133446500352:133446508543",
530 "name": "hypervisor_desc",
532 "clk_domain": "system.clk_domain",
534 "bandwidth": "0.000000",
535 "conf_table_reported": true,
536 "cxx_class": "SimpleMemory",
537 "path": "system.hypervisor_desc",
539 "type": "SimpleMemory",
541 "peer": "system.membus.master[5]",
548 "peer": "system.membus.badaddr_responder.pio",
553 "system.system_port",
554 "system.cpu.icache_port",
555 "system.cpu.dcache_port"
560 "badaddr_responder": {
563 "name": "badaddr_responder",
566 "peer": "system.membus.default",
569 "ret_bad_addr": true,
571 "clk_domain": "system.clk_domain",
574 "ret_data32": 4294967295,
576 "update_data": false,
577 "ret_data64": 18446744073709551615,
578 "cxx_class": "IsaFake",
579 "path": "system.membus.badaddr_responder",
584 "snoop_filter": null,
585 "clk_domain": "system.clk_domain",
592 "system.t1000.iob.pio",
593 "system.t1000.htod.pio",
594 "system.bridge.slave",
597 "system.hypervisor_desc.port",
598 "system.partition_desc.port",
599 "system.physmem0.port",
600 "system.physmem1.port"
604 "cxx_class": "CoherentXBar",
605 "path": "system.membus",
606 "type": "CoherentXBar",
607 "use_default_range": false
610 "range": "133429198848:133429207039",
614 "clk_domain": "system.clk_domain",
616 "bandwidth": "0.000000",
617 "conf_table_reported": true,
618 "cxx_class": "SimpleMemory",
619 "path": "system.nvram",
621 "type": "SimpleMemory",
623 "peer": "system.membus.master[4]",
629 "work_begin_cpu_id_exit": -1,
632 "name": "dvfs_handler",
633 "sys_clk_domain": "system.clk_domain",
634 "transition_latency": 200000,
636 "cxx_class": "DVFSHandler",
638 "path": "system.dvfs_handler",
639 "type": "DVFSHandler"
641 "work_end_exit_count": 0,
642 "hypervisor_desc_bin": "/dist/m5/system/binaries/1up-hv.bin",
643 "openboot_bin": "/dist/m5/system/binaries/openboot_new.bin",
645 "name": "voltage_domain",
650 "cxx_class": "VoltageDomain",
651 "path": "system.voltage_domain",
652 "type": "VoltageDomain"
654 "cache_line_size": 64,
657 "peer": "system.membus.slave[0]",
662 "range": "1048576:68157439",
666 "clk_domain": "system.clk_domain",
668 "bandwidth": "0.000000",
669 "conf_table_reported": true,
670 "cxx_class": "SimpleMemory",
671 "path": "system.physmem0",
673 "type": "SimpleMemory",
675 "peer": "system.membus.master[7]",
681 "range": "2147483648:2415919103",
685 "clk_domain": "system.clk_domain",
687 "bandwidth": "0.000000",
688 "conf_table_reported": true,
689 "cxx_class": "SimpleMemory",
690 "path": "system.physmem1",
692 "type": "SimpleMemory",
694 "peer": "system.membus.master[8]",
700 "work_cpus_ckpt_count": 0,
701 "work_begin_exit_count": 0,
703 "hypervisor_bin": "/dist/m5/system/binaries/q_new.bin",
705 "name": "cpu_clk_domain",
709 "init_perf_level": 0,
710 "voltage_domain": "system.voltage_domain",
712 "cxx_class": "SrcClockDomain",
713 "path": "system.cpu_clk_domain",
714 "type": "SrcClockDomain",
717 "nvram_bin": "/dist/m5/system/binaries/nvram1",
718 "mem_mode": "atomic",
721 "type": "SparcSystem",
722 "partition_desc_bin": "/dist/m5/system/binaries/1up-md.bin",
723 "load_addr_mask": 1099511627775,
725 "do_statistics_insts": true,
730 "cxx_class": "SparcISA::TLB",
731 "path": "system.cpu.itb",
735 "simulate_data_stalls": false,
736 "function_trace": false,
737 "do_checkpoint_insts": true,
738 "cxx_class": "AtomicSimpleCPU",
739 "max_loads_all_threads": 0,
741 "clk_domain": "system.cpu_clk_domain",
742 "function_trace_start": 0,
748 "type": "AtomicSimpleCPU",
752 "peer": "system.membus.slave[1]",
757 "path": "system.cpu.interrupts",
758 "type": "SparcInterrupts",
759 "name": "interrupts",
760 "cxx_class": "SparcISA::Interrupts"
763 "peer": "system.membus.slave[2]",
767 "max_insts_all_threads": 0,
768 "path": "system.cpu",
769 "max_loads_any_thread": 0,
770 "switched_out": false,
776 "cxx_class": "SparcISA::TLB",
777 "path": "system.cpu.dtb",
781 "simpoint_start_insts": [],
782 "max_insts_any_thread": 0,
783 "simulate_inst_stalls": false,
784 "progress_interval": 0,
789 "path": "system.cpu.isa",
792 "cxx_class": "SparcISA::ISA"
797 "path": "system.cpu.tracer",
800 "cxx_class": "Trace::ExeTracer"
807 "cxx_class": "IntrControl",
808 "path": "system.intrctrl",
809 "type": "IntrControl"
814 "peer": "system.iobus.master[14]",
820 "cxx_class": "CowDiskImage",
826 "cxx_class": "RawDiskImage",
827 "path": "system.disk0.image.child",
828 "image_file": "/dist/m5/system/disks/disk.s10hw2",
829 "type": "RawDiskImage"
831 "path": "system.disk0.image",
833 "type": "CowDiskImage",
837 "clk_domain": "system.clk_domain",
840 "cxx_class": "MmDisk",
841 "path": "system.disk0",
842 "pio_addr": 134217728000,
845 "reset_addr": 1099243192320,
846 "hypervisor_desc_addr": 133446500352,
847 "partition_desc_addr": 133445976064,
851 "time_sync_period": 200000000,
853 "time_sync_spin_threshold": 200000,
856 "time_sync_enable": false,