6 "mmap_using_noreserve": false,
7 "kernel_addr_check": true,
9 "range": "1099243192320:1099251580927",
13 "clk_domain": "system.clk_domain",
15 "bandwidth": "0.000000",
16 "conf_table_reported": true,
17 "cxx_class": "SimpleMemory",
20 "type": "SimpleMemory",
22 "peer": "system.membus.master[3]",
29 "133412421632:133412421639",
30 "134217728000:554050781183",
31 "644245094400:652835028991",
32 "725849473024:1095485095935",
33 "1099255955456:1099255955463"
36 "peer": "system.membus.master[2]",
41 "clk_domain": "system.clk_domain",
45 "peer": "system.iobus.slave[0]",
48 "cxx_class": "Bridge",
49 "path": "system.bridge",
56 "system.bridge.master"
62 "clk_domain": "system.clk_domain",
67 "system.t1000.fake_clk.pio",
68 "system.t1000.fake_membnks.pio",
69 "system.t1000.fake_l2_1.pio",
70 "system.t1000.fake_l2_2.pio",
71 "system.t1000.fake_l2_3.pio",
72 "system.t1000.fake_l2_4.pio",
73 "system.t1000.fake_l2esr_1.pio",
74 "system.t1000.fake_l2esr_2.pio",
75 "system.t1000.fake_l2esr_3.pio",
76 "system.t1000.fake_l2esr_4.pio",
77 "system.t1000.fake_ssi.pio",
78 "system.t1000.fake_jbi.pio",
79 "system.t1000.puart0.pio",
80 "system.t1000.hvuart.pio",
85 "response_latency": 2,
86 "cxx_class": "NoncoherentXBar",
87 "path": "system.iobus",
88 "type": "NoncoherentXBar",
89 "use_default_range": false,
96 "peer": "system.membus.master[1]",
99 "time": "Thu Jan 1 00:00:00 2009",
101 "clk_domain": "system.clk_domain",
104 "cxx_class": "DumbTOD",
105 "path": "system.t1000.htod",
106 "pio_addr": 1099255906296,
112 "peer": "system.iobus.master[12]",
116 "clk_domain": "system.clk_domain",
118 "terminal": "system.t1000.pterm",
119 "platform": "system.t1000",
121 "cxx_class": "Uart8250",
122 "path": "system.t1000.puart0",
123 "pio_addr": 133412421632,
129 "name": "fake_membnks",
132 "peer": "system.iobus.master[1]",
135 "ret_bad_addr": false,
137 "clk_domain": "system.clk_domain",
140 "ret_data32": 4294967295,
142 "update_data": false,
144 "cxx_class": "IsaFake",
145 "path": "system.t1000.fake_membnks",
146 "pio_addr": 648540061696,
150 "cxx_class": "T1000",
157 "peer": "system.iobus.master[11]",
160 "ret_bad_addr": false,
162 "clk_domain": "system.clk_domain",
164 "pio_size": 4294967296,
165 "ret_data32": 4294967295,
167 "update_data": false,
168 "ret_data64": 18446744073709551615,
169 "cxx_class": "IsaFake",
170 "path": "system.t1000.fake_jbi",
171 "pio_addr": 549755813888,
175 "intrctrl": "system.intrctrl",
179 "name": "fake_l2esr_2",
182 "peer": "system.iobus.master[7]",
185 "ret_bad_addr": false,
187 "clk_domain": "system.clk_domain",
190 "ret_data32": 4294967295,
194 "cxx_class": "IsaFake",
195 "path": "system.t1000.fake_l2esr_2",
196 "pio_addr": 734439407680,
206 "intr_control": "system.intrctrl",
208 "cxx_class": "Terminal",
209 "path": "system.t1000.hterm",
220 "peer": "system.iobus.master[5]",
223 "ret_bad_addr": false,
225 "clk_domain": "system.clk_domain",
228 "ret_data32": 4294967295,
232 "cxx_class": "IsaFake",
233 "path": "system.t1000.fake_l2_4",
234 "pio_addr": 725849473216,
244 "peer": "system.iobus.master[2]",
247 "ret_bad_addr": false,
249 "clk_domain": "system.clk_domain",
252 "ret_data32": 4294967295,
256 "cxx_class": "IsaFake",
257 "path": "system.t1000.fake_l2_1",
258 "pio_addr": 725849473024,
268 "peer": "system.iobus.master[3]",
271 "ret_bad_addr": false,
273 "clk_domain": "system.clk_domain",
276 "ret_data32": 4294967295,
280 "cxx_class": "IsaFake",
281 "path": "system.t1000.fake_l2_2",
282 "pio_addr": 725849473088,
292 "peer": "system.iobus.master[4]",
295 "ret_bad_addr": false,
297 "clk_domain": "system.clk_domain",
300 "ret_data32": 4294967295,
304 "cxx_class": "IsaFake",
305 "path": "system.t1000.fake_l2_3",
306 "pio_addr": 725849473152,
314 "intr_control": "system.intrctrl",
316 "cxx_class": "Terminal",
317 "path": "system.t1000.pterm",
321 "path": "system.t1000",
325 "peer": "system.membus.master[0]",
329 "clk_domain": "system.clk_domain",
331 "platform": "system.t1000",
334 "path": "system.t1000.iob",
340 "peer": "system.iobus.master[13]",
344 "clk_domain": "system.clk_domain",
346 "terminal": "system.t1000.hterm",
347 "platform": "system.t1000",
349 "cxx_class": "Uart8250",
350 "path": "system.t1000.hvuart",
351 "pio_addr": 1099255955456,
358 "name": "fake_l2esr_3",
361 "peer": "system.iobus.master[8]",
364 "ret_bad_addr": false,
366 "clk_domain": "system.clk_domain",
369 "ret_data32": 4294967295,
373 "cxx_class": "IsaFake",
374 "path": "system.t1000.fake_l2esr_3",
375 "pio_addr": 734439407744,
385 "peer": "system.iobus.master[10]",
388 "ret_bad_addr": false,
390 "clk_domain": "system.clk_domain",
392 "pio_size": 268435456,
393 "ret_data32": 4294967295,
395 "update_data": false,
396 "ret_data64": 18446744073709551615,
397 "cxx_class": "IsaFake",
398 "path": "system.t1000.fake_ssi",
399 "pio_addr": 1095216660480,
406 "name": "fake_l2esr_1",
409 "peer": "system.iobus.master[6]",
412 "ret_bad_addr": false,
414 "clk_domain": "system.clk_domain",
417 "ret_data32": 4294967295,
421 "cxx_class": "IsaFake",
422 "path": "system.t1000.fake_l2esr_1",
423 "pio_addr": 734439407616,
430 "name": "fake_l2esr_4",
433 "peer": "system.iobus.master[9]",
436 "ret_bad_addr": false,
438 "clk_domain": "system.clk_domain",
441 "ret_data32": 4294967295,
445 "cxx_class": "IsaFake",
446 "path": "system.t1000.fake_l2esr_4",
447 "pio_addr": 734439407808,
457 "peer": "system.iobus.master[0]",
460 "ret_bad_addr": false,
462 "clk_domain": "system.clk_domain",
464 "pio_size": 4294967296,
465 "ret_data32": 4294967295,
467 "update_data": false,
468 "ret_data64": 18446744073709551615,
469 "cxx_class": "IsaFake",
470 "path": "system.t1000.fake_clk",
471 "pio_addr": 644245094400,
476 "partition_desc_addr": 133445976064,
478 "readfile": "/z/stever/hg/gem5/tests/halt.sh",
479 "hypervisor_addr": 1099243257856,
482 "2147483648:2415919103"
484 "cxx_class": "SparcSystem",
486 "reset_bin": "/dist/m5/system/binaries/reset_new.bin",
487 "openboot_addr": 1099243716608,
488 "work_end_ckpt_count": 0,
489 "nvram_addr": 133429198848,
491 "system.hypervisor_desc",
493 "system.partition_desc",
498 "work_begin_ckpt_count": 0,
500 "range": "133445976064:133445984255",
502 "name": "partition_desc",
504 "clk_domain": "system.clk_domain",
506 "bandwidth": "0.000000",
507 "conf_table_reported": true,
508 "cxx_class": "SimpleMemory",
509 "path": "system.partition_desc",
511 "type": "SimpleMemory",
513 "peer": "system.membus.master[6]",
519 "name": "clk_domain",
523 "init_perf_level": 0,
524 "voltage_domain": "system.voltage_domain",
526 "cxx_class": "SrcClockDomain",
527 "path": "system.clk_domain",
528 "type": "SrcClockDomain",
532 "range": "133446500352:133446508543",
534 "name": "hypervisor_desc",
536 "clk_domain": "system.clk_domain",
538 "bandwidth": "0.000000",
539 "conf_table_reported": true,
540 "cxx_class": "SimpleMemory",
541 "path": "system.hypervisor_desc",
543 "type": "SimpleMemory",
545 "peer": "system.membus.master[5]",
552 "peer": "system.membus.badaddr_responder.pio",
557 "system.system_port",
558 "system.cpu.icache_port",
559 "system.cpu.dcache_port"
564 "badaddr_responder": {
567 "name": "badaddr_responder",
570 "peer": "system.membus.default",
573 "ret_bad_addr": true,
575 "clk_domain": "system.clk_domain",
578 "ret_data32": 4294967295,
580 "update_data": false,
581 "ret_data64": 18446744073709551615,
582 "cxx_class": "IsaFake",
583 "path": "system.membus.badaddr_responder",
588 "snoop_filter": null,
589 "forward_latency": 4,
590 "clk_domain": "system.clk_domain",
596 "system.t1000.iob.pio",
597 "system.t1000.htod.pio",
598 "system.bridge.slave",
601 "system.hypervisor_desc.port",
602 "system.partition_desc.port",
603 "system.physmem0.port",
604 "system.physmem1.port"
608 "response_latency": 2,
609 "cxx_class": "CoherentXBar",
610 "path": "system.membus",
611 "snoop_response_latency": 4,
612 "type": "CoherentXBar",
613 "use_default_range": false,
614 "frontend_latency": 3
617 "range": "133429198848:133429207039",
621 "clk_domain": "system.clk_domain",
623 "bandwidth": "0.000000",
624 "conf_table_reported": true,
625 "cxx_class": "SimpleMemory",
626 "path": "system.nvram",
628 "type": "SimpleMemory",
630 "peer": "system.membus.master[4]",
636 "work_begin_cpu_id_exit": -1,
639 "name": "dvfs_handler",
640 "sys_clk_domain": "system.clk_domain",
641 "transition_latency": 200000,
643 "cxx_class": "DVFSHandler",
645 "path": "system.dvfs_handler",
646 "type": "DVFSHandler"
648 "work_end_exit_count": 0,
649 "hypervisor_desc_bin": "/dist/m5/system/binaries/1up-hv.bin",
650 "openboot_bin": "/dist/m5/system/binaries/openboot_new.bin",
652 "name": "voltage_domain",
657 "cxx_class": "VoltageDomain",
658 "path": "system.voltage_domain",
659 "type": "VoltageDomain"
661 "cache_line_size": 64,
664 "peer": "system.membus.slave[0]",
669 "range": "1048576:68157439",
673 "clk_domain": "system.clk_domain",
675 "bandwidth": "0.000000",
676 "conf_table_reported": true,
677 "cxx_class": "SimpleMemory",
678 "path": "system.physmem0",
680 "type": "SimpleMemory",
682 "peer": "system.membus.master[7]",
688 "range": "2147483648:2415919103",
692 "clk_domain": "system.clk_domain",
694 "bandwidth": "0.000000",
695 "conf_table_reported": true,
696 "cxx_class": "SimpleMemory",
697 "path": "system.physmem1",
699 "type": "SimpleMemory",
701 "peer": "system.membus.master[8]",
707 "work_cpus_ckpt_count": 0,
708 "work_begin_exit_count": 0,
710 "hypervisor_bin": "/dist/m5/system/binaries/q_new.bin",
712 "name": "cpu_clk_domain",
716 "init_perf_level": 0,
717 "voltage_domain": "system.voltage_domain",
719 "cxx_class": "SrcClockDomain",
720 "path": "system.cpu_clk_domain",
721 "type": "SrcClockDomain",
724 "nvram_bin": "/dist/m5/system/binaries/nvram1",
725 "mem_mode": "atomic",
728 "type": "SparcSystem",
729 "partition_desc_bin": "/dist/m5/system/binaries/1up-md.bin",
730 "load_addr_mask": 1099511627775,
732 "do_statistics_insts": true,
737 "cxx_class": "SparcISA::TLB",
738 "path": "system.cpu.itb",
742 "simulate_data_stalls": false,
743 "function_trace": false,
744 "do_checkpoint_insts": true,
745 "cxx_class": "AtomicSimpleCPU",
746 "max_loads_all_threads": 0,
748 "clk_domain": "system.cpu_clk_domain",
749 "function_trace_start": 0,
755 "type": "AtomicSimpleCPU",
759 "peer": "system.membus.slave[1]",
765 "path": "system.cpu.interrupts",
766 "type": "SparcInterrupts",
767 "name": "interrupts",
768 "cxx_class": "SparcISA::Interrupts"
772 "peer": "system.membus.slave[2]",
776 "max_insts_all_threads": 0,
777 "path": "system.cpu",
778 "max_loads_any_thread": 0,
779 "switched_out": false,
785 "cxx_class": "SparcISA::TLB",
786 "path": "system.cpu.dtb",
790 "simpoint_start_insts": [],
791 "max_insts_any_thread": 0,
792 "simulate_inst_stalls": false,
793 "progress_interval": 0,
798 "path": "system.cpu.isa",
801 "cxx_class": "SparcISA::ISA"
806 "path": "system.cpu.tracer",
809 "cxx_class": "Trace::ExeTracer"
816 "cxx_class": "IntrControl",
817 "path": "system.intrctrl",
818 "type": "IntrControl"
823 "peer": "system.iobus.master[14]",
829 "cxx_class": "CowDiskImage",
835 "cxx_class": "RawDiskImage",
836 "path": "system.disk0.image.child",
837 "image_file": "/dist/m5/system/disks/disk.s10hw2",
838 "type": "RawDiskImage"
840 "path": "system.disk0.image",
842 "type": "CowDiskImage",
846 "clk_domain": "system.clk_domain",
849 "cxx_class": "MmDisk",
850 "path": "system.disk0",
851 "pio_addr": 134217728000,
854 "multi_thread": false,
855 "reset_addr": 1099243192320,
856 "hypervisor_desc_addr": 133446500352,
859 "exit_on_work_items": false
861 "time_sync_period": 200000000,
863 "time_sync_spin_threshold": 200000,
866 "time_sync_enable": false,