2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.796763 # Number of seconds simulated
4 sim_ticks 796762926000 # Number of ticks simulated
5 final_tick 796762926000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 2008356 # Simulator instruction rate (inst/s)
8 host_op_rate 2120897 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 2814551305 # Simulator tick rate (ticks/s)
10 host_mem_usage 222752 # Number of bytes of host memory used
11 host_seconds 283.09 # Real time elapsed on the host
12 sim_insts 568539343 # Number of instructions simulated
13 sim_ops 600398281 # Number of ops (including micro ops) simulated
14 system.physmem.bytes_read 5759488 # Number of bytes read from this memory
15 system.physmem.bytes_inst_read 39424 # Number of instructions bytes read from this memory
16 system.physmem.bytes_written 3704704 # Number of bytes written to this memory
17 system.physmem.num_reads 89992 # Number of read requests responded to by this memory
18 system.physmem.num_writes 57886 # Number of write requests responded to by this memory
19 system.physmem.num_other 0 # Number of other requests responded to by this memory
20 system.physmem.bw_read 7228609 # Total read bandwidth from this memory (bytes/s)
21 system.physmem.bw_inst_read 49480 # Instruction read bandwidth from this memory (bytes/s)
22 system.physmem.bw_write 4649694 # Write bandwidth from this memory (bytes/s)
23 system.physmem.bw_total 11878304 # Total bandwidth to/from this memory (bytes/s)
24 system.cpu.dtb.inst_hits 0 # ITB inst hits
25 system.cpu.dtb.inst_misses 0 # ITB inst misses
26 system.cpu.dtb.read_hits 0 # DTB read hits
27 system.cpu.dtb.read_misses 0 # DTB read misses
28 system.cpu.dtb.write_hits 0 # DTB write hits
29 system.cpu.dtb.write_misses 0 # DTB write misses
30 system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
31 system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
32 system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
33 system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
34 system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
35 system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
36 system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
37 system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
38 system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
39 system.cpu.dtb.read_accesses 0 # DTB read accesses
40 system.cpu.dtb.write_accesses 0 # DTB write accesses
41 system.cpu.dtb.inst_accesses 0 # ITB inst accesses
42 system.cpu.dtb.hits 0 # DTB hits
43 system.cpu.dtb.misses 0 # DTB misses
44 system.cpu.dtb.accesses 0 # DTB accesses
45 system.cpu.itb.inst_hits 0 # ITB inst hits
46 system.cpu.itb.inst_misses 0 # ITB inst misses
47 system.cpu.itb.read_hits 0 # DTB read hits
48 system.cpu.itb.read_misses 0 # DTB read misses
49 system.cpu.itb.write_hits 0 # DTB write hits
50 system.cpu.itb.write_misses 0 # DTB write misses
51 system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
52 system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
53 system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
54 system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
55 system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
56 system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
57 system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
58 system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
59 system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
60 system.cpu.itb.read_accesses 0 # DTB read accesses
61 system.cpu.itb.write_accesses 0 # DTB write accesses
62 system.cpu.itb.inst_accesses 0 # ITB inst accesses
63 system.cpu.itb.hits 0 # DTB hits
64 system.cpu.itb.misses 0 # DTB misses
65 system.cpu.itb.accesses 0 # DTB accesses
66 system.cpu.workload.num_syscalls 48 # Number of system calls
67 system.cpu.numCycles 1593525852 # number of cpu cycles simulated
68 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
69 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
70 system.cpu.committedInsts 568539343 # Number of instructions committed
71 system.cpu.committedOps 600398281 # Number of ops (including micro ops) committed
72 system.cpu.num_int_alu_accesses 533522639 # Number of integer alu accesses
73 system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
74 system.cpu.num_func_calls 1993546 # number of times a function call or return occured
75 system.cpu.num_conditional_control_insts 67017095 # number of instructions that are conditional controls
76 system.cpu.num_int_insts 533522639 # number of integer instructions
77 system.cpu.num_fp_insts 16 # number of float instructions
78 system.cpu.num_int_register_reads 3212467108 # number of times the integer registers were read
79 system.cpu.num_int_register_writes 614470985 # number of times the integer registers were written
80 system.cpu.num_fp_register_reads 16 # number of times the floating registers were read
81 system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
82 system.cpu.num_mem_refs 219173607 # number of memory refs
83 system.cpu.num_load_insts 148952594 # Number of load instructions
84 system.cpu.num_store_insts 70221013 # Number of store instructions
85 system.cpu.num_idle_cycles 0 # Number of idle cycles
86 system.cpu.num_busy_cycles 1593525852 # Number of busy cycles
87 system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
88 system.cpu.idle_fraction 0 # Percentage of idle cycles
89 system.cpu.icache.replacements 12 # number of replacements
90 system.cpu.icache.tagsinuse 577.728532 # Cycle average of tags in use
91 system.cpu.icache.total_refs 570073892 # Total number of references to valid blocks.
92 system.cpu.icache.sampled_refs 643 # Sample count of references to valid blocks.
93 system.cpu.icache.avg_refs 886584.590980 # Average number of references to valid blocks.
94 system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
95 system.cpu.icache.occ_blocks::cpu.inst 577.728532 # Average occupied blocks per requestor
96 system.cpu.icache.occ_percent::cpu.inst 0.282094 # Average percentage of cache occupancy
97 system.cpu.icache.occ_percent::total 0.282094 # Average percentage of cache occupancy
98 system.cpu.icache.ReadReq_hits::cpu.inst 570073892 # number of ReadReq hits
99 system.cpu.icache.ReadReq_hits::total 570073892 # number of ReadReq hits
100 system.cpu.icache.demand_hits::cpu.inst 570073892 # number of demand (read+write) hits
101 system.cpu.icache.demand_hits::total 570073892 # number of demand (read+write) hits
102 system.cpu.icache.overall_hits::cpu.inst 570073892 # number of overall hits
103 system.cpu.icache.overall_hits::total 570073892 # number of overall hits
104 system.cpu.icache.ReadReq_misses::cpu.inst 643 # number of ReadReq misses
105 system.cpu.icache.ReadReq_misses::total 643 # number of ReadReq misses
106 system.cpu.icache.demand_misses::cpu.inst 643 # number of demand (read+write) misses
107 system.cpu.icache.demand_misses::total 643 # number of demand (read+write) misses
108 system.cpu.icache.overall_misses::cpu.inst 643 # number of overall misses
109 system.cpu.icache.overall_misses::total 643 # number of overall misses
110 system.cpu.icache.ReadReq_miss_latency::cpu.inst 34874000 # number of ReadReq miss cycles
111 system.cpu.icache.ReadReq_miss_latency::total 34874000 # number of ReadReq miss cycles
112 system.cpu.icache.demand_miss_latency::cpu.inst 34874000 # number of demand (read+write) miss cycles
113 system.cpu.icache.demand_miss_latency::total 34874000 # number of demand (read+write) miss cycles
114 system.cpu.icache.overall_miss_latency::cpu.inst 34874000 # number of overall miss cycles
115 system.cpu.icache.overall_miss_latency::total 34874000 # number of overall miss cycles
116 system.cpu.icache.ReadReq_accesses::cpu.inst 570074535 # number of ReadReq accesses(hits+misses)
117 system.cpu.icache.ReadReq_accesses::total 570074535 # number of ReadReq accesses(hits+misses)
118 system.cpu.icache.demand_accesses::cpu.inst 570074535 # number of demand (read+write) accesses
119 system.cpu.icache.demand_accesses::total 570074535 # number of demand (read+write) accesses
120 system.cpu.icache.overall_accesses::cpu.inst 570074535 # number of overall (read+write) accesses
121 system.cpu.icache.overall_accesses::total 570074535 # number of overall (read+write) accesses
122 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000001 # miss rate for ReadReq accesses
123 system.cpu.icache.demand_miss_rate::cpu.inst 0.000001 # miss rate for demand accesses
124 system.cpu.icache.overall_miss_rate::cpu.inst 0.000001 # miss rate for overall accesses
125 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54236.391913 # average ReadReq miss latency
126 system.cpu.icache.demand_avg_miss_latency::cpu.inst 54236.391913 # average overall miss latency
127 system.cpu.icache.overall_avg_miss_latency::cpu.inst 54236.391913 # average overall miss latency
128 system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
129 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
130 system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
131 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
132 system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
133 system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
134 system.cpu.icache.fast_writes 0 # number of fast writes performed
135 system.cpu.icache.cache_copies 0 # number of cache copies performed
136 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 643 # number of ReadReq MSHR misses
137 system.cpu.icache.ReadReq_mshr_misses::total 643 # number of ReadReq MSHR misses
138 system.cpu.icache.demand_mshr_misses::cpu.inst 643 # number of demand (read+write) MSHR misses
139 system.cpu.icache.demand_mshr_misses::total 643 # number of demand (read+write) MSHR misses
140 system.cpu.icache.overall_mshr_misses::cpu.inst 643 # number of overall MSHR misses
141 system.cpu.icache.overall_mshr_misses::total 643 # number of overall MSHR misses
142 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 32945000 # number of ReadReq MSHR miss cycles
143 system.cpu.icache.ReadReq_mshr_miss_latency::total 32945000 # number of ReadReq MSHR miss cycles
144 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 32945000 # number of demand (read+write) MSHR miss cycles
145 system.cpu.icache.demand_mshr_miss_latency::total 32945000 # number of demand (read+write) MSHR miss cycles
146 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 32945000 # number of overall MSHR miss cycles
147 system.cpu.icache.overall_mshr_miss_latency::total 32945000 # number of overall MSHR miss cycles
148 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for ReadReq accesses
149 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for demand accesses
150 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for overall accesses
151 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51236.391913 # average ReadReq mshr miss latency
152 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51236.391913 # average overall mshr miss latency
153 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51236.391913 # average overall mshr miss latency
154 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
155 system.cpu.dcache.replacements 433468 # number of replacements
156 system.cpu.dcache.tagsinuse 4094.222434 # Cycle average of tags in use
157 system.cpu.dcache.total_refs 216774473 # Total number of references to valid blocks.
158 system.cpu.dcache.sampled_refs 437564 # Sample count of references to valid blocks.
159 system.cpu.dcache.avg_refs 495.412038 # Average number of references to valid blocks.
160 system.cpu.dcache.warmup_cycle 537031000 # Cycle when the warmup percentage was hit.
161 system.cpu.dcache.occ_blocks::cpu.data 4094.222434 # Average occupied blocks per requestor
162 system.cpu.dcache.occ_percent::cpu.data 0.999566 # Average percentage of cache occupancy
163 system.cpu.dcache.occ_percent::total 0.999566 # Average percentage of cache occupancy
164 system.cpu.dcache.ReadReq_hits::cpu.data 147602036 # number of ReadReq hits
165 system.cpu.dcache.ReadReq_hits::total 147602036 # number of ReadReq hits
166 system.cpu.dcache.WriteReq_hits::cpu.data 69169783 # number of WriteReq hits
167 system.cpu.dcache.WriteReq_hits::total 69169783 # number of WriteReq hits
168 system.cpu.dcache.LoadLockedReq_hits::cpu.data 1327 # number of LoadLockedReq hits
169 system.cpu.dcache.LoadLockedReq_hits::total 1327 # number of LoadLockedReq hits
170 system.cpu.dcache.StoreCondReq_hits::cpu.data 1327 # number of StoreCondReq hits
171 system.cpu.dcache.StoreCondReq_hits::total 1327 # number of StoreCondReq hits
172 system.cpu.dcache.demand_hits::cpu.data 216771819 # number of demand (read+write) hits
173 system.cpu.dcache.demand_hits::total 216771819 # number of demand (read+write) hits
174 system.cpu.dcache.overall_hits::cpu.data 216771819 # number of overall hits
175 system.cpu.dcache.overall_hits::total 216771819 # number of overall hits
176 system.cpu.dcache.ReadReq_misses::cpu.data 189816 # number of ReadReq misses
177 system.cpu.dcache.ReadReq_misses::total 189816 # number of ReadReq misses
178 system.cpu.dcache.WriteReq_misses::cpu.data 247748 # number of WriteReq misses
179 system.cpu.dcache.WriteReq_misses::total 247748 # number of WriteReq misses
180 system.cpu.dcache.demand_misses::cpu.data 437564 # number of demand (read+write) misses
181 system.cpu.dcache.demand_misses::total 437564 # number of demand (read+write) misses
182 system.cpu.dcache.overall_misses::cpu.data 437564 # number of overall misses
183 system.cpu.dcache.overall_misses::total 437564 # number of overall misses
184 system.cpu.dcache.ReadReq_miss_latency::cpu.data 3956274000 # number of ReadReq miss cycles
185 system.cpu.dcache.ReadReq_miss_latency::total 3956274000 # number of ReadReq miss cycles
186 system.cpu.dcache.WriteReq_miss_latency::cpu.data 5923414000 # number of WriteReq miss cycles
187 system.cpu.dcache.WriteReq_miss_latency::total 5923414000 # number of WriteReq miss cycles
188 system.cpu.dcache.demand_miss_latency::cpu.data 9879688000 # number of demand (read+write) miss cycles
189 system.cpu.dcache.demand_miss_latency::total 9879688000 # number of demand (read+write) miss cycles
190 system.cpu.dcache.overall_miss_latency::cpu.data 9879688000 # number of overall miss cycles
191 system.cpu.dcache.overall_miss_latency::total 9879688000 # number of overall miss cycles
192 system.cpu.dcache.ReadReq_accesses::cpu.data 147791852 # number of ReadReq accesses(hits+misses)
193 system.cpu.dcache.ReadReq_accesses::total 147791852 # number of ReadReq accesses(hits+misses)
194 system.cpu.dcache.WriteReq_accesses::cpu.data 69417531 # number of WriteReq accesses(hits+misses)
195 system.cpu.dcache.WriteReq_accesses::total 69417531 # number of WriteReq accesses(hits+misses)
196 system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1327 # number of LoadLockedReq accesses(hits+misses)
197 system.cpu.dcache.LoadLockedReq_accesses::total 1327 # number of LoadLockedReq accesses(hits+misses)
198 system.cpu.dcache.StoreCondReq_accesses::cpu.data 1327 # number of StoreCondReq accesses(hits+misses)
199 system.cpu.dcache.StoreCondReq_accesses::total 1327 # number of StoreCondReq accesses(hits+misses)
200 system.cpu.dcache.demand_accesses::cpu.data 217209383 # number of demand (read+write) accesses
201 system.cpu.dcache.demand_accesses::total 217209383 # number of demand (read+write) accesses
202 system.cpu.dcache.overall_accesses::cpu.data 217209383 # number of overall (read+write) accesses
203 system.cpu.dcache.overall_accesses::total 217209383 # number of overall (read+write) accesses
204 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001284 # miss rate for ReadReq accesses
205 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003569 # miss rate for WriteReq accesses
206 system.cpu.dcache.demand_miss_rate::cpu.data 0.002014 # miss rate for demand accesses
207 system.cpu.dcache.overall_miss_rate::cpu.data 0.002014 # miss rate for overall accesses
208 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20842.679226 # average ReadReq miss latency
209 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23909.028529 # average WriteReq miss latency
210 system.cpu.dcache.demand_avg_miss_latency::cpu.data 22578.841038 # average overall miss latency
211 system.cpu.dcache.overall_avg_miss_latency::cpu.data 22578.841038 # average overall miss latency
212 system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
213 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
214 system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
215 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
216 system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
217 system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
218 system.cpu.dcache.fast_writes 0 # number of fast writes performed
219 system.cpu.dcache.cache_copies 0 # number of cache copies performed
220 system.cpu.dcache.writebacks::writebacks 392392 # number of writebacks
221 system.cpu.dcache.writebacks::total 392392 # number of writebacks
222 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 189816 # number of ReadReq MSHR misses
223 system.cpu.dcache.ReadReq_mshr_misses::total 189816 # number of ReadReq MSHR misses
224 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 247748 # number of WriteReq MSHR misses
225 system.cpu.dcache.WriteReq_mshr_misses::total 247748 # number of WriteReq MSHR misses
226 system.cpu.dcache.demand_mshr_misses::cpu.data 437564 # number of demand (read+write) MSHR misses
227 system.cpu.dcache.demand_mshr_misses::total 437564 # number of demand (read+write) MSHR misses
228 system.cpu.dcache.overall_mshr_misses::cpu.data 437564 # number of overall MSHR misses
229 system.cpu.dcache.overall_mshr_misses::total 437564 # number of overall MSHR misses
230 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3386826000 # number of ReadReq MSHR miss cycles
231 system.cpu.dcache.ReadReq_mshr_miss_latency::total 3386826000 # number of ReadReq MSHR miss cycles
232 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5180170000 # number of WriteReq MSHR miss cycles
233 system.cpu.dcache.WriteReq_mshr_miss_latency::total 5180170000 # number of WriteReq MSHR miss cycles
234 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8566996000 # number of demand (read+write) MSHR miss cycles
235 system.cpu.dcache.demand_mshr_miss_latency::total 8566996000 # number of demand (read+write) MSHR miss cycles
236 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8566996000 # number of overall MSHR miss cycles
237 system.cpu.dcache.overall_mshr_miss_latency::total 8566996000 # number of overall MSHR miss cycles
238 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001284 # mshr miss rate for ReadReq accesses
239 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003569 # mshr miss rate for WriteReq accesses
240 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002014 # mshr miss rate for demand accesses
241 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002014 # mshr miss rate for overall accesses
242 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17842.679226 # average ReadReq mshr miss latency
243 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 20909.028529 # average WriteReq mshr miss latency
244 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19578.841038 # average overall mshr miss latency
245 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19578.841038 # average overall mshr miss latency
246 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
247 system.cpu.l2cache.replacements 71804 # number of replacements
248 system.cpu.l2cache.tagsinuse 17904.014680 # Cycle average of tags in use
249 system.cpu.l2cache.total_refs 411836 # Total number of references to valid blocks.
250 system.cpu.l2cache.sampled_refs 87286 # Sample count of references to valid blocks.
251 system.cpu.l2cache.avg_refs 4.718237 # Average number of references to valid blocks.
252 system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
253 system.cpu.l2cache.occ_blocks::writebacks 16141.835335 # Average occupied blocks per requestor
254 system.cpu.l2cache.occ_blocks::cpu.inst 24.672100 # Average occupied blocks per requestor
255 system.cpu.l2cache.occ_blocks::cpu.data 1737.507245 # Average occupied blocks per requestor
256 system.cpu.l2cache.occ_percent::writebacks 0.492610 # Average percentage of cache occupancy
257 system.cpu.l2cache.occ_percent::cpu.inst 0.000753 # Average percentage of cache occupancy
258 system.cpu.l2cache.occ_percent::cpu.data 0.053025 # Average percentage of cache occupancy
259 system.cpu.l2cache.occ_percent::total 0.546387 # Average percentage of cache occupancy
260 system.cpu.l2cache.ReadReq_hits::cpu.inst 27 # number of ReadReq hits
261 system.cpu.l2cache.ReadReq_hits::cpu.data 158891 # number of ReadReq hits
262 system.cpu.l2cache.ReadReq_hits::total 158918 # number of ReadReq hits
263 system.cpu.l2cache.Writeback_hits::writebacks 392392 # number of Writeback hits
264 system.cpu.l2cache.Writeback_hits::total 392392 # number of Writeback hits
265 system.cpu.l2cache.ReadExReq_hits::cpu.data 189297 # number of ReadExReq hits
266 system.cpu.l2cache.ReadExReq_hits::total 189297 # number of ReadExReq hits
267 system.cpu.l2cache.demand_hits::cpu.inst 27 # number of demand (read+write) hits
268 system.cpu.l2cache.demand_hits::cpu.data 348188 # number of demand (read+write) hits
269 system.cpu.l2cache.demand_hits::total 348215 # number of demand (read+write) hits
270 system.cpu.l2cache.overall_hits::cpu.inst 27 # number of overall hits
271 system.cpu.l2cache.overall_hits::cpu.data 348188 # number of overall hits
272 system.cpu.l2cache.overall_hits::total 348215 # number of overall hits
273 system.cpu.l2cache.ReadReq_misses::cpu.inst 616 # number of ReadReq misses
274 system.cpu.l2cache.ReadReq_misses::cpu.data 30925 # number of ReadReq misses
275 system.cpu.l2cache.ReadReq_misses::total 31541 # number of ReadReq misses
276 system.cpu.l2cache.ReadExReq_misses::cpu.data 58451 # number of ReadExReq misses
277 system.cpu.l2cache.ReadExReq_misses::total 58451 # number of ReadExReq misses
278 system.cpu.l2cache.demand_misses::cpu.inst 616 # number of demand (read+write) misses
279 system.cpu.l2cache.demand_misses::cpu.data 89376 # number of demand (read+write) misses
280 system.cpu.l2cache.demand_misses::total 89992 # number of demand (read+write) misses
281 system.cpu.l2cache.overall_misses::cpu.inst 616 # number of overall misses
282 system.cpu.l2cache.overall_misses::cpu.data 89376 # number of overall misses
283 system.cpu.l2cache.overall_misses::total 89992 # number of overall misses
284 system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 32032000 # number of ReadReq miss cycles
285 system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1608100000 # number of ReadReq miss cycles
286 system.cpu.l2cache.ReadReq_miss_latency::total 1640132000 # number of ReadReq miss cycles
287 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3039452000 # number of ReadExReq miss cycles
288 system.cpu.l2cache.ReadExReq_miss_latency::total 3039452000 # number of ReadExReq miss cycles
289 system.cpu.l2cache.demand_miss_latency::cpu.inst 32032000 # number of demand (read+write) miss cycles
290 system.cpu.l2cache.demand_miss_latency::cpu.data 4647552000 # number of demand (read+write) miss cycles
291 system.cpu.l2cache.demand_miss_latency::total 4679584000 # number of demand (read+write) miss cycles
292 system.cpu.l2cache.overall_miss_latency::cpu.inst 32032000 # number of overall miss cycles
293 system.cpu.l2cache.overall_miss_latency::cpu.data 4647552000 # number of overall miss cycles
294 system.cpu.l2cache.overall_miss_latency::total 4679584000 # number of overall miss cycles
295 system.cpu.l2cache.ReadReq_accesses::cpu.inst 643 # number of ReadReq accesses(hits+misses)
296 system.cpu.l2cache.ReadReq_accesses::cpu.data 189816 # number of ReadReq accesses(hits+misses)
297 system.cpu.l2cache.ReadReq_accesses::total 190459 # number of ReadReq accesses(hits+misses)
298 system.cpu.l2cache.Writeback_accesses::writebacks 392392 # number of Writeback accesses(hits+misses)
299 system.cpu.l2cache.Writeback_accesses::total 392392 # number of Writeback accesses(hits+misses)
300 system.cpu.l2cache.ReadExReq_accesses::cpu.data 247748 # number of ReadExReq accesses(hits+misses)
301 system.cpu.l2cache.ReadExReq_accesses::total 247748 # number of ReadExReq accesses(hits+misses)
302 system.cpu.l2cache.demand_accesses::cpu.inst 643 # number of demand (read+write) accesses
303 system.cpu.l2cache.demand_accesses::cpu.data 437564 # number of demand (read+write) accesses
304 system.cpu.l2cache.demand_accesses::total 438207 # number of demand (read+write) accesses
305 system.cpu.l2cache.overall_accesses::cpu.inst 643 # number of overall (read+write) accesses
306 system.cpu.l2cache.overall_accesses::cpu.data 437564 # number of overall (read+write) accesses
307 system.cpu.l2cache.overall_accesses::total 438207 # number of overall (read+write) accesses
308 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.958009 # miss rate for ReadReq accesses
309 system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.162921 # miss rate for ReadReq accesses
310 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.235929 # miss rate for ReadExReq accesses
311 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.958009 # miss rate for demand accesses
312 system.cpu.l2cache.demand_miss_rate::cpu.data 0.204258 # miss rate for demand accesses
313 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.958009 # miss rate for overall accesses
314 system.cpu.l2cache.overall_miss_rate::cpu.data 0.204258 # miss rate for overall accesses
315 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
316 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
317 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
318 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
319 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
320 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
321 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
322 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
323 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
324 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
325 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
326 system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
327 system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
328 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
329 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
330 system.cpu.l2cache.writebacks::writebacks 57886 # number of writebacks
331 system.cpu.l2cache.writebacks::total 57886 # number of writebacks
332 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 616 # number of ReadReq MSHR misses
333 system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 30925 # number of ReadReq MSHR misses
334 system.cpu.l2cache.ReadReq_mshr_misses::total 31541 # number of ReadReq MSHR misses
335 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 58451 # number of ReadExReq MSHR misses
336 system.cpu.l2cache.ReadExReq_mshr_misses::total 58451 # number of ReadExReq MSHR misses
337 system.cpu.l2cache.demand_mshr_misses::cpu.inst 616 # number of demand (read+write) MSHR misses
338 system.cpu.l2cache.demand_mshr_misses::cpu.data 89376 # number of demand (read+write) MSHR misses
339 system.cpu.l2cache.demand_mshr_misses::total 89992 # number of demand (read+write) MSHR misses
340 system.cpu.l2cache.overall_mshr_misses::cpu.inst 616 # number of overall MSHR misses
341 system.cpu.l2cache.overall_mshr_misses::cpu.data 89376 # number of overall MSHR misses
342 system.cpu.l2cache.overall_mshr_misses::total 89992 # number of overall MSHR misses
343 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 24640000 # number of ReadReq MSHR miss cycles
344 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1237000000 # number of ReadReq MSHR miss cycles
345 system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1261640000 # number of ReadReq MSHR miss cycles
346 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2338040000 # number of ReadExReq MSHR miss cycles
347 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2338040000 # number of ReadExReq MSHR miss cycles
348 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24640000 # number of demand (read+write) MSHR miss cycles
349 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3575040000 # number of demand (read+write) MSHR miss cycles
350 system.cpu.l2cache.demand_mshr_miss_latency::total 3599680000 # number of demand (read+write) MSHR miss cycles
351 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24640000 # number of overall MSHR miss cycles
352 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3575040000 # number of overall MSHR miss cycles
353 system.cpu.l2cache.overall_mshr_miss_latency::total 3599680000 # number of overall MSHR miss cycles
354 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.958009 # mshr miss rate for ReadReq accesses
355 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.162921 # mshr miss rate for ReadReq accesses
356 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.235929 # mshr miss rate for ReadExReq accesses
357 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.958009 # mshr miss rate for demand accesses
358 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.204258 # mshr miss rate for demand accesses
359 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.958009 # mshr miss rate for overall accesses
360 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.204258 # mshr miss rate for overall accesses
361 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
362 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
363 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
364 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
365 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
366 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
367 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
368 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
370 ---------- End Simulation Statistics ----------
projects / gem5.git / blob