tests/long/se/00.gzip/ref/sparc/linux/o3-timing/config.ini

   1 [root]
   2 type=Root
   3 children=system
   4 full_system=false
   5 time_sync_enable=false
   6 time_sync_period=100000000000
   7 time_sync_spin_threshold=100000000
   8
   9 [system]
  10 type=System
  11 children=cpu membus physmem
  12 boot_osflags=a
  13 clock=1000
  14 init_param=0
  15 kernel=
  16 load_addr_mask=1099511627775
  17 mem_mode=timing
  18 mem_ranges=
  19 memories=system.physmem
  20 num_work_ids=16
  21 readfile=
  22 symbolfile=
  23 work_begin_ckpt_count=0
  24 work_begin_cpu_id_exit=-1
  25 work_begin_exit_count=0
  26 work_cpus_ckpt_count=0
  27 work_end_ckpt_count=0
  28 work_end_exit_count=0
  29 work_item_id=-1
  30 system_port=system.membus.slave[0]
  31
  32 [system.cpu]
  33 type=DerivO3CPU
  34 children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
  35 BTBEntries=4096
  36 BTBTagSize=16
  37 LFSTSize=1024
  38 LQEntries=32
  39 LSQCheckLoads=true
  40 LSQDepCheckShift=4
  41 RASSize=16
  42 SQEntries=32
  43 SSITSize=1024
  44 activity=0
  45 backComSize=5
  46 cachePorts=200
  47 checker=Null
  48 choiceCtrBits=2
  49 choicePredictorSize=8192
  50 clock=500
  51 commitToDecodeDelay=1
  52 commitToFetchDelay=1
  53 commitToIEWDelay=1
  54 commitToRenameDelay=1
  55 commitWidth=8
  56 cpu_id=0
  57 decodeToFetchDelay=1
  58 decodeToRenameDelay=1
  59 decodeWidth=8
  60 dispatchWidth=8
  61 do_checkpoint_insts=true
  62 do_quiesce=true
  63 do_statistics_insts=true
  64 dtb=system.cpu.dtb
  65 fetchToDecodeDelay=1
  66 fetchTrapLatency=1
  67 fetchWidth=8
  68 forwardComSize=5
  69 fuPool=system.cpu.fuPool
  70 function_trace=false
  71 function_trace_start=0
  72 globalCtrBits=2
  73 globalHistoryBits=13
  74 globalPredictorSize=8192
  75 iewToCommitDelay=1
  76 iewToDecodeDelay=1
  77 iewToFetchDelay=1
  78 iewToRenameDelay=1
  79 instShiftAmt=2
  80 interrupts=system.cpu.interrupts
  81 isa=system.cpu.isa
  82 issueToExecuteDelay=1
  83 issueWidth=8
  84 itb=system.cpu.itb
  85 localCtrBits=2
  86 localHistoryBits=11
  87 localHistoryTableSize=2048
  88 localPredictorSize=2048
  89 max_insts_all_threads=0
  90 max_insts_any_thread=0
  91 max_loads_all_threads=0
  92 max_loads_any_thread=0
  93 needsTSO=false
  94 numIQEntries=64
  95 numPhysFloatRegs=256
  96 numPhysIntRegs=256
  97 numROBEntries=192
  98 numRobs=1
  99 numThreads=1
 100 predType=tournament
 101 profile=0
 102 progress_interval=0
 103 renameToDecodeDelay=1
 104 renameToFetchDelay=1
 105 renameToIEWDelay=2
 106 renameToROBDelay=1
 107 renameWidth=8
 108 smtCommitPolicy=RoundRobin
 109 smtFetchPolicy=SingleThread
 110 smtIQPolicy=Partitioned
 111 smtIQThreshold=100
 112 smtLSQPolicy=Partitioned
 113 smtLSQThreshold=100
 114 smtNumFetchingThreads=1
 115 smtROBPolicy=Partitioned
 116 smtROBThreshold=100
 117 squashWidth=8
 118 store_set_clear_period=250000
 119 switched_out=false
 120 system=system
 121 tracer=system.cpu.tracer
 122 trapLatency=13
 123 wbDepth=1
 124 wbWidth=8
 125 workload=system.cpu.workload
 126 dcache_port=system.cpu.dcache.cpu_side
 127 icache_port=system.cpu.icache.cpu_side
 128
 129 [system.cpu.dcache]
 130 type=BaseCache
 131 addr_ranges=0:18446744073709551615
 132 assoc=2
 133 block_size=64
 134 clock=500
 135 forward_snoops=true
 136 hit_latency=2
 137 is_top_level=true
 138 max_miss_count=0
 139 mshrs=4
 140 prefetch_on_access=false
 141 prefetcher=Null
 142 response_latency=2
 143 size=262144
 144 system=system
 145 tgts_per_mshr=20
 146 two_queue=false
 147 write_buffers=8
 148 cpu_side=system.cpu.dcache_port
 149 mem_side=system.cpu.toL2Bus.slave[1]
 150
 151 [system.cpu.dtb]
 152 type=SparcTLB
 153 size=64
 154
 155 [system.cpu.fuPool]
 156 type=FUPool
 157 children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
 158 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
 159
 160 [system.cpu.fuPool.FUList0]
 161 type=FUDesc
 162 children=opList
 163 count=6
 164 opList=system.cpu.fuPool.FUList0.opList
 165
 166 [system.cpu.fuPool.FUList0.opList]
 167 type=OpDesc
 168 issueLat=1
 169 opClass=IntAlu
 170 opLat=1
 171
 172 [system.cpu.fuPool.FUList1]
 173 type=FUDesc
 174 children=opList0 opList1
 175 count=2
 176 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
 177
 178 [system.cpu.fuPool.FUList1.opList0]
 179 type=OpDesc
 180 issueLat=1
 181 opClass=IntMult
 182 opLat=3
 183
 184 [system.cpu.fuPool.FUList1.opList1]
 185 type=OpDesc
 186 issueLat=19
 187 opClass=IntDiv
 188 opLat=20
 189
 190 [system.cpu.fuPool.FUList2]
 191 type=FUDesc
 192 children=opList0 opList1 opList2
 193 count=4
 194 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
 195
 196 [system.cpu.fuPool.FUList2.opList0]
 197 type=OpDesc
 198 issueLat=1
 199 opClass=FloatAdd
 200 opLat=2
 201
 202 [system.cpu.fuPool.FUList2.opList1]
 203 type=OpDesc
 204 issueLat=1
 205 opClass=FloatCmp
 206 opLat=2
 207
 208 [system.cpu.fuPool.FUList2.opList2]
 209 type=OpDesc
 210 issueLat=1
 211 opClass=FloatCvt
 212 opLat=2
 213
 214 [system.cpu.fuPool.FUList3]
 215 type=FUDesc
 216 children=opList0 opList1 opList2
 217 count=2
 218 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
 219
 220 [system.cpu.fuPool.FUList3.opList0]
 221 type=OpDesc
 222 issueLat=1
 223 opClass=FloatMult
 224 opLat=4
 225
 226 [system.cpu.fuPool.FUList3.opList1]
 227 type=OpDesc
 228 issueLat=12
 229 opClass=FloatDiv
 230 opLat=12
 231
 232 [system.cpu.fuPool.FUList3.opList2]
 233 type=OpDesc
 234 issueLat=24
 235 opClass=FloatSqrt
 236 opLat=24
 237
 238 [system.cpu.fuPool.FUList4]
 239 type=FUDesc
 240 children=opList
 241 count=0
 242 opList=system.cpu.fuPool.FUList4.opList
 243
 244 [system.cpu.fuPool.FUList4.opList]
 245 type=OpDesc
 246 issueLat=1
 247 opClass=MemRead
 248 opLat=1
 249
 250 [system.cpu.fuPool.FUList5]
 251 type=FUDesc
 252 children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
 253 count=4
 254 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
 255
 256 [system.cpu.fuPool.FUList5.opList00]
 257 type=OpDesc
 258 issueLat=1
 259 opClass=SimdAdd
 260 opLat=1
 261
 262 [system.cpu.fuPool.FUList5.opList01]
 263 type=OpDesc
 264 issueLat=1
 265 opClass=SimdAddAcc
 266 opLat=1
 267
 268 [system.cpu.fuPool.FUList5.opList02]
 269 type=OpDesc
 270 issueLat=1
 271 opClass=SimdAlu
 272 opLat=1
 273
 274 [system.cpu.fuPool.FUList5.opList03]
 275 type=OpDesc
 276 issueLat=1
 277 opClass=SimdCmp
 278 opLat=1
 279
 280 [system.cpu.fuPool.FUList5.opList04]
 281 type=OpDesc
 282 issueLat=1
 283 opClass=SimdCvt
 284 opLat=1
 285
 286 [system.cpu.fuPool.FUList5.opList05]
 287 type=OpDesc
 288 issueLat=1
 289 opClass=SimdMisc
 290 opLat=1
 291
 292 [system.cpu.fuPool.FUList5.opList06]
 293 type=OpDesc
 294 issueLat=1
 295 opClass=SimdMult
 296 opLat=1
 297
 298 [system.cpu.fuPool.FUList5.opList07]
 299 type=OpDesc
 300 issueLat=1
 301 opClass=SimdMultAcc
 302 opLat=1
 303
 304 [system.cpu.fuPool.FUList5.opList08]
 305 type=OpDesc
 306 issueLat=1
 307 opClass=SimdShift
 308 opLat=1
 309
 310 [system.cpu.fuPool.FUList5.opList09]
 311 type=OpDesc
 312 issueLat=1
 313 opClass=SimdShiftAcc
 314 opLat=1
 315
 316 [system.cpu.fuPool.FUList5.opList10]
 317 type=OpDesc
 318 issueLat=1
 319 opClass=SimdSqrt
 320 opLat=1
 321
 322 [system.cpu.fuPool.FUList5.opList11]
 323 type=OpDesc
 324 issueLat=1
 325 opClass=SimdFloatAdd
 326 opLat=1
 327
 328 [system.cpu.fuPool.FUList5.opList12]
 329 type=OpDesc
 330 issueLat=1
 331 opClass=SimdFloatAlu
 332 opLat=1
 333
 334 [system.cpu.fuPool.FUList5.opList13]
 335 type=OpDesc
 336 issueLat=1
 337 opClass=SimdFloatCmp
 338 opLat=1
 339
 340 [system.cpu.fuPool.FUList5.opList14]
 341 type=OpDesc
 342 issueLat=1
 343 opClass=SimdFloatCvt
 344 opLat=1
 345
 346 [system.cpu.fuPool.FUList5.opList15]
 347 type=OpDesc
 348 issueLat=1
 349 opClass=SimdFloatDiv
 350 opLat=1
 351
 352 [system.cpu.fuPool.FUList5.opList16]
 353 type=OpDesc
 354 issueLat=1
 355 opClass=SimdFloatMisc
 356 opLat=1
 357
 358 [system.cpu.fuPool.FUList5.opList17]
 359 type=OpDesc
 360 issueLat=1
 361 opClass=SimdFloatMult
 362 opLat=1
 363
 364 [system.cpu.fuPool.FUList5.opList18]
 365 type=OpDesc
 366 issueLat=1
 367 opClass=SimdFloatMultAcc
 368 opLat=1
 369
 370 [system.cpu.fuPool.FUList5.opList19]
 371 type=OpDesc
 372 issueLat=1
 373 opClass=SimdFloatSqrt
 374 opLat=1
 375
 376 [system.cpu.fuPool.FUList6]
 377 type=FUDesc
 378 children=opList
 379 count=0
 380 opList=system.cpu.fuPool.FUList6.opList
 381
 382 [system.cpu.fuPool.FUList6.opList]
 383 type=OpDesc
 384 issueLat=1
 385 opClass=MemWrite
 386 opLat=1
 387
 388 [system.cpu.fuPool.FUList7]
 389 type=FUDesc
 390 children=opList0 opList1
 391 count=4
 392 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
 393
 394 [system.cpu.fuPool.FUList7.opList0]
 395 type=OpDesc
 396 issueLat=1
 397 opClass=MemRead
 398 opLat=1
 399
 400 [system.cpu.fuPool.FUList7.opList1]
 401 type=OpDesc
 402 issueLat=1
 403 opClass=MemWrite
 404 opLat=1
 405
 406 [system.cpu.fuPool.FUList8]
 407 type=FUDesc
 408 children=opList
 409 count=1
 410 opList=system.cpu.fuPool.FUList8.opList
 411
 412 [system.cpu.fuPool.FUList8.opList]
 413 type=OpDesc
 414 issueLat=3
 415 opClass=IprAccess
 416 opLat=3
 417
 418 [system.cpu.icache]
 419 type=BaseCache
 420 addr_ranges=0:18446744073709551615
 421 assoc=2
 422 block_size=64
 423 clock=500
 424 forward_snoops=true
 425 hit_latency=2
 426 is_top_level=true
 427 max_miss_count=0
 428 mshrs=4
 429 prefetch_on_access=false
 430 prefetcher=Null
 431 response_latency=2
 432 size=131072
 433 system=system
 434 tgts_per_mshr=20
 435 two_queue=false
 436 write_buffers=8
 437 cpu_side=system.cpu.icache_port
 438 mem_side=system.cpu.toL2Bus.slave[0]
 439
 440 [system.cpu.interrupts]
 441 type=SparcInterrupts
 442
 443 [system.cpu.isa]
 444 type=SparcISA
 445
 446 [system.cpu.itb]
 447 type=SparcTLB
 448 size=64
 449
 450 [system.cpu.l2cache]
 451 type=BaseCache
 452 addr_ranges=0:18446744073709551615
 453 assoc=8
 454 block_size=64
 455 clock=500
 456 forward_snoops=true
 457 hit_latency=20
 458 is_top_level=false
 459 max_miss_count=0
 460 mshrs=20
 461 prefetch_on_access=false
 462 prefetcher=Null
 463 response_latency=20
 464 size=2097152
 465 system=system
 466 tgts_per_mshr=12
 467 two_queue=false
 468 write_buffers=8
 469 cpu_side=system.cpu.toL2Bus.master[0]
 470 mem_side=system.membus.slave[1]
 471
 472 [system.cpu.toL2Bus]
 473 type=CoherentBus
 474 block_size=64
 475 clock=500
 476 header_cycles=1
 477 use_default_range=false
 478 width=32
 479 master=system.cpu.l2cache.cpu_side
 480 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
 481
 482 [system.cpu.tracer]
 483 type=ExeTracer
 484
 485 [system.cpu.workload]
 486 type=LiveProcess
 487 cmd=gzip input.log 1
 488 cwd=build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/o3-timing
 489 egid=100
 490 env=
 491 errout=cerr
 492 euid=100
 493 executable=/gem5/dist/cpu2000/binaries/sparc/linux/gzip
 494 gid=100
 495 input=cin
 496 max_stack_size=67108864
 497 output=cout
 498 pid=100
 499 ppid=99
 500 simpoint=0
 501 system=system
 502 uid=100
 503
 504 [system.membus]
 505 type=CoherentBus
 506 block_size=64
 507 clock=1000
 508 header_cycles=1
 509 use_default_range=false
 510 width=8
 511 master=system.physmem.port
 512 slave=system.system_port system.cpu.l2cache.mem_side
 513
 514 [system.physmem]
 515 type=SimpleDRAM
 516 addr_mapping=openmap
 517 banks_per_rank=8
 518 clock=1000
 519 conf_table_reported=false
 520 in_addr_map=true
 521 lines_per_rowbuffer=64
 522 mem_sched_policy=fcfs
 523 null=false
 524 page_policy=open
 525 range=0:134217727
 526 ranks_per_channel=2
 527 read_buffer_size=32
 528 tBURST=4000
 529 tCL=14000
 530 tRCD=14000
 531 tREFI=7800000
 532 tRFC=300000
 533 tRP=14000
 534 tWTR=1000
 535 write_buffer_size=32
 536 write_thresh_perc=70
 537 zero=false
 538 port=system.membus.master[0]
 539