tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini

   1 [root]
   2 type=Root
   3 children=system
   4 time_sync_enable=false
   5 time_sync_period=100000000000
   6 time_sync_spin_threshold=100000000
   7
   8 [system]
   9 type=System
  10 children=cpu membus physmem
  11 mem_mode=atomic
  12 memories=system.physmem
  13 num_work_ids=16
  14 physmem=system.physmem
  15 work_begin_ckpt_count=0
  16 work_begin_cpu_id_exit=-1
  17 work_begin_exit_count=0
  18 work_cpus_ckpt_count=0
  19 work_end_ckpt_count=0
  20 work_end_exit_count=0
  21 work_item_id=-1
  22 system_port=system.membus.port[0]
  23
  24 [system.cpu]
  25 type=DerivO3CPU
  26 children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload
  27 BTBEntries=4096
  28 BTBTagSize=16
  29 LFSTSize=1024
  30 LQEntries=32
  31 LSQCheckLoads=true
  32 LSQDepCheckShift=4
  33 RASSize=16
  34 SQEntries=32
  35 SSITSize=1024
  36 activity=0
  37 backComSize=5
  38 cachePorts=200
  39 checker=Null
  40 choiceCtrBits=2
  41 choicePredictorSize=8192
  42 clock=500
  43 commitToDecodeDelay=1
  44 commitToFetchDelay=1
  45 commitToIEWDelay=1
  46 commitToRenameDelay=1
  47 commitWidth=8
  48 cpu_id=0
  49 decodeToFetchDelay=1
  50 decodeToRenameDelay=1
  51 decodeWidth=8
  52 defer_registration=false
  53 dispatchWidth=8
  54 do_checkpoint_insts=true
  55 do_statistics_insts=true
  56 dtb=system.cpu.dtb
  57 fetchToDecodeDelay=1
  58 fetchTrapLatency=1
  59 fetchWidth=8
  60 forwardComSize=5
  61 fuPool=system.cpu.fuPool
  62 function_trace=false
  63 function_trace_start=0
  64 globalCtrBits=2
  65 globalHistoryBits=13
  66 globalPredictorSize=8192
  67 iewToCommitDelay=1
  68 iewToDecodeDelay=1
  69 iewToFetchDelay=1
  70 iewToRenameDelay=1
  71 instShiftAmt=2
  72 issueToExecuteDelay=1
  73 issueWidth=8
  74 itb=system.cpu.itb
  75 localCtrBits=2
  76 localHistoryBits=11
  77 localHistoryTableSize=2048
  78 localPredictorSize=2048
  79 max_insts_all_threads=0
  80 max_insts_any_thread=0
  81 max_loads_all_threads=0
  82 max_loads_any_thread=0
  83 needsTSO=true
  84 numIQEntries=64
  85 numPhysFloatRegs=256
  86 numPhysIntRegs=256
  87 numROBEntries=192
  88 numRobs=1
  89 numThreads=1
  90 phase=0
  91 predType=tournament
  92 progress_interval=0
  93 renameToDecodeDelay=1
  94 renameToFetchDelay=1
  95 renameToIEWDelay=2
  96 renameToROBDelay=1
  97 renameWidth=8
  98 smtCommitPolicy=RoundRobin
  99 smtFetchPolicy=SingleThread
 100 smtIQPolicy=Partitioned
 101 smtIQThreshold=100
 102 smtLSQPolicy=Partitioned
 103 smtLSQThreshold=100
 104 smtNumFetchingThreads=1
 105 smtROBPolicy=Partitioned
 106 smtROBThreshold=100
 107 squashWidth=8
 108 store_set_clear_period=250000
 109 system=system
 110 tracer=system.cpu.tracer
 111 trapLatency=13
 112 wbDepth=1
 113 wbWidth=8
 114 workload=system.cpu.workload
 115 dcache_port=system.cpu.dcache.cpu_side
 116 icache_port=system.cpu.icache.cpu_side
 117
 118 [system.cpu.dcache]
 119 type=BaseCache
 120 addr_range=0:18446744073709551615
 121 assoc=2
 122 block_size=64
 123 forward_snoops=true
 124 hash_delay=1
 125 is_top_level=true
 126 latency=1000
 127 max_miss_count=0
 128 mshrs=10
 129 num_cpus=1
 130 prefetch_data_accesses_only=false
 131 prefetch_degree=1
 132 prefetch_latency=10000
 133 prefetch_on_access=false
 134 prefetch_past_page=false
 135 prefetch_policy=none
 136 prefetch_serial_squash=false
 137 prefetch_use_cpu_id=true
 138 prefetcher_size=100
 139 prioritizeRequests=false
 140 repl=Null
 141 size=262144
 142 subblock_size=0
 143 tgts_per_mshr=20
 144 trace_addr=0
 145 two_queue=false
 146 write_buffers=8
 147 cpu_side=system.cpu.dcache_port
 148 mem_side=system.cpu.toL2Bus.port[1]
 149
 150 [system.cpu.dtb]
 151 type=X86TLB
 152 size=64
 153
 154 [system.cpu.fuPool]
 155 type=FUPool
 156 children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
 157 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
 158
 159 [system.cpu.fuPool.FUList0]
 160 type=FUDesc
 161 children=opList
 162 count=6
 163 opList=system.cpu.fuPool.FUList0.opList
 164
 165 [system.cpu.fuPool.FUList0.opList]
 166 type=OpDesc
 167 issueLat=1
 168 opClass=IntAlu
 169 opLat=1
 170
 171 [system.cpu.fuPool.FUList1]
 172 type=FUDesc
 173 children=opList0 opList1
 174 count=2
 175 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
 176
 177 [system.cpu.fuPool.FUList1.opList0]
 178 type=OpDesc
 179 issueLat=1
 180 opClass=IntMult
 181 opLat=3
 182
 183 [system.cpu.fuPool.FUList1.opList1]
 184 type=OpDesc
 185 issueLat=19
 186 opClass=IntDiv
 187 opLat=20
 188
 189 [system.cpu.fuPool.FUList2]
 190 type=FUDesc
 191 children=opList0 opList1 opList2
 192 count=4
 193 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
 194
 195 [system.cpu.fuPool.FUList2.opList0]
 196 type=OpDesc
 197 issueLat=1
 198 opClass=FloatAdd
 199 opLat=2
 200
 201 [system.cpu.fuPool.FUList2.opList1]
 202 type=OpDesc
 203 issueLat=1
 204 opClass=FloatCmp
 205 opLat=2
 206
 207 [system.cpu.fuPool.FUList2.opList2]
 208 type=OpDesc
 209 issueLat=1
 210 opClass=FloatCvt
 211 opLat=2
 212
 213 [system.cpu.fuPool.FUList3]
 214 type=FUDesc
 215 children=opList0 opList1 opList2
 216 count=2
 217 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
 218
 219 [system.cpu.fuPool.FUList3.opList0]
 220 type=OpDesc
 221 issueLat=1
 222 opClass=FloatMult
 223 opLat=4
 224
 225 [system.cpu.fuPool.FUList3.opList1]
 226 type=OpDesc
 227 issueLat=12
 228 opClass=FloatDiv
 229 opLat=12
 230
 231 [system.cpu.fuPool.FUList3.opList2]
 232 type=OpDesc
 233 issueLat=24
 234 opClass=FloatSqrt
 235 opLat=24
 236
 237 [system.cpu.fuPool.FUList4]
 238 type=FUDesc
 239 children=opList
 240 count=0
 241 opList=system.cpu.fuPool.FUList4.opList
 242
 243 [system.cpu.fuPool.FUList4.opList]
 244 type=OpDesc
 245 issueLat=1
 246 opClass=MemRead
 247 opLat=1
 248
 249 [system.cpu.fuPool.FUList5]
 250 type=FUDesc
 251 children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
 252 count=4
 253 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
 254
 255 [system.cpu.fuPool.FUList5.opList00]
 256 type=OpDesc
 257 issueLat=1
 258 opClass=SimdAdd
 259 opLat=1
 260
 261 [system.cpu.fuPool.FUList5.opList01]
 262 type=OpDesc
 263 issueLat=1
 264 opClass=SimdAddAcc
 265 opLat=1
 266
 267 [system.cpu.fuPool.FUList5.opList02]
 268 type=OpDesc
 269 issueLat=1
 270 opClass=SimdAlu
 271 opLat=1
 272
 273 [system.cpu.fuPool.FUList5.opList03]
 274 type=OpDesc
 275 issueLat=1
 276 opClass=SimdCmp
 277 opLat=1
 278
 279 [system.cpu.fuPool.FUList5.opList04]
 280 type=OpDesc
 281 issueLat=1
 282 opClass=SimdCvt
 283 opLat=1
 284
 285 [system.cpu.fuPool.FUList5.opList05]
 286 type=OpDesc
 287 issueLat=1
 288 opClass=SimdMisc
 289 opLat=1
 290
 291 [system.cpu.fuPool.FUList5.opList06]
 292 type=OpDesc
 293 issueLat=1
 294 opClass=SimdMult
 295 opLat=1
 296
 297 [system.cpu.fuPool.FUList5.opList07]
 298 type=OpDesc
 299 issueLat=1
 300 opClass=SimdMultAcc
 301 opLat=1
 302
 303 [system.cpu.fuPool.FUList5.opList08]
 304 type=OpDesc
 305 issueLat=1
 306 opClass=SimdShift
 307 opLat=1
 308
 309 [system.cpu.fuPool.FUList5.opList09]
 310 type=OpDesc
 311 issueLat=1
 312 opClass=SimdShiftAcc
 313 opLat=1
 314
 315 [system.cpu.fuPool.FUList5.opList10]
 316 type=OpDesc
 317 issueLat=1
 318 opClass=SimdSqrt
 319 opLat=1
 320
 321 [system.cpu.fuPool.FUList5.opList11]
 322 type=OpDesc
 323 issueLat=1
 324 opClass=SimdFloatAdd
 325 opLat=1
 326
 327 [system.cpu.fuPool.FUList5.opList12]
 328 type=OpDesc
 329 issueLat=1
 330 opClass=SimdFloatAlu
 331 opLat=1
 332
 333 [system.cpu.fuPool.FUList5.opList13]
 334 type=OpDesc
 335 issueLat=1
 336 opClass=SimdFloatCmp
 337 opLat=1
 338
 339 [system.cpu.fuPool.FUList5.opList14]
 340 type=OpDesc
 341 issueLat=1
 342 opClass=SimdFloatCvt
 343 opLat=1
 344
 345 [system.cpu.fuPool.FUList5.opList15]
 346 type=OpDesc
 347 issueLat=1
 348 opClass=SimdFloatDiv
 349 opLat=1
 350
 351 [system.cpu.fuPool.FUList5.opList16]
 352 type=OpDesc
 353 issueLat=1
 354 opClass=SimdFloatMisc
 355 opLat=1
 356
 357 [system.cpu.fuPool.FUList5.opList17]
 358 type=OpDesc
 359 issueLat=1
 360 opClass=SimdFloatMult
 361 opLat=1
 362
 363 [system.cpu.fuPool.FUList5.opList18]
 364 type=OpDesc
 365 issueLat=1
 366 opClass=SimdFloatMultAcc
 367 opLat=1
 368
 369 [system.cpu.fuPool.FUList5.opList19]
 370 type=OpDesc
 371 issueLat=1
 372 opClass=SimdFloatSqrt
 373 opLat=1
 374
 375 [system.cpu.fuPool.FUList6]
 376 type=FUDesc
 377 children=opList
 378 count=0
 379 opList=system.cpu.fuPool.FUList6.opList
 380
 381 [system.cpu.fuPool.FUList6.opList]
 382 type=OpDesc
 383 issueLat=1
 384 opClass=MemWrite
 385 opLat=1
 386
 387 [system.cpu.fuPool.FUList7]
 388 type=FUDesc
 389 children=opList0 opList1
 390 count=4
 391 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
 392
 393 [system.cpu.fuPool.FUList7.opList0]
 394 type=OpDesc
 395 issueLat=1
 396 opClass=MemRead
 397 opLat=1
 398
 399 [system.cpu.fuPool.FUList7.opList1]
 400 type=OpDesc
 401 issueLat=1
 402 opClass=MemWrite
 403 opLat=1
 404
 405 [system.cpu.fuPool.FUList8]
 406 type=FUDesc
 407 children=opList
 408 count=1
 409 opList=system.cpu.fuPool.FUList8.opList
 410
 411 [system.cpu.fuPool.FUList8.opList]
 412 type=OpDesc
 413 issueLat=3
 414 opClass=IprAccess
 415 opLat=3
 416
 417 [system.cpu.icache]
 418 type=BaseCache
 419 addr_range=0:18446744073709551615
 420 assoc=2
 421 block_size=64
 422 forward_snoops=true
 423 hash_delay=1
 424 is_top_level=true
 425 latency=1000
 426 max_miss_count=0
 427 mshrs=10
 428 num_cpus=1
 429 prefetch_data_accesses_only=false
 430 prefetch_degree=1
 431 prefetch_latency=10000
 432 prefetch_on_access=false
 433 prefetch_past_page=false
 434 prefetch_policy=none
 435 prefetch_serial_squash=false
 436 prefetch_use_cpu_id=true
 437 prefetcher_size=100
 438 prioritizeRequests=false
 439 repl=Null
 440 size=131072
 441 subblock_size=0
 442 tgts_per_mshr=20
 443 trace_addr=0
 444 two_queue=false
 445 write_buffers=8
 446 cpu_side=system.cpu.icache_port
 447 mem_side=system.cpu.toL2Bus.port[0]
 448
 449 [system.cpu.itb]
 450 type=X86TLB
 451 size=64
 452
 453 [system.cpu.l2cache]
 454 type=BaseCache
 455 addr_range=0:18446744073709551615
 456 assoc=2
 457 block_size=64
 458 forward_snoops=true
 459 hash_delay=1
 460 is_top_level=false
 461 latency=1000
 462 max_miss_count=0
 463 mshrs=10
 464 num_cpus=1
 465 prefetch_data_accesses_only=false
 466 prefetch_degree=1
 467 prefetch_latency=10000
 468 prefetch_on_access=false
 469 prefetch_past_page=false
 470 prefetch_policy=none
 471 prefetch_serial_squash=false
 472 prefetch_use_cpu_id=true
 473 prefetcher_size=100
 474 prioritizeRequests=false
 475 repl=Null
 476 size=2097152
 477 subblock_size=0
 478 tgts_per_mshr=5
 479 trace_addr=0
 480 two_queue=false
 481 write_buffers=8
 482 cpu_side=system.cpu.toL2Bus.port[2]
 483 mem_side=system.membus.port[2]
 484
 485 [system.cpu.toL2Bus]
 486 type=Bus
 487 block_size=64
 488 bus_id=0
 489 clock=1000
 490 header_cycles=1
 491 use_default_range=false
 492 width=64
 493 port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
 494
 495 [system.cpu.tracer]
 496 type=ExeTracer
 497
 498 [system.cpu.workload]
 499 type=LiveProcess
 500 cmd=gzip input.log 1
 501 cwd=build/X86_SE/tests/opt/long/00.gzip/x86/linux/o3-timing
 502 egid=100
 503 env=
 504 errout=cerr
 505 euid=100
 506 executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/gzip
 507 gid=100
 508 input=cin
 509 max_stack_size=67108864
 510 output=cout
 511 pid=100
 512 ppid=99
 513 simpoint=0
 514 system=system
 515 uid=100
 516
 517 [system.membus]
 518 type=Bus
 519 block_size=64
 520 bus_id=0
 521 clock=1000
 522 header_cycles=1
 523 use_default_range=false
 524 width=64
 525 port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
 526
 527 [system.physmem]
 528 type=PhysicalMemory
 529 file=
 530 latency=30000
 531 latency_var=0
 532 null=false
 533 range=0:134217727
 534 zero=false
 535 port=system.membus.port[1]
 536