tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini

   1 [root]
   2 type=Root
   3 children=system
   4 full_system=false
   5 time_sync_enable=false
   6 time_sync_period=100000000000
   7 time_sync_spin_threshold=100000000
   8
   9 [system]
  10 type=System
  11 children=cpu membus physmem
  12 boot_osflags=a
  13 clock=1000
  14 init_param=0
  15 kernel=
  16 load_addr_mask=1099511627775
  17 mem_mode=timing
  18 mem_ranges=
  19 memories=system.physmem
  20 num_work_ids=16
  21 readfile=
  22 symbolfile=
  23 work_begin_ckpt_count=0
  24 work_begin_cpu_id_exit=-1
  25 work_begin_exit_count=0
  26 work_cpus_ckpt_count=0
  27 work_end_ckpt_count=0
  28 work_end_exit_count=0
  29 work_item_id=-1
  30 system_port=system.membus.slave[0]
  31
  32 [system.cpu]
  33 type=DerivO3CPU
  34 children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
  35 LFSTSize=1024
  36 LQEntries=32
  37 LSQCheckLoads=true
  38 LSQDepCheckShift=4
  39 SQEntries=32
  40 SSITSize=1024
  41 activity=0
  42 backComSize=5
  43 branchPred=system.cpu.branchPred
  44 cachePorts=200
  45 checker=Null
  46 clock=500
  47 commitToDecodeDelay=1
  48 commitToFetchDelay=1
  49 commitToIEWDelay=1
  50 commitToRenameDelay=1
  51 commitWidth=8
  52 cpu_id=0
  53 decodeToFetchDelay=1
  54 decodeToRenameDelay=1
  55 decodeWidth=8
  56 dispatchWidth=8
  57 do_checkpoint_insts=true
  58 do_quiesce=true
  59 do_statistics_insts=true
  60 dtb=system.cpu.dtb
  61 fetchToDecodeDelay=1
  62 fetchTrapLatency=1
  63 fetchWidth=8
  64 forwardComSize=5
  65 fuPool=system.cpu.fuPool
  66 function_trace=false
  67 function_trace_start=0
  68 iewToCommitDelay=1
  69 iewToDecodeDelay=1
  70 iewToFetchDelay=1
  71 iewToRenameDelay=1
  72 interrupts=system.cpu.interrupts
  73 isa=system.cpu.isa
  74 issueToExecuteDelay=1
  75 issueWidth=8
  76 itb=system.cpu.itb
  77 max_insts_all_threads=0
  78 max_insts_any_thread=0
  79 max_loads_all_threads=0
  80 max_loads_any_thread=0
  81 needsTSO=true
  82 numIQEntries=64
  83 numPhysFloatRegs=256
  84 numPhysIntRegs=256
  85 numROBEntries=192
  86 numRobs=1
  87 numThreads=1
  88 profile=0
  89 progress_interval=0
  90 renameToDecodeDelay=1
  91 renameToFetchDelay=1
  92 renameToIEWDelay=2
  93 renameToROBDelay=1
  94 renameWidth=8
  95 smtCommitPolicy=RoundRobin
  96 smtFetchPolicy=SingleThread
  97 smtIQPolicy=Partitioned
  98 smtIQThreshold=100
  99 smtLSQPolicy=Partitioned
 100 smtLSQThreshold=100
 101 smtNumFetchingThreads=1
 102 smtROBPolicy=Partitioned
 103 smtROBThreshold=100
 104 squashWidth=8
 105 store_set_clear_period=250000
 106 switched_out=false
 107 system=system
 108 tracer=system.cpu.tracer
 109 trapLatency=13
 110 wbDepth=1
 111 wbWidth=8
 112 workload=system.cpu.workload
 113 dcache_port=system.cpu.dcache.cpu_side
 114 icache_port=system.cpu.icache.cpu_side
 115
 116 [system.cpu.branchPred]
 117 type=BranchPredictor
 118 BTBEntries=4096
 119 BTBTagSize=16
 120 RASSize=16
 121 choiceCtrBits=2
 122 choicePredictorSize=8192
 123 globalCtrBits=2
 124 globalHistoryBits=13
 125 globalPredictorSize=8192
 126 instShiftAmt=2
 127 localCtrBits=2
 128 localHistoryBits=11
 129 localHistoryTableSize=2048
 130 localPredictorSize=2048
 131 numThreads=1
 132 predType=tournament
 133
 134 [system.cpu.dcache]
 135 type=BaseCache
 136 addr_ranges=0:18446744073709551615
 137 assoc=2
 138 block_size=64
 139 clock=500
 140 forward_snoops=true
 141 hit_latency=2
 142 is_top_level=true
 143 max_miss_count=0
 144 mshrs=4
 145 prefetch_on_access=false
 146 prefetcher=Null
 147 response_latency=2
 148 size=262144
 149 system=system
 150 tgts_per_mshr=20
 151 two_queue=false
 152 write_buffers=8
 153 cpu_side=system.cpu.dcache_port
 154 mem_side=system.cpu.toL2Bus.slave[1]
 155
 156 [system.cpu.dtb]
 157 type=X86TLB
 158 children=walker
 159 size=64
 160 walker=system.cpu.dtb.walker
 161
 162 [system.cpu.dtb.walker]
 163 type=X86PagetableWalker
 164 clock=500
 165 system=system
 166 port=system.cpu.toL2Bus.slave[3]
 167
 168 [system.cpu.fuPool]
 169 type=FUPool
 170 children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
 171 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
 172
 173 [system.cpu.fuPool.FUList0]
 174 type=FUDesc
 175 children=opList
 176 count=6
 177 opList=system.cpu.fuPool.FUList0.opList
 178
 179 [system.cpu.fuPool.FUList0.opList]
 180 type=OpDesc
 181 issueLat=1
 182 opClass=IntAlu
 183 opLat=1
 184
 185 [system.cpu.fuPool.FUList1]
 186 type=FUDesc
 187 children=opList0 opList1
 188 count=2
 189 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
 190
 191 [system.cpu.fuPool.FUList1.opList0]
 192 type=OpDesc
 193 issueLat=1
 194 opClass=IntMult
 195 opLat=3
 196
 197 [system.cpu.fuPool.FUList1.opList1]
 198 type=OpDesc
 199 issueLat=19
 200 opClass=IntDiv
 201 opLat=20
 202
 203 [system.cpu.fuPool.FUList2]
 204 type=FUDesc
 205 children=opList0 opList1 opList2
 206 count=4
 207 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
 208
 209 [system.cpu.fuPool.FUList2.opList0]
 210 type=OpDesc
 211 issueLat=1
 212 opClass=FloatAdd
 213 opLat=2
 214
 215 [system.cpu.fuPool.FUList2.opList1]
 216 type=OpDesc
 217 issueLat=1
 218 opClass=FloatCmp
 219 opLat=2
 220
 221 [system.cpu.fuPool.FUList2.opList2]
 222 type=OpDesc
 223 issueLat=1
 224 opClass=FloatCvt
 225 opLat=2
 226
 227 [system.cpu.fuPool.FUList3]
 228 type=FUDesc
 229 children=opList0 opList1 opList2
 230 count=2
 231 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
 232
 233 [system.cpu.fuPool.FUList3.opList0]
 234 type=OpDesc
 235 issueLat=1
 236 opClass=FloatMult
 237 opLat=4
 238
 239 [system.cpu.fuPool.FUList3.opList1]
 240 type=OpDesc
 241 issueLat=12
 242 opClass=FloatDiv
 243 opLat=12
 244
 245 [system.cpu.fuPool.FUList3.opList2]
 246 type=OpDesc
 247 issueLat=24
 248 opClass=FloatSqrt
 249 opLat=24
 250
 251 [system.cpu.fuPool.FUList4]
 252 type=FUDesc
 253 children=opList
 254 count=0
 255 opList=system.cpu.fuPool.FUList4.opList
 256
 257 [system.cpu.fuPool.FUList4.opList]
 258 type=OpDesc
 259 issueLat=1
 260 opClass=MemRead
 261 opLat=1
 262
 263 [system.cpu.fuPool.FUList5]
 264 type=FUDesc
 265 children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
 266 count=4
 267 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
 268
 269 [system.cpu.fuPool.FUList5.opList00]
 270 type=OpDesc
 271 issueLat=1
 272 opClass=SimdAdd
 273 opLat=1
 274
 275 [system.cpu.fuPool.FUList5.opList01]
 276 type=OpDesc
 277 issueLat=1
 278 opClass=SimdAddAcc
 279 opLat=1
 280
 281 [system.cpu.fuPool.FUList5.opList02]
 282 type=OpDesc
 283 issueLat=1
 284 opClass=SimdAlu
 285 opLat=1
 286
 287 [system.cpu.fuPool.FUList5.opList03]
 288 type=OpDesc
 289 issueLat=1
 290 opClass=SimdCmp
 291 opLat=1
 292
 293 [system.cpu.fuPool.FUList5.opList04]
 294 type=OpDesc
 295 issueLat=1
 296 opClass=SimdCvt
 297 opLat=1
 298
 299 [system.cpu.fuPool.FUList5.opList05]
 300 type=OpDesc
 301 issueLat=1
 302 opClass=SimdMisc
 303 opLat=1
 304
 305 [system.cpu.fuPool.FUList5.opList06]
 306 type=OpDesc
 307 issueLat=1
 308 opClass=SimdMult
 309 opLat=1
 310
 311 [system.cpu.fuPool.FUList5.opList07]
 312 type=OpDesc
 313 issueLat=1
 314 opClass=SimdMultAcc
 315 opLat=1
 316
 317 [system.cpu.fuPool.FUList5.opList08]
 318 type=OpDesc
 319 issueLat=1
 320 opClass=SimdShift
 321 opLat=1
 322
 323 [system.cpu.fuPool.FUList5.opList09]
 324 type=OpDesc
 325 issueLat=1
 326 opClass=SimdShiftAcc
 327 opLat=1
 328
 329 [system.cpu.fuPool.FUList5.opList10]
 330 type=OpDesc
 331 issueLat=1
 332 opClass=SimdSqrt
 333 opLat=1
 334
 335 [system.cpu.fuPool.FUList5.opList11]
 336 type=OpDesc
 337 issueLat=1
 338 opClass=SimdFloatAdd
 339 opLat=1
 340
 341 [system.cpu.fuPool.FUList5.opList12]
 342 type=OpDesc
 343 issueLat=1
 344 opClass=SimdFloatAlu
 345 opLat=1
 346
 347 [system.cpu.fuPool.FUList5.opList13]
 348 type=OpDesc
 349 issueLat=1
 350 opClass=SimdFloatCmp
 351 opLat=1
 352
 353 [system.cpu.fuPool.FUList5.opList14]
 354 type=OpDesc
 355 issueLat=1
 356 opClass=SimdFloatCvt
 357 opLat=1
 358
 359 [system.cpu.fuPool.FUList5.opList15]
 360 type=OpDesc
 361 issueLat=1
 362 opClass=SimdFloatDiv
 363 opLat=1
 364
 365 [system.cpu.fuPool.FUList5.opList16]
 366 type=OpDesc
 367 issueLat=1
 368 opClass=SimdFloatMisc
 369 opLat=1
 370
 371 [system.cpu.fuPool.FUList5.opList17]
 372 type=OpDesc
 373 issueLat=1
 374 opClass=SimdFloatMult
 375 opLat=1
 376
 377 [system.cpu.fuPool.FUList5.opList18]
 378 type=OpDesc
 379 issueLat=1
 380 opClass=SimdFloatMultAcc
 381 opLat=1
 382
 383 [system.cpu.fuPool.FUList5.opList19]
 384 type=OpDesc
 385 issueLat=1
 386 opClass=SimdFloatSqrt
 387 opLat=1
 388
 389 [system.cpu.fuPool.FUList6]
 390 type=FUDesc
 391 children=opList
 392 count=0
 393 opList=system.cpu.fuPool.FUList6.opList
 394
 395 [system.cpu.fuPool.FUList6.opList]
 396 type=OpDesc
 397 issueLat=1
 398 opClass=MemWrite
 399 opLat=1
 400
 401 [system.cpu.fuPool.FUList7]
 402 type=FUDesc
 403 children=opList0 opList1
 404 count=4
 405 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
 406
 407 [system.cpu.fuPool.FUList7.opList0]
 408 type=OpDesc
 409 issueLat=1
 410 opClass=MemRead
 411 opLat=1
 412
 413 [system.cpu.fuPool.FUList7.opList1]
 414 type=OpDesc
 415 issueLat=1
 416 opClass=MemWrite
 417 opLat=1
 418
 419 [system.cpu.fuPool.FUList8]
 420 type=FUDesc
 421 children=opList
 422 count=1
 423 opList=system.cpu.fuPool.FUList8.opList
 424
 425 [system.cpu.fuPool.FUList8.opList]
 426 type=OpDesc
 427 issueLat=3
 428 opClass=IprAccess
 429 opLat=3
 430
 431 [system.cpu.icache]
 432 type=BaseCache
 433 addr_ranges=0:18446744073709551615
 434 assoc=2
 435 block_size=64
 436 clock=500
 437 forward_snoops=true
 438 hit_latency=2
 439 is_top_level=true
 440 max_miss_count=0
 441 mshrs=4
 442 prefetch_on_access=false
 443 prefetcher=Null
 444 response_latency=2
 445 size=131072
 446 system=system
 447 tgts_per_mshr=20
 448 two_queue=false
 449 write_buffers=8
 450 cpu_side=system.cpu.icache_port
 451 mem_side=system.cpu.toL2Bus.slave[0]
 452
 453 [system.cpu.interrupts]
 454 type=X86LocalApic
 455 clock=500
 456 int_latency=1000
 457 pio_addr=2305843009213693952
 458 pio_latency=100000
 459 system=system
 460 int_master=system.membus.slave[2]
 461 int_slave=system.membus.master[2]
 462 pio=system.membus.master[1]
 463
 464 [system.cpu.isa]
 465 type=X86ISA
 466
 467 [system.cpu.itb]
 468 type=X86TLB
 469 children=walker
 470 size=64
 471 walker=system.cpu.itb.walker
 472
 473 [system.cpu.itb.walker]
 474 type=X86PagetableWalker
 475 clock=500
 476 system=system
 477 port=system.cpu.toL2Bus.slave[2]
 478
 479 [system.cpu.l2cache]
 480 type=BaseCache
 481 addr_ranges=0:18446744073709551615
 482 assoc=8
 483 block_size=64
 484 clock=500
 485 forward_snoops=true
 486 hit_latency=20
 487 is_top_level=false
 488 max_miss_count=0
 489 mshrs=20
 490 prefetch_on_access=false
 491 prefetcher=Null
 492 response_latency=20
 493 size=2097152
 494 system=system
 495 tgts_per_mshr=12
 496 two_queue=false
 497 write_buffers=8
 498 cpu_side=system.cpu.toL2Bus.master[0]
 499 mem_side=system.membus.slave[1]
 500
 501 [system.cpu.toL2Bus]
 502 type=CoherentBus
 503 block_size=64
 504 clock=500
 505 header_cycles=1
 506 use_default_range=false
 507 width=32
 508 master=system.cpu.l2cache.cpu_side
 509 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
 510
 511 [system.cpu.tracer]
 512 type=ExeTracer
 513
 514 [system.cpu.workload]
 515 type=LiveProcess
 516 cmd=gzip input.log 1
 517 cwd=build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing
 518 egid=100
 519 env=
 520 errout=cerr
 521 euid=100
 522 executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/gzip
 523 gid=100
 524 input=cin
 525 max_stack_size=67108864
 526 output=cout
 527 pid=100
 528 ppid=99
 529 simpoint=0
 530 system=system
 531 uid=100
 532
 533 [system.membus]
 534 type=CoherentBus
 535 block_size=64
 536 clock=1000
 537 header_cycles=1
 538 use_default_range=false
 539 width=8
 540 master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave
 541 slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
 542
 543 [system.physmem]
 544 type=SimpleDRAM
 545 addr_mapping=openmap
 546 banks_per_rank=8
 547 clock=1000
 548 conf_table_reported=false
 549 in_addr_map=true
 550 lines_per_rowbuffer=64
 551 mem_sched_policy=fcfs
 552 null=false
 553 page_policy=open
 554 range=0:134217727
 555 ranks_per_channel=2
 556 read_buffer_size=32
 557 tBURST=4000
 558 tCL=14000
 559 tRCD=14000
 560 tREFI=7800000
 561 tRFC=300000
 562 tRP=14000
 563 tWTR=1000
 564 write_buffer_size=32
 565 write_thresh_perc=70
 566 zero=false
 567 port=system.membus.master[0]
 568