2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.636988 # Number of seconds simulated
4 sim_ticks 636988382500 # Number of ticks simulated
5 final_tick 636988382500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 47331 # Simulator instruction rate (inst/s)
8 host_op_rate 87209 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 34259348 # Simulator tick rate (ticks/s)
10 host_mem_usage 276376 # Number of bytes of host memory used
11 host_seconds 18593.13 # Real time elapsed on the host
12 sim_insts 880025312 # Number of instructions simulated
13 sim_ops 1621493982 # Number of ops (including micro ops) simulated
14 system.physmem.bytes_read 5834048 # Number of bytes read from this memory
15 system.physmem.bytes_inst_read 59200 # Number of instructions bytes read from this memory
16 system.physmem.bytes_written 3731712 # Number of bytes written to this memory
17 system.physmem.num_reads 91157 # Number of read requests responded to by this memory
18 system.physmem.num_writes 58308 # Number of write requests responded to by this memory
19 system.physmem.num_other 0 # Number of other requests responded to by this memory
20 system.physmem.bw_read 9158798 # Total read bandwidth from this memory (bytes/s)
21 system.physmem.bw_inst_read 92937 # Instruction read bandwidth from this memory (bytes/s)
22 system.physmem.bw_write 5858367 # Write bandwidth from this memory (bytes/s)
23 system.physmem.bw_total 15017166 # Total bandwidth to/from this memory (bytes/s)
24 system.cpu.workload.num_syscalls 48 # Number of system calls
25 system.cpu.numCycles 1273976766 # number of cpu cycles simulated
26 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
27 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
28 system.cpu.BPredUnit.lookups 154678064 # Number of BP lookups
29 system.cpu.BPredUnit.condPredicted 154678064 # Number of conditional branches predicted
30 system.cpu.BPredUnit.condIncorrect 26667110 # Number of conditional branches incorrect
31 system.cpu.BPredUnit.BTBLookups 77406078 # Number of BTB lookups
32 system.cpu.BPredUnit.BTBHits 77035710 # Number of BTB hits
33 system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
34 system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
35 system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
36 system.cpu.fetch.icacheStallCycles 180711057 # Number of cycles fetch is stalled on an Icache miss
37 system.cpu.fetch.Insts 1490230522 # Number of instructions fetch has processed
38 system.cpu.fetch.Branches 154678064 # Number of branches that fetch encountered
39 system.cpu.fetch.predictedBranches 77035710 # Number of branches that fetch has predicted taken
40 system.cpu.fetch.Cycles 402278451 # Number of cycles fetch has run and was not squashing or blocked
41 system.cpu.fetch.SquashCycles 93695646 # Number of cycles fetch has spent squashing
42 system.cpu.fetch.BlockedCycles 624053491 # Number of cycles fetch has spent blocked
43 system.cpu.fetch.MiscStallCycles 174 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
44 system.cpu.fetch.PendingTrapStallCycles 1298 # Number of stall cycles due to pending traps
45 system.cpu.fetch.CacheLines 186830267 # Number of cache lines fetched
46 system.cpu.fetch.IcacheSquashes 9529255 # Number of outstanding Icache misses that were squashed
47 system.cpu.fetch.rateDist::samples 1273914012 # Number of instructions fetched each cycle (Total)
48 system.cpu.fetch.rateDist::mean 1.999814 # Number of instructions fetched each cycle (Total)
49 system.cpu.fetch.rateDist::stdev 3.235188 # Number of instructions fetched each cycle (Total)
50 system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
51 system.cpu.fetch.rateDist::0 878853214 68.99% 68.99% # Number of instructions fetched each cycle (Total)
52 system.cpu.fetch.rateDist::1 24303546 1.91% 70.90% # Number of instructions fetched each cycle (Total)
53 system.cpu.fetch.rateDist::2 15677834 1.23% 72.13% # Number of instructions fetched each cycle (Total)
54 system.cpu.fetch.rateDist::3 17928928 1.41% 73.53% # Number of instructions fetched each cycle (Total)
55 system.cpu.fetch.rateDist::4 26735770 2.10% 75.63% # Number of instructions fetched each cycle (Total)
56 system.cpu.fetch.rateDist::5 18262172 1.43% 77.07% # Number of instructions fetched each cycle (Total)
57 system.cpu.fetch.rateDist::6 28765750 2.26% 79.32% # Number of instructions fetched each cycle (Total)
58 system.cpu.fetch.rateDist::7 39797773 3.12% 82.45% # Number of instructions fetched each cycle (Total)
59 system.cpu.fetch.rateDist::8 223589025 17.55% 100.00% # Number of instructions fetched each cycle (Total)
60 system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
61 system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
62 system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
63 system.cpu.fetch.rateDist::total 1273914012 # Number of instructions fetched each cycle (Total)
64 system.cpu.fetch.branchRate 0.121414 # Number of branch fetches per cycle
65 system.cpu.fetch.rate 1.169747 # Number of inst fetches per cycle
66 system.cpu.decode.IdleCycles 300082895 # Number of cycles decode is idle
67 system.cpu.decode.BlockedCycles 537078967 # Number of cycles decode is blocked
68 system.cpu.decode.RunCycles 281798821 # Number of cycles decode is running
69 system.cpu.decode.UnblockCycles 88083788 # Number of cycles decode is unblocking
70 system.cpu.decode.SquashCycles 66869541 # Number of cycles decode is squashing
71 system.cpu.decode.DecodedInsts 2368899404 # Number of instructions handled by decode
72 system.cpu.rename.SquashCycles 66869541 # Number of cycles rename is squashing
73 system.cpu.rename.IdleCycles 352603459 # Number of cycles rename is idle
74 system.cpu.rename.BlockCycles 124071504 # Number of cycles rename is blocking
75 system.cpu.rename.serializeStallCycles 2838 # count of cycles rename stalled for serializing inst
76 system.cpu.rename.RunCycles 302490800 # Number of cycles rename is running
77 system.cpu.rename.UnblockCycles 427875870 # Number of cycles rename is unblocking
78 system.cpu.rename.RenamedInsts 2273771459 # Number of instructions processed by rename
79 system.cpu.rename.ROBFullEvents 200 # Number of times rename has blocked due to ROB full
80 system.cpu.rename.IQFullEvents 293326885 # Number of times rename has blocked due to IQ full
81 system.cpu.rename.LSQFullEvents 103161675 # Number of times rename has blocked due to LSQ full
82 system.cpu.rename.FullRegisterEvents 640 # Number of times there has been no free registers
83 system.cpu.rename.RenamedOperands 3463149697 # Number of destination operands rename has renamed
84 system.cpu.rename.RenameLookups 7120628186 # Number of register rename lookups that rename has made
85 system.cpu.rename.int_rename_lookups 7120621006 # Number of integer rename lookups
86 system.cpu.rename.fp_rename_lookups 7180 # Number of floating rename lookups
87 system.cpu.rename.CommittedMaps 2493860970 # Number of HB maps that are committed
88 system.cpu.rename.UndoneMaps 969288727 # Number of HB maps that are undone due to squashing
89 system.cpu.rename.serializingInsts 110 # count of serializing insts renamed
90 system.cpu.rename.tempSerializingInsts 110 # count of temporary serializing insts renamed
91 system.cpu.rename.skidInsts 746079760 # count of insts added to the skid buffer
92 system.cpu.memDep0.insertedLoads 546341437 # Number of loads inserted to the mem dependence unit.
93 system.cpu.memDep0.insertedStores 222247757 # Number of stores inserted to the mem dependence unit.
94 system.cpu.memDep0.conflictingLoads 352469730 # Number of conflicting loads.
95 system.cpu.memDep0.conflictingStores 147023702 # Number of conflicting stores.
96 system.cpu.iq.iqInstsAdded 2027529381 # Number of instructions added to the IQ (excludes non-spec)
97 system.cpu.iq.iqNonSpecInstsAdded 546 # Number of non-speculative instructions added to the IQ
98 system.cpu.iq.iqInstsIssued 1785574895 # Number of instructions issued
99 system.cpu.iq.iqSquashedInstsIssued 118982 # Number of squashed instructions issued
100 system.cpu.iq.iqSquashedInstsExamined 405869160 # Number of squashed instructions iterated over during squash; mainly for profiling
101 system.cpu.iq.iqSquashedOperandsExamined 1051620727 # Number of squashed operands that are examined and possibly removed from graph
102 system.cpu.iq.iqSquashedNonSpecRemoved 496 # Number of squashed non-spec instructions that were removed
103 system.cpu.iq.issued_per_cycle::samples 1273914012 # Number of insts issued each cycle
104 system.cpu.iq.issued_per_cycle::mean 1.401645 # Number of insts issued each cycle
105 system.cpu.iq.issued_per_cycle::stdev 1.311838 # Number of insts issued each cycle
106 system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
107 system.cpu.iq.issued_per_cycle::0 347011243 27.24% 27.24% # Number of insts issued each cycle
108 system.cpu.iq.issued_per_cycle::1 447440187 35.12% 62.36% # Number of insts issued each cycle
109 system.cpu.iq.issued_per_cycle::2 243114047 19.08% 81.45% # Number of insts issued each cycle
110 system.cpu.iq.issued_per_cycle::3 151317630 11.88% 93.33% # Number of insts issued each cycle
111 system.cpu.iq.issued_per_cycle::4 40944695 3.21% 96.54% # Number of insts issued each cycle
112 system.cpu.iq.issued_per_cycle::5 32410749 2.54% 99.08% # Number of insts issued each cycle
113 system.cpu.iq.issued_per_cycle::6 9957171 0.78% 99.87% # Number of insts issued each cycle
114 system.cpu.iq.issued_per_cycle::7 1368147 0.11% 99.97% # Number of insts issued each cycle
115 system.cpu.iq.issued_per_cycle::8 350143 0.03% 100.00% # Number of insts issued each cycle
116 system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
117 system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
118 system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
119 system.cpu.iq.issued_per_cycle::total 1273914012 # Number of insts issued each cycle
120 system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
121 system.cpu.iq.fu_full::IntAlu 237387 9.29% 9.29% # attempts to use FU when none available
122 system.cpu.iq.fu_full::IntMult 0 0.00% 9.29% # attempts to use FU when none available
123 system.cpu.iq.fu_full::IntDiv 0 0.00% 9.29% # attempts to use FU when none available
124 system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.29% # attempts to use FU when none available
125 system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.29% # attempts to use FU when none available
126 system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.29% # attempts to use FU when none available
127 system.cpu.iq.fu_full::FloatMult 0 0.00% 9.29% # attempts to use FU when none available
128 system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.29% # attempts to use FU when none available
129 system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.29% # attempts to use FU when none available
130 system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.29% # attempts to use FU when none available
131 system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.29% # attempts to use FU when none available
132 system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.29% # attempts to use FU when none available
133 system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.29% # attempts to use FU when none available
134 system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.29% # attempts to use FU when none available
135 system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.29% # attempts to use FU when none available
136 system.cpu.iq.fu_full::SimdMult 0 0.00% 9.29% # attempts to use FU when none available
137 system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.29% # attempts to use FU when none available
138 system.cpu.iq.fu_full::SimdShift 0 0.00% 9.29% # attempts to use FU when none available
139 system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.29% # attempts to use FU when none available
140 system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.29% # attempts to use FU when none available
141 system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.29% # attempts to use FU when none available
142 system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.29% # attempts to use FU when none available
143 system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.29% # attempts to use FU when none available
144 system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.29% # attempts to use FU when none available
145 system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.29% # attempts to use FU when none available
146 system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.29% # attempts to use FU when none available
147 system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.29% # attempts to use FU when none available
148 system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.29% # attempts to use FU when none available
149 system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.29% # attempts to use FU when none available
150 system.cpu.iq.fu_full::MemRead 2138623 83.73% 93.02% # attempts to use FU when none available
151 system.cpu.iq.fu_full::MemWrite 178205 6.98% 100.00% # attempts to use FU when none available
152 system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
153 system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
154 system.cpu.iq.FU_type_0::No_OpClass 46809715 2.62% 2.62% # Type of FU issued
155 system.cpu.iq.FU_type_0::IntAlu 1066790690 59.74% 62.37% # Type of FU issued
156 system.cpu.iq.FU_type_0::IntMult 0 0.00% 62.37% # Type of FU issued
157 system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.37% # Type of FU issued
158 system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.37% # Type of FU issued
159 system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.37% # Type of FU issued
160 system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.37% # Type of FU issued
161 system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.37% # Type of FU issued
162 system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.37% # Type of FU issued
163 system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.37% # Type of FU issued
164 system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.37% # Type of FU issued
165 system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.37% # Type of FU issued
166 system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.37% # Type of FU issued
167 system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.37% # Type of FU issued
168 system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.37% # Type of FU issued
169 system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.37% # Type of FU issued
170 system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.37% # Type of FU issued
171 system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.37% # Type of FU issued
172 system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.37% # Type of FU issued
173 system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.37% # Type of FU issued
174 system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.37% # Type of FU issued
175 system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.37% # Type of FU issued
176 system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.37% # Type of FU issued
177 system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.37% # Type of FU issued
178 system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.37% # Type of FU issued
179 system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.37% # Type of FU issued
180 system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.37% # Type of FU issued
181 system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.37% # Type of FU issued
182 system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.37% # Type of FU issued
183 system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.37% # Type of FU issued
184 system.cpu.iq.FU_type_0::MemRead 479501542 26.85% 89.22% # Type of FU issued
185 system.cpu.iq.FU_type_0::MemWrite 192472948 10.78% 100.00% # Type of FU issued
186 system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
187 system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
188 system.cpu.iq.FU_type_0::total 1785574895 # Type of FU issued
189 system.cpu.iq.rate 1.401576 # Inst issue rate
190 system.cpu.iq.fu_busy_cnt 2554215 # FU busy when requested
191 system.cpu.iq.fu_busy_rate 0.001430 # FU busy rate (busy events/executed inst)
192 system.cpu.iq.int_inst_queue_reads 4847736227 # Number of integer instruction queue reads
193 system.cpu.iq.int_inst_queue_writes 2433580235 # Number of integer instruction queue writes
194 system.cpu.iq.int_inst_queue_wakeup_accesses 1726806271 # Number of integer instruction queue wakeup accesses
195 system.cpu.iq.fp_inst_queue_reads 772 # Number of floating instruction queue reads
196 system.cpu.iq.fp_inst_queue_writes 2168 # Number of floating instruction queue writes
197 system.cpu.iq.fp_inst_queue_wakeup_accesses 84 # Number of floating instruction queue wakeup accesses
198 system.cpu.iq.int_alu_accesses 1741319146 # Number of integer alu accesses
199 system.cpu.iq.fp_alu_accesses 249 # Number of floating point alu accesses
200 system.cpu.iew.lsq.thread0.forwLoads 208956586 # Number of loads that had data forwarded from stores
201 system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
202 system.cpu.iew.lsq.thread0.squashedLoads 127299312 # Number of loads squashed
203 system.cpu.iew.lsq.thread0.ignoredResponses 36681 # Number of memory responses ignored because the instruction is squashed
204 system.cpu.iew.lsq.thread0.memOrderViolation 190307 # Number of memory ordering violations
205 system.cpu.iew.lsq.thread0.squashedStores 34061700 # Number of stores squashed
206 system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
207 system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
208 system.cpu.iew.lsq.thread0.rescheduledLoads 1845 # Number of loads that were rescheduled
209 system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
210 system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
211 system.cpu.iew.iewSquashCycles 66869541 # Number of cycles IEW is squashing
212 system.cpu.iew.iewBlockCycles 356934 # Number of cycles IEW is blocking
213 system.cpu.iew.iewUnblockCycles 88692 # Number of cycles IEW is unblocking
214 system.cpu.iew.iewDispatchedInsts 2027529927 # Number of instructions dispatched to IQ
215 system.cpu.iew.iewDispSquashedInsts 63849570 # Number of squashed instructions skipped by dispatch
216 system.cpu.iew.iewDispLoadInsts 546341437 # Number of dispatched load instructions
217 system.cpu.iew.iewDispStoreInsts 222247757 # Number of dispatched store instructions
218 system.cpu.iew.iewDispNonSpecInsts 103 # Number of dispatched non-speculative instructions
219 system.cpu.iew.iewIQFullEvents 48888 # Number of times the IQ has become full, causing a stall
220 system.cpu.iew.iewLSQFullEvents 421 # Number of times the LSQ has become full, causing a stall
221 system.cpu.iew.memOrderViolationEvents 190307 # Number of memory order violations
222 system.cpu.iew.predictedTakenIncorrect 2139656 # Number of branches that were predicted taken incorrectly
223 system.cpu.iew.predictedNotTakenIncorrect 24653796 # Number of branches that were predicted not taken incorrectly
224 system.cpu.iew.branchMispredicts 26793452 # Number of branch mispredicts detected at execute
225 system.cpu.iew.iewExecutedInsts 1767588629 # Number of executed instructions
226 system.cpu.iew.iewExecLoadInsts 473898164 # Number of load instructions executed
227 system.cpu.iew.iewExecSquashedInsts 17986266 # Number of squashed instructions skipped in execute
228 system.cpu.iew.exec_swp 0 # number of swp insts executed
229 system.cpu.iew.exec_nop 0 # number of nop insts executed
230 system.cpu.iew.exec_refs 665742013 # number of memory reference insts executed
231 system.cpu.iew.exec_branches 109684623 # Number of branches executed
232 system.cpu.iew.exec_stores 191843849 # Number of stores executed
233 system.cpu.iew.exec_rate 1.387458 # Inst execution rate
234 system.cpu.iew.wb_sent 1728148485 # cumulative count of insts sent to commit
235 system.cpu.iew.wb_count 1726806355 # cumulative count of insts written-back
236 system.cpu.iew.wb_producers 1262041827 # num instructions producing a value
237 system.cpu.iew.wb_consumers 2984894242 # num instructions consuming a value
238 system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
239 system.cpu.iew.wb_rate 1.355446 # insts written-back per cycle
240 system.cpu.iew.wb_fanout 0.422810 # average fanout of values written-back
241 system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
242 system.cpu.commit.commitCommittedInsts 880025312 # The number of committed instructions
243 system.cpu.commit.commitCommittedOps 1621493982 # The number of committed instructions
244 system.cpu.commit.commitSquashedInsts 406040141 # The number of squashed insts skipped by commit
245 system.cpu.commit.commitNonSpecStalls 50 # The number of times commit has been forced to stall to communicate backwards
246 system.cpu.commit.branchMispredicts 26667277 # The number of times a branch was mispredicted
247 system.cpu.commit.committed_per_cycle::samples 1207044471 # Number of insts commited each cycle
248 system.cpu.commit.committed_per_cycle::mean 1.343359 # Number of insts commited each cycle
249 system.cpu.commit.committed_per_cycle::stdev 1.660546 # Number of insts commited each cycle
250 system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
251 system.cpu.commit.committed_per_cycle::0 437250010 36.22% 36.22% # Number of insts commited each cycle
252 system.cpu.commit.committed_per_cycle::1 432641487 35.84% 72.07% # Number of insts commited each cycle
253 system.cpu.commit.committed_per_cycle::2 93464877 7.74% 79.81% # Number of insts commited each cycle
254 system.cpu.commit.committed_per_cycle::3 134893392 11.18% 90.99% # Number of insts commited each cycle
255 system.cpu.commit.committed_per_cycle::4 35716518 2.96% 93.95% # Number of insts commited each cycle
256 system.cpu.commit.committed_per_cycle::5 23306370 1.93% 95.88% # Number of insts commited each cycle
257 system.cpu.commit.committed_per_cycle::6 25727632 2.13% 98.01% # Number of insts commited each cycle
258 system.cpu.commit.committed_per_cycle::7 8874629 0.74% 98.74% # Number of insts commited each cycle
259 system.cpu.commit.committed_per_cycle::8 15169556 1.26% 100.00% # Number of insts commited each cycle
260 system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
261 system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
262 system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
263 system.cpu.commit.committed_per_cycle::total 1207044471 # Number of insts commited each cycle
264 system.cpu.commit.committedInsts 880025312 # Number of instructions committed
265 system.cpu.commit.committedOps 1621493982 # Number of ops (including micro ops) committed
266 system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
267 system.cpu.commit.refs 607228182 # Number of memory references committed
268 system.cpu.commit.loads 419042125 # Number of loads committed
269 system.cpu.commit.membars 0 # Number of memory barriers committed
270 system.cpu.commit.branches 107161579 # Number of branches committed
271 system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
272 system.cpu.commit.int_insts 1621354492 # Number of committed integer instructions.
273 system.cpu.commit.function_calls 0 # Number of function calls committed.
274 system.cpu.commit.bw_lim_events 15169556 # number cycles where commit BW limit reached
275 system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
276 system.cpu.rob.rob_reads 3219409038 # The number of ROB reads
277 system.cpu.rob.rob_writes 4121954747 # The number of ROB writes
278 system.cpu.timesIdled 1354 # Number of times that the entire CPU went into an idle state and unscheduled itself
279 system.cpu.idleCycles 62754 # Total number of cycles that the CPU has spent unscheduled due to idling
280 system.cpu.committedInsts 880025312 # Number of Instructions Simulated
281 system.cpu.committedOps 1621493982 # Number of Ops (including micro ops) Simulated
282 system.cpu.committedInsts_total 880025312 # Number of Instructions Simulated
283 system.cpu.cpi 1.447659 # CPI: Cycles Per Instruction
284 system.cpu.cpi_total 1.447659 # CPI: Total CPI of All Threads
285 system.cpu.ipc 0.690770 # IPC: Instructions Per Cycle
286 system.cpu.ipc_total 0.690770 # IPC: Total IPC of All Threads
287 system.cpu.int_regfile_reads 4473469244 # number of integer regfile reads
288 system.cpu.int_regfile_writes 2589680881 # number of integer regfile writes
289 system.cpu.fp_regfile_reads 84 # number of floating regfile reads
290 system.cpu.misc_regfile_reads 911429698 # number of misc regfile reads
291 system.cpu.icache.replacements 22 # number of replacements
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293 system.cpu.icache.total_refs 186828876 # Total number of references to valid blocks.
294 system.cpu.icache.sampled_refs 928 # Sample count of references to valid blocks.
295 system.cpu.icache.avg_refs 201324.219828 # Average number of references to valid blocks.
296 system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
297 system.cpu.icache.occ_blocks::cpu.inst 827.099302 # Average occupied blocks per requestor
298 system.cpu.icache.occ_percent::cpu.inst 0.403857 # Average percentage of cache occupancy
299 system.cpu.icache.occ_percent::total 0.403857 # Average percentage of cache occupancy
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303 system.cpu.icache.demand_hits::total 186828882 # number of demand (read+write) hits
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305 system.cpu.icache.overall_hits::total 186828882 # number of overall hits
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307 system.cpu.icache.ReadReq_misses::total 1385 # number of ReadReq misses
308 system.cpu.icache.demand_misses::cpu.inst 1385 # number of demand (read+write) misses
309 system.cpu.icache.demand_misses::total 1385 # number of demand (read+write) misses
310 system.cpu.icache.overall_misses::cpu.inst 1385 # number of overall misses
311 system.cpu.icache.overall_misses::total 1385 # number of overall misses
312 system.cpu.icache.ReadReq_miss_latency::cpu.inst 46636000 # number of ReadReq miss cycles
313 system.cpu.icache.ReadReq_miss_latency::total 46636000 # number of ReadReq miss cycles
314 system.cpu.icache.demand_miss_latency::cpu.inst 46636000 # number of demand (read+write) miss cycles
315 system.cpu.icache.demand_miss_latency::total 46636000 # number of demand (read+write) miss cycles
316 system.cpu.icache.overall_miss_latency::cpu.inst 46636000 # number of overall miss cycles
317 system.cpu.icache.overall_miss_latency::total 46636000 # number of overall miss cycles
318 system.cpu.icache.ReadReq_accesses::cpu.inst 186830267 # number of ReadReq accesses(hits+misses)
319 system.cpu.icache.ReadReq_accesses::total 186830267 # number of ReadReq accesses(hits+misses)
320 system.cpu.icache.demand_accesses::cpu.inst 186830267 # number of demand (read+write) accesses
321 system.cpu.icache.demand_accesses::total 186830267 # number of demand (read+write) accesses
322 system.cpu.icache.overall_accesses::cpu.inst 186830267 # number of overall (read+write) accesses
323 system.cpu.icache.overall_accesses::total 186830267 # number of overall (read+write) accesses
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325 system.cpu.icache.demand_miss_rate::cpu.inst 0.000007 # miss rate for demand accesses
326 system.cpu.icache.overall_miss_rate::cpu.inst 0.000007 # miss rate for overall accesses
327 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 33672.202166 # average ReadReq miss latency
328 system.cpu.icache.demand_avg_miss_latency::cpu.inst 33672.202166 # average overall miss latency
329 system.cpu.icache.overall_avg_miss_latency::cpu.inst 33672.202166 # average overall miss latency
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340 system.cpu.icache.demand_mshr_hits::cpu.inst 450 # number of demand (read+write) MSHR hits
341 system.cpu.icache.demand_mshr_hits::total 450 # number of demand (read+write) MSHR hits
342 system.cpu.icache.overall_mshr_hits::cpu.inst 450 # number of overall MSHR hits
343 system.cpu.icache.overall_mshr_hits::total 450 # number of overall MSHR hits
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345 system.cpu.icache.ReadReq_mshr_misses::total 935 # number of ReadReq MSHR misses
346 system.cpu.icache.demand_mshr_misses::cpu.inst 935 # number of demand (read+write) MSHR misses
347 system.cpu.icache.demand_mshr_misses::total 935 # number of demand (read+write) MSHR misses
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349 system.cpu.icache.overall_mshr_misses::total 935 # number of overall MSHR misses
350 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 32805000 # number of ReadReq MSHR miss cycles
351 system.cpu.icache.ReadReq_mshr_miss_latency::total 32805000 # number of ReadReq MSHR miss cycles
352 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 32805000 # number of demand (read+write) MSHR miss cycles
353 system.cpu.icache.demand_mshr_miss_latency::total 32805000 # number of demand (read+write) MSHR miss cycles
354 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 32805000 # number of overall MSHR miss cycles
355 system.cpu.icache.overall_mshr_miss_latency::total 32805000 # number of overall MSHR miss cycles
356 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for ReadReq accesses
357 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for demand accesses
358 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for overall accesses
359 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35085.561497 # average ReadReq mshr miss latency
360 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35085.561497 # average overall mshr miss latency
361 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35085.561497 # average overall mshr miss latency
362 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
363 system.cpu.dcache.replacements 445407 # number of replacements
364 system.cpu.dcache.tagsinuse 4093.514636 # Cycle average of tags in use
365 system.cpu.dcache.total_refs 452671406 # Total number of references to valid blocks.
366 system.cpu.dcache.sampled_refs 449503 # Sample count of references to valid blocks.
367 system.cpu.dcache.avg_refs 1007.048687 # Average number of references to valid blocks.
368 system.cpu.dcache.warmup_cycle 723816000 # Cycle when the warmup percentage was hit.
369 system.cpu.dcache.occ_blocks::cpu.data 4093.514636 # Average occupied blocks per requestor
370 system.cpu.dcache.occ_percent::cpu.data 0.999393 # Average percentage of cache occupancy
371 system.cpu.dcache.occ_percent::total 0.999393 # Average percentage of cache occupancy
372 system.cpu.dcache.ReadReq_hits::cpu.data 264731564 # number of ReadReq hits
373 system.cpu.dcache.ReadReq_hits::total 264731564 # number of ReadReq hits
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375 system.cpu.dcache.WriteReq_hits::total 187939830 # number of WriteReq hits
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377 system.cpu.dcache.demand_hits::total 452671394 # number of demand (read+write) hits
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379 system.cpu.dcache.overall_hits::total 452671394 # number of overall hits
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381 system.cpu.dcache.ReadReq_misses::total 206744 # number of ReadReq misses
382 system.cpu.dcache.WriteReq_misses::cpu.data 246227 # number of WriteReq misses
383 system.cpu.dcache.WriteReq_misses::total 246227 # number of WriteReq misses
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385 system.cpu.dcache.demand_misses::total 452971 # number of demand (read+write) misses
386 system.cpu.dcache.overall_misses::cpu.data 452971 # number of overall misses
387 system.cpu.dcache.overall_misses::total 452971 # number of overall misses
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389 system.cpu.dcache.ReadReq_miss_latency::total 2148724000 # number of ReadReq miss cycles
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391 system.cpu.dcache.WriteReq_miss_latency::total 3224322500 # number of WriteReq miss cycles
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393 system.cpu.dcache.demand_miss_latency::total 5373046500 # number of demand (read+write) miss cycles
394 system.cpu.dcache.overall_miss_latency::cpu.data 5373046500 # number of overall miss cycles
395 system.cpu.dcache.overall_miss_latency::total 5373046500 # number of overall miss cycles
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397 system.cpu.dcache.ReadReq_accesses::total 264938308 # number of ReadReq accesses(hits+misses)
398 system.cpu.dcache.WriteReq_accesses::cpu.data 188186057 # number of WriteReq accesses(hits+misses)
399 system.cpu.dcache.WriteReq_accesses::total 188186057 # number of WriteReq accesses(hits+misses)
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403 system.cpu.dcache.overall_accesses::total 453124365 # number of overall (read+write) accesses
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405 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001308 # miss rate for WriteReq accesses
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407 system.cpu.dcache.overall_miss_rate::cpu.data 0.001000 # miss rate for overall accesses
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409 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 13094.918510 # average WriteReq miss latency
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411 system.cpu.dcache.overall_avg_miss_latency::cpu.data 11861.789165 # average overall miss latency
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417 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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423 system.cpu.dcache.ReadReq_mshr_hits::total 3434 # number of ReadReq MSHR hits
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427 system.cpu.dcache.demand_mshr_hits::total 3459 # number of demand (read+write) MSHR hits
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429 system.cpu.dcache.overall_mshr_hits::total 3459 # number of overall MSHR hits
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431 system.cpu.dcache.ReadReq_mshr_misses::total 203310 # number of ReadReq MSHR misses
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433 system.cpu.dcache.WriteReq_mshr_misses::total 246202 # number of WriteReq MSHR misses
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435 system.cpu.dcache.demand_mshr_misses::total 449512 # number of demand (read+write) MSHR misses
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437 system.cpu.dcache.overall_mshr_misses::total 449512 # number of overall MSHR misses
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439 system.cpu.dcache.ReadReq_mshr_miss_latency::total 1511006000 # number of ReadReq MSHR miss cycles
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441 system.cpu.dcache.WriteReq_mshr_miss_latency::total 2485166000 # number of WriteReq MSHR miss cycles
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445 system.cpu.dcache.overall_mshr_miss_latency::total 3996172000 # number of overall MSHR miss cycles
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447 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001308 # mshr miss rate for WriteReq accesses
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449 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000992 # mshr miss rate for overall accesses
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451 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10094.012234 # average WriteReq mshr miss latency
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453 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8890.022958 # average overall mshr miss latency
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455 system.cpu.l2cache.replacements 72883 # number of replacements
456 system.cpu.l2cache.tagsinuse 17779.692577 # Cycle average of tags in use
457 system.cpu.l2cache.total_refs 433456 # Total number of references to valid blocks.
458 system.cpu.l2cache.sampled_refs 88505 # Sample count of references to valid blocks.
459 system.cpu.l2cache.avg_refs 4.897531 # Average number of references to valid blocks.
460 system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
461 system.cpu.l2cache.occ_blocks::writebacks 15879.164577 # Average occupied blocks per requestor
462 system.cpu.l2cache.occ_blocks::cpu.inst 61.338092 # Average occupied blocks per requestor
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469 system.cpu.l2cache.ReadReq_hits::cpu.data 171391 # number of ReadReq hits
470 system.cpu.l2cache.ReadReq_hits::total 171394 # number of ReadReq hits
471 system.cpu.l2cache.Writeback_hits::writebacks 400713 # number of Writeback hits
472 system.cpu.l2cache.Writeback_hits::total 400713 # number of Writeback hits
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474 system.cpu.l2cache.UpgradeReq_hits::total 7 # number of UpgradeReq hits
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476 system.cpu.l2cache.ReadExReq_hits::total 187882 # number of ReadExReq hits
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478 system.cpu.l2cache.demand_hits::cpu.data 359273 # number of demand (read+write) hits
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481 system.cpu.l2cache.overall_hits::cpu.data 359273 # number of overall hits
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487 system.cpu.l2cache.ReadExReq_misses::total 58321 # number of ReadExReq misses
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492 system.cpu.l2cache.overall_misses::cpu.data 90232 # number of overall misses
493 system.cpu.l2cache.overall_misses::total 91157 # number of overall misses
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495 system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1094294500 # number of ReadReq miss cycles
496 system.cpu.l2cache.ReadReq_miss_latency::total 1126002000 # number of ReadReq miss cycles
497 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1998540500 # number of ReadExReq miss cycles
498 system.cpu.l2cache.ReadExReq_miss_latency::total 1998540500 # number of ReadExReq miss cycles
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503 system.cpu.l2cache.overall_miss_latency::cpu.data 3092835000 # number of overall miss cycles
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508 system.cpu.l2cache.Writeback_accesses::writebacks 400713 # number of Writeback accesses(hits+misses)
509 system.cpu.l2cache.Writeback_accesses::total 400713 # number of Writeback accesses(hits+misses)
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522 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.236882 # miss rate for ReadExReq accesses
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527 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34278.378378 # average ReadReq miss latency
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529 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34267.939507 # average ReadExReq miss latency
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536 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
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539 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
540 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
541 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
542 system.cpu.l2cache.writebacks::writebacks 58308 # number of writebacks
543 system.cpu.l2cache.writebacks::total 58308 # number of writebacks
544 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 925 # number of ReadReq MSHR misses
545 system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 31911 # number of ReadReq MSHR misses
546 system.cpu.l2cache.ReadReq_mshr_misses::total 32836 # number of ReadReq MSHR misses
547 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 58321 # number of ReadExReq MSHR misses
548 system.cpu.l2cache.ReadExReq_mshr_misses::total 58321 # number of ReadExReq MSHR misses
549 system.cpu.l2cache.demand_mshr_misses::cpu.inst 925 # number of demand (read+write) MSHR misses
550 system.cpu.l2cache.demand_mshr_misses::cpu.data 90232 # number of demand (read+write) MSHR misses
551 system.cpu.l2cache.demand_mshr_misses::total 91157 # number of demand (read+write) MSHR misses
552 system.cpu.l2cache.overall_mshr_misses::cpu.inst 925 # number of overall MSHR misses
553 system.cpu.l2cache.overall_mshr_misses::cpu.data 90232 # number of overall MSHR misses
554 system.cpu.l2cache.overall_mshr_misses::total 91157 # number of overall MSHR misses
555 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 28735500 # number of ReadReq MSHR miss cycles
556 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 989353500 # number of ReadReq MSHR miss cycles
557 system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1018089000 # number of ReadReq MSHR miss cycles
558 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1807989500 # number of ReadExReq MSHR miss cycles
559 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1807989500 # number of ReadExReq MSHR miss cycles
560 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 28735500 # number of demand (read+write) MSHR miss cycles
561 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 2797343000 # number of demand (read+write) MSHR miss cycles
562 system.cpu.l2cache.demand_mshr_miss_latency::total 2826078500 # number of demand (read+write) MSHR miss cycles
563 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 28735500 # number of overall MSHR miss cycles
564 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2797343000 # number of overall MSHR miss cycles
565 system.cpu.l2cache.overall_mshr_miss_latency::total 2826078500 # number of overall MSHR miss cycles
566 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996767 # mshr miss rate for ReadReq accesses
567 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.156964 # mshr miss rate for ReadReq accesses
568 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.236882 # mshr miss rate for ReadExReq accesses
569 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996767 # mshr miss rate for demand accesses
570 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.200736 # mshr miss rate for demand accesses
571 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996767 # mshr miss rate for overall accesses
572 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.200736 # mshr miss rate for overall accesses
573 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31065.405405 # average ReadReq mshr miss latency
574 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31003.525430 # average ReadReq mshr miss latency
575 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31000.660140 # average ReadExReq mshr miss latency
576 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31065.405405 # average overall mshr miss latency
577 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31001.673464 # average overall mshr miss latency
578 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31065.405405 # average overall mshr miss latency
579 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31001.673464 # average overall mshr miss latency
580 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
582 ---------- End Simulation Statistics ----------
projects / gem5.git / blob