2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 1.800193 # Number of seconds simulated
4 sim_ticks 1800193398000 # Number of ticks simulated
5 final_tick 1800193398000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 392596 # Simulator instruction rate (inst/s)
8 host_op_rate 723379 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 803099848 # Simulator tick rate (ticks/s)
10 host_mem_usage 292568 # Number of bytes of host memory used
11 host_seconds 2241.56 # Real time elapsed on the host
12 sim_insts 880025278 # Number of instructions simulated
13 sim_ops 1621493928 # Number of ops (including micro ops) simulated
14 system.physmem.bytes_read::cpu.inst 46208 # Number of bytes read from this memory
15 system.physmem.bytes_read::cpu.data 1682368 # Number of bytes read from this memory
16 system.physmem.bytes_read::total 1728576 # Number of bytes read from this memory
17 system.physmem.bytes_inst_read::cpu.inst 46208 # Number of instructions bytes read from this memory
18 system.physmem.bytes_inst_read::total 46208 # Number of instructions bytes read from this memory
19 system.physmem.bytes_written::writebacks 160704 # Number of bytes written to this memory
20 system.physmem.bytes_written::total 160704 # Number of bytes written to this memory
21 system.physmem.num_reads::cpu.inst 722 # Number of read requests responded to by this memory
22 system.physmem.num_reads::cpu.data 26287 # Number of read requests responded to by this memory
23 system.physmem.num_reads::total 27009 # Number of read requests responded to by this memory
24 system.physmem.num_writes::writebacks 2511 # Number of write requests responded to by this memory
25 system.physmem.num_writes::total 2511 # Number of write requests responded to by this memory
26 system.physmem.bw_read::cpu.inst 25668 # Total read bandwidth from this memory (bytes/s)
27 system.physmem.bw_read::cpu.data 934548 # Total read bandwidth from this memory (bytes/s)
28 system.physmem.bw_read::total 960217 # Total read bandwidth from this memory (bytes/s)
29 system.physmem.bw_inst_read::cpu.inst 25668 # Instruction read bandwidth from this memory (bytes/s)
30 system.physmem.bw_inst_read::total 25668 # Instruction read bandwidth from this memory (bytes/s)
31 system.physmem.bw_write::writebacks 89270 # Write bandwidth from this memory (bytes/s)
32 system.physmem.bw_write::total 89270 # Write bandwidth from this memory (bytes/s)
33 system.physmem.bw_total::writebacks 89270 # Total bandwidth to/from this memory (bytes/s)
34 system.physmem.bw_total::cpu.inst 25668 # Total bandwidth to/from this memory (bytes/s)
35 system.physmem.bw_total::cpu.data 934548 # Total bandwidth to/from this memory (bytes/s)
36 system.physmem.bw_total::total 1049487 # Total bandwidth to/from this memory (bytes/s)
37 system.cpu.workload.num_syscalls 48 # Number of system calls
38 system.cpu.numCycles 3600386796 # number of cpu cycles simulated
39 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
40 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
41 system.cpu.committedInsts 880025278 # Number of instructions committed
42 system.cpu.committedOps 1621493928 # Number of ops (including micro ops) committed
43 system.cpu.num_int_alu_accesses 1621354440 # Number of integer alu accesses
44 system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
45 system.cpu.num_func_calls 0 # number of times a function call or return occured
46 system.cpu.num_conditional_control_insts 99478856 # number of instructions that are conditional controls
47 system.cpu.num_int_insts 1621354440 # number of integer instructions
48 system.cpu.num_fp_insts 0 # number of float instructions
49 system.cpu.num_int_register_reads 4204103517 # number of times the integer registers were read
50 system.cpu.num_int_register_writes 1886895260 # number of times the integer registers were written
51 system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
52 system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
53 system.cpu.num_mem_refs 607228180 # number of memory refs
54 system.cpu.num_load_insts 419042122 # Number of load instructions
55 system.cpu.num_store_insts 188186058 # Number of store instructions
56 system.cpu.num_idle_cycles 0 # Number of idle cycles
57 system.cpu.num_busy_cycles 3600386796 # Number of busy cycles
58 system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
59 system.cpu.idle_fraction 0 # Percentage of idle cycles
60 system.cpu.icache.replacements 4 # number of replacements
61 system.cpu.icache.tagsinuse 660.197305 # Cycle average of tags in use
62 system.cpu.icache.total_refs 1186515974 # Total number of references to valid blocks.
63 system.cpu.icache.sampled_refs 722 # Sample count of references to valid blocks.
64 system.cpu.icache.avg_refs 1643373.925208 # Average number of references to valid blocks.
65 system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
66 system.cpu.icache.occ_blocks::cpu.inst 660.197305 # Average occupied blocks per requestor
67 system.cpu.icache.occ_percent::cpu.inst 0.322362 # Average percentage of cache occupancy
68 system.cpu.icache.occ_percent::total 0.322362 # Average percentage of cache occupancy
69 system.cpu.icache.ReadReq_hits::cpu.inst 1186515974 # number of ReadReq hits
70 system.cpu.icache.ReadReq_hits::total 1186515974 # number of ReadReq hits
71 system.cpu.icache.demand_hits::cpu.inst 1186515974 # number of demand (read+write) hits
72 system.cpu.icache.demand_hits::total 1186515974 # number of demand (read+write) hits
73 system.cpu.icache.overall_hits::cpu.inst 1186515974 # number of overall hits
74 system.cpu.icache.overall_hits::total 1186515974 # number of overall hits
75 system.cpu.icache.ReadReq_misses::cpu.inst 722 # number of ReadReq misses
76 system.cpu.icache.ReadReq_misses::total 722 # number of ReadReq misses
77 system.cpu.icache.demand_misses::cpu.inst 722 # number of demand (read+write) misses
78 system.cpu.icache.demand_misses::total 722 # number of demand (read+write) misses
79 system.cpu.icache.overall_misses::cpu.inst 722 # number of overall misses
80 system.cpu.icache.overall_misses::total 722 # number of overall misses
81 system.cpu.icache.ReadReq_miss_latency::cpu.inst 39712000 # number of ReadReq miss cycles
82 system.cpu.icache.ReadReq_miss_latency::total 39712000 # number of ReadReq miss cycles
83 system.cpu.icache.demand_miss_latency::cpu.inst 39712000 # number of demand (read+write) miss cycles
84 system.cpu.icache.demand_miss_latency::total 39712000 # number of demand (read+write) miss cycles
85 system.cpu.icache.overall_miss_latency::cpu.inst 39712000 # number of overall miss cycles
86 system.cpu.icache.overall_miss_latency::total 39712000 # number of overall miss cycles
87 system.cpu.icache.ReadReq_accesses::cpu.inst 1186516696 # number of ReadReq accesses(hits+misses)
88 system.cpu.icache.ReadReq_accesses::total 1186516696 # number of ReadReq accesses(hits+misses)
89 system.cpu.icache.demand_accesses::cpu.inst 1186516696 # number of demand (read+write) accesses
90 system.cpu.icache.demand_accesses::total 1186516696 # number of demand (read+write) accesses
91 system.cpu.icache.overall_accesses::cpu.inst 1186516696 # number of overall (read+write) accesses
92 system.cpu.icache.overall_accesses::total 1186516696 # number of overall (read+write) accesses
93 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000001 # miss rate for ReadReq accesses
94 system.cpu.icache.ReadReq_miss_rate::total 0.000001 # miss rate for ReadReq accesses
95 system.cpu.icache.demand_miss_rate::cpu.inst 0.000001 # miss rate for demand accesses
96 system.cpu.icache.demand_miss_rate::total 0.000001 # miss rate for demand accesses
97 system.cpu.icache.overall_miss_rate::cpu.inst 0.000001 # miss rate for overall accesses
98 system.cpu.icache.overall_miss_rate::total 0.000001 # miss rate for overall accesses
99 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55002.770083 # average ReadReq miss latency
100 system.cpu.icache.ReadReq_avg_miss_latency::total 55002.770083 # average ReadReq miss latency
101 system.cpu.icache.demand_avg_miss_latency::cpu.inst 55002.770083 # average overall miss latency
102 system.cpu.icache.demand_avg_miss_latency::total 55002.770083 # average overall miss latency
103 system.cpu.icache.overall_avg_miss_latency::cpu.inst 55002.770083 # average overall miss latency
104 system.cpu.icache.overall_avg_miss_latency::total 55002.770083 # average overall miss latency
105 system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
106 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
107 system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
108 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
109 system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
110 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
111 system.cpu.icache.fast_writes 0 # number of fast writes performed
112 system.cpu.icache.cache_copies 0 # number of cache copies performed
113 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 722 # number of ReadReq MSHR misses
114 system.cpu.icache.ReadReq_mshr_misses::total 722 # number of ReadReq MSHR misses
115 system.cpu.icache.demand_mshr_misses::cpu.inst 722 # number of demand (read+write) MSHR misses
116 system.cpu.icache.demand_mshr_misses::total 722 # number of demand (read+write) MSHR misses
117 system.cpu.icache.overall_mshr_misses::cpu.inst 722 # number of overall MSHR misses
118 system.cpu.icache.overall_mshr_misses::total 722 # number of overall MSHR misses
119 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 38268000 # number of ReadReq MSHR miss cycles
120 system.cpu.icache.ReadReq_mshr_miss_latency::total 38268000 # number of ReadReq MSHR miss cycles
121 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 38268000 # number of demand (read+write) MSHR miss cycles
122 system.cpu.icache.demand_mshr_miss_latency::total 38268000 # number of demand (read+write) MSHR miss cycles
123 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 38268000 # number of overall MSHR miss cycles
124 system.cpu.icache.overall_mshr_miss_latency::total 38268000 # number of overall MSHR miss cycles
125 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for ReadReq accesses
126 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000001 # mshr miss rate for ReadReq accesses
127 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for demand accesses
128 system.cpu.icache.demand_mshr_miss_rate::total 0.000001 # mshr miss rate for demand accesses
129 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for overall accesses
130 system.cpu.icache.overall_mshr_miss_rate::total 0.000001 # mshr miss rate for overall accesses
131 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53002.770083 # average ReadReq mshr miss latency
132 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53002.770083 # average ReadReq mshr miss latency
133 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53002.770083 # average overall mshr miss latency
134 system.cpu.icache.demand_avg_mshr_miss_latency::total 53002.770083 # average overall mshr miss latency
135 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53002.770083 # average overall mshr miss latency
136 system.cpu.icache.overall_avg_mshr_miss_latency::total 53002.770083 # average overall mshr miss latency
137 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
138 system.cpu.l2cache.replacements 2532 # number of replacements
139 system.cpu.l2cache.tagsinuse 22211.029315 # Cycle average of tags in use
140 system.cpu.l2cache.total_refs 519268 # Total number of references to valid blocks.
141 system.cpu.l2cache.sampled_refs 23832 # Sample count of references to valid blocks.
142 system.cpu.l2cache.avg_refs 21.788687 # Average number of references to valid blocks.
143 system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
144 system.cpu.l2cache.occ_blocks::writebacks 21021.301343 # Average occupied blocks per requestor
145 system.cpu.l2cache.occ_blocks::cpu.inst 643.199216 # Average occupied blocks per requestor
146 system.cpu.l2cache.occ_blocks::cpu.data 546.528756 # Average occupied blocks per requestor
147 system.cpu.l2cache.occ_percent::writebacks 0.641519 # Average percentage of cache occupancy
148 system.cpu.l2cache.occ_percent::cpu.inst 0.019629 # Average percentage of cache occupancy
149 system.cpu.l2cache.occ_percent::cpu.data 0.016679 # Average percentage of cache occupancy
150 system.cpu.l2cache.occ_percent::total 0.677827 # Average percentage of cache occupancy
151 system.cpu.l2cache.ReadReq_hits::cpu.data 193009 # number of ReadReq hits
152 system.cpu.l2cache.ReadReq_hits::total 193009 # number of ReadReq hits
153 system.cpu.l2cache.Writeback_hits::writebacks 422980 # number of Writeback hits
154 system.cpu.l2cache.Writeback_hits::total 422980 # number of Writeback hits
155 system.cpu.l2cache.ReadExReq_hits::cpu.data 222752 # number of ReadExReq hits
156 system.cpu.l2cache.ReadExReq_hits::total 222752 # number of ReadExReq hits
157 system.cpu.l2cache.demand_hits::cpu.data 415761 # number of demand (read+write) hits
158 system.cpu.l2cache.demand_hits::total 415761 # number of demand (read+write) hits
159 system.cpu.l2cache.overall_hits::cpu.data 415761 # number of overall hits
160 system.cpu.l2cache.overall_hits::total 415761 # number of overall hits
161 system.cpu.l2cache.ReadReq_misses::cpu.inst 722 # number of ReadReq misses
162 system.cpu.l2cache.ReadReq_misses::cpu.data 4317 # number of ReadReq misses
163 system.cpu.l2cache.ReadReq_misses::total 5039 # number of ReadReq misses
164 system.cpu.l2cache.ReadExReq_misses::cpu.data 21970 # number of ReadExReq misses
165 system.cpu.l2cache.ReadExReq_misses::total 21970 # number of ReadExReq misses
166 system.cpu.l2cache.demand_misses::cpu.inst 722 # number of demand (read+write) misses
167 system.cpu.l2cache.demand_misses::cpu.data 26287 # number of demand (read+write) misses
168 system.cpu.l2cache.demand_misses::total 27009 # number of demand (read+write) misses
169 system.cpu.l2cache.overall_misses::cpu.inst 722 # number of overall misses
170 system.cpu.l2cache.overall_misses::cpu.data 26287 # number of overall misses
171 system.cpu.l2cache.overall_misses::total 27009 # number of overall misses
172 system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 37546000 # number of ReadReq miss cycles
173 system.cpu.l2cache.ReadReq_miss_latency::cpu.data 224484000 # number of ReadReq miss cycles
174 system.cpu.l2cache.ReadReq_miss_latency::total 262030000 # number of ReadReq miss cycles
175 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1143343000 # number of ReadExReq miss cycles
176 system.cpu.l2cache.ReadExReq_miss_latency::total 1143343000 # number of ReadExReq miss cycles
177 system.cpu.l2cache.demand_miss_latency::cpu.inst 37546000 # number of demand (read+write) miss cycles
178 system.cpu.l2cache.demand_miss_latency::cpu.data 1367827000 # number of demand (read+write) miss cycles
179 system.cpu.l2cache.demand_miss_latency::total 1405373000 # number of demand (read+write) miss cycles
180 system.cpu.l2cache.overall_miss_latency::cpu.inst 37546000 # number of overall miss cycles
181 system.cpu.l2cache.overall_miss_latency::cpu.data 1367827000 # number of overall miss cycles
182 system.cpu.l2cache.overall_miss_latency::total 1405373000 # number of overall miss cycles
183 system.cpu.l2cache.ReadReq_accesses::cpu.inst 722 # number of ReadReq accesses(hits+misses)
184 system.cpu.l2cache.ReadReq_accesses::cpu.data 197326 # number of ReadReq accesses(hits+misses)
185 system.cpu.l2cache.ReadReq_accesses::total 198048 # number of ReadReq accesses(hits+misses)
186 system.cpu.l2cache.Writeback_accesses::writebacks 422980 # number of Writeback accesses(hits+misses)
187 system.cpu.l2cache.Writeback_accesses::total 422980 # number of Writeback accesses(hits+misses)
188 system.cpu.l2cache.ReadExReq_accesses::cpu.data 244722 # number of ReadExReq accesses(hits+misses)
189 system.cpu.l2cache.ReadExReq_accesses::total 244722 # number of ReadExReq accesses(hits+misses)
190 system.cpu.l2cache.demand_accesses::cpu.inst 722 # number of demand (read+write) accesses
191 system.cpu.l2cache.demand_accesses::cpu.data 442048 # number of demand (read+write) accesses
192 system.cpu.l2cache.demand_accesses::total 442770 # number of demand (read+write) accesses
193 system.cpu.l2cache.overall_accesses::cpu.inst 722 # number of overall (read+write) accesses
194 system.cpu.l2cache.overall_accesses::cpu.data 442048 # number of overall (read+write) accesses
195 system.cpu.l2cache.overall_accesses::total 442770 # number of overall (read+write) accesses
196 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses
197 system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.021878 # miss rate for ReadReq accesses
198 system.cpu.l2cache.ReadReq_miss_rate::total 0.025443 # miss rate for ReadReq accesses
199 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.089775 # miss rate for ReadExReq accesses
200 system.cpu.l2cache.ReadExReq_miss_rate::total 0.089775 # miss rate for ReadExReq accesses
201 system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses
202 system.cpu.l2cache.demand_miss_rate::cpu.data 0.059466 # miss rate for demand accesses
203 system.cpu.l2cache.demand_miss_rate::total 0.061000 # miss rate for demand accesses
204 system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
205 system.cpu.l2cache.overall_miss_rate::cpu.data 0.059466 # miss rate for overall accesses
206 system.cpu.l2cache.overall_miss_rate::total 0.061000 # miss rate for overall accesses
207 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52002.770083 # average ReadReq miss latency
208 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
209 system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000.396904 # average ReadReq miss latency
210 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52041.101502 # average ReadExReq miss latency
211 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52041.101502 # average ReadExReq miss latency
212 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52002.770083 # average overall miss latency
213 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52034.351581 # average overall miss latency
214 system.cpu.l2cache.demand_avg_miss_latency::total 52033.507349 # average overall miss latency
215 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52002.770083 # average overall miss latency
216 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52034.351581 # average overall miss latency
217 system.cpu.l2cache.overall_avg_miss_latency::total 52033.507349 # average overall miss latency
218 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
219 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
220 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
221 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
222 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
223 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
224 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
225 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
226 system.cpu.l2cache.writebacks::writebacks 2511 # number of writebacks
227 system.cpu.l2cache.writebacks::total 2511 # number of writebacks
228 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 722 # number of ReadReq MSHR misses
229 system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4317 # number of ReadReq MSHR misses
230 system.cpu.l2cache.ReadReq_mshr_misses::total 5039 # number of ReadReq MSHR misses
231 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21970 # number of ReadExReq MSHR misses
232 system.cpu.l2cache.ReadExReq_mshr_misses::total 21970 # number of ReadExReq MSHR misses
233 system.cpu.l2cache.demand_mshr_misses::cpu.inst 722 # number of demand (read+write) MSHR misses
234 system.cpu.l2cache.demand_mshr_misses::cpu.data 26287 # number of demand (read+write) MSHR misses
235 system.cpu.l2cache.demand_mshr_misses::total 27009 # number of demand (read+write) MSHR misses
236 system.cpu.l2cache.overall_mshr_misses::cpu.inst 722 # number of overall MSHR misses
237 system.cpu.l2cache.overall_mshr_misses::cpu.data 26287 # number of overall MSHR misses
238 system.cpu.l2cache.overall_mshr_misses::total 27009 # number of overall MSHR misses
239 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 28882000 # number of ReadReq MSHR miss cycles
240 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 172680000 # number of ReadReq MSHR miss cycles
241 system.cpu.l2cache.ReadReq_mshr_miss_latency::total 201562000 # number of ReadReq MSHR miss cycles
242 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 879703000 # number of ReadExReq MSHR miss cycles
243 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 879703000 # number of ReadExReq MSHR miss cycles
244 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 28882000 # number of demand (read+write) MSHR miss cycles
245 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1052383000 # number of demand (read+write) MSHR miss cycles
246 system.cpu.l2cache.demand_mshr_miss_latency::total 1081265000 # number of demand (read+write) MSHR miss cycles
247 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 28882000 # number of overall MSHR miss cycles
248 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1052383000 # number of overall MSHR miss cycles
249 system.cpu.l2cache.overall_mshr_miss_latency::total 1081265000 # number of overall MSHR miss cycles
250 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses
251 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.021878 # mshr miss rate for ReadReq accesses
252 system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.025443 # mshr miss rate for ReadReq accesses
253 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.089775 # mshr miss rate for ReadExReq accesses
254 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.089775 # mshr miss rate for ReadExReq accesses
255 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
256 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.059466 # mshr miss rate for demand accesses
257 system.cpu.l2cache.demand_mshr_miss_rate::total 0.061000 # mshr miss rate for demand accesses
258 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
259 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.059466 # mshr miss rate for overall accesses
260 system.cpu.l2cache.overall_mshr_miss_rate::total 0.061000 # mshr miss rate for overall accesses
261 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40002.770083 # average ReadReq mshr miss latency
262 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
263 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000.396904 # average ReadReq mshr miss latency
264 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40041.101502 # average ReadExReq mshr miss latency
265 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40041.101502 # average ReadExReq mshr miss latency
266 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40002.770083 # average overall mshr miss latency
267 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40034.351581 # average overall mshr miss latency
268 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40033.507349 # average overall mshr miss latency
269 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40002.770083 # average overall mshr miss latency
270 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40034.351581 # average overall mshr miss latency
271 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40033.507349 # average overall mshr miss latency
272 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
273 system.cpu.dcache.replacements 437952 # number of replacements
274 system.cpu.dcache.tagsinuse 4094.905740 # Cycle average of tags in use
275 system.cpu.dcache.total_refs 606786132 # Total number of references to valid blocks.
276 system.cpu.dcache.sampled_refs 442048 # Sample count of references to valid blocks.
277 system.cpu.dcache.avg_refs 1372.670235 # Average number of references to valid blocks.
278 system.cpu.dcache.warmup_cycle 771788000 # Cycle when the warmup percentage was hit.
279 system.cpu.dcache.occ_blocks::cpu.data 4094.905740 # Average occupied blocks per requestor
280 system.cpu.dcache.occ_percent::cpu.data 0.999733 # Average percentage of cache occupancy
281 system.cpu.dcache.occ_percent::total 0.999733 # Average percentage of cache occupancy
282 system.cpu.dcache.ReadReq_hits::cpu.data 418844796 # number of ReadReq hits
283 system.cpu.dcache.ReadReq_hits::total 418844796 # number of ReadReq hits
284 system.cpu.dcache.WriteReq_hits::cpu.data 187941336 # number of WriteReq hits
285 system.cpu.dcache.WriteReq_hits::total 187941336 # number of WriteReq hits
286 system.cpu.dcache.demand_hits::cpu.data 606786132 # number of demand (read+write) hits
287 system.cpu.dcache.demand_hits::total 606786132 # number of demand (read+write) hits
288 system.cpu.dcache.overall_hits::cpu.data 606786132 # number of overall hits
289 system.cpu.dcache.overall_hits::total 606786132 # number of overall hits
290 system.cpu.dcache.ReadReq_misses::cpu.data 197326 # number of ReadReq misses
291 system.cpu.dcache.ReadReq_misses::total 197326 # number of ReadReq misses
292 system.cpu.dcache.WriteReq_misses::cpu.data 244722 # number of WriteReq misses
293 system.cpu.dcache.WriteReq_misses::total 244722 # number of WriteReq misses
294 system.cpu.dcache.demand_misses::cpu.data 442048 # number of demand (read+write) misses
295 system.cpu.dcache.demand_misses::total 442048 # number of demand (read+write) misses
296 system.cpu.dcache.overall_misses::cpu.data 442048 # number of overall misses
297 system.cpu.dcache.overall_misses::total 442048 # number of overall misses
298 system.cpu.dcache.ReadReq_miss_latency::cpu.data 2746552000 # number of ReadReq miss cycles
299 system.cpu.dcache.ReadReq_miss_latency::total 2746552000 # number of ReadReq miss cycles
300 system.cpu.dcache.WriteReq_miss_latency::cpu.data 4105029000 # number of WriteReq miss cycles
301 system.cpu.dcache.WriteReq_miss_latency::total 4105029000 # number of WriteReq miss cycles
302 system.cpu.dcache.demand_miss_latency::cpu.data 6851581000 # number of demand (read+write) miss cycles
303 system.cpu.dcache.demand_miss_latency::total 6851581000 # number of demand (read+write) miss cycles
304 system.cpu.dcache.overall_miss_latency::cpu.data 6851581000 # number of overall miss cycles
305 system.cpu.dcache.overall_miss_latency::total 6851581000 # number of overall miss cycles
306 system.cpu.dcache.ReadReq_accesses::cpu.data 419042122 # number of ReadReq accesses(hits+misses)
307 system.cpu.dcache.ReadReq_accesses::total 419042122 # number of ReadReq accesses(hits+misses)
308 system.cpu.dcache.WriteReq_accesses::cpu.data 188186058 # number of WriteReq accesses(hits+misses)
309 system.cpu.dcache.WriteReq_accesses::total 188186058 # number of WriteReq accesses(hits+misses)
310 system.cpu.dcache.demand_accesses::cpu.data 607228180 # number of demand (read+write) accesses
311 system.cpu.dcache.demand_accesses::total 607228180 # number of demand (read+write) accesses
312 system.cpu.dcache.overall_accesses::cpu.data 607228180 # number of overall (read+write) accesses
313 system.cpu.dcache.overall_accesses::total 607228180 # number of overall (read+write) accesses
314 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000471 # miss rate for ReadReq accesses
315 system.cpu.dcache.ReadReq_miss_rate::total 0.000471 # miss rate for ReadReq accesses
316 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001300 # miss rate for WriteReq accesses
317 system.cpu.dcache.WriteReq_miss_rate::total 0.001300 # miss rate for WriteReq accesses
318 system.cpu.dcache.demand_miss_rate::cpu.data 0.000728 # miss rate for demand accesses
319 system.cpu.dcache.demand_miss_rate::total 0.000728 # miss rate for demand accesses
320 system.cpu.dcache.overall_miss_rate::cpu.data 0.000728 # miss rate for overall accesses
321 system.cpu.dcache.overall_miss_rate::total 0.000728 # miss rate for overall accesses
322 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13918.855093 # average ReadReq miss latency
323 system.cpu.dcache.ReadReq_avg_miss_latency::total 13918.855093 # average ReadReq miss latency
324 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16774.254052 # average WriteReq miss latency
325 system.cpu.dcache.WriteReq_avg_miss_latency::total 16774.254052 # average WriteReq miss latency
326 system.cpu.dcache.demand_avg_miss_latency::cpu.data 15499.631262 # average overall miss latency
327 system.cpu.dcache.demand_avg_miss_latency::total 15499.631262 # average overall miss latency
328 system.cpu.dcache.overall_avg_miss_latency::cpu.data 15499.631262 # average overall miss latency
329 system.cpu.dcache.overall_avg_miss_latency::total 15499.631262 # average overall miss latency
330 system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
331 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
332 system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
333 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
334 system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
335 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
336 system.cpu.dcache.fast_writes 0 # number of fast writes performed
337 system.cpu.dcache.cache_copies 0 # number of cache copies performed
338 system.cpu.dcache.writebacks::writebacks 422980 # number of writebacks
339 system.cpu.dcache.writebacks::total 422980 # number of writebacks
340 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 197326 # number of ReadReq MSHR misses
341 system.cpu.dcache.ReadReq_mshr_misses::total 197326 # number of ReadReq MSHR misses
342 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 244722 # number of WriteReq MSHR misses
343 system.cpu.dcache.WriteReq_mshr_misses::total 244722 # number of WriteReq MSHR misses
344 system.cpu.dcache.demand_mshr_misses::cpu.data 442048 # number of demand (read+write) MSHR misses
345 system.cpu.dcache.demand_mshr_misses::total 442048 # number of demand (read+write) MSHR misses
346 system.cpu.dcache.overall_mshr_misses::cpu.data 442048 # number of overall MSHR misses
347 system.cpu.dcache.overall_mshr_misses::total 442048 # number of overall MSHR misses
348 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2351900000 # number of ReadReq MSHR miss cycles
349 system.cpu.dcache.ReadReq_mshr_miss_latency::total 2351900000 # number of ReadReq MSHR miss cycles
350 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3615585000 # number of WriteReq MSHR miss cycles
351 system.cpu.dcache.WriteReq_mshr_miss_latency::total 3615585000 # number of WriteReq MSHR miss cycles
352 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5967485000 # number of demand (read+write) MSHR miss cycles
353 system.cpu.dcache.demand_mshr_miss_latency::total 5967485000 # number of demand (read+write) MSHR miss cycles
354 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5967485000 # number of overall MSHR miss cycles
355 system.cpu.dcache.overall_mshr_miss_latency::total 5967485000 # number of overall MSHR miss cycles
356 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000471 # mshr miss rate for ReadReq accesses
357 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000471 # mshr miss rate for ReadReq accesses
358 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001300 # mshr miss rate for WriteReq accesses
359 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.001300 # mshr miss rate for WriteReq accesses
360 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000728 # mshr miss rate for demand accesses
361 system.cpu.dcache.demand_mshr_miss_rate::total 0.000728 # mshr miss rate for demand accesses
362 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000728 # mshr miss rate for overall accesses
363 system.cpu.dcache.overall_mshr_miss_rate::total 0.000728 # mshr miss rate for overall accesses
364 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11918.855093 # average ReadReq mshr miss latency
365 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11918.855093 # average ReadReq mshr miss latency
366 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14774.254052 # average WriteReq mshr miss latency
367 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14774.254052 # average WriteReq mshr miss latency
368 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13499.631262 # average overall mshr miss latency
369 system.cpu.dcache.demand_avg_mshr_miss_latency::total 13499.631262 # average overall mshr miss latency
370 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13499.631262 # average overall mshr miss latency
371 system.cpu.dcache.overall_avg_mshr_miss_latency::total 13499.631262 # average overall mshr miss latency
372 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
374 ---------- End Simulation Statistics ----------
projects / gem5.git / blob