arch: Fix VecReg container alignement to 128bits view
[gem5.git] / tests / long / se / 10.mcf / ref / arm / linux / minor-timing / simout
1 Redirecting stdout to build/ARM/tests/opt/long/se/10.mcf/arm/linux/minor-timing/simout
2 Redirecting stderr to build/ARM/tests/opt/long/se/10.mcf/arm/linux/minor-timing/simerr
3 gem5 Simulator System. http://gem5.org
4 gem5 is copyrighted software; use the --copyright option for details.
5
6 gem5 compiled Oct 11 2016 00:00:58
7 gem5 started Oct 13 2016 20:43:02
8 gem5 executing on e108600-lin, pid 17345
9 command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/minor-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/10.mcf/arm/linux/minor-timing
10
11 Global frequency set at 1000000000000 ticks per second
12 info: Entering event queue @ 0. Starting simulation...
13
14 MCF SPEC version 1.6.I
15 by Andreas Loebel
16 Copyright (c) 1998,1999 ZIB Berlin
17 All Rights Reserved.
18
19 nodes : 500
20 active arcs : 1905
21 simplex iterations : 1502
22 flow value : 4990014995
23 new implicit arcs : 23867
24 active arcs : 25772
25 simplex iterations : 2663
26 flow value : 3080014995
27 checksum : 68389
28 optimal
29 Exiting @ tick 62552970500 because target called exit()