tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini

   1 [root]
   2 type=Root
   3 children=system
   4 eventq_index=0
   5 full_system=false
   6 sim_quantum=0
   7 time_sync_enable=false
   8 time_sync_period=100000000000
   9 time_sync_spin_threshold=100000000
  10
  11 [system]
  12 type=System
  13 children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
  14 boot_osflags=a
  15 cache_line_size=64
  16 clk_domain=system.clk_domain
  17 eventq_index=0
  18 init_param=0
  19 kernel=
  20 load_addr_mask=1099511627775
  21 mem_mode=timing
  22 mem_ranges=
  23 memories=system.physmem
  24 num_work_ids=16
  25 readfile=
  26 symbolfile=
  27 work_begin_ckpt_count=0
  28 work_begin_cpu_id_exit=-1
  29 work_begin_exit_count=0
  30 work_cpus_ckpt_count=0
  31 work_end_ckpt_count=0
  32 work_end_exit_count=0
  33 work_item_id=-1
  34 system_port=system.membus.slave[0]
  35
  36 [system.clk_domain]
  37 type=SrcClockDomain
  38 clock=1000
  39 eventq_index=0
  40 voltage_domain=system.voltage_domain
  41
  42 [system.cpu]
  43 type=DerivO3CPU
  44 children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
  45 LFSTSize=1024
  46 LQEntries=32
  47 LSQCheckLoads=true
  48 LSQDepCheckShift=4
  49 SQEntries=32
  50 SSITSize=1024
  51 activity=0
  52 backComSize=5
  53 branchPred=system.cpu.branchPred
  54 cachePorts=200
  55 checker=Null
  56 clk_domain=system.cpu_clk_domain
  57 commitToDecodeDelay=1
  58 commitToFetchDelay=1
  59 commitToIEWDelay=1
  60 commitToRenameDelay=1
  61 commitWidth=8
  62 cpu_id=0
  63 decodeToFetchDelay=1
  64 decodeToRenameDelay=1
  65 decodeWidth=8
  66 dispatchWidth=8
  67 do_checkpoint_insts=true
  68 do_quiesce=true
  69 do_statistics_insts=true
  70 dtb=system.cpu.dtb
  71 eventq_index=0
  72 fetchBufferSize=64
  73 fetchToDecodeDelay=1
  74 fetchTrapLatency=1
  75 fetchWidth=8
  76 forwardComSize=5
  77 fuPool=system.cpu.fuPool
  78 function_trace=false
  79 function_trace_start=0
  80 iewToCommitDelay=1
  81 iewToDecodeDelay=1
  82 iewToFetchDelay=1
  83 iewToRenameDelay=1
  84 interrupts=system.cpu.interrupts
  85 isa=system.cpu.isa
  86 issueToExecuteDelay=1
  87 issueWidth=8
  88 itb=system.cpu.itb
  89 max_insts_all_threads=0
  90 max_insts_any_thread=0
  91 max_loads_all_threads=0
  92 max_loads_any_thread=0
  93 needsTSO=false
  94 numIQEntries=64
  95 numPhysCCRegs=0
  96 numPhysFloatRegs=256
  97 numPhysIntRegs=256
  98 numROBEntries=192
  99 numRobs=1
 100 numThreads=1
 101 profile=0
 102 progress_interval=0
 103 renameToDecodeDelay=1
 104 renameToFetchDelay=1
 105 renameToIEWDelay=2
 106 renameToROBDelay=1
 107 renameWidth=8
 108 simpoint_start_insts=
 109 smtCommitPolicy=RoundRobin
 110 smtFetchPolicy=SingleThread
 111 smtIQPolicy=Partitioned
 112 smtIQThreshold=100
 113 smtLSQPolicy=Partitioned
 114 smtLSQThreshold=100
 115 smtNumFetchingThreads=1
 116 smtROBPolicy=Partitioned
 117 smtROBThreshold=100
 118 squashWidth=8
 119 store_set_clear_period=250000
 120 switched_out=false
 121 system=system
 122 tracer=system.cpu.tracer
 123 trapLatency=13
 124 wbDepth=1
 125 wbWidth=8
 126 workload=system.cpu.workload
 127 dcache_port=system.cpu.dcache.cpu_side
 128 icache_port=system.cpu.icache.cpu_side
 129
 130 [system.cpu.branchPred]
 131 type=BranchPredictor
 132 BTBEntries=4096
 133 BTBTagSize=16
 134 RASSize=16
 135 choiceCtrBits=2
 136 choicePredictorSize=8192
 137 eventq_index=0
 138 globalCtrBits=2
 139 globalPredictorSize=8192
 140 instShiftAmt=2
 141 localCtrBits=2
 142 localHistoryTableSize=2048
 143 localPredictorSize=2048
 144 numThreads=1
 145 predType=tournament
 146
 147 [system.cpu.dcache]
 148 type=BaseCache
 149 children=tags
 150 addr_ranges=0:18446744073709551615
 151 assoc=2
 152 clk_domain=system.cpu_clk_domain
 153 eventq_index=0
 154 forward_snoops=true
 155 hit_latency=2
 156 is_top_level=true
 157 max_miss_count=0
 158 mshrs=4
 159 prefetch_on_access=false
 160 prefetcher=Null
 161 response_latency=2
 162 sequential_access=false
 163 size=262144
 164 system=system
 165 tags=system.cpu.dcache.tags
 166 tgts_per_mshr=20
 167 two_queue=false
 168 write_buffers=8
 169 cpu_side=system.cpu.dcache_port
 170 mem_side=system.cpu.toL2Bus.slave[1]
 171
 172 [system.cpu.dcache.tags]
 173 type=LRU
 174 assoc=2
 175 block_size=64
 176 clk_domain=system.cpu_clk_domain
 177 eventq_index=0
 178 hit_latency=2
 179 sequential_access=false
 180 size=262144
 181
 182 [system.cpu.dtb]
 183 type=ArmTLB
 184 children=walker
 185 eventq_index=0
 186 size=64
 187 walker=system.cpu.dtb.walker
 188
 189 [system.cpu.dtb.walker]
 190 type=ArmTableWalker
 191 clk_domain=system.cpu_clk_domain
 192 eventq_index=0
 193 num_squash_per_cycle=2
 194 sys=system
 195 port=system.cpu.toL2Bus.slave[3]
 196
 197 [system.cpu.fuPool]
 198 type=FUPool
 199 children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
 200 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
 201 eventq_index=0
 202
 203 [system.cpu.fuPool.FUList0]
 204 type=FUDesc
 205 children=opList
 206 count=6
 207 eventq_index=0
 208 opList=system.cpu.fuPool.FUList0.opList
 209
 210 [system.cpu.fuPool.FUList0.opList]
 211 type=OpDesc
 212 eventq_index=0
 213 issueLat=1
 214 opClass=IntAlu
 215 opLat=1
 216
 217 [system.cpu.fuPool.FUList1]
 218 type=FUDesc
 219 children=opList0 opList1
 220 count=2
 221 eventq_index=0
 222 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
 223
 224 [system.cpu.fuPool.FUList1.opList0]
 225 type=OpDesc
 226 eventq_index=0
 227 issueLat=1
 228 opClass=IntMult
 229 opLat=3
 230
 231 [system.cpu.fuPool.FUList1.opList1]
 232 type=OpDesc
 233 eventq_index=0
 234 issueLat=19
 235 opClass=IntDiv
 236 opLat=20
 237
 238 [system.cpu.fuPool.FUList2]
 239 type=FUDesc
 240 children=opList0 opList1 opList2
 241 count=4
 242 eventq_index=0
 243 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
 244
 245 [system.cpu.fuPool.FUList2.opList0]
 246 type=OpDesc
 247 eventq_index=0
 248 issueLat=1
 249 opClass=FloatAdd
 250 opLat=2
 251
 252 [system.cpu.fuPool.FUList2.opList1]
 253 type=OpDesc
 254 eventq_index=0
 255 issueLat=1
 256 opClass=FloatCmp
 257 opLat=2
 258
 259 [system.cpu.fuPool.FUList2.opList2]
 260 type=OpDesc
 261 eventq_index=0
 262 issueLat=1
 263 opClass=FloatCvt
 264 opLat=2
 265
 266 [system.cpu.fuPool.FUList3]
 267 type=FUDesc
 268 children=opList0 opList1 opList2
 269 count=2
 270 eventq_index=0
 271 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
 272
 273 [system.cpu.fuPool.FUList3.opList0]
 274 type=OpDesc
 275 eventq_index=0
 276 issueLat=1
 277 opClass=FloatMult
 278 opLat=4
 279
 280 [system.cpu.fuPool.FUList3.opList1]
 281 type=OpDesc
 282 eventq_index=0
 283 issueLat=12
 284 opClass=FloatDiv
 285 opLat=12
 286
 287 [system.cpu.fuPool.FUList3.opList2]
 288 type=OpDesc
 289 eventq_index=0
 290 issueLat=24
 291 opClass=FloatSqrt
 292 opLat=24
 293
 294 [system.cpu.fuPool.FUList4]
 295 type=FUDesc
 296 children=opList
 297 count=0
 298 eventq_index=0
 299 opList=system.cpu.fuPool.FUList4.opList
 300
 301 [system.cpu.fuPool.FUList4.opList]
 302 type=OpDesc
 303 eventq_index=0
 304 issueLat=1
 305 opClass=MemRead
 306 opLat=1
 307
 308 [system.cpu.fuPool.FUList5]
 309 type=FUDesc
 310 children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
 311 count=4
 312 eventq_index=0
 313 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
 314
 315 [system.cpu.fuPool.FUList5.opList00]
 316 type=OpDesc
 317 eventq_index=0
 318 issueLat=1
 319 opClass=SimdAdd
 320 opLat=1
 321
 322 [system.cpu.fuPool.FUList5.opList01]
 323 type=OpDesc
 324 eventq_index=0
 325 issueLat=1
 326 opClass=SimdAddAcc
 327 opLat=1
 328
 329 [system.cpu.fuPool.FUList5.opList02]
 330 type=OpDesc
 331 eventq_index=0
 332 issueLat=1
 333 opClass=SimdAlu
 334 opLat=1
 335
 336 [system.cpu.fuPool.FUList5.opList03]
 337 type=OpDesc
 338 eventq_index=0
 339 issueLat=1
 340 opClass=SimdCmp
 341 opLat=1
 342
 343 [system.cpu.fuPool.FUList5.opList04]
 344 type=OpDesc
 345 eventq_index=0
 346 issueLat=1
 347 opClass=SimdCvt
 348 opLat=1
 349
 350 [system.cpu.fuPool.FUList5.opList05]
 351 type=OpDesc
 352 eventq_index=0
 353 issueLat=1
 354 opClass=SimdMisc
 355 opLat=1
 356
 357 [system.cpu.fuPool.FUList5.opList06]
 358 type=OpDesc
 359 eventq_index=0
 360 issueLat=1
 361 opClass=SimdMult
 362 opLat=1
 363
 364 [system.cpu.fuPool.FUList5.opList07]
 365 type=OpDesc
 366 eventq_index=0
 367 issueLat=1
 368 opClass=SimdMultAcc
 369 opLat=1
 370
 371 [system.cpu.fuPool.FUList5.opList08]
 372 type=OpDesc
 373 eventq_index=0
 374 issueLat=1
 375 opClass=SimdShift
 376 opLat=1
 377
 378 [system.cpu.fuPool.FUList5.opList09]
 379 type=OpDesc
 380 eventq_index=0
 381 issueLat=1
 382 opClass=SimdShiftAcc
 383 opLat=1
 384
 385 [system.cpu.fuPool.FUList5.opList10]
 386 type=OpDesc
 387 eventq_index=0
 388 issueLat=1
 389 opClass=SimdSqrt
 390 opLat=1
 391
 392 [system.cpu.fuPool.FUList5.opList11]
 393 type=OpDesc
 394 eventq_index=0
 395 issueLat=1
 396 opClass=SimdFloatAdd
 397 opLat=1
 398
 399 [system.cpu.fuPool.FUList5.opList12]
 400 type=OpDesc
 401 eventq_index=0
 402 issueLat=1
 403 opClass=SimdFloatAlu
 404 opLat=1
 405
 406 [system.cpu.fuPool.FUList5.opList13]
 407 type=OpDesc
 408 eventq_index=0
 409 issueLat=1
 410 opClass=SimdFloatCmp
 411 opLat=1
 412
 413 [system.cpu.fuPool.FUList5.opList14]
 414 type=OpDesc
 415 eventq_index=0
 416 issueLat=1
 417 opClass=SimdFloatCvt
 418 opLat=1
 419
 420 [system.cpu.fuPool.FUList5.opList15]
 421 type=OpDesc
 422 eventq_index=0
 423 issueLat=1
 424 opClass=SimdFloatDiv
 425 opLat=1
 426
 427 [system.cpu.fuPool.FUList5.opList16]
 428 type=OpDesc
 429 eventq_index=0
 430 issueLat=1
 431 opClass=SimdFloatMisc
 432 opLat=1
 433
 434 [system.cpu.fuPool.FUList5.opList17]
 435 type=OpDesc
 436 eventq_index=0
 437 issueLat=1
 438 opClass=SimdFloatMult
 439 opLat=1
 440
 441 [system.cpu.fuPool.FUList5.opList18]
 442 type=OpDesc
 443 eventq_index=0
 444 issueLat=1
 445 opClass=SimdFloatMultAcc
 446 opLat=1
 447
 448 [system.cpu.fuPool.FUList5.opList19]
 449 type=OpDesc
 450 eventq_index=0
 451 issueLat=1
 452 opClass=SimdFloatSqrt
 453 opLat=1
 454
 455 [system.cpu.fuPool.FUList6]
 456 type=FUDesc
 457 children=opList
 458 count=0
 459 eventq_index=0
 460 opList=system.cpu.fuPool.FUList6.opList
 461
 462 [system.cpu.fuPool.FUList6.opList]
 463 type=OpDesc
 464 eventq_index=0
 465 issueLat=1
 466 opClass=MemWrite
 467 opLat=1
 468
 469 [system.cpu.fuPool.FUList7]
 470 type=FUDesc
 471 children=opList0 opList1
 472 count=4
 473 eventq_index=0
 474 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
 475
 476 [system.cpu.fuPool.FUList7.opList0]
 477 type=OpDesc
 478 eventq_index=0
 479 issueLat=1
 480 opClass=MemRead
 481 opLat=1
 482
 483 [system.cpu.fuPool.FUList7.opList1]
 484 type=OpDesc
 485 eventq_index=0
 486 issueLat=1
 487 opClass=MemWrite
 488 opLat=1
 489
 490 [system.cpu.fuPool.FUList8]
 491 type=FUDesc
 492 children=opList
 493 count=1
 494 eventq_index=0
 495 opList=system.cpu.fuPool.FUList8.opList
 496
 497 [system.cpu.fuPool.FUList8.opList]
 498 type=OpDesc
 499 eventq_index=0
 500 issueLat=3
 501 opClass=IprAccess
 502 opLat=3
 503
 504 [system.cpu.icache]
 505 type=BaseCache
 506 children=tags
 507 addr_ranges=0:18446744073709551615
 508 assoc=2
 509 clk_domain=system.cpu_clk_domain
 510 eventq_index=0
 511 forward_snoops=true
 512 hit_latency=2
 513 is_top_level=true
 514 max_miss_count=0
 515 mshrs=4
 516 prefetch_on_access=false
 517 prefetcher=Null
 518 response_latency=2
 519 sequential_access=false
 520 size=131072
 521 system=system
 522 tags=system.cpu.icache.tags
 523 tgts_per_mshr=20
 524 two_queue=false
 525 write_buffers=8
 526 cpu_side=system.cpu.icache_port
 527 mem_side=system.cpu.toL2Bus.slave[0]
 528
 529 [system.cpu.icache.tags]
 530 type=LRU
 531 assoc=2
 532 block_size=64
 533 clk_domain=system.cpu_clk_domain
 534 eventq_index=0
 535 hit_latency=2
 536 sequential_access=false
 537 size=131072
 538
 539 [system.cpu.interrupts]
 540 type=ArmInterrupts
 541 eventq_index=0
 542
 543 [system.cpu.isa]
 544 type=ArmISA
 545 eventq_index=0
 546 fpsid=1090793632
 547 id_isar0=34607377
 548 id_isar1=34677009
 549 id_isar2=555950401
 550 id_isar3=17899825
 551 id_isar4=268501314
 552 id_isar5=0
 553 id_mmfr0=3
 554 id_mmfr1=0
 555 id_mmfr2=19070976
 556 id_mmfr3=4027589137
 557 id_pfr0=49
 558 id_pfr1=1
 559 midr=890224640
 560
 561 [system.cpu.itb]
 562 type=ArmTLB
 563 children=walker
 564 eventq_index=0
 565 size=64
 566 walker=system.cpu.itb.walker
 567
 568 [system.cpu.itb.walker]
 569 type=ArmTableWalker
 570 clk_domain=system.cpu_clk_domain
 571 eventq_index=0
 572 num_squash_per_cycle=2
 573 sys=system
 574 port=system.cpu.toL2Bus.slave[2]
 575
 576 [system.cpu.l2cache]
 577 type=BaseCache
 578 children=tags
 579 addr_ranges=0:18446744073709551615
 580 assoc=8
 581 clk_domain=system.cpu_clk_domain
 582 eventq_index=0
 583 forward_snoops=true
 584 hit_latency=20
 585 is_top_level=false
 586 max_miss_count=0
 587 mshrs=20
 588 prefetch_on_access=false
 589 prefetcher=Null
 590 response_latency=20
 591 sequential_access=false
 592 size=2097152
 593 system=system
 594 tags=system.cpu.l2cache.tags
 595 tgts_per_mshr=12
 596 two_queue=false
 597 write_buffers=8
 598 cpu_side=system.cpu.toL2Bus.master[0]
 599 mem_side=system.membus.slave[1]
 600
 601 [system.cpu.l2cache.tags]
 602 type=LRU
 603 assoc=8
 604 block_size=64
 605 clk_domain=system.cpu_clk_domain
 606 eventq_index=0
 607 hit_latency=20
 608 sequential_access=false
 609 size=2097152
 610
 611 [system.cpu.toL2Bus]
 612 type=CoherentBus
 613 clk_domain=system.cpu_clk_domain
 614 eventq_index=0
 615 header_cycles=1
 616 system=system
 617 use_default_range=false
 618 width=32
 619 master=system.cpu.l2cache.cpu_side
 620 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
 621
 622 [system.cpu.tracer]
 623 type=ExeTracer
 624 eventq_index=0
 625
 626 [system.cpu.workload]
 627 type=LiveProcess
 628 cmd=mcf mcf.in
 629 cwd=build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing
 630 egid=100
 631 env=
 632 errout=cerr
 633 euid=100
 634 eventq_index=0
 635 executable=/dist/cpu2000/binaries/arm/linux/mcf
 636 gid=100
 637 input=/dist/cpu2000/data/mcf/smred/input/mcf.in
 638 max_stack_size=67108864
 639 output=cout
 640 pid=100
 641 ppid=99
 642 simpoint=55300000000
 643 system=system
 644 uid=100
 645
 646 [system.cpu_clk_domain]
 647 type=SrcClockDomain
 648 clock=500
 649 eventq_index=0
 650 voltage_domain=system.voltage_domain
 651
 652 [system.membus]
 653 type=CoherentBus
 654 clk_domain=system.clk_domain
 655 eventq_index=0
 656 header_cycles=1
 657 system=system
 658 use_default_range=false
 659 width=8
 660 master=system.physmem.port
 661 slave=system.system_port system.cpu.l2cache.mem_side
 662
 663 [system.physmem]
 664 type=SimpleDRAM
 665 activation_limit=4
 666 addr_mapping=RaBaChCo
 667 banks_per_rank=8
 668 burst_length=8
 669 channels=1
 670 clk_domain=system.clk_domain
 671 conf_table_reported=true
 672 device_bus_width=8
 673 device_rowbuffer_size=1024
 674 devices_per_rank=8
 675 eventq_index=0
 676 in_addr_map=true
 677 mem_sched_policy=frfcfs
 678 null=false
 679 page_policy=open
 680 range=0:268435455
 681 ranks_per_channel=2
 682 read_buffer_size=32
 683 static_backend_latency=10000
 684 static_frontend_latency=10000
 685 tBURST=5000
 686 tCL=13750
 687 tRAS=35000
 688 tRCD=13750
 689 tREFI=7800000
 690 tRFC=300000
 691 tRP=13750
 692 tRRD=6250
 693 tWTR=7500
 694 tXAW=40000
 695 write_buffer_size=32
 696 write_high_thresh_perc=70
 697 write_low_thresh_perc=0
 698 port=system.membus.master[0]
 699
 700 [system.voltage_domain]
 701 type=VoltageDomain
 702 eventq_index=0
 703 voltage=1.000000
 704