arch: Fix VecReg container alignement to 128bits view
[gem5.git] / tests / long / se / 10.mcf / ref / arm / linux / o3-timing / simerr
1 warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
2 warn: Sockets disabled, not accepting gdb connections
3 warn: ClockedObject: More than one power state change request encountered within the same simulation tick
4 info: Entering event queue @ 0. Starting simulation...
5 warn: CP14 unimplemented crn[8], opc1[2], crm[9], opc2[4]