2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.026911 # Number of seconds simulated
4 sim_ticks 26911413000 # Number of ticks simulated
5 final_tick 26911413000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 116759 # Simulator instruction rate (inst/s)
8 host_op_rate 117598 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 34685583 # Simulator tick rate (ticks/s)
10 host_mem_usage 427272 # Number of bytes of host memory used
11 host_seconds 775.87 # Real time elapsed on the host
12 sim_insts 90589798 # Number of instructions simulated
13 sim_ops 91240351 # Number of ops (including micro ops) simulated
14 system.physmem.bytes_read::cpu.inst 45440 # Number of bytes read from this memory
15 system.physmem.bytes_read::cpu.data 947712 # Number of bytes read from this memory
16 system.physmem.bytes_read::total 993152 # Number of bytes read from this memory
17 system.physmem.bytes_inst_read::cpu.inst 45440 # Number of instructions bytes read from this memory
18 system.physmem.bytes_inst_read::total 45440 # Number of instructions bytes read from this memory
19 system.physmem.num_reads::cpu.inst 710 # Number of read requests responded to by this memory
20 system.physmem.num_reads::cpu.data 14808 # Number of read requests responded to by this memory
21 system.physmem.num_reads::total 15518 # Number of read requests responded to by this memory
22 system.physmem.bw_read::cpu.inst 1688503 # Total read bandwidth from this memory (bytes/s)
23 system.physmem.bw_read::cpu.data 35215988 # Total read bandwidth from this memory (bytes/s)
24 system.physmem.bw_read::total 36904491 # Total read bandwidth from this memory (bytes/s)
25 system.physmem.bw_inst_read::cpu.inst 1688503 # Instruction read bandwidth from this memory (bytes/s)
26 system.physmem.bw_inst_read::total 1688503 # Instruction read bandwidth from this memory (bytes/s)
27 system.physmem.bw_total::cpu.inst 1688503 # Total bandwidth to/from this memory (bytes/s)
28 system.physmem.bw_total::cpu.data 35215988 # Total bandwidth to/from this memory (bytes/s)
29 system.physmem.bw_total::total 36904491 # Total bandwidth to/from this memory (bytes/s)
30 system.physmem.readReqs 15518 # Number of read requests accepted
31 system.physmem.writeReqs 0 # Number of write requests accepted
32 system.physmem.readBursts 15518 # Number of DRAM read bursts, including those serviced by the write queue
33 system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
34 system.physmem.bytesReadDRAM 993152 # Total number of bytes read from DRAM
35 system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
36 system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
37 system.physmem.bytesReadSys 993152 # Total read bytes from the system interface side
38 system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
39 system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
40 system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
41 system.physmem.neitherReadNorWriteReqs 1 # Number of requests that are neither read nor write
42 system.physmem.perBankRdBursts::0 987 # Per bank write bursts
43 system.physmem.perBankRdBursts::1 886 # Per bank write bursts
44 system.physmem.perBankRdBursts::2 942 # Per bank write bursts
45 system.physmem.perBankRdBursts::3 1028 # Per bank write bursts
46 system.physmem.perBankRdBursts::4 1050 # Per bank write bursts
47 system.physmem.perBankRdBursts::5 1105 # Per bank write bursts
48 system.physmem.perBankRdBursts::6 1078 # Per bank write bursts
49 system.physmem.perBankRdBursts::7 1080 # Per bank write bursts
50 system.physmem.perBankRdBursts::8 1024 # Per bank write bursts
51 system.physmem.perBankRdBursts::9 959 # Per bank write bursts
52 system.physmem.perBankRdBursts::10 938 # Per bank write bursts
53 system.physmem.perBankRdBursts::11 899 # Per bank write bursts
54 system.physmem.perBankRdBursts::12 904 # Per bank write bursts
55 system.physmem.perBankRdBursts::13 865 # Per bank write bursts
56 system.physmem.perBankRdBursts::14 877 # Per bank write bursts
57 system.physmem.perBankRdBursts::15 896 # Per bank write bursts
58 system.physmem.perBankWrBursts::0 0 # Per bank write bursts
59 system.physmem.perBankWrBursts::1 0 # Per bank write bursts
60 system.physmem.perBankWrBursts::2 0 # Per bank write bursts
61 system.physmem.perBankWrBursts::3 0 # Per bank write bursts
62 system.physmem.perBankWrBursts::4 0 # Per bank write bursts
63 system.physmem.perBankWrBursts::5 0 # Per bank write bursts
64 system.physmem.perBankWrBursts::6 0 # Per bank write bursts
65 system.physmem.perBankWrBursts::7 0 # Per bank write bursts
66 system.physmem.perBankWrBursts::8 0 # Per bank write bursts
67 system.physmem.perBankWrBursts::9 0 # Per bank write bursts
68 system.physmem.perBankWrBursts::10 0 # Per bank write bursts
69 system.physmem.perBankWrBursts::11 0 # Per bank write bursts
70 system.physmem.perBankWrBursts::12 0 # Per bank write bursts
71 system.physmem.perBankWrBursts::13 0 # Per bank write bursts
72 system.physmem.perBankWrBursts::14 0 # Per bank write bursts
73 system.physmem.perBankWrBursts::15 0 # Per bank write bursts
74 system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
75 system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
76 system.physmem.totGap 26911220500 # Total gap between requests
77 system.physmem.readPktSize::0 0 # Read request sizes (log2)
78 system.physmem.readPktSize::1 0 # Read request sizes (log2)
79 system.physmem.readPktSize::2 0 # Read request sizes (log2)
80 system.physmem.readPktSize::3 0 # Read request sizes (log2)
81 system.physmem.readPktSize::4 0 # Read request sizes (log2)
82 system.physmem.readPktSize::5 0 # Read request sizes (log2)
83 system.physmem.readPktSize::6 15518 # Read request sizes (log2)
84 system.physmem.writePktSize::0 0 # Write request sizes (log2)
85 system.physmem.writePktSize::1 0 # Write request sizes (log2)
86 system.physmem.writePktSize::2 0 # Write request sizes (log2)
87 system.physmem.writePktSize::3 0 # Write request sizes (log2)
88 system.physmem.writePktSize::4 0 # Write request sizes (log2)
89 system.physmem.writePktSize::5 0 # Write request sizes (log2)
90 system.physmem.writePktSize::6 0 # Write request sizes (log2)
91 system.physmem.rdQLenPdf::0 11172 # What read queue length does an incoming req see
92 system.physmem.rdQLenPdf::1 4157 # What read queue length does an incoming req see
93 system.physmem.rdQLenPdf::2 169 # What read queue length does an incoming req see
94 system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see
95 system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see
96 system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see
97 system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
98 system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
99 system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
100 system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
101 system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
102 system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
103 system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
104 system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
105 system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
106 system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
107 system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
108 system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
109 system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
110 system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
111 system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
112 system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
113 system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
114 system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
115 system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
116 system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
117 system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
118 system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
119 system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
120 system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
121 system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
122 system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
123 system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
124 system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
125 system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
126 system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
127 system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
128 system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
129 system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
130 system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
131 system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
132 system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
133 system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
134 system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
135 system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
136 system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
137 system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
138 system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
139 system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
140 system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
141 system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
142 system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
143 system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
144 system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
145 system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
146 system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
147 system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
148 system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
149 system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
150 system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
151 system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
152 system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
153 system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
154 system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
155 system.physmem.bytesPerActivate::samples 619 # Bytes accessed per row activation
156 system.physmem.bytesPerActivate::mean 1598.759289 # Bytes accessed per row activation
157 system.physmem.bytesPerActivate::gmean 481.680955 # Bytes accessed per row activation
158 system.physmem.bytesPerActivate::stdev 2200.761860 # Bytes accessed per row activation
159 system.physmem.bytesPerActivate::64-65 153 24.72% 24.72% # Bytes accessed per row activation
160 system.physmem.bytesPerActivate::128-129 75 12.12% 36.83% # Bytes accessed per row activation
161 system.physmem.bytesPerActivate::192-193 40 6.46% 43.30% # Bytes accessed per row activation
162 system.physmem.bytesPerActivate::256-257 20 3.23% 46.53% # Bytes accessed per row activation
163 system.physmem.bytesPerActivate::320-321 12 1.94% 48.47% # Bytes accessed per row activation
164 system.physmem.bytesPerActivate::384-385 6 0.97% 49.43% # Bytes accessed per row activation
165 system.physmem.bytesPerActivate::448-449 27 4.36% 53.80% # Bytes accessed per row activation
166 system.physmem.bytesPerActivate::512-513 12 1.94% 55.74% # Bytes accessed per row activation
167 system.physmem.bytesPerActivate::576-577 5 0.81% 56.54% # Bytes accessed per row activation
168 system.physmem.bytesPerActivate::640-641 10 1.62% 58.16% # Bytes accessed per row activation
169 system.physmem.bytesPerActivate::704-705 3 0.48% 58.64% # Bytes accessed per row activation
170 system.physmem.bytesPerActivate::768-769 4 0.65% 59.29% # Bytes accessed per row activation
171 system.physmem.bytesPerActivate::832-833 5 0.81% 60.10% # Bytes accessed per row activation
172 system.physmem.bytesPerActivate::896-897 8 1.29% 61.39% # Bytes accessed per row activation
173 system.physmem.bytesPerActivate::960-961 3 0.48% 61.87% # Bytes accessed per row activation
174 system.physmem.bytesPerActivate::1024-1025 3 0.48% 62.36% # Bytes accessed per row activation
175 system.physmem.bytesPerActivate::1088-1089 6 0.97% 63.33% # Bytes accessed per row activation
176 system.physmem.bytesPerActivate::1152-1153 2 0.32% 63.65% # Bytes accessed per row activation
177 system.physmem.bytesPerActivate::1216-1217 2 0.32% 63.97% # Bytes accessed per row activation
178 system.physmem.bytesPerActivate::1280-1281 3 0.48% 64.46% # Bytes accessed per row activation
179 system.physmem.bytesPerActivate::1344-1345 2 0.32% 64.78% # Bytes accessed per row activation
180 system.physmem.bytesPerActivate::1408-1409 4 0.65% 65.43% # Bytes accessed per row activation
181 system.physmem.bytesPerActivate::1472-1473 6 0.97% 66.40% # Bytes accessed per row activation
182 system.physmem.bytesPerActivate::1536-1537 19 3.07% 69.47% # Bytes accessed per row activation
183 system.physmem.bytesPerActivate::1600-1601 6 0.97% 70.44% # Bytes accessed per row activation
184 system.physmem.bytesPerActivate::1664-1665 6 0.97% 71.41% # Bytes accessed per row activation
185 system.physmem.bytesPerActivate::1792-1793 3 0.48% 71.89% # Bytes accessed per row activation
186 system.physmem.bytesPerActivate::1856-1857 3 0.48% 72.37% # Bytes accessed per row activation
187 system.physmem.bytesPerActivate::1984-1985 1 0.16% 72.54% # Bytes accessed per row activation
188 system.physmem.bytesPerActivate::2048-2049 6 0.97% 73.51% # Bytes accessed per row activation
189 system.physmem.bytesPerActivate::2112-2113 2 0.32% 73.83% # Bytes accessed per row activation
190 system.physmem.bytesPerActivate::2176-2177 6 0.97% 74.80% # Bytes accessed per row activation
191 system.physmem.bytesPerActivate::2304-2305 2 0.32% 75.12% # Bytes accessed per row activation
192 system.physmem.bytesPerActivate::2368-2369 1 0.16% 75.28% # Bytes accessed per row activation
193 system.physmem.bytesPerActivate::2496-2497 3 0.48% 75.77% # Bytes accessed per row activation
194 system.physmem.bytesPerActivate::2560-2561 1 0.16% 75.93% # Bytes accessed per row activation
195 system.physmem.bytesPerActivate::2624-2625 2 0.32% 76.25% # Bytes accessed per row activation
196 system.physmem.bytesPerActivate::2688-2689 1 0.16% 76.41% # Bytes accessed per row activation
197 system.physmem.bytesPerActivate::2752-2753 5 0.81% 77.22% # Bytes accessed per row activation
198 system.physmem.bytesPerActivate::2816-2817 4 0.65% 77.87% # Bytes accessed per row activation
199 system.physmem.bytesPerActivate::2944-2945 2 0.32% 78.19% # Bytes accessed per row activation
200 system.physmem.bytesPerActivate::3008-3009 3 0.48% 78.68% # Bytes accessed per row activation
201 system.physmem.bytesPerActivate::3072-3073 4 0.65% 79.32% # Bytes accessed per row activation
202 system.physmem.bytesPerActivate::3136-3137 2 0.32% 79.64% # Bytes accessed per row activation
203 system.physmem.bytesPerActivate::3200-3201 2 0.32% 79.97% # Bytes accessed per row activation
204 system.physmem.bytesPerActivate::3264-3265 2 0.32% 80.29% # Bytes accessed per row activation
205 system.physmem.bytesPerActivate::3392-3393 3 0.48% 80.78% # Bytes accessed per row activation
206 system.physmem.bytesPerActivate::3456-3457 1 0.16% 80.94% # Bytes accessed per row activation
207 system.physmem.bytesPerActivate::3520-3521 2 0.32% 81.26% # Bytes accessed per row activation
208 system.physmem.bytesPerActivate::3584-3585 1 0.16% 81.42% # Bytes accessed per row activation
209 system.physmem.bytesPerActivate::3648-3649 3 0.48% 81.91% # Bytes accessed per row activation
210 system.physmem.bytesPerActivate::3712-3713 3 0.48% 82.39% # Bytes accessed per row activation
211 system.physmem.bytesPerActivate::3776-3777 2 0.32% 82.71% # Bytes accessed per row activation
212 system.physmem.bytesPerActivate::3904-3905 1 0.16% 82.88% # Bytes accessed per row activation
213 system.physmem.bytesPerActivate::3968-3969 1 0.16% 83.04% # Bytes accessed per row activation
214 system.physmem.bytesPerActivate::4032-4033 1 0.16% 83.20% # Bytes accessed per row activation
215 system.physmem.bytesPerActivate::4096-4097 3 0.48% 83.68% # Bytes accessed per row activation
216 system.physmem.bytesPerActivate::4160-4161 2 0.32% 84.01% # Bytes accessed per row activation
217 system.physmem.bytesPerActivate::4224-4225 1 0.16% 84.17% # Bytes accessed per row activation
218 system.physmem.bytesPerActivate::4416-4417 3 0.48% 84.65% # Bytes accessed per row activation
219 system.physmem.bytesPerActivate::4480-4481 4 0.65% 85.30% # Bytes accessed per row activation
220 system.physmem.bytesPerActivate::4544-4545 4 0.65% 85.95% # Bytes accessed per row activation
221 system.physmem.bytesPerActivate::4608-4609 1 0.16% 86.11% # Bytes accessed per row activation
222 system.physmem.bytesPerActivate::4672-4673 3 0.48% 86.59% # Bytes accessed per row activation
223 system.physmem.bytesPerActivate::4736-4737 2 0.32% 86.91% # Bytes accessed per row activation
224 system.physmem.bytesPerActivate::4800-4801 2 0.32% 87.24% # Bytes accessed per row activation
225 system.physmem.bytesPerActivate::4864-4865 1 0.16% 87.40% # Bytes accessed per row activation
226 system.physmem.bytesPerActivate::4928-4929 2 0.32% 87.72% # Bytes accessed per row activation
227 system.physmem.bytesPerActivate::4992-4993 1 0.16% 87.88% # Bytes accessed per row activation
228 system.physmem.bytesPerActivate::5056-5057 2 0.32% 88.21% # Bytes accessed per row activation
229 system.physmem.bytesPerActivate::5120-5121 5 0.81% 89.01% # Bytes accessed per row activation
230 system.physmem.bytesPerActivate::5184-5185 3 0.48% 89.50% # Bytes accessed per row activation
231 system.physmem.bytesPerActivate::5248-5249 4 0.65% 90.15% # Bytes accessed per row activation
232 system.physmem.bytesPerActivate::5376-5377 2 0.32% 90.47% # Bytes accessed per row activation
233 system.physmem.bytesPerActivate::5440-5441 6 0.97% 91.44% # Bytes accessed per row activation
234 system.physmem.bytesPerActivate::5504-5505 3 0.48% 91.92% # Bytes accessed per row activation
235 system.physmem.bytesPerActivate::5568-5569 1 0.16% 92.08% # Bytes accessed per row activation
236 system.physmem.bytesPerActivate::5696-5697 1 0.16% 92.25% # Bytes accessed per row activation
237 system.physmem.bytesPerActivate::5824-5825 1 0.16% 92.41% # Bytes accessed per row activation
238 system.physmem.bytesPerActivate::5888-5889 1 0.16% 92.57% # Bytes accessed per row activation
239 system.physmem.bytesPerActivate::6016-6017 3 0.48% 93.05% # Bytes accessed per row activation
240 system.physmem.bytesPerActivate::6080-6081 1 0.16% 93.21% # Bytes accessed per row activation
241 system.physmem.bytesPerActivate::6144-6145 2 0.32% 93.54% # Bytes accessed per row activation
242 system.physmem.bytesPerActivate::6208-6209 1 0.16% 93.70% # Bytes accessed per row activation
243 system.physmem.bytesPerActivate::6272-6273 2 0.32% 94.02% # Bytes accessed per row activation
244 system.physmem.bytesPerActivate::6336-6337 3 0.48% 94.51% # Bytes accessed per row activation
245 system.physmem.bytesPerActivate::6400-6401 1 0.16% 94.67% # Bytes accessed per row activation
246 system.physmem.bytesPerActivate::6528-6529 2 0.32% 94.99% # Bytes accessed per row activation
247 system.physmem.bytesPerActivate::6592-6593 1 0.16% 95.15% # Bytes accessed per row activation
248 system.physmem.bytesPerActivate::6656-6657 3 0.48% 95.64% # Bytes accessed per row activation
249 system.physmem.bytesPerActivate::6720-6721 1 0.16% 95.80% # Bytes accessed per row activation
250 system.physmem.bytesPerActivate::6784-6785 1 0.16% 95.96% # Bytes accessed per row activation
251 system.physmem.bytesPerActivate::6912-6913 1 0.16% 96.12% # Bytes accessed per row activation
252 system.physmem.bytesPerActivate::6976-6977 1 0.16% 96.28% # Bytes accessed per row activation
253 system.physmem.bytesPerActivate::7040-7041 1 0.16% 96.45% # Bytes accessed per row activation
254 system.physmem.bytesPerActivate::7104-7105 2 0.32% 96.77% # Bytes accessed per row activation
255 system.physmem.bytesPerActivate::7168-7169 1 0.16% 96.93% # Bytes accessed per row activation
256 system.physmem.bytesPerActivate::7424-7425 1 0.16% 97.09% # Bytes accessed per row activation
257 system.physmem.bytesPerActivate::7616-7617 1 0.16% 97.25% # Bytes accessed per row activation
258 system.physmem.bytesPerActivate::7680-7681 1 0.16% 97.42% # Bytes accessed per row activation
259 system.physmem.bytesPerActivate::7744-7745 1 0.16% 97.58% # Bytes accessed per row activation
260 system.physmem.bytesPerActivate::7872-7873 1 0.16% 97.74% # Bytes accessed per row activation
261 system.physmem.bytesPerActivate::8128-8129 2 0.32% 98.06% # Bytes accessed per row activation
262 system.physmem.bytesPerActivate::8192-8193 12 1.94% 100.00% # Bytes accessed per row activation
263 system.physmem.bytesPerActivate::total 619 # Bytes accessed per row activation
264 system.physmem.totQLat 103760250 # Total ticks spent queuing
265 system.physmem.totMemAccLat 357130250 # Total ticks spent from burst creation until serviced by the DRAM
266 system.physmem.totBusLat 77590000 # Total ticks spent in databus transfers
267 system.physmem.totBankLat 175780000 # Total ticks spent accessing banks
268 system.physmem.avgQLat 6686.44 # Average queueing delay per DRAM burst
269 system.physmem.avgBankLat 11327.49 # Average bank access latency per DRAM burst
270 system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
271 system.physmem.avgMemAccLat 23013.94 # Average memory access latency per DRAM burst
272 system.physmem.avgRdBW 36.90 # Average DRAM read bandwidth in MiByte/s
273 system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
274 system.physmem.avgRdBWSys 36.90 # Average system read bandwidth in MiByte/s
275 system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
276 system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
277 system.physmem.busUtil 0.29 # Data bus utilization in percentage
278 system.physmem.busUtilRead 0.29 # Data bus utilization in percentage for reads
279 system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
280 system.physmem.avgRdQLen 0.01 # Average read queue length when enqueuing
281 system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
282 system.physmem.readRowHits 14899 # Number of row buffer hits during reads
283 system.physmem.writeRowHits 0 # Number of row buffer hits during writes
284 system.physmem.readRowHitRate 96.01 # Row buffer hit rate for reads
285 system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
286 system.physmem.avgGap 1734193.87 # Average gap between requests
287 system.physmem.pageHitRate 96.01 # Row buffer hit rate, read and write combined
288 system.physmem.prechargeAllPercent 1.04 # Percentage of time for which DRAM has all the banks in precharge state
289 system.membus.throughput 36904491 # Throughput (bytes/s)
290 system.membus.trans_dist::ReadReq 980 # Transaction distribution
291 system.membus.trans_dist::ReadResp 980 # Transaction distribution
292 system.membus.trans_dist::UpgradeReq 1 # Transaction distribution
293 system.membus.trans_dist::UpgradeResp 1 # Transaction distribution
294 system.membus.trans_dist::ReadExReq 14538 # Transaction distribution
295 system.membus.trans_dist::ReadExResp 14538 # Transaction distribution
296 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31038 # Packet count per connected master and slave (bytes)
297 system.membus.pkt_count::total 31038 # Packet count per connected master and slave (bytes)
298 system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 993152 # Cumulative packet size per connected master and slave (bytes)
299 system.membus.tot_pkt_size::total 993152 # Cumulative packet size per connected master and slave (bytes)
300 system.membus.data_through_bus 993152 # Total data (bytes)
301 system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
302 system.membus.reqLayer0.occupancy 19253000 # Layer occupancy (ticks)
303 system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
304 system.membus.respLayer1.occupancy 145189999 # Layer occupancy (ticks)
305 system.membus.respLayer1.utilization 0.5 # Layer utilization (%)
306 system.cpu.branchPred.lookups 26686306 # Number of BP lookups
307 system.cpu.branchPred.condPredicted 22003847 # Number of conditional branches predicted
308 system.cpu.branchPred.condIncorrect 843168 # Number of conditional branches incorrect
309 system.cpu.branchPred.BTBLookups 11366672 # Number of BTB lookups
310 system.cpu.branchPred.BTBHits 11283030 # Number of BTB hits
311 system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
312 system.cpu.branchPred.BTBHitPct 99.264147 # BTB Hit Percentage
313 system.cpu.branchPred.usedRAS 70474 # Number of times the RAS was used to get a target.
314 system.cpu.branchPred.RASInCorrect 170 # Number of incorrect RAS predictions.
315 system.cpu.dtb.inst_hits 0 # ITB inst hits
316 system.cpu.dtb.inst_misses 0 # ITB inst misses
317 system.cpu.dtb.read_hits 0 # DTB read hits
318 system.cpu.dtb.read_misses 0 # DTB read misses
319 system.cpu.dtb.write_hits 0 # DTB write hits
320 system.cpu.dtb.write_misses 0 # DTB write misses
321 system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
322 system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
323 system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
324 system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
325 system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
326 system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
327 system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
328 system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
329 system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
330 system.cpu.dtb.read_accesses 0 # DTB read accesses
331 system.cpu.dtb.write_accesses 0 # DTB write accesses
332 system.cpu.dtb.inst_accesses 0 # ITB inst accesses
333 system.cpu.dtb.hits 0 # DTB hits
334 system.cpu.dtb.misses 0 # DTB misses
335 system.cpu.dtb.accesses 0 # DTB accesses
336 system.cpu.itb.inst_hits 0 # ITB inst hits
337 system.cpu.itb.inst_misses 0 # ITB inst misses
338 system.cpu.itb.read_hits 0 # DTB read hits
339 system.cpu.itb.read_misses 0 # DTB read misses
340 system.cpu.itb.write_hits 0 # DTB write hits
341 system.cpu.itb.write_misses 0 # DTB write misses
342 system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
343 system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
344 system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
345 system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
346 system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
347 system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
348 system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
349 system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
350 system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
351 system.cpu.itb.read_accesses 0 # DTB read accesses
352 system.cpu.itb.write_accesses 0 # DTB write accesses
353 system.cpu.itb.inst_accesses 0 # ITB inst accesses
354 system.cpu.itb.hits 0 # DTB hits
355 system.cpu.itb.misses 0 # DTB misses
356 system.cpu.itb.accesses 0 # DTB accesses
357 system.cpu.workload.num_syscalls 442 # Number of system calls
358 system.cpu.numCycles 53822827 # number of cpu cycles simulated
359 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
360 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
361 system.cpu.fetch.icacheStallCycles 14174375 # Number of cycles fetch is stalled on an Icache miss
362 system.cpu.fetch.Insts 127897951 # Number of instructions fetch has processed
363 system.cpu.fetch.Branches 26686306 # Number of branches that fetch encountered
364 system.cpu.fetch.predictedBranches 11353504 # Number of branches that fetch has predicted taken
365 system.cpu.fetch.Cycles 24037647 # Number of cycles fetch has run and was not squashing or blocked
366 system.cpu.fetch.SquashCycles 4766390 # Number of cycles fetch has spent squashing
367 system.cpu.fetch.BlockedCycles 11312706 # Number of cycles fetch has spent blocked
368 system.cpu.fetch.MiscStallCycles 108 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
369 system.cpu.fetch.PendingTrapStallCycles 8 # Number of stall cycles due to pending traps
370 system.cpu.fetch.IcacheWaitRetryStallCycles 52 # Number of stall cycles due to full MSHR
371 system.cpu.fetch.CacheLines 13845393 # Number of cache lines fetched
372 system.cpu.fetch.IcacheSquashes 329438 # Number of outstanding Icache misses that were squashed
373 system.cpu.fetch.rateDist::samples 53431463 # Number of instructions fetched each cycle (Total)
374 system.cpu.fetch.rateDist::mean 2.410222 # Number of instructions fetched each cycle (Total)
375 system.cpu.fetch.rateDist::stdev 3.214882 # Number of instructions fetched each cycle (Total)
376 system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
377 system.cpu.fetch.rateDist::0 29432152 55.08% 55.08% # Number of instructions fetched each cycle (Total)
378 system.cpu.fetch.rateDist::1 3389873 6.34% 61.43% # Number of instructions fetched each cycle (Total)
379 system.cpu.fetch.rateDist::2 2028658 3.80% 65.23% # Number of instructions fetched each cycle (Total)
380 system.cpu.fetch.rateDist::3 1553769 2.91% 68.13% # Number of instructions fetched each cycle (Total)
381 system.cpu.fetch.rateDist::4 1668148 3.12% 71.26% # Number of instructions fetched each cycle (Total)
382 system.cpu.fetch.rateDist::5 2920061 5.47% 76.72% # Number of instructions fetched each cycle (Total)
383 system.cpu.fetch.rateDist::6 1509677 2.83% 79.55% # Number of instructions fetched each cycle (Total)
384 system.cpu.fetch.rateDist::7 1090745 2.04% 81.59% # Number of instructions fetched each cycle (Total)
385 system.cpu.fetch.rateDist::8 9838380 18.41% 100.00% # Number of instructions fetched each cycle (Total)
386 system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
387 system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
388 system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
389 system.cpu.fetch.rateDist::total 53431463 # Number of instructions fetched each cycle (Total)
390 system.cpu.fetch.branchRate 0.495818 # Number of branch fetches per cycle
391 system.cpu.fetch.rate 2.376277 # Number of inst fetches per cycle
392 system.cpu.decode.IdleCycles 16937925 # Number of cycles decode is idle
393 system.cpu.decode.BlockedCycles 9159010 # Number of cycles decode is blocked
394 system.cpu.decode.RunCycles 22405754 # Number of cycles decode is running
395 system.cpu.decode.UnblockCycles 1030805 # Number of cycles decode is unblocking
396 system.cpu.decode.SquashCycles 3897969 # Number of cycles decode is squashing
397 system.cpu.decode.BranchResolved 4444268 # Number of times decode resolved a branch
398 system.cpu.decode.BranchMispred 8691 # Number of times decode detected a branch misprediction
399 system.cpu.decode.DecodedInsts 126081524 # Number of instructions handled by decode
400 system.cpu.decode.SquashedInsts 42632 # Number of squashed instructions handled by decode
401 system.cpu.rename.SquashCycles 3897969 # Number of cycles rename is squashing
402 system.cpu.rename.IdleCycles 18719458 # Number of cycles rename is idle
403 system.cpu.rename.BlockCycles 3589629 # Number of cycles rename is blocking
404 system.cpu.rename.serializeStallCycles 186437 # count of cycles rename stalled for serializing inst
405 system.cpu.rename.RunCycles 21552986 # Number of cycles rename is running
406 system.cpu.rename.UnblockCycles 5484984 # Number of cycles rename is unblocking
407 system.cpu.rename.RenamedInsts 123156725 # Number of instructions processed by rename
408 system.cpu.rename.ROBFullEvents 9 # Number of times rename has blocked due to ROB full
409 system.cpu.rename.IQFullEvents 425837 # Number of times rename has blocked due to IQ full
410 system.cpu.rename.LSQFullEvents 4596994 # Number of times rename has blocked due to LSQ full
411 system.cpu.rename.FullRegisterEvents 1284 # Number of times there has been no free registers
412 system.cpu.rename.RenamedOperands 143603336 # Number of destination operands rename has renamed
413 system.cpu.rename.RenameLookups 536446832 # Number of register rename lookups that rename has made
414 system.cpu.rename.int_rename_lookups 500029218 # Number of integer rename lookups
415 system.cpu.rename.fp_rename_lookups 672 # Number of floating rename lookups
416 system.cpu.rename.CommittedMaps 107414186 # Number of HB maps that are committed
417 system.cpu.rename.UndoneMaps 36189150 # Number of HB maps that are undone due to squashing
418 system.cpu.rename.serializingInsts 4635 # count of serializing insts renamed
419 system.cpu.rename.tempSerializingInsts 4633 # count of temporary serializing insts renamed
420 system.cpu.rename.skidInsts 12540789 # count of insts added to the skid buffer
421 system.cpu.memDep0.insertedLoads 29477429 # Number of loads inserted to the mem dependence unit.
422 system.cpu.memDep0.insertedStores 5520545 # Number of stores inserted to the mem dependence unit.
423 system.cpu.memDep0.conflictingLoads 2151265 # Number of conflicting loads.
424 system.cpu.memDep0.conflictingStores 1294097 # Number of conflicting stores.
425 system.cpu.iq.iqInstsAdded 118170448 # Number of instructions added to the IQ (excludes non-spec)
426 system.cpu.iq.iqNonSpecInstsAdded 8500 # Number of non-speculative instructions added to the IQ
427 system.cpu.iq.iqInstsIssued 105167442 # Number of instructions issued
428 system.cpu.iq.iqSquashedInstsIssued 79307 # Number of squashed instructions issued
429 system.cpu.iq.iqSquashedInstsExamined 26742090 # Number of squashed instructions iterated over during squash; mainly for profiling
430 system.cpu.iq.iqSquashedOperandsExamined 65583646 # Number of squashed operands that are examined and possibly removed from graph
431 system.cpu.iq.iqSquashedNonSpecRemoved 282 # Number of squashed non-spec instructions that were removed
432 system.cpu.iq.issued_per_cycle::samples 53431463 # Number of insts issued each cycle
433 system.cpu.iq.issued_per_cycle::mean 1.968268 # Number of insts issued each cycle
434 system.cpu.iq.issued_per_cycle::stdev 1.908949 # Number of insts issued each cycle
435 system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
436 system.cpu.iq.issued_per_cycle::0 15374280 28.77% 28.77% # Number of insts issued each cycle
437 system.cpu.iq.issued_per_cycle::1 11649569 21.80% 50.58% # Number of insts issued each cycle
438 system.cpu.iq.issued_per_cycle::2 8250468 15.44% 66.02% # Number of insts issued each cycle
439 system.cpu.iq.issued_per_cycle::3 6827782 12.78% 78.80% # Number of insts issued each cycle
440 system.cpu.iq.issued_per_cycle::4 4953380 9.27% 88.07% # Number of insts issued each cycle
441 system.cpu.iq.issued_per_cycle::5 2948609 5.52% 93.59% # Number of insts issued each cycle
442 system.cpu.iq.issued_per_cycle::6 2456731 4.60% 98.18% # Number of insts issued each cycle
443 system.cpu.iq.issued_per_cycle::7 528512 0.99% 99.17% # Number of insts issued each cycle
444 system.cpu.iq.issued_per_cycle::8 442132 0.83% 100.00% # Number of insts issued each cycle
445 system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
446 system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
447 system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
448 system.cpu.iq.issued_per_cycle::total 53431463 # Number of insts issued each cycle
449 system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
450 system.cpu.iq.fu_full::IntAlu 45750 6.92% 6.92% # attempts to use FU when none available
451 system.cpu.iq.fu_full::IntMult 27 0.00% 6.92% # attempts to use FU when none available
452 system.cpu.iq.fu_full::IntDiv 0 0.00% 6.92% # attempts to use FU when none available
453 system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.92% # attempts to use FU when none available
454 system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.92% # attempts to use FU when none available
455 system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.92% # attempts to use FU when none available
456 system.cpu.iq.fu_full::FloatMult 0 0.00% 6.92% # attempts to use FU when none available
457 system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.92% # attempts to use FU when none available
458 system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.92% # attempts to use FU when none available
459 system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.92% # attempts to use FU when none available
460 system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.92% # attempts to use FU when none available
461 system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.92% # attempts to use FU when none available
462 system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.92% # attempts to use FU when none available
463 system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.92% # attempts to use FU when none available
464 system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.92% # attempts to use FU when none available
465 system.cpu.iq.fu_full::SimdMult 0 0.00% 6.92% # attempts to use FU when none available
466 system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.92% # attempts to use FU when none available
467 system.cpu.iq.fu_full::SimdShift 0 0.00% 6.92% # attempts to use FU when none available
468 system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.92% # attempts to use FU when none available
469 system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.92% # attempts to use FU when none available
470 system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.92% # attempts to use FU when none available
471 system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.92% # attempts to use FU when none available
472 system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.92% # attempts to use FU when none available
473 system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.92% # attempts to use FU when none available
474 system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.92% # attempts to use FU when none available
475 system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.92% # attempts to use FU when none available
476 system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.92% # attempts to use FU when none available
477 system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.92% # attempts to use FU when none available
478 system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.92% # attempts to use FU when none available
479 system.cpu.iq.fu_full::MemRead 340320 51.44% 58.36% # attempts to use FU when none available
480 system.cpu.iq.fu_full::MemWrite 275443 41.64% 100.00% # attempts to use FU when none available
481 system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
482 system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
483 system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
484 system.cpu.iq.FU_type_0::IntAlu 74429619 70.77% 70.77% # Type of FU issued
485 system.cpu.iq.FU_type_0::IntMult 10979 0.01% 70.78% # Type of FU issued
486 system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.78% # Type of FU issued
487 system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.78% # Type of FU issued
488 system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.78% # Type of FU issued
489 system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.78% # Type of FU issued
490 system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.78% # Type of FU issued
491 system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.78% # Type of FU issued
492 system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.78% # Type of FU issued
493 system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.78% # Type of FU issued
494 system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.78% # Type of FU issued
495 system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.78% # Type of FU issued
496 system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.78% # Type of FU issued
497 system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.78% # Type of FU issued
498 system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.78% # Type of FU issued
499 system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.78% # Type of FU issued
500 system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.78% # Type of FU issued
501 system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.78% # Type of FU issued
502 system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.78% # Type of FU issued
503 system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.78% # Type of FU issued
504 system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.78% # Type of FU issued
505 system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.78% # Type of FU issued
506 system.cpu.iq.FU_type_0::SimdFloatCmp 1 0.00% 70.78% # Type of FU issued
507 system.cpu.iq.FU_type_0::SimdFloatCvt 129 0.00% 70.78% # Type of FU issued
508 system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.78% # Type of FU issued
509 system.cpu.iq.FU_type_0::SimdFloatMisc 165 0.00% 70.78% # Type of FU issued
510 system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.78% # Type of FU issued
511 system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 70.78% # Type of FU issued
512 system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.78% # Type of FU issued
513 system.cpu.iq.FU_type_0::MemRead 25613153 24.35% 95.14% # Type of FU issued
514 system.cpu.iq.FU_type_0::MemWrite 5113394 4.86% 100.00% # Type of FU issued
515 system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
516 system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
517 system.cpu.iq.FU_type_0::total 105167442 # Type of FU issued
518 system.cpu.iq.rate 1.953956 # Inst issue rate
519 system.cpu.iq.fu_busy_cnt 661540 # FU busy when requested
520 system.cpu.iq.fu_busy_rate 0.006290 # FU busy rate (busy events/executed inst)
521 system.cpu.iq.int_inst_queue_reads 264506537 # Number of integer instruction queue reads
522 system.cpu.iq.int_inst_queue_writes 144925816 # Number of integer instruction queue writes
523 system.cpu.iq.int_inst_queue_wakeup_accesses 102691564 # Number of integer instruction queue wakeup accesses
524 system.cpu.iq.fp_inst_queue_reads 657 # Number of floating instruction queue reads
525 system.cpu.iq.fp_inst_queue_writes 923 # Number of floating instruction queue writes
526 system.cpu.iq.fp_inst_queue_wakeup_accesses 287 # Number of floating instruction queue wakeup accesses
527 system.cpu.iq.int_alu_accesses 105828655 # Number of integer alu accesses
528 system.cpu.iq.fp_alu_accesses 327 # Number of floating point alu accesses
529 system.cpu.iew.lsq.thread0.forwLoads 441760 # Number of loads that had data forwarded from stores
530 system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
531 system.cpu.iew.lsq.thread0.squashedLoads 6903463 # Number of loads squashed
532 system.cpu.iew.lsq.thread0.ignoredResponses 6716 # Number of memory responses ignored because the instruction is squashed
533 system.cpu.iew.lsq.thread0.memOrderViolation 6442 # Number of memory ordering violations
534 system.cpu.iew.lsq.thread0.squashedStores 775701 # Number of stores squashed
535 system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
536 system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
537 system.cpu.iew.lsq.thread0.rescheduledLoads 2 # Number of loads that were rescheduled
538 system.cpu.iew.lsq.thread0.cacheBlocked 31606 # Number of times an access to memory failed due to the cache being blocked
539 system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
540 system.cpu.iew.iewSquashCycles 3897969 # Number of cycles IEW is squashing
541 system.cpu.iew.iewBlockCycles 957023 # Number of cycles IEW is blocking
542 system.cpu.iew.iewUnblockCycles 126637 # Number of cycles IEW is unblocking
543 system.cpu.iew.iewDispatchedInsts 118191644 # Number of instructions dispatched to IQ
544 system.cpu.iew.iewDispSquashedInsts 310003 # Number of squashed instructions skipped by dispatch
545 system.cpu.iew.iewDispLoadInsts 29477429 # Number of dispatched load instructions
546 system.cpu.iew.iewDispStoreInsts 5520545 # Number of dispatched store instructions
547 system.cpu.iew.iewDispNonSpecInsts 4612 # Number of dispatched non-speculative instructions
548 system.cpu.iew.iewIQFullEvents 65722 # Number of times the IQ has become full, causing a stall
549 system.cpu.iew.iewLSQFullEvents 6738 # Number of times the LSQ has become full, causing a stall
550 system.cpu.iew.memOrderViolationEvents 6442 # Number of memory order violations
551 system.cpu.iew.predictedTakenIncorrect 447212 # Number of branches that were predicted taken incorrectly
552 system.cpu.iew.predictedNotTakenIncorrect 446019 # Number of branches that were predicted not taken incorrectly
553 system.cpu.iew.branchMispredicts 893231 # Number of branch mispredicts detected at execute
554 system.cpu.iew.iewExecutedInsts 104191675 # Number of executed instructions
555 system.cpu.iew.iewExecLoadInsts 25292948 # Number of load instructions executed
556 system.cpu.iew.iewExecSquashedInsts 975767 # Number of squashed instructions skipped in execute
557 system.cpu.iew.exec_swp 0 # number of swp insts executed
558 system.cpu.iew.exec_nop 12696 # number of nop insts executed
559 system.cpu.iew.exec_refs 30349771 # number of memory reference insts executed
560 system.cpu.iew.exec_branches 21326762 # Number of branches executed
561 system.cpu.iew.exec_stores 5056823 # Number of stores executed
562 system.cpu.iew.exec_rate 1.935827 # Inst execution rate
563 system.cpu.iew.wb_sent 102970942 # cumulative count of insts sent to commit
564 system.cpu.iew.wb_count 102691851 # cumulative count of insts written-back
565 system.cpu.iew.wb_producers 62249009 # num instructions producing a value
566 system.cpu.iew.wb_consumers 104309545 # num instructions consuming a value
567 system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
568 system.cpu.iew.wb_rate 1.907961 # insts written-back per cycle
569 system.cpu.iew.wb_fanout 0.596772 # average fanout of values written-back
570 system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
571 system.cpu.commit.commitSquashedInsts 26941617 # The number of squashed insts skipped by commit
572 system.cpu.commit.commitNonSpecStalls 8218 # The number of times commit has been forced to stall to communicate backwards
573 system.cpu.commit.branchMispredicts 834570 # The number of times a branch was mispredicted
574 system.cpu.commit.committed_per_cycle::samples 49533494 # Number of insts commited each cycle
575 system.cpu.commit.committed_per_cycle::mean 1.842248 # Number of insts commited each cycle
576 system.cpu.commit.committed_per_cycle::stdev 2.540561 # Number of insts commited each cycle
577 system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
578 system.cpu.commit.committed_per_cycle::0 20042935 40.46% 40.46% # Number of insts commited each cycle
579 system.cpu.commit.committed_per_cycle::1 13146551 26.54% 67.00% # Number of insts commited each cycle
580 system.cpu.commit.committed_per_cycle::2 4167484 8.41% 75.42% # Number of insts commited each cycle
581 system.cpu.commit.committed_per_cycle::3 3431298 6.93% 82.34% # Number of insts commited each cycle
582 system.cpu.commit.committed_per_cycle::4 1535317 3.10% 85.44% # Number of insts commited each cycle
583 system.cpu.commit.committed_per_cycle::5 726626 1.47% 86.91% # Number of insts commited each cycle
584 system.cpu.commit.committed_per_cycle::6 954928 1.93% 88.84% # Number of insts commited each cycle
585 system.cpu.commit.committed_per_cycle::7 253259 0.51% 89.35% # Number of insts commited each cycle
586 system.cpu.commit.committed_per_cycle::8 5275096 10.65% 100.00% # Number of insts commited each cycle
587 system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
588 system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
589 system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
590 system.cpu.commit.committed_per_cycle::total 49533494 # Number of insts commited each cycle
591 system.cpu.commit.committedInsts 90602407 # Number of instructions committed
592 system.cpu.commit.committedOps 91252960 # Number of ops (including micro ops) committed
593 system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
594 system.cpu.commit.refs 27318810 # Number of memory references committed
595 system.cpu.commit.loads 22573966 # Number of loads committed
596 system.cpu.commit.membars 3888 # Number of memory barriers committed
597 system.cpu.commit.branches 18732304 # Number of branches committed
598 system.cpu.commit.fp_insts 48 # Number of committed floating point instructions.
599 system.cpu.commit.int_insts 72525674 # Number of committed integer instructions.
600 system.cpu.commit.function_calls 56148 # Number of function calls committed.
601 system.cpu.commit.bw_lim_events 5275096 # number cycles where commit BW limit reached
602 system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
603 system.cpu.rob.rob_reads 162447241 # The number of ROB reads
604 system.cpu.rob.rob_writes 240306728 # The number of ROB writes
605 system.cpu.timesIdled 46009 # Number of times that the entire CPU went into an idle state and unscheduled itself
606 system.cpu.idleCycles 391364 # Total number of cycles that the CPU has spent unscheduled due to idling
607 system.cpu.committedInsts 90589798 # Number of Instructions Simulated
608 system.cpu.committedOps 91240351 # Number of Ops (including micro ops) Simulated
609 system.cpu.committedInsts_total 90589798 # Number of Instructions Simulated
610 system.cpu.cpi 0.594138 # CPI: Cycles Per Instruction
611 system.cpu.cpi_total 0.594138 # CPI: Total CPI of All Threads
612 system.cpu.ipc 1.683111 # IPC: Instructions Per Cycle
613 system.cpu.ipc_total 1.683111 # IPC: Total IPC of All Threads
614 system.cpu.int_regfile_reads 495604527 # number of integer regfile reads
615 system.cpu.int_regfile_writes 120552200 # number of integer regfile writes
616 system.cpu.fp_regfile_reads 148 # number of floating regfile reads
617 system.cpu.fp_regfile_writes 360 # number of floating regfile writes
618 system.cpu.misc_regfile_reads 29090078 # number of misc regfile reads
619 system.cpu.misc_regfile_writes 7784 # number of misc regfile writes
620 system.cpu.toL2Bus.throughput 4497665284 # Throughput (bytes/s)
621 system.cpu.toL2Bus.trans_dist::ReadReq 904635 # Transaction distribution
622 system.cpu.toL2Bus.trans_dist::ReadResp 904635 # Transaction distribution
623 system.cpu.toL2Bus.trans_dist::Writeback 942892 # Transaction distribution
624 system.cpu.toL2Bus.trans_dist::UpgradeReq 2 # Transaction distribution
625 system.cpu.toL2Bus.trans_dist::UpgradeResp 2 # Transaction distribution
626 system.cpu.toL2Bus.trans_dist::ReadExReq 43700 # Transaction distribution
627 system.cpu.toL2Bus.trans_dist::ReadExResp 43700 # Transaction distribution
628 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1472 # Packet count per connected master and slave (bytes)
629 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2838092 # Packet count per connected master and slave (bytes)
630 system.cpu.toL2Bus.pkt_count::total 2839564 # Packet count per connected master and slave (bytes)
631 system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 47040 # Cumulative packet size per connected master and slave (bytes)
632 system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 120991360 # Cumulative packet size per connected master and slave (bytes)
633 system.cpu.toL2Bus.tot_pkt_size::total 121038400 # Cumulative packet size per connected master and slave (bytes)
634 system.cpu.toL2Bus.data_through_bus 121038400 # Total data (bytes)
635 system.cpu.toL2Bus.snoop_data_through_bus 128 # Total snoop data (bytes)
636 system.cpu.toL2Bus.reqLayer0.occupancy 1888506500 # Layer occupancy (ticks)
637 system.cpu.toL2Bus.reqLayer0.utilization 7.0 # Layer utilization (%)
638 system.cpu.toL2Bus.respLayer0.occupancy 1222499 # Layer occupancy (ticks)
639 system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
640 system.cpu.toL2Bus.respLayer1.occupancy 1424110491 # Layer occupancy (ticks)
641 system.cpu.toL2Bus.respLayer1.utilization 5.3 # Layer utilization (%)
642 system.cpu.icache.tags.replacements 3 # number of replacements
643 system.cpu.icache.tags.tagsinuse 632.612747 # Cycle average of tags in use
644 system.cpu.icache.tags.total_refs 13844401 # Total number of references to valid blocks.
645 system.cpu.icache.tags.sampled_refs 735 # Sample count of references to valid blocks.
646 system.cpu.icache.tags.avg_refs 18835.919728 # Average number of references to valid blocks.
647 system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
648 system.cpu.icache.tags.occ_blocks::cpu.inst 632.612747 # Average occupied blocks per requestor
649 system.cpu.icache.tags.occ_percent::cpu.inst 0.308893 # Average percentage of cache occupancy
650 system.cpu.icache.tags.occ_percent::total 0.308893 # Average percentage of cache occupancy
651 system.cpu.icache.ReadReq_hits::cpu.inst 13844401 # number of ReadReq hits
652 system.cpu.icache.ReadReq_hits::total 13844401 # number of ReadReq hits
653 system.cpu.icache.demand_hits::cpu.inst 13844401 # number of demand (read+write) hits
654 system.cpu.icache.demand_hits::total 13844401 # number of demand (read+write) hits
655 system.cpu.icache.overall_hits::cpu.inst 13844401 # number of overall hits
656 system.cpu.icache.overall_hits::total 13844401 # number of overall hits
657 system.cpu.icache.ReadReq_misses::cpu.inst 991 # number of ReadReq misses
658 system.cpu.icache.ReadReq_misses::total 991 # number of ReadReq misses
659 system.cpu.icache.demand_misses::cpu.inst 991 # number of demand (read+write) misses
660 system.cpu.icache.demand_misses::total 991 # number of demand (read+write) misses
661 system.cpu.icache.overall_misses::cpu.inst 991 # number of overall misses
662 system.cpu.icache.overall_misses::total 991 # number of overall misses
663 system.cpu.icache.ReadReq_miss_latency::cpu.inst 67770748 # number of ReadReq miss cycles
664 system.cpu.icache.ReadReq_miss_latency::total 67770748 # number of ReadReq miss cycles
665 system.cpu.icache.demand_miss_latency::cpu.inst 67770748 # number of demand (read+write) miss cycles
666 system.cpu.icache.demand_miss_latency::total 67770748 # number of demand (read+write) miss cycles
667 system.cpu.icache.overall_miss_latency::cpu.inst 67770748 # number of overall miss cycles
668 system.cpu.icache.overall_miss_latency::total 67770748 # number of overall miss cycles
669 system.cpu.icache.ReadReq_accesses::cpu.inst 13845392 # number of ReadReq accesses(hits+misses)
670 system.cpu.icache.ReadReq_accesses::total 13845392 # number of ReadReq accesses(hits+misses)
671 system.cpu.icache.demand_accesses::cpu.inst 13845392 # number of demand (read+write) accesses
672 system.cpu.icache.demand_accesses::total 13845392 # number of demand (read+write) accesses
673 system.cpu.icache.overall_accesses::cpu.inst 13845392 # number of overall (read+write) accesses
674 system.cpu.icache.overall_accesses::total 13845392 # number of overall (read+write) accesses
675 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000072 # miss rate for ReadReq accesses
676 system.cpu.icache.ReadReq_miss_rate::total 0.000072 # miss rate for ReadReq accesses
677 system.cpu.icache.demand_miss_rate::cpu.inst 0.000072 # miss rate for demand accesses
678 system.cpu.icache.demand_miss_rate::total 0.000072 # miss rate for demand accesses
679 system.cpu.icache.overall_miss_rate::cpu.inst 0.000072 # miss rate for overall accesses
680 system.cpu.icache.overall_miss_rate::total 0.000072 # miss rate for overall accesses
681 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68386.224016 # average ReadReq miss latency
682 system.cpu.icache.ReadReq_avg_miss_latency::total 68386.224016 # average ReadReq miss latency
683 system.cpu.icache.demand_avg_miss_latency::cpu.inst 68386.224016 # average overall miss latency
684 system.cpu.icache.demand_avg_miss_latency::total 68386.224016 # average overall miss latency
685 system.cpu.icache.overall_avg_miss_latency::cpu.inst 68386.224016 # average overall miss latency
686 system.cpu.icache.overall_avg_miss_latency::total 68386.224016 # average overall miss latency
687 system.cpu.icache.blocked_cycles::no_mshrs 651 # number of cycles access was blocked
688 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
689 system.cpu.icache.blocked::no_mshrs 11 # number of cycles access was blocked
690 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
691 system.cpu.icache.avg_blocked_cycles::no_mshrs 59.181818 # average number of cycles each access was blocked
692 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
693 system.cpu.icache.fast_writes 0 # number of fast writes performed
694 system.cpu.icache.cache_copies 0 # number of cache copies performed
695 system.cpu.icache.ReadReq_mshr_hits::cpu.inst 254 # number of ReadReq MSHR hits
696 system.cpu.icache.ReadReq_mshr_hits::total 254 # number of ReadReq MSHR hits
697 system.cpu.icache.demand_mshr_hits::cpu.inst 254 # number of demand (read+write) MSHR hits
698 system.cpu.icache.demand_mshr_hits::total 254 # number of demand (read+write) MSHR hits
699 system.cpu.icache.overall_mshr_hits::cpu.inst 254 # number of overall MSHR hits
700 system.cpu.icache.overall_mshr_hits::total 254 # number of overall MSHR hits
701 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 737 # number of ReadReq MSHR misses
702 system.cpu.icache.ReadReq_mshr_misses::total 737 # number of ReadReq MSHR misses
703 system.cpu.icache.demand_mshr_misses::cpu.inst 737 # number of demand (read+write) MSHR misses
704 system.cpu.icache.demand_mshr_misses::total 737 # number of demand (read+write) MSHR misses
705 system.cpu.icache.overall_mshr_misses::cpu.inst 737 # number of overall MSHR misses
706 system.cpu.icache.overall_mshr_misses::total 737 # number of overall MSHR misses
707 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 51712250 # number of ReadReq MSHR miss cycles
708 system.cpu.icache.ReadReq_mshr_miss_latency::total 51712250 # number of ReadReq MSHR miss cycles
709 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 51712250 # number of demand (read+write) MSHR miss cycles
710 system.cpu.icache.demand_mshr_miss_latency::total 51712250 # number of demand (read+write) MSHR miss cycles
711 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 51712250 # number of overall MSHR miss cycles
712 system.cpu.icache.overall_mshr_miss_latency::total 51712250 # number of overall MSHR miss cycles
713 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for ReadReq accesses
714 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000053 # mshr miss rate for ReadReq accesses
715 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for demand accesses
716 system.cpu.icache.demand_mshr_miss_rate::total 0.000053 # mshr miss rate for demand accesses
717 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for overall accesses
718 system.cpu.icache.overall_mshr_miss_rate::total 0.000053 # mshr miss rate for overall accesses
719 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 70165.875170 # average ReadReq mshr miss latency
720 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 70165.875170 # average ReadReq mshr miss latency
721 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 70165.875170 # average overall mshr miss latency
722 system.cpu.icache.demand_avg_mshr_miss_latency::total 70165.875170 # average overall mshr miss latency
723 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 70165.875170 # average overall mshr miss latency
724 system.cpu.icache.overall_avg_mshr_miss_latency::total 70165.875170 # average overall mshr miss latency
725 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
726 system.cpu.l2cache.tags.replacements 0 # number of replacements
727 system.cpu.l2cache.tags.tagsinuse 10730.950237 # Cycle average of tags in use
728 system.cpu.l2cache.tags.total_refs 1831391 # Total number of references to valid blocks.
729 system.cpu.l2cache.tags.sampled_refs 15501 # Sample count of references to valid blocks.
730 system.cpu.l2cache.tags.avg_refs 118.146636 # Average number of references to valid blocks.
731 system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
732 system.cpu.l2cache.tags.occ_blocks::writebacks 9880.493814 # Average occupied blocks per requestor
733 system.cpu.l2cache.tags.occ_blocks::cpu.inst 618.630242 # Average occupied blocks per requestor
734 system.cpu.l2cache.tags.occ_blocks::cpu.data 231.826182 # Average occupied blocks per requestor
735 system.cpu.l2cache.tags.occ_percent::writebacks 0.301529 # Average percentage of cache occupancy
736 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.018879 # Average percentage of cache occupancy
737 system.cpu.l2cache.tags.occ_percent::cpu.data 0.007075 # Average percentage of cache occupancy
738 system.cpu.l2cache.tags.occ_percent::total 0.327483 # Average percentage of cache occupancy
739 system.cpu.l2cache.ReadReq_hits::cpu.inst 24 # number of ReadReq hits
740 system.cpu.l2cache.ReadReq_hits::cpu.data 903618 # number of ReadReq hits
741 system.cpu.l2cache.ReadReq_hits::total 903642 # number of ReadReq hits
742 system.cpu.l2cache.Writeback_hits::writebacks 942892 # number of Writeback hits
743 system.cpu.l2cache.Writeback_hits::total 942892 # number of Writeback hits
744 system.cpu.l2cache.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits
745 system.cpu.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits
746 system.cpu.l2cache.ReadExReq_hits::cpu.data 29162 # number of ReadExReq hits
747 system.cpu.l2cache.ReadExReq_hits::total 29162 # number of ReadExReq hits
748 system.cpu.l2cache.demand_hits::cpu.inst 24 # number of demand (read+write) hits
749 system.cpu.l2cache.demand_hits::cpu.data 932780 # number of demand (read+write) hits
750 system.cpu.l2cache.demand_hits::total 932804 # number of demand (read+write) hits
751 system.cpu.l2cache.overall_hits::cpu.inst 24 # number of overall hits
752 system.cpu.l2cache.overall_hits::cpu.data 932780 # number of overall hits
753 system.cpu.l2cache.overall_hits::total 932804 # number of overall hits
754 system.cpu.l2cache.ReadReq_misses::cpu.inst 711 # number of ReadReq misses
755 system.cpu.l2cache.ReadReq_misses::cpu.data 280 # number of ReadReq misses
756 system.cpu.l2cache.ReadReq_misses::total 991 # number of ReadReq misses
757 system.cpu.l2cache.UpgradeReq_misses::cpu.data 1 # number of UpgradeReq misses
758 system.cpu.l2cache.UpgradeReq_misses::total 1 # number of UpgradeReq misses
759 system.cpu.l2cache.ReadExReq_misses::cpu.data 14538 # number of ReadExReq misses
760 system.cpu.l2cache.ReadExReq_misses::total 14538 # number of ReadExReq misses
761 system.cpu.l2cache.demand_misses::cpu.inst 711 # number of demand (read+write) misses
762 system.cpu.l2cache.demand_misses::cpu.data 14818 # number of demand (read+write) misses
763 system.cpu.l2cache.demand_misses::total 15529 # number of demand (read+write) misses
764 system.cpu.l2cache.overall_misses::cpu.inst 711 # number of overall misses
765 system.cpu.l2cache.overall_misses::cpu.data 14818 # number of overall misses
766 system.cpu.l2cache.overall_misses::total 15529 # number of overall misses
767 system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 50729000 # number of ReadReq miss cycles
768 system.cpu.l2cache.ReadReq_miss_latency::cpu.data 21404500 # number of ReadReq miss cycles
769 system.cpu.l2cache.ReadReq_miss_latency::total 72133500 # number of ReadReq miss cycles
770 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 962429750 # number of ReadExReq miss cycles
771 system.cpu.l2cache.ReadExReq_miss_latency::total 962429750 # number of ReadExReq miss cycles
772 system.cpu.l2cache.demand_miss_latency::cpu.inst 50729000 # number of demand (read+write) miss cycles
773 system.cpu.l2cache.demand_miss_latency::cpu.data 983834250 # number of demand (read+write) miss cycles
774 system.cpu.l2cache.demand_miss_latency::total 1034563250 # number of demand (read+write) miss cycles
775 system.cpu.l2cache.overall_miss_latency::cpu.inst 50729000 # number of overall miss cycles
776 system.cpu.l2cache.overall_miss_latency::cpu.data 983834250 # number of overall miss cycles
777 system.cpu.l2cache.overall_miss_latency::total 1034563250 # number of overall miss cycles
778 system.cpu.l2cache.ReadReq_accesses::cpu.inst 735 # number of ReadReq accesses(hits+misses)
779 system.cpu.l2cache.ReadReq_accesses::cpu.data 903898 # number of ReadReq accesses(hits+misses)
780 system.cpu.l2cache.ReadReq_accesses::total 904633 # number of ReadReq accesses(hits+misses)
781 system.cpu.l2cache.Writeback_accesses::writebacks 942892 # number of Writeback accesses(hits+misses)
782 system.cpu.l2cache.Writeback_accesses::total 942892 # number of Writeback accesses(hits+misses)
783 system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2 # number of UpgradeReq accesses(hits+misses)
784 system.cpu.l2cache.UpgradeReq_accesses::total 2 # number of UpgradeReq accesses(hits+misses)
785 system.cpu.l2cache.ReadExReq_accesses::cpu.data 43700 # number of ReadExReq accesses(hits+misses)
786 system.cpu.l2cache.ReadExReq_accesses::total 43700 # number of ReadExReq accesses(hits+misses)
787 system.cpu.l2cache.demand_accesses::cpu.inst 735 # number of demand (read+write) accesses
788 system.cpu.l2cache.demand_accesses::cpu.data 947598 # number of demand (read+write) accesses
789 system.cpu.l2cache.demand_accesses::total 948333 # number of demand (read+write) accesses
790 system.cpu.l2cache.overall_accesses::cpu.inst 735 # number of overall (read+write) accesses
791 system.cpu.l2cache.overall_accesses::cpu.data 947598 # number of overall (read+write) accesses
792 system.cpu.l2cache.overall_accesses::total 948333 # number of overall (read+write) accesses
793 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.967347 # miss rate for ReadReq accesses
794 system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000310 # miss rate for ReadReq accesses
795 system.cpu.l2cache.ReadReq_miss_rate::total 0.001095 # miss rate for ReadReq accesses
796 system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.500000 # miss rate for UpgradeReq accesses
797 system.cpu.l2cache.UpgradeReq_miss_rate::total 0.500000 # miss rate for UpgradeReq accesses
798 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.332677 # miss rate for ReadExReq accesses
799 system.cpu.l2cache.ReadExReq_miss_rate::total 0.332677 # miss rate for ReadExReq accesses
800 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.967347 # miss rate for demand accesses
801 system.cpu.l2cache.demand_miss_rate::cpu.data 0.015637 # miss rate for demand accesses
802 system.cpu.l2cache.demand_miss_rate::total 0.016375 # miss rate for demand accesses
803 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.967347 # miss rate for overall accesses
804 system.cpu.l2cache.overall_miss_rate::cpu.data 0.015637 # miss rate for overall accesses
805 system.cpu.l2cache.overall_miss_rate::total 0.016375 # miss rate for overall accesses
806 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71348.804501 # average ReadReq miss latency
807 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76444.642857 # average ReadReq miss latency
808 system.cpu.l2cache.ReadReq_avg_miss_latency::total 72788.597376 # average ReadReq miss latency
809 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 66200.973311 # average ReadExReq miss latency
810 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66200.973311 # average ReadExReq miss latency
811 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71348.804501 # average overall miss latency
812 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 66394.537050 # average overall miss latency
813 system.cpu.l2cache.demand_avg_miss_latency::total 66621.369695 # average overall miss latency
814 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71348.804501 # average overall miss latency
815 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 66394.537050 # average overall miss latency
816 system.cpu.l2cache.overall_avg_miss_latency::total 66621.369695 # average overall miss latency
817 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
818 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
819 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
820 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
821 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
822 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
823 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
824 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
825 system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits
826 system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 10 # number of ReadReq MSHR hits
827 system.cpu.l2cache.ReadReq_mshr_hits::total 11 # number of ReadReq MSHR hits
828 system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
829 system.cpu.l2cache.demand_mshr_hits::cpu.data 10 # number of demand (read+write) MSHR hits
830 system.cpu.l2cache.demand_mshr_hits::total 11 # number of demand (read+write) MSHR hits
831 system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
832 system.cpu.l2cache.overall_mshr_hits::cpu.data 10 # number of overall MSHR hits
833 system.cpu.l2cache.overall_mshr_hits::total 11 # number of overall MSHR hits
834 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 710 # number of ReadReq MSHR misses
835 system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 270 # number of ReadReq MSHR misses
836 system.cpu.l2cache.ReadReq_mshr_misses::total 980 # number of ReadReq MSHR misses
837 system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1 # number of UpgradeReq MSHR misses
838 system.cpu.l2cache.UpgradeReq_mshr_misses::total 1 # number of UpgradeReq MSHR misses
839 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14538 # number of ReadExReq MSHR misses
840 system.cpu.l2cache.ReadExReq_mshr_misses::total 14538 # number of ReadExReq MSHR misses
841 system.cpu.l2cache.demand_mshr_misses::cpu.inst 710 # number of demand (read+write) MSHR misses
842 system.cpu.l2cache.demand_mshr_misses::cpu.data 14808 # number of demand (read+write) MSHR misses
843 system.cpu.l2cache.demand_mshr_misses::total 15518 # number of demand (read+write) MSHR misses
844 system.cpu.l2cache.overall_mshr_misses::cpu.inst 710 # number of overall MSHR misses
845 system.cpu.l2cache.overall_mshr_misses::cpu.data 14808 # number of overall MSHR misses
846 system.cpu.l2cache.overall_mshr_misses::total 15518 # number of overall MSHR misses
847 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 41786750 # number of ReadReq MSHR miss cycles
848 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 17438000 # number of ReadReq MSHR miss cycles
849 system.cpu.l2cache.ReadReq_mshr_miss_latency::total 59224750 # number of ReadReq MSHR miss cycles
850 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 10001 # number of UpgradeReq MSHR miss cycles
851 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 10001 # number of UpgradeReq MSHR miss cycles
852 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 780053750 # number of ReadExReq MSHR miss cycles
853 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 780053750 # number of ReadExReq MSHR miss cycles
854 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 41786750 # number of demand (read+write) MSHR miss cycles
855 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 797491750 # number of demand (read+write) MSHR miss cycles
856 system.cpu.l2cache.demand_mshr_miss_latency::total 839278500 # number of demand (read+write) MSHR miss cycles
857 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 41786750 # number of overall MSHR miss cycles
858 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 797491750 # number of overall MSHR miss cycles
859 system.cpu.l2cache.overall_mshr_miss_latency::total 839278500 # number of overall MSHR miss cycles
860 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.965986 # mshr miss rate for ReadReq accesses
861 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000299 # mshr miss rate for ReadReq accesses
862 system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001083 # mshr miss rate for ReadReq accesses
863 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for UpgradeReq accesses
864 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for UpgradeReq accesses
865 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.332677 # mshr miss rate for ReadExReq accesses
866 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.332677 # mshr miss rate for ReadExReq accesses
867 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.965986 # mshr miss rate for demand accesses
868 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015627 # mshr miss rate for demand accesses
869 system.cpu.l2cache.demand_mshr_miss_rate::total 0.016363 # mshr miss rate for demand accesses
870 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965986 # mshr miss rate for overall accesses
871 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015627 # mshr miss rate for overall accesses
872 system.cpu.l2cache.overall_mshr_miss_rate::total 0.016363 # mshr miss rate for overall accesses
873 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58854.577465 # average ReadReq mshr miss latency
874 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64585.185185 # average ReadReq mshr miss latency
875 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60433.418367 # average ReadReq mshr miss latency
876 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency
877 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency
878 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 53656.194112 # average ReadExReq mshr miss latency
879 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 53656.194112 # average ReadExReq mshr miss latency
880 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58854.577465 # average overall mshr miss latency
881 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53855.466640 # average overall mshr miss latency
882 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54084.192551 # average overall mshr miss latency
883 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58854.577465 # average overall mshr miss latency
884 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53855.466640 # average overall mshr miss latency
885 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54084.192551 # average overall mshr miss latency
886 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
887 system.cpu.dcache.tags.replacements 943502 # number of replacements
888 system.cpu.dcache.tags.tagsinuse 3671.733270 # Cycle average of tags in use
889 system.cpu.dcache.tags.total_refs 28144425 # Total number of references to valid blocks.
890 system.cpu.dcache.tags.sampled_refs 947598 # Sample count of references to valid blocks.
891 system.cpu.dcache.tags.avg_refs 29.700807 # Average number of references to valid blocks.
892 system.cpu.dcache.tags.warmup_cycle 8006035000 # Cycle when the warmup percentage was hit.
893 system.cpu.dcache.tags.occ_blocks::cpu.data 3671.733270 # Average occupied blocks per requestor
894 system.cpu.dcache.tags.occ_percent::cpu.data 0.896419 # Average percentage of cache occupancy
895 system.cpu.dcache.tags.occ_percent::total 0.896419 # Average percentage of cache occupancy
896 system.cpu.dcache.ReadReq_hits::cpu.data 23603772 # number of ReadReq hits
897 system.cpu.dcache.ReadReq_hits::total 23603772 # number of ReadReq hits
898 system.cpu.dcache.WriteReq_hits::cpu.data 4532846 # number of WriteReq hits
899 system.cpu.dcache.WriteReq_hits::total 4532846 # number of WriteReq hits
900 system.cpu.dcache.LoadLockedReq_hits::cpu.data 3913 # number of LoadLockedReq hits
901 system.cpu.dcache.LoadLockedReq_hits::total 3913 # number of LoadLockedReq hits
902 system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits
903 system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits
904 system.cpu.dcache.demand_hits::cpu.data 28136618 # number of demand (read+write) hits
905 system.cpu.dcache.demand_hits::total 28136618 # number of demand (read+write) hits
906 system.cpu.dcache.overall_hits::cpu.data 28136618 # number of overall hits
907 system.cpu.dcache.overall_hits::total 28136618 # number of overall hits
908 system.cpu.dcache.ReadReq_misses::cpu.data 1173981 # number of ReadReq misses
909 system.cpu.dcache.ReadReq_misses::total 1173981 # number of ReadReq misses
910 system.cpu.dcache.WriteReq_misses::cpu.data 202135 # number of WriteReq misses
911 system.cpu.dcache.WriteReq_misses::total 202135 # number of WriteReq misses
912 system.cpu.dcache.LoadLockedReq_misses::cpu.data 7 # number of LoadLockedReq misses
913 system.cpu.dcache.LoadLockedReq_misses::total 7 # number of LoadLockedReq misses
914 system.cpu.dcache.demand_misses::cpu.data 1376116 # number of demand (read+write) misses
915 system.cpu.dcache.demand_misses::total 1376116 # number of demand (read+write) misses
916 system.cpu.dcache.overall_misses::cpu.data 1376116 # number of overall misses
917 system.cpu.dcache.overall_misses::total 1376116 # number of overall misses
918 system.cpu.dcache.ReadReq_miss_latency::cpu.data 13894448479 # number of ReadReq miss cycles
919 system.cpu.dcache.ReadReq_miss_latency::total 13894448479 # number of ReadReq miss cycles
920 system.cpu.dcache.WriteReq_miss_latency::cpu.data 8458649331 # number of WriteReq miss cycles
921 system.cpu.dcache.WriteReq_miss_latency::total 8458649331 # number of WriteReq miss cycles
922 system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 251500 # number of LoadLockedReq miss cycles
923 system.cpu.dcache.LoadLockedReq_miss_latency::total 251500 # number of LoadLockedReq miss cycles
924 system.cpu.dcache.demand_miss_latency::cpu.data 22353097810 # number of demand (read+write) miss cycles
925 system.cpu.dcache.demand_miss_latency::total 22353097810 # number of demand (read+write) miss cycles
926 system.cpu.dcache.overall_miss_latency::cpu.data 22353097810 # number of overall miss cycles
927 system.cpu.dcache.overall_miss_latency::total 22353097810 # number of overall miss cycles
928 system.cpu.dcache.ReadReq_accesses::cpu.data 24777753 # number of ReadReq accesses(hits+misses)
929 system.cpu.dcache.ReadReq_accesses::total 24777753 # number of ReadReq accesses(hits+misses)
930 system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses)
931 system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses)
932 system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3920 # number of LoadLockedReq accesses(hits+misses)
933 system.cpu.dcache.LoadLockedReq_accesses::total 3920 # number of LoadLockedReq accesses(hits+misses)
934 system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses)
935 system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses)
936 system.cpu.dcache.demand_accesses::cpu.data 29512734 # number of demand (read+write) accesses
937 system.cpu.dcache.demand_accesses::total 29512734 # number of demand (read+write) accesses
938 system.cpu.dcache.overall_accesses::cpu.data 29512734 # number of overall (read+write) accesses
939 system.cpu.dcache.overall_accesses::total 29512734 # number of overall (read+write) accesses
940 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.047380 # miss rate for ReadReq accesses
941 system.cpu.dcache.ReadReq_miss_rate::total 0.047380 # miss rate for ReadReq accesses
942 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.042690 # miss rate for WriteReq accesses
943 system.cpu.dcache.WriteReq_miss_rate::total 0.042690 # miss rate for WriteReq accesses
944 system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001786 # miss rate for LoadLockedReq accesses
945 system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001786 # miss rate for LoadLockedReq accesses
946 system.cpu.dcache.demand_miss_rate::cpu.data 0.046628 # miss rate for demand accesses
947 system.cpu.dcache.demand_miss_rate::total 0.046628 # miss rate for demand accesses
948 system.cpu.dcache.overall_miss_rate::cpu.data 0.046628 # miss rate for overall accesses
949 system.cpu.dcache.overall_miss_rate::total 0.046628 # miss rate for overall accesses
950 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11835.326533 # average ReadReq miss latency
951 system.cpu.dcache.ReadReq_avg_miss_latency::total 11835.326533 # average ReadReq miss latency
952 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41846.534895 # average WriteReq miss latency
953 system.cpu.dcache.WriteReq_avg_miss_latency::total 41846.534895 # average WriteReq miss latency
954 system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 35928.571429 # average LoadLockedReq miss latency
955 system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 35928.571429 # average LoadLockedReq miss latency
956 system.cpu.dcache.demand_avg_miss_latency::cpu.data 16243.614499 # average overall miss latency
957 system.cpu.dcache.demand_avg_miss_latency::total 16243.614499 # average overall miss latency
958 system.cpu.dcache.overall_avg_miss_latency::cpu.data 16243.614499 # average overall miss latency
959 system.cpu.dcache.overall_avg_miss_latency::total 16243.614499 # average overall miss latency
960 system.cpu.dcache.blocked_cycles::no_mshrs 154190 # number of cycles access was blocked
961 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
962 system.cpu.dcache.blocked::no_mshrs 23957 # number of cycles access was blocked
963 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
964 system.cpu.dcache.avg_blocked_cycles::no_mshrs 6.436115 # average number of cycles each access was blocked
965 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
966 system.cpu.dcache.fast_writes 0 # number of fast writes performed
967 system.cpu.dcache.cache_copies 0 # number of cache copies performed
968 system.cpu.dcache.writebacks::writebacks 942892 # number of writebacks
969 system.cpu.dcache.writebacks::total 942892 # number of writebacks
970 system.cpu.dcache.ReadReq_mshr_hits::cpu.data 270066 # number of ReadReq MSHR hits
971 system.cpu.dcache.ReadReq_mshr_hits::total 270066 # number of ReadReq MSHR hits
972 system.cpu.dcache.WriteReq_mshr_hits::cpu.data 158450 # number of WriteReq MSHR hits
973 system.cpu.dcache.WriteReq_mshr_hits::total 158450 # number of WriteReq MSHR hits
974 system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 7 # number of LoadLockedReq MSHR hits
975 system.cpu.dcache.LoadLockedReq_mshr_hits::total 7 # number of LoadLockedReq MSHR hits
976 system.cpu.dcache.demand_mshr_hits::cpu.data 428516 # number of demand (read+write) MSHR hits
977 system.cpu.dcache.demand_mshr_hits::total 428516 # number of demand (read+write) MSHR hits
978 system.cpu.dcache.overall_mshr_hits::cpu.data 428516 # number of overall MSHR hits
979 system.cpu.dcache.overall_mshr_hits::total 428516 # number of overall MSHR hits
980 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 903915 # number of ReadReq MSHR misses
981 system.cpu.dcache.ReadReq_mshr_misses::total 903915 # number of ReadReq MSHR misses
982 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43685 # number of WriteReq MSHR misses
983 system.cpu.dcache.WriteReq_mshr_misses::total 43685 # number of WriteReq MSHR misses
984 system.cpu.dcache.demand_mshr_misses::cpu.data 947600 # number of demand (read+write) MSHR misses
985 system.cpu.dcache.demand_mshr_misses::total 947600 # number of demand (read+write) MSHR misses
986 system.cpu.dcache.overall_mshr_misses::cpu.data 947600 # number of overall MSHR misses
987 system.cpu.dcache.overall_mshr_misses::total 947600 # number of overall MSHR misses
988 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9994483010 # number of ReadReq MSHR miss cycles
989 system.cpu.dcache.ReadReq_mshr_miss_latency::total 9994483010 # number of ReadReq MSHR miss cycles
990 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1318924416 # number of WriteReq MSHR miss cycles
991 system.cpu.dcache.WriteReq_mshr_miss_latency::total 1318924416 # number of WriteReq MSHR miss cycles
992 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11313407426 # number of demand (read+write) MSHR miss cycles
993 system.cpu.dcache.demand_mshr_miss_latency::total 11313407426 # number of demand (read+write) MSHR miss cycles
994 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11313407426 # number of overall MSHR miss cycles
995 system.cpu.dcache.overall_mshr_miss_latency::total 11313407426 # number of overall MSHR miss cycles
996 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036481 # mshr miss rate for ReadReq accesses
997 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036481 # mshr miss rate for ReadReq accesses
998 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009226 # mshr miss rate for WriteReq accesses
999 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009226 # mshr miss rate for WriteReq accesses
1000 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032108 # mshr miss rate for demand accesses
1001 system.cpu.dcache.demand_mshr_miss_rate::total 0.032108 # mshr miss rate for demand accesses
1002 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032108 # mshr miss rate for overall accesses
1003 system.cpu.dcache.overall_mshr_miss_rate::total 0.032108 # mshr miss rate for overall accesses
1004 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11056.883678 # average ReadReq mshr miss latency
1005 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11056.883678 # average ReadReq mshr miss latency
1006 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30191.700034 # average WriteReq mshr miss latency
1007 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30191.700034 # average WriteReq mshr miss latency
1008 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11939.011636 # average overall mshr miss latency
1009 system.cpu.dcache.demand_avg_mshr_miss_latency::total 11939.011636 # average overall mshr miss latency
1010 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11939.011636 # average overall mshr miss latency
1011 system.cpu.dcache.overall_avg_mshr_miss_latency::total 11939.011636 # average overall mshr miss latency
1012 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1014 ---------- End Simulation Statistics ----------
projects / gem5.git / blob