2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.026781 # Number of seconds simulated
4 sim_ticks 26780899500 # Number of ticks simulated
5 final_tick 26780899500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 55932 # Simulator instruction rate (inst/s)
8 host_op_rate 56334 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 16535050 # Simulator tick rate (ticks/s)
10 host_mem_usage 421208 # Number of bytes of host memory used
11 host_seconds 1619.64 # Real time elapsed on the host
12 sim_insts 90589798 # Number of instructions simulated
13 sim_ops 91240351 # Number of ops (including micro ops) simulated
14 system.physmem.bytes_read::cpu.inst 44992 # Number of bytes read from this memory
15 system.physmem.bytes_read::cpu.data 947648 # Number of bytes read from this memory
16 system.physmem.bytes_read::total 992640 # Number of bytes read from this memory
17 system.physmem.bytes_inst_read::cpu.inst 44992 # Number of instructions bytes read from this memory
18 system.physmem.bytes_inst_read::total 44992 # Number of instructions bytes read from this memory
19 system.physmem.num_reads::cpu.inst 703 # Number of read requests responded to by this memory
20 system.physmem.num_reads::cpu.data 14807 # Number of read requests responded to by this memory
21 system.physmem.num_reads::total 15510 # Number of read requests responded to by this memory
22 system.physmem.bw_read::cpu.inst 1680003 # Total read bandwidth from this memory (bytes/s)
23 system.physmem.bw_read::cpu.data 35385219 # Total read bandwidth from this memory (bytes/s)
24 system.physmem.bw_read::total 37065223 # Total read bandwidth from this memory (bytes/s)
25 system.physmem.bw_inst_read::cpu.inst 1680003 # Instruction read bandwidth from this memory (bytes/s)
26 system.physmem.bw_inst_read::total 1680003 # Instruction read bandwidth from this memory (bytes/s)
27 system.physmem.bw_total::cpu.inst 1680003 # Total bandwidth to/from this memory (bytes/s)
28 system.physmem.bw_total::cpu.data 35385219 # Total bandwidth to/from this memory (bytes/s)
29 system.physmem.bw_total::total 37065223 # Total bandwidth to/from this memory (bytes/s)
30 system.physmem.readReqs 15510 # Total number of read requests seen
31 system.physmem.writeReqs 0 # Total number of write requests seen
32 system.physmem.cpureqs 15513 # Reqs generatd by CPU via cache - shady
33 system.physmem.bytesRead 992640 # Total number of bytes read from memory
34 system.physmem.bytesWritten 0 # Total number of bytes written to memory
35 system.physmem.bytesConsumedRd 992640 # bytesRead derated as per pkt->getSize()
36 system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
37 system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
38 system.physmem.neitherReadNorWrite 3 # Reqs where no action is needed
39 system.physmem.perBankRdReqs::0 996 # Track reads on a per bank basis
40 system.physmem.perBankRdReqs::1 960 # Track reads on a per bank basis
41 system.physmem.perBankRdReqs::2 998 # Track reads on a per bank basis
42 system.physmem.perBankRdReqs::3 1012 # Track reads on a per bank basis
43 system.physmem.perBankRdReqs::4 996 # Track reads on a per bank basis
44 system.physmem.perBankRdReqs::5 1010 # Track reads on a per bank basis
45 system.physmem.perBankRdReqs::6 925 # Track reads on a per bank basis
46 system.physmem.perBankRdReqs::7 882 # Track reads on a per bank basis
47 system.physmem.perBankRdReqs::8 885 # Track reads on a per bank basis
48 system.physmem.perBankRdReqs::9 951 # Track reads on a per bank basis
49 system.physmem.perBankRdReqs::10 993 # Track reads on a per bank basis
50 system.physmem.perBankRdReqs::11 1001 # Track reads on a per bank basis
51 system.physmem.perBankRdReqs::12 966 # Track reads on a per bank basis
52 system.physmem.perBankRdReqs::13 968 # Track reads on a per bank basis
53 system.physmem.perBankRdReqs::14 968 # Track reads on a per bank basis
54 system.physmem.perBankRdReqs::15 999 # Track reads on a per bank basis
55 system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
56 system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
57 system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
58 system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
59 system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
60 system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
61 system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
62 system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
63 system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
64 system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
65 system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
66 system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
67 system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
68 system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
69 system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
70 system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
71 system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
72 system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
73 system.physmem.totGap 26780729500 # Total gap between requests
74 system.physmem.readPktSize::0 0 # Categorize read packet sizes
75 system.physmem.readPktSize::1 0 # Categorize read packet sizes
76 system.physmem.readPktSize::2 0 # Categorize read packet sizes
77 system.physmem.readPktSize::3 0 # Categorize read packet sizes
78 system.physmem.readPktSize::4 0 # Categorize read packet sizes
79 system.physmem.readPktSize::5 0 # Categorize read packet sizes
80 system.physmem.readPktSize::6 15510 # Categorize read packet sizes
81 system.physmem.writePktSize::0 0 # Categorize write packet sizes
82 system.physmem.writePktSize::1 0 # Categorize write packet sizes
83 system.physmem.writePktSize::2 0 # Categorize write packet sizes
84 system.physmem.writePktSize::3 0 # Categorize write packet sizes
85 system.physmem.writePktSize::4 0 # Categorize write packet sizes
86 system.physmem.writePktSize::5 0 # Categorize write packet sizes
87 system.physmem.writePktSize::6 0 # Categorize write packet sizes
88 system.physmem.rdQLenPdf::0 10153 # What read queue length does an incoming req see
89 system.physmem.rdQLenPdf::1 5074 # What read queue length does an incoming req see
90 system.physmem.rdQLenPdf::2 253 # What read queue length does an incoming req see
91 system.physmem.rdQLenPdf::3 19 # What read queue length does an incoming req see
92 system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see
93 system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see
94 system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
95 system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
96 system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
97 system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
98 system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
99 system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
100 system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
101 system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
102 system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
103 system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
104 system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
105 system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
106 system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
107 system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
108 system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
109 system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
110 system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
111 system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
112 system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
113 system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
114 system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
115 system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
116 system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
117 system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
118 system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
119 system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
120 system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
121 system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
122 system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
123 system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
124 system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
125 system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
126 system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
127 system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
128 system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
129 system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
130 system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
131 system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
132 system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
133 system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
134 system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
135 system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
136 system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
137 system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
138 system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
139 system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
140 system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
141 system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
142 system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
143 system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
144 system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
145 system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
146 system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
147 system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
148 system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
149 system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
150 system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
151 system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
152 system.physmem.totQLat 54693250 # Total cycles spent in queuing delays
153 system.physmem.totMemAccLat 313977000 # Sum of mem lat for all requests
154 system.physmem.totBusLat 77550000 # Total cycles spent in databus access
155 system.physmem.totBankLat 181733750 # Total cycles spent in bank access
156 system.physmem.avgQLat 3526.32 # Average queueing delay per request
157 system.physmem.avgBankLat 11717.20 # Average bank access latency per request
158 system.physmem.avgBusLat 5000.00 # Average bus latency per request
159 system.physmem.avgMemAccLat 20243.52 # Average memory access latency
160 system.physmem.avgRdBW 37.07 # Average achieved read bandwidth in MB/s
161 system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
162 system.physmem.avgConsumedRdBW 37.07 # Average consumed read bandwidth in MB/s
163 system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
164 system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
165 system.physmem.busUtil 0.29 # Data bus utilization in percentage
166 system.physmem.avgRdQLen 0.01 # Average read queue length over time
167 system.physmem.avgWrQLen 0.00 # Average write queue length over time
168 system.physmem.readRowHits 14776 # Number of row buffer hits during reads
169 system.physmem.writeRowHits 0 # Number of row buffer hits during writes
170 system.physmem.readRowHitRate 95.27 # Row buffer hit rate for reads
171 system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
172 system.physmem.avgGap 1726675.02 # Average gap between requests
173 system.cpu.branchPred.lookups 26686067 # Number of BP lookups
174 system.cpu.branchPred.condPredicted 22003641 # Number of conditional branches predicted
175 system.cpu.branchPred.condIncorrect 842721 # Number of conditional branches incorrect
176 system.cpu.branchPred.BTBLookups 11370784 # Number of BTB lookups
177 system.cpu.branchPred.BTBHits 11281397 # Number of BTB hits
178 system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
179 system.cpu.branchPred.BTBHitPct 99.213889 # BTB Hit Percentage
180 system.cpu.branchPred.usedRAS 70454 # Number of times the RAS was used to get a target.
181 system.cpu.branchPred.RASInCorrect 189 # Number of incorrect RAS predictions.
182 system.cpu.dtb.inst_hits 0 # ITB inst hits
183 system.cpu.dtb.inst_misses 0 # ITB inst misses
184 system.cpu.dtb.read_hits 0 # DTB read hits
185 system.cpu.dtb.read_misses 0 # DTB read misses
186 system.cpu.dtb.write_hits 0 # DTB write hits
187 system.cpu.dtb.write_misses 0 # DTB write misses
188 system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
189 system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
190 system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
191 system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
192 system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
193 system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
194 system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
195 system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
196 system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
197 system.cpu.dtb.read_accesses 0 # DTB read accesses
198 system.cpu.dtb.write_accesses 0 # DTB write accesses
199 system.cpu.dtb.inst_accesses 0 # ITB inst accesses
200 system.cpu.dtb.hits 0 # DTB hits
201 system.cpu.dtb.misses 0 # DTB misses
202 system.cpu.dtb.accesses 0 # DTB accesses
203 system.cpu.itb.inst_hits 0 # ITB inst hits
204 system.cpu.itb.inst_misses 0 # ITB inst misses
205 system.cpu.itb.read_hits 0 # DTB read hits
206 system.cpu.itb.read_misses 0 # DTB read misses
207 system.cpu.itb.write_hits 0 # DTB write hits
208 system.cpu.itb.write_misses 0 # DTB write misses
209 system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
210 system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
211 system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
212 system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
213 system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
214 system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
215 system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
216 system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
217 system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
218 system.cpu.itb.read_accesses 0 # DTB read accesses
219 system.cpu.itb.write_accesses 0 # DTB write accesses
220 system.cpu.itb.inst_accesses 0 # ITB inst accesses
221 system.cpu.itb.hits 0 # DTB hits
222 system.cpu.itb.misses 0 # DTB misses
223 system.cpu.itb.accesses 0 # DTB accesses
224 system.cpu.workload.num_syscalls 442 # Number of system calls
225 system.cpu.numCycles 53561800 # number of cpu cycles simulated
226 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
227 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
228 system.cpu.fetch.icacheStallCycles 14175164 # Number of cycles fetch is stalled on an Icache miss
229 system.cpu.fetch.Insts 127899633 # Number of instructions fetch has processed
230 system.cpu.fetch.Branches 26686067 # Number of branches that fetch encountered
231 system.cpu.fetch.predictedBranches 11351851 # Number of branches that fetch has predicted taken
232 system.cpu.fetch.Cycles 24037657 # Number of cycles fetch has run and was not squashing or blocked
233 system.cpu.fetch.SquashCycles 4765030 # Number of cycles fetch has spent squashing
234 system.cpu.fetch.BlockedCycles 11217249 # Number of cycles fetch has spent blocked
235 system.cpu.fetch.MiscStallCycles 94 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
236 system.cpu.fetch.PendingTrapStallCycles 11 # Number of stall cycles due to pending traps
237 system.cpu.fetch.IcacheWaitRetryStallCycles 9 # Number of stall cycles due to full MSHR
238 system.cpu.fetch.CacheLines 13847383 # Number of cache lines fetched
239 system.cpu.fetch.IcacheSquashes 331199 # Number of outstanding Icache misses that were squashed
240 system.cpu.fetch.rateDist::samples 53336140 # Number of instructions fetched each cycle (Total)
241 system.cpu.fetch.rateDist::mean 2.414591 # Number of instructions fetched each cycle (Total)
242 system.cpu.fetch.rateDist::stdev 3.216158 # Number of instructions fetched each cycle (Total)
243 system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
244 system.cpu.fetch.rateDist::0 29336778 55.00% 55.00% # Number of instructions fetched each cycle (Total)
245 system.cpu.fetch.rateDist::1 3388806 6.35% 61.36% # Number of instructions fetched each cycle (Total)
246 system.cpu.fetch.rateDist::2 2028790 3.80% 65.16% # Number of instructions fetched each cycle (Total)
247 system.cpu.fetch.rateDist::3 1556293 2.92% 68.08% # Number of instructions fetched each cycle (Total)
248 system.cpu.fetch.rateDist::4 1665637 3.12% 71.20% # Number of instructions fetched each cycle (Total)
249 system.cpu.fetch.rateDist::5 2919109 5.47% 76.67% # Number of instructions fetched each cycle (Total)
250 system.cpu.fetch.rateDist::6 1511505 2.83% 79.51% # Number of instructions fetched each cycle (Total)
251 system.cpu.fetch.rateDist::7 1091219 2.05% 81.55% # Number of instructions fetched each cycle (Total)
252 system.cpu.fetch.rateDist::8 9838003 18.45% 100.00% # Number of instructions fetched each cycle (Total)
253 system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
254 system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
255 system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
256 system.cpu.fetch.rateDist::total 53336140 # Number of instructions fetched each cycle (Total)
257 system.cpu.fetch.branchRate 0.498229 # Number of branch fetches per cycle
258 system.cpu.fetch.rate 2.387889 # Number of inst fetches per cycle
259 system.cpu.decode.IdleCycles 16937190 # Number of cycles decode is idle
260 system.cpu.decode.BlockedCycles 9066542 # Number of cycles decode is blocked
261 system.cpu.decode.RunCycles 22437695 # Number of cycles decode is running
262 system.cpu.decode.UnblockCycles 997386 # Number of cycles decode is unblocking
263 system.cpu.decode.SquashCycles 3897327 # Number of cycles decode is squashing
264 system.cpu.decode.BranchResolved 4443416 # Number of times decode resolved a branch
265 system.cpu.decode.BranchMispred 8715 # Number of times decode detected a branch misprediction
266 system.cpu.decode.DecodedInsts 126080182 # Number of instructions handled by decode
267 system.cpu.decode.SquashedInsts 42547 # Number of squashed instructions handled by decode
268 system.cpu.rename.SquashCycles 3897327 # Number of cycles rename is squashing
269 system.cpu.rename.IdleCycles 18717098 # Number of cycles rename is idle
270 system.cpu.rename.BlockCycles 3539811 # Number of cycles rename is blocking
271 system.cpu.rename.serializeStallCycles 156330 # count of cycles rename stalled for serializing inst
272 system.cpu.rename.RunCycles 21553550 # Number of cycles rename is running
273 system.cpu.rename.UnblockCycles 5472024 # Number of cycles rename is unblocking
274 system.cpu.rename.RenamedInsts 123163469 # Number of instructions processed by rename
275 system.cpu.rename.ROBFullEvents 22 # Number of times rename has blocked due to ROB full
276 system.cpu.rename.IQFullEvents 421860 # Number of times rename has blocked due to IQ full
277 system.cpu.rename.LSQFullEvents 4589739 # Number of times rename has blocked due to LSQ full
278 system.cpu.rename.FullRegisterEvents 1294 # Number of times there has been no free registers
279 system.cpu.rename.RenamedOperands 143620029 # Number of destination operands rename has renamed
280 system.cpu.rename.RenameLookups 536487458 # Number of register rename lookups that rename has made
281 system.cpu.rename.int_rename_lookups 536482847 # Number of integer rename lookups
282 system.cpu.rename.fp_rename_lookups 4611 # Number of floating rename lookups
283 system.cpu.rename.CommittedMaps 107414186 # Number of HB maps that are committed
284 system.cpu.rename.UndoneMaps 36205843 # Number of HB maps that are undone due to squashing
285 system.cpu.rename.serializingInsts 4601 # count of serializing insts renamed
286 system.cpu.rename.tempSerializingInsts 4599 # count of temporary serializing insts renamed
287 system.cpu.rename.skidInsts 12496499 # count of insts added to the skid buffer
288 system.cpu.memDep0.insertedLoads 29481175 # Number of loads inserted to the mem dependence unit.
289 system.cpu.memDep0.insertedStores 5524207 # Number of stores inserted to the mem dependence unit.
290 system.cpu.memDep0.conflictingLoads 2105622 # Number of conflicting loads.
291 system.cpu.memDep0.conflictingStores 1304065 # Number of conflicting stores.
292 system.cpu.iq.iqInstsAdded 118177785 # Number of instructions added to the IQ (excludes non-spec)
293 system.cpu.iq.iqNonSpecInstsAdded 8472 # Number of non-speculative instructions added to the IQ
294 system.cpu.iq.iqInstsIssued 105170475 # Number of instructions issued
295 system.cpu.iq.iqSquashedInstsIssued 79267 # Number of squashed instructions issued
296 system.cpu.iq.iqSquashedInstsExamined 26750487 # Number of squashed instructions iterated over during squash; mainly for profiling
297 system.cpu.iq.iqSquashedOperandsExamined 65594281 # Number of squashed operands that are examined and possibly removed from graph
298 system.cpu.iq.iqSquashedNonSpecRemoved 254 # Number of squashed non-spec instructions that were removed
299 system.cpu.iq.issued_per_cycle::samples 53336140 # Number of insts issued each cycle
300 system.cpu.iq.issued_per_cycle::mean 1.971843 # Number of insts issued each cycle
301 system.cpu.iq.issued_per_cycle::stdev 1.910853 # Number of insts issued each cycle
302 system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
303 system.cpu.iq.issued_per_cycle::0 15308492 28.70% 28.70% # Number of insts issued each cycle
304 system.cpu.iq.issued_per_cycle::1 11622242 21.79% 50.49% # Number of insts issued each cycle
305 system.cpu.iq.issued_per_cycle::2 8283131 15.53% 66.02% # Number of insts issued each cycle
306 system.cpu.iq.issued_per_cycle::3 6774123 12.70% 78.72% # Number of insts issued each cycle
307 system.cpu.iq.issued_per_cycle::4 4939733 9.26% 87.98% # Number of insts issued each cycle
308 system.cpu.iq.issued_per_cycle::5 2964995 5.56% 93.54% # Number of insts issued each cycle
309 system.cpu.iq.issued_per_cycle::6 2471425 4.63% 98.18% # Number of insts issued each cycle
310 system.cpu.iq.issued_per_cycle::7 528847 0.99% 99.17% # Number of insts issued each cycle
311 system.cpu.iq.issued_per_cycle::8 443152 0.83% 100.00% # Number of insts issued each cycle
312 system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
313 system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
314 system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
315 system.cpu.iq.issued_per_cycle::total 53336140 # Number of insts issued each cycle
316 system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
317 system.cpu.iq.fu_full::IntAlu 45613 6.89% 6.89% # attempts to use FU when none available
318 system.cpu.iq.fu_full::IntMult 27 0.00% 6.90% # attempts to use FU when none available
319 system.cpu.iq.fu_full::IntDiv 0 0.00% 6.90% # attempts to use FU when none available
320 system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.90% # attempts to use FU when none available
321 system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.90% # attempts to use FU when none available
322 system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.90% # attempts to use FU when none available
323 system.cpu.iq.fu_full::FloatMult 0 0.00% 6.90% # attempts to use FU when none available
324 system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.90% # attempts to use FU when none available
325 system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.90% # attempts to use FU when none available
326 system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.90% # attempts to use FU when none available
327 system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.90% # attempts to use FU when none available
328 system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.90% # attempts to use FU when none available
329 system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.90% # attempts to use FU when none available
330 system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.90% # attempts to use FU when none available
331 system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.90% # attempts to use FU when none available
332 system.cpu.iq.fu_full::SimdMult 0 0.00% 6.90% # attempts to use FU when none available
333 system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.90% # attempts to use FU when none available
334 system.cpu.iq.fu_full::SimdShift 0 0.00% 6.90% # attempts to use FU when none available
335 system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.90% # attempts to use FU when none available
336 system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.90% # attempts to use FU when none available
337 system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.90% # attempts to use FU when none available
338 system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.90% # attempts to use FU when none available
339 system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.90% # attempts to use FU when none available
340 system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.90% # attempts to use FU when none available
341 system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.90% # attempts to use FU when none available
342 system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.90% # attempts to use FU when none available
343 system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.90% # attempts to use FU when none available
344 system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.90% # attempts to use FU when none available
345 system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.90% # attempts to use FU when none available
346 system.cpu.iq.fu_full::MemRead 340087 51.41% 58.31% # attempts to use FU when none available
347 system.cpu.iq.fu_full::MemWrite 275830 41.69% 100.00% # attempts to use FU when none available
348 system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
349 system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
350 system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
351 system.cpu.iq.FU_type_0::IntAlu 74428958 70.77% 70.77% # Type of FU issued
352 system.cpu.iq.FU_type_0::IntMult 10973 0.01% 70.78% # Type of FU issued
353 system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.78% # Type of FU issued
354 system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.78% # Type of FU issued
355 system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.78% # Type of FU issued
356 system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.78% # Type of FU issued
357 system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.78% # Type of FU issued
358 system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.78% # Type of FU issued
359 system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.78% # Type of FU issued
360 system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.78% # Type of FU issued
361 system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.78% # Type of FU issued
362 system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.78% # Type of FU issued
363 system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.78% # Type of FU issued
364 system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.78% # Type of FU issued
365 system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.78% # Type of FU issued
366 system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.78% # Type of FU issued
367 system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.78% # Type of FU issued
368 system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.78% # Type of FU issued
369 system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.78% # Type of FU issued
370 system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.78% # Type of FU issued
371 system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.78% # Type of FU issued
372 system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.78% # Type of FU issued
373 system.cpu.iq.FU_type_0::SimdFloatCmp 1 0.00% 70.78% # Type of FU issued
374 system.cpu.iq.FU_type_0::SimdFloatCvt 145 0.00% 70.78% # Type of FU issued
375 system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.78% # Type of FU issued
376 system.cpu.iq.FU_type_0::SimdFloatMisc 185 0.00% 70.78% # Type of FU issued
377 system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.78% # Type of FU issued
378 system.cpu.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 70.78% # Type of FU issued
379 system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.78% # Type of FU issued
380 system.cpu.iq.FU_type_0::MemRead 25611753 24.35% 95.13% # Type of FU issued
381 system.cpu.iq.FU_type_0::MemWrite 5118456 4.87% 100.00% # Type of FU issued
382 system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
383 system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
384 system.cpu.iq.FU_type_0::total 105170475 # Type of FU issued
385 system.cpu.iq.rate 1.963535 # Inst issue rate
386 system.cpu.iq.fu_busy_cnt 661557 # FU busy when requested
387 system.cpu.iq.fu_busy_rate 0.006290 # FU busy rate (busy events/executed inst)
388 system.cpu.iq.int_inst_queue_reads 264417181 # Number of integer instruction queue reads
389 system.cpu.iq.int_inst_queue_writes 144941243 # Number of integer instruction queue writes
390 system.cpu.iq.int_inst_queue_wakeup_accesses 102695992 # Number of integer instruction queue wakeup accesses
391 system.cpu.iq.fp_inst_queue_reads 733 # Number of floating instruction queue reads
392 system.cpu.iq.fp_inst_queue_writes 1017 # Number of floating instruction queue writes
393 system.cpu.iq.fp_inst_queue_wakeup_accesses 321 # Number of floating instruction queue wakeup accesses
394 system.cpu.iq.int_alu_accesses 105831667 # Number of integer alu accesses
395 system.cpu.iq.fp_alu_accesses 365 # Number of floating point alu accesses
396 system.cpu.iew.lsq.thread0.forwLoads 444874 # Number of loads that had data forwarded from stores
397 system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
398 system.cpu.iew.lsq.thread0.squashedLoads 6907209 # Number of loads squashed
399 system.cpu.iew.lsq.thread0.ignoredResponses 6633 # Number of memory responses ignored because the instruction is squashed
400 system.cpu.iew.lsq.thread0.memOrderViolation 6354 # Number of memory ordering violations
401 system.cpu.iew.lsq.thread0.squashedStores 779363 # Number of stores squashed
402 system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
403 system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
404 system.cpu.iew.lsq.thread0.rescheduledLoads 2 # Number of loads that were rescheduled
405 system.cpu.iew.lsq.thread0.cacheBlocked 31305 # Number of times an access to memory failed due to the cache being blocked
406 system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
407 system.cpu.iew.iewSquashCycles 3897327 # Number of cycles IEW is squashing
408 system.cpu.iew.iewBlockCycles 927642 # Number of cycles IEW is blocking
409 system.cpu.iew.iewUnblockCycles 126590 # Number of cycles IEW is unblocking
410 system.cpu.iew.iewDispatchedInsts 118198971 # Number of instructions dispatched to IQ
411 system.cpu.iew.iewDispSquashedInsts 309734 # Number of squashed instructions skipped by dispatch
412 system.cpu.iew.iewDispLoadInsts 29481175 # Number of dispatched load instructions
413 system.cpu.iew.iewDispStoreInsts 5524207 # Number of dispatched store instructions
414 system.cpu.iew.iewDispNonSpecInsts 4584 # Number of dispatched non-speculative instructions
415 system.cpu.iew.iewIQFullEvents 66006 # Number of times the IQ has become full, causing a stall
416 system.cpu.iew.iewLSQFullEvents 6795 # Number of times the LSQ has become full, causing a stall
417 system.cpu.iew.memOrderViolationEvents 6354 # Number of memory order violations
418 system.cpu.iew.predictedTakenIncorrect 446949 # Number of branches that were predicted taken incorrectly
419 system.cpu.iew.predictedNotTakenIncorrect 445983 # Number of branches that were predicted not taken incorrectly
420 system.cpu.iew.branchMispredicts 892932 # Number of branch mispredicts detected at execute
421 system.cpu.iew.iewExecutedInsts 104193042 # Number of executed instructions
422 system.cpu.iew.iewExecLoadInsts 25290857 # Number of load instructions executed
423 system.cpu.iew.iewExecSquashedInsts 977433 # Number of squashed instructions skipped in execute
424 system.cpu.iew.exec_swp 0 # number of swp insts executed
425 system.cpu.iew.exec_nop 12714 # number of nop insts executed
426 system.cpu.iew.exec_refs 30352506 # number of memory reference insts executed
427 system.cpu.iew.exec_branches 21328586 # Number of branches executed
428 system.cpu.iew.exec_stores 5061649 # Number of stores executed
429 system.cpu.iew.exec_rate 1.945286 # Inst execution rate
430 system.cpu.iew.wb_sent 102976105 # cumulative count of insts sent to commit
431 system.cpu.iew.wb_count 102696313 # cumulative count of insts written-back
432 system.cpu.iew.wb_producers 62237913 # num instructions producing a value
433 system.cpu.iew.wb_consumers 104299650 # num instructions consuming a value
434 system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
435 system.cpu.iew.wb_rate 1.917342 # insts written-back per cycle
436 system.cpu.iew.wb_fanout 0.596722 # average fanout of values written-back
437 system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
438 system.cpu.commit.commitSquashedInsts 26949111 # The number of squashed insts skipped by commit
439 system.cpu.commit.commitNonSpecStalls 8218 # The number of times commit has been forced to stall to communicate backwards
440 system.cpu.commit.branchMispredicts 834092 # The number of times a branch was mispredicted
441 system.cpu.commit.committed_per_cycle::samples 49438813 # Number of insts commited each cycle
442 system.cpu.commit.committed_per_cycle::mean 1.845776 # Number of insts commited each cycle
443 system.cpu.commit.committed_per_cycle::stdev 2.541803 # Number of insts commited each cycle
444 system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
445 system.cpu.commit.committed_per_cycle::0 19950290 40.35% 40.35% # Number of insts commited each cycle
446 system.cpu.commit.committed_per_cycle::1 13144948 26.59% 66.94% # Number of insts commited each cycle
447 system.cpu.commit.committed_per_cycle::2 4163783 8.42% 75.36% # Number of insts commited each cycle
448 system.cpu.commit.committed_per_cycle::3 3432949 6.94% 82.31% # Number of insts commited each cycle
449 system.cpu.commit.committed_per_cycle::4 1533470 3.10% 85.41% # Number of insts commited each cycle
450 system.cpu.commit.committed_per_cycle::5 746046 1.51% 86.92% # Number of insts commited each cycle
451 system.cpu.commit.committed_per_cycle::6 934782 1.89% 88.81% # Number of insts commited each cycle
452 system.cpu.commit.committed_per_cycle::7 251563 0.51% 89.32% # Number of insts commited each cycle
453 system.cpu.commit.committed_per_cycle::8 5280982 10.68% 100.00% # Number of insts commited each cycle
454 system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
455 system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
456 system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
457 system.cpu.commit.committed_per_cycle::total 49438813 # Number of insts commited each cycle
458 system.cpu.commit.committedInsts 90602407 # Number of instructions committed
459 system.cpu.commit.committedOps 91252960 # Number of ops (including micro ops) committed
460 system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
461 system.cpu.commit.refs 27318810 # Number of memory references committed
462 system.cpu.commit.loads 22573966 # Number of loads committed
463 system.cpu.commit.membars 3888 # Number of memory barriers committed
464 system.cpu.commit.branches 18732304 # Number of branches committed
465 system.cpu.commit.fp_insts 48 # Number of committed floating point instructions.
466 system.cpu.commit.int_insts 72525674 # Number of committed integer instructions.
467 system.cpu.commit.function_calls 56148 # Number of function calls committed.
468 system.cpu.commit.bw_lim_events 5280982 # number cycles where commit BW limit reached
469 system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
470 system.cpu.rob.rob_reads 162354168 # The number of ROB reads
471 system.cpu.rob.rob_writes 240321058 # The number of ROB writes
472 system.cpu.timesIdled 43778 # Number of times that the entire CPU went into an idle state and unscheduled itself
473 system.cpu.idleCycles 225660 # Total number of cycles that the CPU has spent unscheduled due to idling
474 system.cpu.committedInsts 90589798 # Number of Instructions Simulated
475 system.cpu.committedOps 91240351 # Number of Ops (including micro ops) Simulated
476 system.cpu.committedInsts_total 90589798 # Number of Instructions Simulated
477 system.cpu.cpi 0.591256 # CPI: Cycles Per Instruction
478 system.cpu.cpi_total 0.591256 # CPI: Total CPI of All Threads
479 system.cpu.ipc 1.691314 # IPC: Instructions Per Cycle
480 system.cpu.ipc_total 1.691314 # IPC: Total IPC of All Threads
481 system.cpu.int_regfile_reads 495624515 # number of integer regfile reads
482 system.cpu.int_regfile_writes 120561799 # number of integer regfile writes
483 system.cpu.fp_regfile_reads 167 # number of floating regfile reads
484 system.cpu.fp_regfile_writes 408 # number of floating regfile writes
485 system.cpu.misc_regfile_reads 29097050 # number of misc regfile reads
486 system.cpu.misc_regfile_writes 7784 # number of misc regfile writes
487 system.cpu.icache.replacements 3 # number of replacements
488 system.cpu.icache.tagsinuse 630.487158 # Cycle average of tags in use
489 system.cpu.icache.total_refs 13846398 # Total number of references to valid blocks.
490 system.cpu.icache.sampled_refs 729 # Sample count of references to valid blocks.
491 system.cpu.icache.avg_refs 18993.687243 # Average number of references to valid blocks.
492 system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
493 system.cpu.icache.occ_blocks::cpu.inst 630.487158 # Average occupied blocks per requestor
494 system.cpu.icache.occ_percent::cpu.inst 0.307855 # Average percentage of cache occupancy
495 system.cpu.icache.occ_percent::total 0.307855 # Average percentage of cache occupancy
496 system.cpu.icache.ReadReq_hits::cpu.inst 13846398 # number of ReadReq hits
497 system.cpu.icache.ReadReq_hits::total 13846398 # number of ReadReq hits
498 system.cpu.icache.demand_hits::cpu.inst 13846398 # number of demand (read+write) hits
499 system.cpu.icache.demand_hits::total 13846398 # number of demand (read+write) hits
500 system.cpu.icache.overall_hits::cpu.inst 13846398 # number of overall hits
501 system.cpu.icache.overall_hits::total 13846398 # number of overall hits
502 system.cpu.icache.ReadReq_misses::cpu.inst 984 # number of ReadReq misses
503 system.cpu.icache.ReadReq_misses::total 984 # number of ReadReq misses
504 system.cpu.icache.demand_misses::cpu.inst 984 # number of demand (read+write) misses
505 system.cpu.icache.demand_misses::total 984 # number of demand (read+write) misses
506 system.cpu.icache.overall_misses::cpu.inst 984 # number of overall misses
507 system.cpu.icache.overall_misses::total 984 # number of overall misses
508 system.cpu.icache.ReadReq_miss_latency::cpu.inst 49101999 # number of ReadReq miss cycles
509 system.cpu.icache.ReadReq_miss_latency::total 49101999 # number of ReadReq miss cycles
510 system.cpu.icache.demand_miss_latency::cpu.inst 49101999 # number of demand (read+write) miss cycles
511 system.cpu.icache.demand_miss_latency::total 49101999 # number of demand (read+write) miss cycles
512 system.cpu.icache.overall_miss_latency::cpu.inst 49101999 # number of overall miss cycles
513 system.cpu.icache.overall_miss_latency::total 49101999 # number of overall miss cycles
514 system.cpu.icache.ReadReq_accesses::cpu.inst 13847382 # number of ReadReq accesses(hits+misses)
515 system.cpu.icache.ReadReq_accesses::total 13847382 # number of ReadReq accesses(hits+misses)
516 system.cpu.icache.demand_accesses::cpu.inst 13847382 # number of demand (read+write) accesses
517 system.cpu.icache.demand_accesses::total 13847382 # number of demand (read+write) accesses
518 system.cpu.icache.overall_accesses::cpu.inst 13847382 # number of overall (read+write) accesses
519 system.cpu.icache.overall_accesses::total 13847382 # number of overall (read+write) accesses
520 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000071 # miss rate for ReadReq accesses
521 system.cpu.icache.ReadReq_miss_rate::total 0.000071 # miss rate for ReadReq accesses
522 system.cpu.icache.demand_miss_rate::cpu.inst 0.000071 # miss rate for demand accesses
523 system.cpu.icache.demand_miss_rate::total 0.000071 # miss rate for demand accesses
524 system.cpu.icache.overall_miss_rate::cpu.inst 0.000071 # miss rate for overall accesses
525 system.cpu.icache.overall_miss_rate::total 0.000071 # miss rate for overall accesses
526 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49900.405488 # average ReadReq miss latency
527 system.cpu.icache.ReadReq_avg_miss_latency::total 49900.405488 # average ReadReq miss latency
528 system.cpu.icache.demand_avg_miss_latency::cpu.inst 49900.405488 # average overall miss latency
529 system.cpu.icache.demand_avg_miss_latency::total 49900.405488 # average overall miss latency
530 system.cpu.icache.overall_avg_miss_latency::cpu.inst 49900.405488 # average overall miss latency
531 system.cpu.icache.overall_avg_miss_latency::total 49900.405488 # average overall miss latency
532 system.cpu.icache.blocked_cycles::no_mshrs 502 # number of cycles access was blocked
533 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
534 system.cpu.icache.blocked::no_mshrs 9 # number of cycles access was blocked
535 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
536 system.cpu.icache.avg_blocked_cycles::no_mshrs 55.777778 # average number of cycles each access was blocked
537 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
538 system.cpu.icache.fast_writes 0 # number of fast writes performed
539 system.cpu.icache.cache_copies 0 # number of cache copies performed
540 system.cpu.icache.ReadReq_mshr_hits::cpu.inst 251 # number of ReadReq MSHR hits
541 system.cpu.icache.ReadReq_mshr_hits::total 251 # number of ReadReq MSHR hits
542 system.cpu.icache.demand_mshr_hits::cpu.inst 251 # number of demand (read+write) MSHR hits
543 system.cpu.icache.demand_mshr_hits::total 251 # number of demand (read+write) MSHR hits
544 system.cpu.icache.overall_mshr_hits::cpu.inst 251 # number of overall MSHR hits
545 system.cpu.icache.overall_mshr_hits::total 251 # number of overall MSHR hits
546 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 733 # number of ReadReq MSHR misses
547 system.cpu.icache.ReadReq_mshr_misses::total 733 # number of ReadReq MSHR misses
548 system.cpu.icache.demand_mshr_misses::cpu.inst 733 # number of demand (read+write) MSHR misses
549 system.cpu.icache.demand_mshr_misses::total 733 # number of demand (read+write) MSHR misses
550 system.cpu.icache.overall_mshr_misses::cpu.inst 733 # number of overall MSHR misses
551 system.cpu.icache.overall_mshr_misses::total 733 # number of overall MSHR misses
552 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 37481499 # number of ReadReq MSHR miss cycles
553 system.cpu.icache.ReadReq_mshr_miss_latency::total 37481499 # number of ReadReq MSHR miss cycles
554 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 37481499 # number of demand (read+write) MSHR miss cycles
555 system.cpu.icache.demand_mshr_miss_latency::total 37481499 # number of demand (read+write) MSHR miss cycles
556 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 37481499 # number of overall MSHR miss cycles
557 system.cpu.icache.overall_mshr_miss_latency::total 37481499 # number of overall MSHR miss cycles
558 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for ReadReq accesses
559 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000053 # mshr miss rate for ReadReq accesses
560 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for demand accesses
561 system.cpu.icache.demand_mshr_miss_rate::total 0.000053 # mshr miss rate for demand accesses
562 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for overall accesses
563 system.cpu.icache.overall_mshr_miss_rate::total 0.000053 # mshr miss rate for overall accesses
564 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51134.377899 # average ReadReq mshr miss latency
565 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51134.377899 # average ReadReq mshr miss latency
566 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51134.377899 # average overall mshr miss latency
567 system.cpu.icache.demand_avg_mshr_miss_latency::total 51134.377899 # average overall mshr miss latency
568 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51134.377899 # average overall mshr miss latency
569 system.cpu.icache.overall_avg_mshr_miss_latency::total 51134.377899 # average overall mshr miss latency
570 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
571 system.cpu.l2cache.replacements 0 # number of replacements
572 system.cpu.l2cache.tagsinuse 10757.893371 # Cycle average of tags in use
573 system.cpu.l2cache.total_refs 1831525 # Total number of references to valid blocks.
574 system.cpu.l2cache.sampled_refs 15493 # Sample count of references to valid blocks.
575 system.cpu.l2cache.avg_refs 118.216291 # Average number of references to valid blocks.
576 system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
577 system.cpu.l2cache.occ_blocks::writebacks 9911.352176 # Average occupied blocks per requestor
578 system.cpu.l2cache.occ_blocks::cpu.inst 616.806864 # Average occupied blocks per requestor
579 system.cpu.l2cache.occ_blocks::cpu.data 229.734332 # Average occupied blocks per requestor
580 system.cpu.l2cache.occ_percent::writebacks 0.302470 # Average percentage of cache occupancy
581 system.cpu.l2cache.occ_percent::cpu.inst 0.018823 # Average percentage of cache occupancy
582 system.cpu.l2cache.occ_percent::cpu.data 0.007011 # Average percentage of cache occupancy
583 system.cpu.l2cache.occ_percent::total 0.328305 # Average percentage of cache occupancy
584 system.cpu.l2cache.ReadReq_hits::cpu.inst 25 # number of ReadReq hits
585 system.cpu.l2cache.ReadReq_hits::cpu.data 903743 # number of ReadReq hits
586 system.cpu.l2cache.ReadReq_hits::total 903768 # number of ReadReq hits
587 system.cpu.l2cache.Writeback_hits::writebacks 942899 # number of Writeback hits
588 system.cpu.l2cache.Writeback_hits::total 942899 # number of Writeback hits
589 system.cpu.l2cache.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits
590 system.cpu.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits
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592 system.cpu.l2cache.ReadExReq_hits::total 29037 # number of ReadExReq hits
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597 system.cpu.l2cache.overall_hits::cpu.data 932780 # number of overall hits
598 system.cpu.l2cache.overall_hits::total 932805 # number of overall hits
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601 system.cpu.l2cache.ReadReq_misses::total 982 # number of ReadReq misses
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605 system.cpu.l2cache.ReadExReq_misses::total 14539 # number of ReadExReq misses
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608 system.cpu.l2cache.demand_misses::total 15521 # number of demand (read+write) misses
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610 system.cpu.l2cache.overall_misses::cpu.data 14817 # number of overall misses
611 system.cpu.l2cache.overall_misses::total 15521 # number of overall misses
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613 system.cpu.l2cache.ReadReq_miss_latency::cpu.data 15550500 # number of ReadReq miss cycles
614 system.cpu.l2cache.ReadReq_miss_latency::total 52033000 # number of ReadReq miss cycles
615 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 628050000 # number of ReadExReq miss cycles
616 system.cpu.l2cache.ReadExReq_miss_latency::total 628050000 # number of ReadExReq miss cycles
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619 system.cpu.l2cache.demand_miss_latency::total 680083000 # number of demand (read+write) miss cycles
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621 system.cpu.l2cache.overall_miss_latency::cpu.data 643600500 # number of overall miss cycles
622 system.cpu.l2cache.overall_miss_latency::total 680083000 # number of overall miss cycles
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624 system.cpu.l2cache.ReadReq_accesses::cpu.data 904021 # number of ReadReq accesses(hits+misses)
625 system.cpu.l2cache.ReadReq_accesses::total 904750 # number of ReadReq accesses(hits+misses)
626 system.cpu.l2cache.Writeback_accesses::writebacks 942899 # number of Writeback accesses(hits+misses)
627 system.cpu.l2cache.Writeback_accesses::total 942899 # number of Writeback accesses(hits+misses)
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629 system.cpu.l2cache.UpgradeReq_accesses::total 4 # number of UpgradeReq accesses(hits+misses)
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631 system.cpu.l2cache.ReadExReq_accesses::total 43576 # number of ReadExReq accesses(hits+misses)
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639 system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000308 # miss rate for ReadReq accesses
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641 system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.750000 # miss rate for UpgradeReq accesses
642 system.cpu.l2cache.UpgradeReq_miss_rate::total 0.750000 # miss rate for UpgradeReq accesses
643 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.333647 # miss rate for ReadExReq accesses
644 system.cpu.l2cache.ReadExReq_miss_rate::total 0.333647 # miss rate for ReadExReq accesses
645 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.965706 # miss rate for demand accesses
646 system.cpu.l2cache.demand_miss_rate::cpu.data 0.015636 # miss rate for demand accesses
647 system.cpu.l2cache.demand_miss_rate::total 0.016367 # miss rate for demand accesses
648 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.965706 # miss rate for overall accesses
649 system.cpu.l2cache.overall_miss_rate::cpu.data 0.015636 # miss rate for overall accesses
650 system.cpu.l2cache.overall_miss_rate::total 0.016367 # miss rate for overall accesses
651 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 51821.732955 # average ReadReq miss latency
652 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 55937.050360 # average ReadReq miss latency
653 system.cpu.l2cache.ReadReq_avg_miss_latency::total 52986.761711 # average ReadReq miss latency
654 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 43197.606438 # average ReadExReq miss latency
655 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 43197.606438 # average ReadExReq miss latency
656 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 51821.732955 # average overall miss latency
657 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 43436.626848 # average overall miss latency
658 system.cpu.l2cache.demand_avg_miss_latency::total 43816.957670 # average overall miss latency
659 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 51821.732955 # average overall miss latency
660 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 43436.626848 # average overall miss latency
661 system.cpu.l2cache.overall_avg_miss_latency::total 43816.957670 # average overall miss latency
662 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
663 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
664 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
665 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
666 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
667 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
668 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
669 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
670 system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits
671 system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 10 # number of ReadReq MSHR hits
672 system.cpu.l2cache.ReadReq_mshr_hits::total 11 # number of ReadReq MSHR hits
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674 system.cpu.l2cache.demand_mshr_hits::cpu.data 10 # number of demand (read+write) MSHR hits
675 system.cpu.l2cache.demand_mshr_hits::total 11 # number of demand (read+write) MSHR hits
676 system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
677 system.cpu.l2cache.overall_mshr_hits::cpu.data 10 # number of overall MSHR hits
678 system.cpu.l2cache.overall_mshr_hits::total 11 # number of overall MSHR hits
679 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 703 # number of ReadReq MSHR misses
680 system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 268 # number of ReadReq MSHR misses
681 system.cpu.l2cache.ReadReq_mshr_misses::total 971 # number of ReadReq MSHR misses
682 system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 3 # number of UpgradeReq MSHR misses
683 system.cpu.l2cache.UpgradeReq_mshr_misses::total 3 # number of UpgradeReq MSHR misses
684 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14539 # number of ReadExReq MSHR misses
685 system.cpu.l2cache.ReadExReq_mshr_misses::total 14539 # number of ReadExReq MSHR misses
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690 system.cpu.l2cache.overall_mshr_misses::cpu.data 14807 # number of overall MSHR misses
691 system.cpu.l2cache.overall_mshr_misses::total 15510 # number of overall MSHR misses
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693 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 11810706 # number of ReadReq MSHR miss cycles
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696 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 30003 # number of UpgradeReq MSHR miss cycles
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698 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 447813969 # number of ReadExReq MSHR miss cycles
699 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 27504806 # number of demand (read+write) MSHR miss cycles
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702 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 27504806 # number of overall MSHR miss cycles
703 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 459624675 # number of overall MSHR miss cycles
704 system.cpu.l2cache.overall_mshr_miss_latency::total 487129481 # number of overall MSHR miss cycles
705 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.964335 # mshr miss rate for ReadReq accesses
706 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000296 # mshr miss rate for ReadReq accesses
707 system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001073 # mshr miss rate for ReadReq accesses
708 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.750000 # mshr miss rate for UpgradeReq accesses
709 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.750000 # mshr miss rate for UpgradeReq accesses
710 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.333647 # mshr miss rate for ReadExReq accesses
711 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.333647 # mshr miss rate for ReadExReq accesses
712 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.964335 # mshr miss rate for demand accesses
713 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015626 # mshr miss rate for demand accesses
714 system.cpu.l2cache.demand_mshr_miss_rate::total 0.016355 # mshr miss rate for demand accesses
715 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.964335 # mshr miss rate for overall accesses
716 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015626 # mshr miss rate for overall accesses
717 system.cpu.l2cache.overall_mshr_miss_rate::total 0.016355 # mshr miss rate for overall accesses
718 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39124.901849 # average ReadReq mshr miss latency
719 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 44069.798507 # average ReadReq mshr miss latency
720 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40489.713697 # average ReadReq mshr miss latency
721 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency
722 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency
723 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 30800.878258 # average ReadExReq mshr miss latency
724 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 30800.878258 # average ReadExReq mshr miss latency
725 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39124.901849 # average overall mshr miss latency
726 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31041.039711 # average overall mshr miss latency
727 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31407.445583 # average overall mshr miss latency
728 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39124.901849 # average overall mshr miss latency
729 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31041.039711 # average overall mshr miss latency
730 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31407.445583 # average overall mshr miss latency
731 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
732 system.cpu.dcache.replacements 943501 # number of replacements
733 system.cpu.dcache.tagsinuse 3674.828518 # Cycle average of tags in use
734 system.cpu.dcache.total_refs 28143712 # Total number of references to valid blocks.
735 system.cpu.dcache.sampled_refs 947597 # Sample count of references to valid blocks.
736 system.cpu.dcache.avg_refs 29.700086 # Average number of references to valid blocks.
737 system.cpu.dcache.warmup_cycle 7938430000 # Cycle when the warmup percentage was hit.
738 system.cpu.dcache.occ_blocks::cpu.data 3674.828518 # Average occupied blocks per requestor
739 system.cpu.dcache.occ_percent::cpu.data 0.897175 # Average percentage of cache occupancy
740 system.cpu.dcache.occ_percent::total 0.897175 # Average percentage of cache occupancy
741 system.cpu.dcache.ReadReq_hits::cpu.data 23598974 # number of ReadReq hits
742 system.cpu.dcache.ReadReq_hits::total 23598974 # number of ReadReq hits
743 system.cpu.dcache.WriteReq_hits::cpu.data 4536932 # number of WriteReq hits
744 system.cpu.dcache.WriteReq_hits::total 4536932 # number of WriteReq hits
745 system.cpu.dcache.LoadLockedReq_hits::cpu.data 3909 # number of LoadLockedReq hits
746 system.cpu.dcache.LoadLockedReq_hits::total 3909 # number of LoadLockedReq hits
747 system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits
748 system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits
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750 system.cpu.dcache.demand_hits::total 28135906 # number of demand (read+write) hits
751 system.cpu.dcache.overall_hits::cpu.data 28135906 # number of overall hits
752 system.cpu.dcache.overall_hits::total 28135906 # number of overall hits
753 system.cpu.dcache.ReadReq_misses::cpu.data 1174144 # number of ReadReq misses
754 system.cpu.dcache.ReadReq_misses::total 1174144 # number of ReadReq misses
755 system.cpu.dcache.WriteReq_misses::cpu.data 198049 # number of WriteReq misses
756 system.cpu.dcache.WriteReq_misses::total 198049 # number of WriteReq misses
757 system.cpu.dcache.LoadLockedReq_misses::cpu.data 6 # number of LoadLockedReq misses
758 system.cpu.dcache.LoadLockedReq_misses::total 6 # number of LoadLockedReq misses
759 system.cpu.dcache.demand_misses::cpu.data 1372193 # number of demand (read+write) misses
760 system.cpu.dcache.demand_misses::total 1372193 # number of demand (read+write) misses
761 system.cpu.dcache.overall_misses::cpu.data 1372193 # number of overall misses
762 system.cpu.dcache.overall_misses::total 1372193 # number of overall misses
763 system.cpu.dcache.ReadReq_miss_latency::cpu.data 13880291500 # number of ReadReq miss cycles
764 system.cpu.dcache.ReadReq_miss_latency::total 13880291500 # number of ReadReq miss cycles
765 system.cpu.dcache.WriteReq_miss_latency::cpu.data 5594114381 # number of WriteReq miss cycles
766 system.cpu.dcache.WriteReq_miss_latency::total 5594114381 # number of WriteReq miss cycles
767 system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 247000 # number of LoadLockedReq miss cycles
768 system.cpu.dcache.LoadLockedReq_miss_latency::total 247000 # number of LoadLockedReq miss cycles
769 system.cpu.dcache.demand_miss_latency::cpu.data 19474405881 # number of demand (read+write) miss cycles
770 system.cpu.dcache.demand_miss_latency::total 19474405881 # number of demand (read+write) miss cycles
771 system.cpu.dcache.overall_miss_latency::cpu.data 19474405881 # number of overall miss cycles
772 system.cpu.dcache.overall_miss_latency::total 19474405881 # number of overall miss cycles
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777 system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3915 # number of LoadLockedReq accesses(hits+misses)
778 system.cpu.dcache.LoadLockedReq_accesses::total 3915 # number of LoadLockedReq accesses(hits+misses)
779 system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses)
780 system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses)
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782 system.cpu.dcache.demand_accesses::total 29508099 # number of demand (read+write) accesses
783 system.cpu.dcache.overall_accesses::cpu.data 29508099 # number of overall (read+write) accesses
784 system.cpu.dcache.overall_accesses::total 29508099 # number of overall (read+write) accesses
785 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.047396 # miss rate for ReadReq accesses
786 system.cpu.dcache.ReadReq_miss_rate::total 0.047396 # miss rate for ReadReq accesses
787 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.041827 # miss rate for WriteReq accesses
788 system.cpu.dcache.WriteReq_miss_rate::total 0.041827 # miss rate for WriteReq accesses
789 system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001533 # miss rate for LoadLockedReq accesses
790 system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001533 # miss rate for LoadLockedReq accesses
791 system.cpu.dcache.demand_miss_rate::cpu.data 0.046502 # miss rate for demand accesses
792 system.cpu.dcache.demand_miss_rate::total 0.046502 # miss rate for demand accesses
793 system.cpu.dcache.overall_miss_rate::cpu.data 0.046502 # miss rate for overall accesses
794 system.cpu.dcache.overall_miss_rate::total 0.046502 # miss rate for overall accesses
795 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11821.626223 # average ReadReq miss latency
796 system.cpu.dcache.ReadReq_avg_miss_latency::total 11821.626223 # average ReadReq miss latency
797 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28246.112735 # average WriteReq miss latency
798 system.cpu.dcache.WriteReq_avg_miss_latency::total 28246.112735 # average WriteReq miss latency
799 system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 41166.666667 # average LoadLockedReq miss latency
800 system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 41166.666667 # average LoadLockedReq miss latency
801 system.cpu.dcache.demand_avg_miss_latency::cpu.data 14192.176961 # average overall miss latency
802 system.cpu.dcache.demand_avg_miss_latency::total 14192.176961 # average overall miss latency
803 system.cpu.dcache.overall_avg_miss_latency::cpu.data 14192.176961 # average overall miss latency
804 system.cpu.dcache.overall_avg_miss_latency::total 14192.176961 # average overall miss latency
805 system.cpu.dcache.blocked_cycles::no_mshrs 152397 # number of cycles access was blocked
806 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
807 system.cpu.dcache.blocked::no_mshrs 23857 # number of cycles access was blocked
808 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
809 system.cpu.dcache.avg_blocked_cycles::no_mshrs 6.387936 # average number of cycles each access was blocked
810 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
811 system.cpu.dcache.fast_writes 0 # number of fast writes performed
812 system.cpu.dcache.cache_copies 0 # number of cache copies performed
813 system.cpu.dcache.writebacks::writebacks 942899 # number of writebacks
814 system.cpu.dcache.writebacks::total 942899 # number of writebacks
815 system.cpu.dcache.ReadReq_mshr_hits::cpu.data 270103 # number of ReadReq MSHR hits
816 system.cpu.dcache.ReadReq_mshr_hits::total 270103 # number of ReadReq MSHR hits
817 system.cpu.dcache.WriteReq_mshr_hits::cpu.data 154489 # number of WriteReq MSHR hits
818 system.cpu.dcache.WriteReq_mshr_hits::total 154489 # number of WriteReq MSHR hits
819 system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 6 # number of LoadLockedReq MSHR hits
820 system.cpu.dcache.LoadLockedReq_mshr_hits::total 6 # number of LoadLockedReq MSHR hits
821 system.cpu.dcache.demand_mshr_hits::cpu.data 424592 # number of demand (read+write) MSHR hits
822 system.cpu.dcache.demand_mshr_hits::total 424592 # number of demand (read+write) MSHR hits
823 system.cpu.dcache.overall_mshr_hits::cpu.data 424592 # number of overall MSHR hits
824 system.cpu.dcache.overall_mshr_hits::total 424592 # number of overall MSHR hits
825 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 904041 # number of ReadReq MSHR misses
826 system.cpu.dcache.ReadReq_mshr_misses::total 904041 # number of ReadReq MSHR misses
827 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43560 # number of WriteReq MSHR misses
828 system.cpu.dcache.WriteReq_mshr_misses::total 43560 # number of WriteReq MSHR misses
829 system.cpu.dcache.demand_mshr_misses::cpu.data 947601 # number of demand (read+write) MSHR misses
830 system.cpu.dcache.demand_mshr_misses::total 947601 # number of demand (read+write) MSHR misses
831 system.cpu.dcache.overall_mshr_misses::cpu.data 947601 # number of overall MSHR misses
832 system.cpu.dcache.overall_mshr_misses::total 947601 # number of overall MSHR misses
833 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9990058500 # number of ReadReq MSHR miss cycles
834 system.cpu.dcache.ReadReq_mshr_miss_latency::total 9990058500 # number of ReadReq MSHR miss cycles
835 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 983302939 # number of WriteReq MSHR miss cycles
836 system.cpu.dcache.WriteReq_mshr_miss_latency::total 983302939 # number of WriteReq MSHR miss cycles
837 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10973361439 # number of demand (read+write) MSHR miss cycles
838 system.cpu.dcache.demand_mshr_miss_latency::total 10973361439 # number of demand (read+write) MSHR miss cycles
839 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10973361439 # number of overall MSHR miss cycles
840 system.cpu.dcache.overall_mshr_miss_latency::total 10973361439 # number of overall MSHR miss cycles
841 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036493 # mshr miss rate for ReadReq accesses
842 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036493 # mshr miss rate for ReadReq accesses
843 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009200 # mshr miss rate for WriteReq accesses
844 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009200 # mshr miss rate for WriteReq accesses
845 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032113 # mshr miss rate for demand accesses
846 system.cpu.dcache.demand_mshr_miss_rate::total 0.032113 # mshr miss rate for demand accesses
847 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032113 # mshr miss rate for overall accesses
848 system.cpu.dcache.overall_mshr_miss_rate::total 0.032113 # mshr miss rate for overall accesses
849 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11050.448486 # average ReadReq mshr miss latency
850 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11050.448486 # average ReadReq mshr miss latency
851 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22573.529362 # average WriteReq mshr miss latency
852 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22573.529362 # average WriteReq mshr miss latency
853 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11580.149703 # average overall mshr miss latency
854 system.cpu.dcache.demand_avg_mshr_miss_latency::total 11580.149703 # average overall mshr miss latency
855 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11580.149703 # average overall mshr miss latency
856 system.cpu.dcache.overall_avg_mshr_miss_latency::total 11580.149703 # average overall mshr miss latency
857 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
859 ---------- End Simulation Statistics ----------
projects / gem5.git / blob