2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.025432 # Number of seconds simulated
4 sim_ticks 25432499000 # Number of ticks simulated
5 final_tick 25432499000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 141358 # Simulator instruction rate (inst/s)
8 host_op_rate 142373 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 39681246 # Simulator tick rate (ticks/s)
10 host_mem_usage 367916 # Number of bytes of host memory used
11 host_seconds 640.92 # Real time elapsed on the host
12 sim_insts 90599358 # Number of instructions simulated
13 sim_ops 91249911 # Number of ops (including micro ops) simulated
14 system.physmem.bytes_read::cpu.inst 45440 # Number of bytes read from this memory
15 system.physmem.bytes_read::cpu.data 947520 # Number of bytes read from this memory
16 system.physmem.bytes_read::total 992960 # Number of bytes read from this memory
17 system.physmem.bytes_inst_read::cpu.inst 45440 # Number of instructions bytes read from this memory
18 system.physmem.bytes_inst_read::total 45440 # Number of instructions bytes read from this memory
19 system.physmem.num_reads::cpu.inst 710 # Number of read requests responded to by this memory
20 system.physmem.num_reads::cpu.data 14805 # Number of read requests responded to by this memory
21 system.physmem.num_reads::total 15515 # Number of read requests responded to by this memory
22 system.physmem.bw_read::cpu.inst 1786690 # Total read bandwidth from this memory (bytes/s)
23 system.physmem.bw_read::cpu.data 37256268 # Total read bandwidth from this memory (bytes/s)
24 system.physmem.bw_read::total 39042958 # Total read bandwidth from this memory (bytes/s)
25 system.physmem.bw_inst_read::cpu.inst 1786690 # Instruction read bandwidth from this memory (bytes/s)
26 system.physmem.bw_inst_read::total 1786690 # Instruction read bandwidth from this memory (bytes/s)
27 system.physmem.bw_total::cpu.inst 1786690 # Total bandwidth to/from this memory (bytes/s)
28 system.physmem.bw_total::cpu.data 37256268 # Total bandwidth to/from this memory (bytes/s)
29 system.physmem.bw_total::total 39042958 # Total bandwidth to/from this memory (bytes/s)
30 system.cpu.dtb.inst_hits 0 # ITB inst hits
31 system.cpu.dtb.inst_misses 0 # ITB inst misses
32 system.cpu.dtb.read_hits 0 # DTB read hits
33 system.cpu.dtb.read_misses 0 # DTB read misses
34 system.cpu.dtb.write_hits 0 # DTB write hits
35 system.cpu.dtb.write_misses 0 # DTB write misses
36 system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
37 system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
38 system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
39 system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
40 system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
41 system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
42 system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
43 system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
44 system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
45 system.cpu.dtb.read_accesses 0 # DTB read accesses
46 system.cpu.dtb.write_accesses 0 # DTB write accesses
47 system.cpu.dtb.inst_accesses 0 # ITB inst accesses
48 system.cpu.dtb.hits 0 # DTB hits
49 system.cpu.dtb.misses 0 # DTB misses
50 system.cpu.dtb.accesses 0 # DTB accesses
51 system.cpu.itb.inst_hits 0 # ITB inst hits
52 system.cpu.itb.inst_misses 0 # ITB inst misses
53 system.cpu.itb.read_hits 0 # DTB read hits
54 system.cpu.itb.read_misses 0 # DTB read misses
55 system.cpu.itb.write_hits 0 # DTB write hits
56 system.cpu.itb.write_misses 0 # DTB write misses
57 system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
58 system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
59 system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
60 system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
61 system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
62 system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
63 system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
64 system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
65 system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
66 system.cpu.itb.read_accesses 0 # DTB read accesses
67 system.cpu.itb.write_accesses 0 # DTB write accesses
68 system.cpu.itb.inst_accesses 0 # ITB inst accesses
69 system.cpu.itb.hits 0 # DTB hits
70 system.cpu.itb.misses 0 # DTB misses
71 system.cpu.itb.accesses 0 # DTB accesses
72 system.cpu.workload.num_syscalls 442 # Number of system calls
73 system.cpu.numCycles 50864999 # number of cpu cycles simulated
74 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
75 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
76 system.cpu.BPredUnit.lookups 26815832 # Number of BP lookups
77 system.cpu.BPredUnit.condPredicted 22064400 # Number of conditional branches predicted
78 system.cpu.BPredUnit.condIncorrect 887268 # Number of conditional branches incorrect
79 system.cpu.BPredUnit.BTBLookups 11482840 # Number of BTB lookups
80 system.cpu.BPredUnit.BTBHits 11353380 # Number of BTB hits
81 system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
82 system.cpu.BPredUnit.usedRAS 72941 # Number of times the RAS was used to get a target.
83 system.cpu.BPredUnit.RASInCorrect 493 # Number of incorrect RAS predictions.
84 system.cpu.fetch.icacheStallCycles 14339573 # Number of cycles fetch is stalled on an Icache miss
85 system.cpu.fetch.Insts 128641990 # Number of instructions fetch has processed
86 system.cpu.fetch.Branches 26815832 # Number of branches that fetch encountered
87 system.cpu.fetch.predictedBranches 11426321 # Number of branches that fetch has predicted taken
88 system.cpu.fetch.Cycles 24202315 # Number of cycles fetch has run and was not squashing or blocked
89 system.cpu.fetch.SquashCycles 4802086 # Number of cycles fetch has spent squashing
90 system.cpu.fetch.BlockedCycles 8372764 # Number of cycles fetch has spent blocked
91 system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
92 system.cpu.fetch.PendingTrapStallCycles 27 # Number of stall cycles due to pending traps
93 system.cpu.fetch.CacheLines 14019260 # Number of cache lines fetched
94 system.cpu.fetch.IcacheSquashes 376949 # Number of outstanding Icache misses that were squashed
95 system.cpu.fetch.rateDist::samples 50826068 # Number of instructions fetched each cycle (Total)
96 system.cpu.fetch.rateDist::mean 2.549806 # Number of instructions fetched each cycle (Total)
97 system.cpu.fetch.rateDist::stdev 3.252225 # Number of instructions fetched each cycle (Total)
98 system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
99 system.cpu.fetch.rateDist::0 26661639 52.46% 52.46% # Number of instructions fetched each cycle (Total)
100 system.cpu.fetch.rateDist::1 3429294 6.75% 59.20% # Number of instructions fetched each cycle (Total)
101 system.cpu.fetch.rateDist::2 2034587 4.00% 63.21% # Number of instructions fetched each cycle (Total)
102 system.cpu.fetch.rateDist::3 1568872 3.09% 66.29% # Number of instructions fetched each cycle (Total)
103 system.cpu.fetch.rateDist::4 1675049 3.30% 69.59% # Number of instructions fetched each cycle (Total)
104 system.cpu.fetch.rateDist::5 2962794 5.83% 75.42% # Number of instructions fetched each cycle (Total)
105 system.cpu.fetch.rateDist::6 1484032 2.92% 78.34% # Number of instructions fetched each cycle (Total)
106 system.cpu.fetch.rateDist::7 1105241 2.17% 80.51% # Number of instructions fetched each cycle (Total)
107 system.cpu.fetch.rateDist::8 9904560 19.49% 100.00% # Number of instructions fetched each cycle (Total)
108 system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
109 system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
110 system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
111 system.cpu.fetch.rateDist::total 50826068 # Number of instructions fetched each cycle (Total)
112 system.cpu.fetch.branchRate 0.527196 # Number of branch fetches per cycle
113 system.cpu.fetch.rate 2.529087 # Number of inst fetches per cycle
114 system.cpu.decode.IdleCycles 16897392 # Number of cycles decode is idle
115 system.cpu.decode.BlockedCycles 6458273 # Number of cycles decode is blocked
116 system.cpu.decode.RunCycles 22716084 # Number of cycles decode is running
117 system.cpu.decode.UnblockCycles 851770 # Number of cycles decode is unblocking
118 system.cpu.decode.SquashCycles 3902549 # Number of cycles decode is squashing
119 system.cpu.decode.BranchResolved 4473858 # Number of times decode resolved a branch
120 system.cpu.decode.BranchMispred 8976 # Number of times decode detected a branch misprediction
121 system.cpu.decode.DecodedInsts 126855886 # Number of instructions handled by decode
122 system.cpu.decode.SquashedInsts 42929 # Number of squashed instructions handled by decode
123 system.cpu.rename.SquashCycles 3902549 # Number of cycles rename is squashing
124 system.cpu.rename.IdleCycles 18614164 # Number of cycles rename is idle
125 system.cpu.rename.BlockCycles 1601921 # Number of cycles rename is blocking
126 system.cpu.rename.serializeStallCycles 162955 # count of cycles rename stalled for serializing inst
127 system.cpu.rename.RunCycles 21830794 # Number of cycles rename is running
128 system.cpu.rename.UnblockCycles 4713685 # Number of cycles rename is unblocking
129 system.cpu.rename.RenamedInsts 123685119 # Number of instructions processed by rename
130 system.cpu.rename.IQFullEvents 281691 # Number of times rename has blocked due to IQ full
131 system.cpu.rename.LSQFullEvents 3991082 # Number of times rename has blocked due to LSQ full
132 system.cpu.rename.RenamedOperands 144136379 # Number of destination operands rename has renamed
133 system.cpu.rename.RenameLookups 538783715 # Number of register rename lookups that rename has made
134 system.cpu.rename.int_rename_lookups 538776344 # Number of integer rename lookups
135 system.cpu.rename.fp_rename_lookups 7371 # Number of floating rename lookups
136 system.cpu.rename.CommittedMaps 107429482 # Number of HB maps that are committed
137 system.cpu.rename.UndoneMaps 36706897 # Number of HB maps that are undone due to squashing
138 system.cpu.rename.serializingInsts 6470 # count of serializing insts renamed
139 system.cpu.rename.tempSerializingInsts 6468 # count of temporary serializing insts renamed
140 system.cpu.rename.skidInsts 10859255 # count of insts added to the skid buffer
141 system.cpu.memDep0.insertedLoads 29577544 # Number of loads inserted to the mem dependence unit.
142 system.cpu.memDep0.insertedStores 5541374 # Number of stores inserted to the mem dependence unit.
143 system.cpu.memDep0.conflictingLoads 2075747 # Number of conflicting loads.
144 system.cpu.memDep0.conflictingStores 1267218 # Number of conflicting stores.
145 system.cpu.iq.iqInstsAdded 118433426 # Number of instructions added to the IQ (excludes non-spec)
146 system.cpu.iq.iqNonSpecInstsAdded 10344 # Number of non-speculative instructions added to the IQ
147 system.cpu.iq.iqInstsIssued 105554764 # Number of instructions issued
148 system.cpu.iq.iqSquashedInstsIssued 73541 # Number of squashed instructions issued
149 system.cpu.iq.iqSquashedInstsExamined 26995758 # Number of squashed instructions iterated over during squash; mainly for profiling
150 system.cpu.iq.iqSquashedOperandsExamined 66330940 # Number of squashed operands that are examined and possibly removed from graph
151 system.cpu.iq.iqSquashedNonSpecRemoved 214 # Number of squashed non-spec instructions that were removed
152 system.cpu.iq.issued_per_cycle::samples 50826068 # Number of insts issued each cycle
153 system.cpu.iq.issued_per_cycle::mean 2.076784 # Number of insts issued each cycle
154 system.cpu.iq.issued_per_cycle::stdev 1.959181 # Number of insts issued each cycle
155 system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
156 system.cpu.iq.issued_per_cycle::0 13833219 27.22% 27.22% # Number of insts issued each cycle
157 system.cpu.iq.issued_per_cycle::1 10749724 21.15% 48.37% # Number of insts issued each cycle
158 system.cpu.iq.issued_per_cycle::2 7931783 15.61% 63.97% # Number of insts issued each cycle
159 system.cpu.iq.issued_per_cycle::3 6457025 12.70% 76.68% # Number of insts issued each cycle
160 system.cpu.iq.issued_per_cycle::4 4857915 9.56% 86.23% # Number of insts issued each cycle
161 system.cpu.iq.issued_per_cycle::5 3493885 6.87% 93.11% # Number of insts issued each cycle
162 system.cpu.iq.issued_per_cycle::6 2371067 4.67% 97.77% # Number of insts issued each cycle
163 system.cpu.iq.issued_per_cycle::7 608688 1.20% 98.97% # Number of insts issued each cycle
164 system.cpu.iq.issued_per_cycle::8 522762 1.03% 100.00% # Number of insts issued each cycle
165 system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
166 system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
167 system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
168 system.cpu.iq.issued_per_cycle::total 50826068 # Number of insts issued each cycle
169 system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
170 system.cpu.iq.fu_full::IntAlu 142420 18.36% 18.36% # attempts to use FU when none available
171 system.cpu.iq.fu_full::IntMult 27 0.00% 18.37% # attempts to use FU when none available
172 system.cpu.iq.fu_full::IntDiv 0 0.00% 18.37% # attempts to use FU when none available
173 system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.37% # attempts to use FU when none available
174 system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.37% # attempts to use FU when none available
175 system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.37% # attempts to use FU when none available
176 system.cpu.iq.fu_full::FloatMult 0 0.00% 18.37% # attempts to use FU when none available
177 system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.37% # attempts to use FU when none available
178 system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.37% # attempts to use FU when none available
179 system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.37% # attempts to use FU when none available
180 system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.37% # attempts to use FU when none available
181 system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.37% # attempts to use FU when none available
182 system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.37% # attempts to use FU when none available
183 system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.37% # attempts to use FU when none available
184 system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.37% # attempts to use FU when none available
185 system.cpu.iq.fu_full::SimdMult 0 0.00% 18.37% # attempts to use FU when none available
186 system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.37% # attempts to use FU when none available
187 system.cpu.iq.fu_full::SimdShift 0 0.00% 18.37% # attempts to use FU when none available
188 system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.37% # attempts to use FU when none available
189 system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.37% # attempts to use FU when none available
190 system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.37% # attempts to use FU when none available
191 system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.37% # attempts to use FU when none available
192 system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.37% # attempts to use FU when none available
193 system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.37% # attempts to use FU when none available
194 system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.37% # attempts to use FU when none available
195 system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 18.37% # attempts to use FU when none available
196 system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.37% # attempts to use FU when none available
197 system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.37% # attempts to use FU when none available
198 system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.37% # attempts to use FU when none available
199 system.cpu.iq.fu_full::MemRead 354766 45.74% 64.11% # attempts to use FU when none available
200 system.cpu.iq.fu_full::MemWrite 278332 35.89% 100.00% # attempts to use FU when none available
201 system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
202 system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
203 system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
204 system.cpu.iq.FU_type_0::IntAlu 74645911 70.72% 70.72% # Type of FU issued
205 system.cpu.iq.FU_type_0::IntMult 10962 0.01% 70.73% # Type of FU issued
206 system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.73% # Type of FU issued
207 system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.73% # Type of FU issued
208 system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.73% # Type of FU issued
209 system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.73% # Type of FU issued
210 system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.73% # Type of FU issued
211 system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.73% # Type of FU issued
212 system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.73% # Type of FU issued
213 system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.73% # Type of FU issued
214 system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.73% # Type of FU issued
215 system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.73% # Type of FU issued
216 system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.73% # Type of FU issued
217 system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.73% # Type of FU issued
218 system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.73% # Type of FU issued
219 system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.73% # Type of FU issued
220 system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.73% # Type of FU issued
221 system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.73% # Type of FU issued
222 system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.73% # Type of FU issued
223 system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.73% # Type of FU issued
224 system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.73% # Type of FU issued
225 system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.73% # Type of FU issued
226 system.cpu.iq.FU_type_0::SimdFloatCmp 2 0.00% 70.73% # Type of FU issued
227 system.cpu.iq.FU_type_0::SimdFloatCvt 239 0.00% 70.73% # Type of FU issued
228 system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.73% # Type of FU issued
229 system.cpu.iq.FU_type_0::SimdFloatMisc 298 0.00% 70.73% # Type of FU issued
230 system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.73% # Type of FU issued
231 system.cpu.iq.FU_type_0::SimdFloatMultAcc 3 0.00% 70.73% # Type of FU issued
232 system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.73% # Type of FU issued
233 system.cpu.iq.FU_type_0::MemRead 25762945 24.41% 95.14% # Type of FU issued
234 system.cpu.iq.FU_type_0::MemWrite 5134404 4.86% 100.00% # Type of FU issued
235 system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
236 system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
237 system.cpu.iq.FU_type_0::total 105554764 # Type of FU issued
238 system.cpu.iq.rate 2.075194 # Inst issue rate
239 system.cpu.iq.fu_busy_cnt 775545 # FU busy when requested
240 system.cpu.iq.fu_busy_rate 0.007347 # FU busy rate (busy events/executed inst)
241 system.cpu.iq.int_inst_queue_reads 262783539 # Number of integer instruction queue reads
242 system.cpu.iq.int_inst_queue_writes 145440732 # Number of integer instruction queue writes
243 system.cpu.iq.int_inst_queue_wakeup_accesses 102807034 # Number of integer instruction queue wakeup accesses
244 system.cpu.iq.fp_inst_queue_reads 1143 # Number of floating instruction queue reads
245 system.cpu.iq.fp_inst_queue_writes 1553 # Number of floating instruction queue writes
246 system.cpu.iq.fp_inst_queue_wakeup_accesses 495 # Number of floating instruction queue wakeup accesses
247 system.cpu.iq.int_alu_accesses 106329739 # Number of integer alu accesses
248 system.cpu.iq.fp_alu_accesses 570 # Number of floating point alu accesses
249 system.cpu.iew.lsq.thread0.forwLoads 435536 # Number of loads that had data forwarded from stores
250 system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
251 system.cpu.iew.lsq.thread0.squashedLoads 7001666 # Number of loads squashed
252 system.cpu.iew.lsq.thread0.ignoredResponses 7849 # Number of memory responses ignored because the instruction is squashed
253 system.cpu.iew.lsq.thread0.memOrderViolation 3639 # Number of memory ordering violations
254 system.cpu.iew.lsq.thread0.squashedStores 794618 # Number of stores squashed
255 system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
256 system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
257 system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
258 system.cpu.iew.lsq.thread0.cacheBlocked 13641 # Number of times an access to memory failed due to the cache being blocked
259 system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
260 system.cpu.iew.iewSquashCycles 3902549 # Number of cycles IEW is squashing
261 system.cpu.iew.iewBlockCycles 96175 # Number of cycles IEW is blocking
262 system.cpu.iew.iewUnblockCycles 18780 # Number of cycles IEW is unblocking
263 system.cpu.iew.iewDispatchedInsts 118456487 # Number of instructions dispatched to IQ
264 system.cpu.iew.iewDispSquashedInsts 345131 # Number of squashed instructions skipped by dispatch
265 system.cpu.iew.iewDispLoadInsts 29577544 # Number of dispatched load instructions
266 system.cpu.iew.iewDispStoreInsts 5541374 # Number of dispatched store instructions
267 system.cpu.iew.iewDispNonSpecInsts 6439 # Number of dispatched non-speculative instructions
268 system.cpu.iew.iewIQFullEvents 4987 # Number of times the IQ has become full, causing a stall
269 system.cpu.iew.iewLSQFullEvents 4015 # Number of times the LSQ has become full, causing a stall
270 system.cpu.iew.memOrderViolationEvents 3639 # Number of memory order violations
271 system.cpu.iew.predictedTakenIncorrect 474441 # Number of branches that were predicted taken incorrectly
272 system.cpu.iew.predictedNotTakenIncorrect 478533 # Number of branches that were predicted not taken incorrectly
273 system.cpu.iew.branchMispredicts 952974 # Number of branch mispredicts detected at execute
274 system.cpu.iew.iewExecutedInsts 104393226 # Number of executed instructions
275 system.cpu.iew.iewExecLoadInsts 25307547 # Number of load instructions executed
276 system.cpu.iew.iewExecSquashedInsts 1161538 # Number of squashed instructions skipped in execute
277 system.cpu.iew.exec_swp 0 # number of swp insts executed
278 system.cpu.iew.exec_nop 12717 # number of nop insts executed
279 system.cpu.iew.exec_refs 30377969 # number of memory reference insts executed
280 system.cpu.iew.exec_branches 21353332 # Number of branches executed
281 system.cpu.iew.exec_stores 5070422 # Number of stores executed
282 system.cpu.iew.exec_rate 2.052359 # Inst execution rate
283 system.cpu.iew.wb_sent 103118433 # cumulative count of insts sent to commit
284 system.cpu.iew.wb_count 102807529 # cumulative count of insts written-back
285 system.cpu.iew.wb_producers 62180383 # num instructions producing a value
286 system.cpu.iew.wb_consumers 104132992 # num instructions consuming a value
287 system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
288 system.cpu.iew.wb_rate 2.021184 # insts written-back per cycle
289 system.cpu.iew.wb_fanout 0.597125 # average fanout of values written-back
290 system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
291 system.cpu.commit.commitSquashedInsts 27194508 # The number of squashed insts skipped by commit
292 system.cpu.commit.commitNonSpecStalls 10130 # The number of times commit has been forced to stall to communicate backwards
293 system.cpu.commit.branchMispredicts 878429 # The number of times a branch was mispredicted
294 system.cpu.commit.committed_per_cycle::samples 46923520 # Number of insts commited each cycle
295 system.cpu.commit.committed_per_cycle::mean 1.944921 # Number of insts commited each cycle
296 system.cpu.commit.committed_per_cycle::stdev 2.520501 # Number of insts commited each cycle
297 system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
298 system.cpu.commit.committed_per_cycle::0 16620645 35.42% 35.42% # Number of insts commited each cycle
299 system.cpu.commit.committed_per_cycle::1 13501207 28.77% 64.19% # Number of insts commited each cycle
300 system.cpu.commit.committed_per_cycle::2 4487454 9.56% 73.76% # Number of insts commited each cycle
301 system.cpu.commit.committed_per_cycle::3 3864489 8.24% 81.99% # Number of insts commited each cycle
302 system.cpu.commit.committed_per_cycle::4 1521327 3.24% 85.23% # Number of insts commited each cycle
303 system.cpu.commit.committed_per_cycle::5 782022 1.67% 86.90% # Number of insts commited each cycle
304 system.cpu.commit.committed_per_cycle::6 855558 1.82% 88.72% # Number of insts commited each cycle
305 system.cpu.commit.committed_per_cycle::7 262372 0.56% 89.28% # Number of insts commited each cycle
306 system.cpu.commit.committed_per_cycle::8 5028446 10.72% 100.00% # Number of insts commited each cycle
307 system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
308 system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
309 system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
310 system.cpu.commit.committed_per_cycle::total 46923520 # Number of insts commited each cycle
311 system.cpu.commit.committedInsts 90611967 # Number of instructions committed
312 system.cpu.commit.committedOps 91262520 # Number of ops (including micro ops) committed
313 system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
314 system.cpu.commit.refs 27322634 # Number of memory references committed
315 system.cpu.commit.loads 22575878 # Number of loads committed
316 system.cpu.commit.membars 3888 # Number of memory barriers committed
317 system.cpu.commit.branches 18734216 # Number of branches committed
318 system.cpu.commit.fp_insts 48 # Number of committed floating point instructions.
319 system.cpu.commit.int_insts 72533322 # Number of committed integer instructions.
320 system.cpu.commit.function_calls 56148 # Number of function calls committed.
321 system.cpu.commit.bw_lim_events 5028446 # number cycles where commit BW limit reached
322 system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
323 system.cpu.rob.rob_reads 160346368 # The number of ROB reads
324 system.cpu.rob.rob_writes 240838970 # The number of ROB writes
325 system.cpu.timesIdled 1282 # Number of times that the entire CPU went into an idle state and unscheduled itself
326 system.cpu.idleCycles 38931 # Total number of cycles that the CPU has spent unscheduled due to idling
327 system.cpu.committedInsts 90599358 # Number of Instructions Simulated
328 system.cpu.committedOps 91249911 # Number of Ops (including micro ops) Simulated
329 system.cpu.committedInsts_total 90599358 # Number of Instructions Simulated
330 system.cpu.cpi 0.561428 # CPI: Cycles Per Instruction
331 system.cpu.cpi_total 0.561428 # CPI: Total CPI of All Threads
332 system.cpu.ipc 1.781173 # IPC: Instructions Per Cycle
333 system.cpu.ipc_total 1.781173 # IPC: Total IPC of All Threads
334 system.cpu.int_regfile_reads 496237676 # number of integer regfile reads
335 system.cpu.int_regfile_writes 120715642 # number of integer regfile writes
336 system.cpu.fp_regfile_reads 235 # number of floating regfile reads
337 system.cpu.fp_regfile_writes 643 # number of floating regfile writes
338 system.cpu.misc_regfile_reads 182128613 # number of misc regfile reads
339 system.cpu.misc_regfile_writes 11608 # number of misc regfile writes
340 system.cpu.icache.replacements 3 # number of replacements
341 system.cpu.icache.tagsinuse 635.871073 # Cycle average of tags in use
342 system.cpu.icache.total_refs 14018279 # Total number of references to valid blocks.
343 system.cpu.icache.sampled_refs 738 # Sample count of references to valid blocks.
344 system.cpu.icache.avg_refs 18994.957995 # Average number of references to valid blocks.
345 system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
346 system.cpu.icache.occ_blocks::cpu.inst 635.871073 # Average occupied blocks per requestor
347 system.cpu.icache.occ_percent::cpu.inst 0.310484 # Average percentage of cache occupancy
348 system.cpu.icache.occ_percent::total 0.310484 # Average percentage of cache occupancy
349 system.cpu.icache.ReadReq_hits::cpu.inst 14018279 # number of ReadReq hits
350 system.cpu.icache.ReadReq_hits::total 14018279 # number of ReadReq hits
351 system.cpu.icache.demand_hits::cpu.inst 14018279 # number of demand (read+write) hits
352 system.cpu.icache.demand_hits::total 14018279 # number of demand (read+write) hits
353 system.cpu.icache.overall_hits::cpu.inst 14018279 # number of overall hits
354 system.cpu.icache.overall_hits::total 14018279 # number of overall hits
355 system.cpu.icache.ReadReq_misses::cpu.inst 981 # number of ReadReq misses
356 system.cpu.icache.ReadReq_misses::total 981 # number of ReadReq misses
357 system.cpu.icache.demand_misses::cpu.inst 981 # number of demand (read+write) misses
358 system.cpu.icache.demand_misses::total 981 # number of demand (read+write) misses
359 system.cpu.icache.overall_misses::cpu.inst 981 # number of overall misses
360 system.cpu.icache.overall_misses::total 981 # number of overall misses
361 system.cpu.icache.ReadReq_miss_latency::cpu.inst 34205000 # number of ReadReq miss cycles
362 system.cpu.icache.ReadReq_miss_latency::total 34205000 # number of ReadReq miss cycles
363 system.cpu.icache.demand_miss_latency::cpu.inst 34205000 # number of demand (read+write) miss cycles
364 system.cpu.icache.demand_miss_latency::total 34205000 # number of demand (read+write) miss cycles
365 system.cpu.icache.overall_miss_latency::cpu.inst 34205000 # number of overall miss cycles
366 system.cpu.icache.overall_miss_latency::total 34205000 # number of overall miss cycles
367 system.cpu.icache.ReadReq_accesses::cpu.inst 14019260 # number of ReadReq accesses(hits+misses)
368 system.cpu.icache.ReadReq_accesses::total 14019260 # number of ReadReq accesses(hits+misses)
369 system.cpu.icache.demand_accesses::cpu.inst 14019260 # number of demand (read+write) accesses
370 system.cpu.icache.demand_accesses::total 14019260 # number of demand (read+write) accesses
371 system.cpu.icache.overall_accesses::cpu.inst 14019260 # number of overall (read+write) accesses
372 system.cpu.icache.overall_accesses::total 14019260 # number of overall (read+write) accesses
373 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000070 # miss rate for ReadReq accesses
374 system.cpu.icache.ReadReq_miss_rate::total 0.000070 # miss rate for ReadReq accesses
375 system.cpu.icache.demand_miss_rate::cpu.inst 0.000070 # miss rate for demand accesses
376 system.cpu.icache.demand_miss_rate::total 0.000070 # miss rate for demand accesses
377 system.cpu.icache.overall_miss_rate::cpu.inst 0.000070 # miss rate for overall accesses
378 system.cpu.icache.overall_miss_rate::total 0.000070 # miss rate for overall accesses
379 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34867.482161 # average ReadReq miss latency
380 system.cpu.icache.ReadReq_avg_miss_latency::total 34867.482161 # average ReadReq miss latency
381 system.cpu.icache.demand_avg_miss_latency::cpu.inst 34867.482161 # average overall miss latency
382 system.cpu.icache.demand_avg_miss_latency::total 34867.482161 # average overall miss latency
383 system.cpu.icache.overall_avg_miss_latency::cpu.inst 34867.482161 # average overall miss latency
384 system.cpu.icache.overall_avg_miss_latency::total 34867.482161 # average overall miss latency
385 system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
386 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
387 system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
388 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
389 system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
390 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
391 system.cpu.icache.fast_writes 0 # number of fast writes performed
392 system.cpu.icache.cache_copies 0 # number of cache copies performed
393 system.cpu.icache.ReadReq_mshr_hits::cpu.inst 243 # number of ReadReq MSHR hits
394 system.cpu.icache.ReadReq_mshr_hits::total 243 # number of ReadReq MSHR hits
395 system.cpu.icache.demand_mshr_hits::cpu.inst 243 # number of demand (read+write) MSHR hits
396 system.cpu.icache.demand_mshr_hits::total 243 # number of demand (read+write) MSHR hits
397 system.cpu.icache.overall_mshr_hits::cpu.inst 243 # number of overall MSHR hits
398 system.cpu.icache.overall_mshr_hits::total 243 # number of overall MSHR hits
399 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 738 # number of ReadReq MSHR misses
400 system.cpu.icache.ReadReq_mshr_misses::total 738 # number of ReadReq MSHR misses
401 system.cpu.icache.demand_mshr_misses::cpu.inst 738 # number of demand (read+write) MSHR misses
402 system.cpu.icache.demand_mshr_misses::total 738 # number of demand (read+write) MSHR misses
403 system.cpu.icache.overall_mshr_misses::cpu.inst 738 # number of overall MSHR misses
404 system.cpu.icache.overall_mshr_misses::total 738 # number of overall MSHR misses
405 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 26308000 # number of ReadReq MSHR miss cycles
406 system.cpu.icache.ReadReq_mshr_miss_latency::total 26308000 # number of ReadReq MSHR miss cycles
407 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 26308000 # number of demand (read+write) MSHR miss cycles
408 system.cpu.icache.demand_mshr_miss_latency::total 26308000 # number of demand (read+write) MSHR miss cycles
409 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 26308000 # number of overall MSHR miss cycles
410 system.cpu.icache.overall_mshr_miss_latency::total 26308000 # number of overall MSHR miss cycles
411 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for ReadReq accesses
412 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000053 # mshr miss rate for ReadReq accesses
413 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for demand accesses
414 system.cpu.icache.demand_mshr_miss_rate::total 0.000053 # mshr miss rate for demand accesses
415 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for overall accesses
416 system.cpu.icache.overall_mshr_miss_rate::total 0.000053 # mshr miss rate for overall accesses
417 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35647.696477 # average ReadReq mshr miss latency
418 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35647.696477 # average ReadReq mshr miss latency
419 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35647.696477 # average overall mshr miss latency
420 system.cpu.icache.demand_avg_mshr_miss_latency::total 35647.696477 # average overall mshr miss latency
421 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35647.696477 # average overall mshr miss latency
422 system.cpu.icache.overall_avg_mshr_miss_latency::total 35647.696477 # average overall mshr miss latency
423 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
424 system.cpu.dcache.replacements 943636 # number of replacements
425 system.cpu.dcache.tagsinuse 3643.742201 # Cycle average of tags in use
426 system.cpu.dcache.total_refs 28404607 # Total number of references to valid blocks.
427 system.cpu.dcache.sampled_refs 947732 # Sample count of references to valid blocks.
428 system.cpu.dcache.avg_refs 29.971138 # Average number of references to valid blocks.
429 system.cpu.dcache.warmup_cycle 8103531000 # Cycle when the warmup percentage was hit.
430 system.cpu.dcache.occ_blocks::cpu.data 3643.742201 # Average occupied blocks per requestor
431 system.cpu.dcache.occ_percent::cpu.data 0.889585 # Average percentage of cache occupancy
432 system.cpu.dcache.occ_percent::total 0.889585 # Average percentage of cache occupancy
433 system.cpu.dcache.ReadReq_hits::cpu.data 23813813 # number of ReadReq hits
434 system.cpu.dcache.ReadReq_hits::total 23813813 # number of ReadReq hits
435 system.cpu.dcache.WriteReq_hits::cpu.data 4579150 # number of WriteReq hits
436 system.cpu.dcache.WriteReq_hits::total 4579150 # number of WriteReq hits
437 system.cpu.dcache.LoadLockedReq_hits::cpu.data 5845 # number of LoadLockedReq hits
438 system.cpu.dcache.LoadLockedReq_hits::total 5845 # number of LoadLockedReq hits
439 system.cpu.dcache.StoreCondReq_hits::cpu.data 5799 # number of StoreCondReq hits
440 system.cpu.dcache.StoreCondReq_hits::total 5799 # number of StoreCondReq hits
441 system.cpu.dcache.demand_hits::cpu.data 28392963 # number of demand (read+write) hits
442 system.cpu.dcache.demand_hits::total 28392963 # number of demand (read+write) hits
443 system.cpu.dcache.overall_hits::cpu.data 28392963 # number of overall hits
444 system.cpu.dcache.overall_hits::total 28392963 # number of overall hits
445 system.cpu.dcache.ReadReq_misses::cpu.data 995922 # number of ReadReq misses
446 system.cpu.dcache.ReadReq_misses::total 995922 # number of ReadReq misses
447 system.cpu.dcache.WriteReq_misses::cpu.data 155831 # number of WriteReq misses
448 system.cpu.dcache.WriteReq_misses::total 155831 # number of WriteReq misses
449 system.cpu.dcache.LoadLockedReq_misses::cpu.data 7 # number of LoadLockedReq misses
450 system.cpu.dcache.LoadLockedReq_misses::total 7 # number of LoadLockedReq misses
451 system.cpu.dcache.demand_misses::cpu.data 1151753 # number of demand (read+write) misses
452 system.cpu.dcache.demand_misses::total 1151753 # number of demand (read+write) misses
453 system.cpu.dcache.overall_misses::cpu.data 1151753 # number of overall misses
454 system.cpu.dcache.overall_misses::total 1151753 # number of overall misses
455 system.cpu.dcache.ReadReq_miss_latency::cpu.data 4102006500 # number of ReadReq miss cycles
456 system.cpu.dcache.ReadReq_miss_latency::total 4102006500 # number of ReadReq miss cycles
457 system.cpu.dcache.WriteReq_miss_latency::cpu.data 4011864060 # number of WriteReq miss cycles
458 system.cpu.dcache.WriteReq_miss_latency::total 4011864060 # number of WriteReq miss cycles
459 system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 120000 # number of LoadLockedReq miss cycles
460 system.cpu.dcache.LoadLockedReq_miss_latency::total 120000 # number of LoadLockedReq miss cycles
461 system.cpu.dcache.demand_miss_latency::cpu.data 8113870560 # number of demand (read+write) miss cycles
462 system.cpu.dcache.demand_miss_latency::total 8113870560 # number of demand (read+write) miss cycles
463 system.cpu.dcache.overall_miss_latency::cpu.data 8113870560 # number of overall miss cycles
464 system.cpu.dcache.overall_miss_latency::total 8113870560 # number of overall miss cycles
465 system.cpu.dcache.ReadReq_accesses::cpu.data 24809735 # number of ReadReq accesses(hits+misses)
466 system.cpu.dcache.ReadReq_accesses::total 24809735 # number of ReadReq accesses(hits+misses)
467 system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses)
468 system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses)
469 system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5852 # number of LoadLockedReq accesses(hits+misses)
470 system.cpu.dcache.LoadLockedReq_accesses::total 5852 # number of LoadLockedReq accesses(hits+misses)
471 system.cpu.dcache.StoreCondReq_accesses::cpu.data 5799 # number of StoreCondReq accesses(hits+misses)
472 system.cpu.dcache.StoreCondReq_accesses::total 5799 # number of StoreCondReq accesses(hits+misses)
473 system.cpu.dcache.demand_accesses::cpu.data 29544716 # number of demand (read+write) accesses
474 system.cpu.dcache.demand_accesses::total 29544716 # number of demand (read+write) accesses
475 system.cpu.dcache.overall_accesses::cpu.data 29544716 # number of overall (read+write) accesses
476 system.cpu.dcache.overall_accesses::total 29544716 # number of overall (read+write) accesses
477 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040142 # miss rate for ReadReq accesses
478 system.cpu.dcache.ReadReq_miss_rate::total 0.040142 # miss rate for ReadReq accesses
479 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032911 # miss rate for WriteReq accesses
480 system.cpu.dcache.WriteReq_miss_rate::total 0.032911 # miss rate for WriteReq accesses
481 system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001196 # miss rate for LoadLockedReq accesses
482 system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001196 # miss rate for LoadLockedReq accesses
483 system.cpu.dcache.demand_miss_rate::cpu.data 0.038983 # miss rate for demand accesses
484 system.cpu.dcache.demand_miss_rate::total 0.038983 # miss rate for demand accesses
485 system.cpu.dcache.overall_miss_rate::cpu.data 0.038983 # miss rate for overall accesses
486 system.cpu.dcache.overall_miss_rate::total 0.038983 # miss rate for overall accesses
487 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 4118.802979 # average ReadReq miss latency
488 system.cpu.dcache.ReadReq_avg_miss_latency::total 4118.802979 # average ReadReq miss latency
489 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 25744.967689 # average WriteReq miss latency
490 system.cpu.dcache.WriteReq_avg_miss_latency::total 25744.967689 # average WriteReq miss latency
491 system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 17142.857143 # average LoadLockedReq miss latency
492 system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 17142.857143 # average LoadLockedReq miss latency
493 system.cpu.dcache.demand_avg_miss_latency::cpu.data 7044.800890 # average overall miss latency
494 system.cpu.dcache.demand_avg_miss_latency::total 7044.800890 # average overall miss latency
495 system.cpu.dcache.overall_avg_miss_latency::cpu.data 7044.800890 # average overall miss latency
496 system.cpu.dcache.overall_avg_miss_latency::total 7044.800890 # average overall miss latency
497 system.cpu.dcache.blocked_cycles::no_mshrs 8960217 # number of cycles access was blocked
498 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
499 system.cpu.dcache.blocked::no_mshrs 6519 # number of cycles access was blocked
500 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
501 system.cpu.dcache.avg_blocked_cycles::no_mshrs 1374.477220 # average number of cycles each access was blocked
502 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
503 system.cpu.dcache.fast_writes 0 # number of fast writes performed
504 system.cpu.dcache.cache_copies 0 # number of cache copies performed
505 system.cpu.dcache.writebacks::writebacks 943006 # number of writebacks
506 system.cpu.dcache.writebacks::total 943006 # number of writebacks
507 system.cpu.dcache.ReadReq_mshr_hits::cpu.data 82809 # number of ReadReq MSHR hits
508 system.cpu.dcache.ReadReq_mshr_hits::total 82809 # number of ReadReq MSHR hits
509 system.cpu.dcache.WriteReq_mshr_hits::cpu.data 121212 # number of WriteReq MSHR hits
510 system.cpu.dcache.WriteReq_mshr_hits::total 121212 # number of WriteReq MSHR hits
511 system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 7 # number of LoadLockedReq MSHR hits
512 system.cpu.dcache.LoadLockedReq_mshr_hits::total 7 # number of LoadLockedReq MSHR hits
513 system.cpu.dcache.demand_mshr_hits::cpu.data 204021 # number of demand (read+write) MSHR hits
514 system.cpu.dcache.demand_mshr_hits::total 204021 # number of demand (read+write) MSHR hits
515 system.cpu.dcache.overall_mshr_hits::cpu.data 204021 # number of overall MSHR hits
516 system.cpu.dcache.overall_mshr_hits::total 204021 # number of overall MSHR hits
517 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 913113 # number of ReadReq MSHR misses
518 system.cpu.dcache.ReadReq_mshr_misses::total 913113 # number of ReadReq MSHR misses
519 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 34619 # number of WriteReq MSHR misses
520 system.cpu.dcache.WriteReq_mshr_misses::total 34619 # number of WriteReq MSHR misses
521 system.cpu.dcache.demand_mshr_misses::cpu.data 947732 # number of demand (read+write) MSHR misses
522 system.cpu.dcache.demand_mshr_misses::total 947732 # number of demand (read+write) MSHR misses
523 system.cpu.dcache.overall_mshr_misses::cpu.data 947732 # number of overall MSHR misses
524 system.cpu.dcache.overall_mshr_misses::total 947732 # number of overall MSHR misses
525 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1880225500 # number of ReadReq MSHR miss cycles
526 system.cpu.dcache.ReadReq_mshr_miss_latency::total 1880225500 # number of ReadReq MSHR miss cycles
527 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 702020509 # number of WriteReq MSHR miss cycles
528 system.cpu.dcache.WriteReq_mshr_miss_latency::total 702020509 # number of WriteReq MSHR miss cycles
529 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 2582246009 # number of demand (read+write) MSHR miss cycles
530 system.cpu.dcache.demand_mshr_miss_latency::total 2582246009 # number of demand (read+write) MSHR miss cycles
531 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 2582246009 # number of overall MSHR miss cycles
532 system.cpu.dcache.overall_mshr_miss_latency::total 2582246009 # number of overall MSHR miss cycles
533 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036805 # mshr miss rate for ReadReq accesses
534 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036805 # mshr miss rate for ReadReq accesses
535 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.007311 # mshr miss rate for WriteReq accesses
536 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.007311 # mshr miss rate for WriteReq accesses
537 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032078 # mshr miss rate for demand accesses
538 system.cpu.dcache.demand_mshr_miss_rate::total 0.032078 # mshr miss rate for demand accesses
539 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032078 # mshr miss rate for overall accesses
540 system.cpu.dcache.overall_mshr_miss_rate::total 0.032078 # mshr miss rate for overall accesses
541 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 2059.137807 # average ReadReq mshr miss latency
542 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 2059.137807 # average ReadReq mshr miss latency
543 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 20278.474508 # average WriteReq mshr miss latency
544 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 20278.474508 # average WriteReq mshr miss latency
545 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 2724.658457 # average overall mshr miss latency
546 system.cpu.dcache.demand_avg_mshr_miss_latency::total 2724.658457 # average overall mshr miss latency
547 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 2724.658457 # average overall mshr miss latency
548 system.cpu.dcache.overall_avg_mshr_miss_latency::total 2724.658457 # average overall mshr miss latency
549 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
550 system.cpu.l2cache.replacements 0 # number of replacements
551 system.cpu.l2cache.tagsinuse 10473.281508 # Cycle average of tags in use
552 system.cpu.l2cache.total_refs 1840746 # Total number of references to valid blocks.
553 system.cpu.l2cache.sampled_refs 15498 # Sample count of references to valid blocks.
554 system.cpu.l2cache.avg_refs 118.773132 # Average number of references to valid blocks.
555 system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
556 system.cpu.l2cache.occ_blocks::writebacks 9624.671236 # Average occupied blocks per requestor
557 system.cpu.l2cache.occ_blocks::cpu.inst 619.272725 # Average occupied blocks per requestor
558 system.cpu.l2cache.occ_blocks::cpu.data 229.337548 # Average occupied blocks per requestor
559 system.cpu.l2cache.occ_percent::writebacks 0.293722 # Average percentage of cache occupancy
560 system.cpu.l2cache.occ_percent::cpu.inst 0.018899 # Average percentage of cache occupancy
561 system.cpu.l2cache.occ_percent::cpu.data 0.006999 # Average percentage of cache occupancy
562 system.cpu.l2cache.occ_percent::total 0.319619 # Average percentage of cache occupancy
563 system.cpu.l2cache.ReadReq_hits::cpu.inst 26 # number of ReadReq hits
564 system.cpu.l2cache.ReadReq_hits::cpu.data 912835 # number of ReadReq hits
565 system.cpu.l2cache.ReadReq_hits::total 912861 # number of ReadReq hits
566 system.cpu.l2cache.Writeback_hits::writebacks 943006 # number of Writeback hits
567 system.cpu.l2cache.Writeback_hits::total 943006 # number of Writeback hits
568 system.cpu.l2cache.ReadExReq_hits::cpu.data 20082 # number of ReadExReq hits
569 system.cpu.l2cache.ReadExReq_hits::total 20082 # number of ReadExReq hits
570 system.cpu.l2cache.demand_hits::cpu.inst 26 # number of demand (read+write) hits
571 system.cpu.l2cache.demand_hits::cpu.data 932917 # number of demand (read+write) hits
572 system.cpu.l2cache.demand_hits::total 932943 # number of demand (read+write) hits
573 system.cpu.l2cache.overall_hits::cpu.inst 26 # number of overall hits
574 system.cpu.l2cache.overall_hits::cpu.data 932917 # number of overall hits
575 system.cpu.l2cache.overall_hits::total 932943 # number of overall hits
576 system.cpu.l2cache.ReadReq_misses::cpu.inst 712 # number of ReadReq misses
577 system.cpu.l2cache.ReadReq_misses::cpu.data 277 # number of ReadReq misses
578 system.cpu.l2cache.ReadReq_misses::total 989 # number of ReadReq misses
579 system.cpu.l2cache.ReadExReq_misses::cpu.data 14538 # number of ReadExReq misses
580 system.cpu.l2cache.ReadExReq_misses::total 14538 # number of ReadExReq misses
581 system.cpu.l2cache.demand_misses::cpu.inst 712 # number of demand (read+write) misses
582 system.cpu.l2cache.demand_misses::cpu.data 14815 # number of demand (read+write) misses
583 system.cpu.l2cache.demand_misses::total 15527 # number of demand (read+write) misses
584 system.cpu.l2cache.overall_misses::cpu.inst 712 # number of overall misses
585 system.cpu.l2cache.overall_misses::cpu.data 14815 # number of overall misses
586 system.cpu.l2cache.overall_misses::total 15527 # number of overall misses
587 system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 25530000 # number of ReadReq miss cycles
588 system.cpu.l2cache.ReadReq_miss_latency::cpu.data 10241500 # number of ReadReq miss cycles
589 system.cpu.l2cache.ReadReq_miss_latency::total 35771500 # number of ReadReq miss cycles
590 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 499278500 # number of ReadExReq miss cycles
591 system.cpu.l2cache.ReadExReq_miss_latency::total 499278500 # number of ReadExReq miss cycles
592 system.cpu.l2cache.demand_miss_latency::cpu.inst 25530000 # number of demand (read+write) miss cycles
593 system.cpu.l2cache.demand_miss_latency::cpu.data 509520000 # number of demand (read+write) miss cycles
594 system.cpu.l2cache.demand_miss_latency::total 535050000 # number of demand (read+write) miss cycles
595 system.cpu.l2cache.overall_miss_latency::cpu.inst 25530000 # number of overall miss cycles
596 system.cpu.l2cache.overall_miss_latency::cpu.data 509520000 # number of overall miss cycles
597 system.cpu.l2cache.overall_miss_latency::total 535050000 # number of overall miss cycles
598 system.cpu.l2cache.ReadReq_accesses::cpu.inst 738 # number of ReadReq accesses(hits+misses)
599 system.cpu.l2cache.ReadReq_accesses::cpu.data 913112 # number of ReadReq accesses(hits+misses)
600 system.cpu.l2cache.ReadReq_accesses::total 913850 # number of ReadReq accesses(hits+misses)
601 system.cpu.l2cache.Writeback_accesses::writebacks 943006 # number of Writeback accesses(hits+misses)
602 system.cpu.l2cache.Writeback_accesses::total 943006 # number of Writeback accesses(hits+misses)
603 system.cpu.l2cache.ReadExReq_accesses::cpu.data 34620 # number of ReadExReq accesses(hits+misses)
604 system.cpu.l2cache.ReadExReq_accesses::total 34620 # number of ReadExReq accesses(hits+misses)
605 system.cpu.l2cache.demand_accesses::cpu.inst 738 # number of demand (read+write) accesses
606 system.cpu.l2cache.demand_accesses::cpu.data 947732 # number of demand (read+write) accesses
607 system.cpu.l2cache.demand_accesses::total 948470 # number of demand (read+write) accesses
608 system.cpu.l2cache.overall_accesses::cpu.inst 738 # number of overall (read+write) accesses
609 system.cpu.l2cache.overall_accesses::cpu.data 947732 # number of overall (read+write) accesses
610 system.cpu.l2cache.overall_accesses::total 948470 # number of overall (read+write) accesses
611 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.964770 # miss rate for ReadReq accesses
612 system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000303 # miss rate for ReadReq accesses
613 system.cpu.l2cache.ReadReq_miss_rate::total 0.001082 # miss rate for ReadReq accesses
614 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.419931 # miss rate for ReadExReq accesses
615 system.cpu.l2cache.ReadExReq_miss_rate::total 0.419931 # miss rate for ReadExReq accesses
616 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.964770 # miss rate for demand accesses
617 system.cpu.l2cache.demand_miss_rate::cpu.data 0.015632 # miss rate for demand accesses
618 system.cpu.l2cache.demand_miss_rate::total 0.016371 # miss rate for demand accesses
619 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.964770 # miss rate for overall accesses
620 system.cpu.l2cache.overall_miss_rate::cpu.data 0.015632 # miss rate for overall accesses
621 system.cpu.l2cache.overall_miss_rate::total 0.016371 # miss rate for overall accesses
622 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35856.741573 # average ReadReq miss latency
623 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 36972.924188 # average ReadReq miss latency
624 system.cpu.l2cache.ReadReq_avg_miss_latency::total 36169.362993 # average ReadReq miss latency
625 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34342.997661 # average ReadExReq miss latency
626 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34342.997661 # average ReadExReq miss latency
627 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35856.741573 # average overall miss latency
628 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34392.170098 # average overall miss latency
629 system.cpu.l2cache.demand_avg_miss_latency::total 34459.328911 # average overall miss latency
630 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35856.741573 # average overall miss latency
631 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34392.170098 # average overall miss latency
632 system.cpu.l2cache.overall_avg_miss_latency::total 34459.328911 # average overall miss latency
633 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
634 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
635 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
636 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
637 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
638 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
639 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
640 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
641 system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits
642 system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 10 # number of ReadReq MSHR hits
643 system.cpu.l2cache.ReadReq_mshr_hits::total 12 # number of ReadReq MSHR hits
644 system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits
645 system.cpu.l2cache.demand_mshr_hits::cpu.data 10 # number of demand (read+write) MSHR hits
646 system.cpu.l2cache.demand_mshr_hits::total 12 # number of demand (read+write) MSHR hits
647 system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits
648 system.cpu.l2cache.overall_mshr_hits::cpu.data 10 # number of overall MSHR hits
649 system.cpu.l2cache.overall_mshr_hits::total 12 # number of overall MSHR hits
650 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 710 # number of ReadReq MSHR misses
651 system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 267 # number of ReadReq MSHR misses
652 system.cpu.l2cache.ReadReq_mshr_misses::total 977 # number of ReadReq MSHR misses
653 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14538 # number of ReadExReq MSHR misses
654 system.cpu.l2cache.ReadExReq_mshr_misses::total 14538 # number of ReadExReq MSHR misses
655 system.cpu.l2cache.demand_mshr_misses::cpu.inst 710 # number of demand (read+write) MSHR misses
656 system.cpu.l2cache.demand_mshr_misses::cpu.data 14805 # number of demand (read+write) MSHR misses
657 system.cpu.l2cache.demand_mshr_misses::total 15515 # number of demand (read+write) MSHR misses
658 system.cpu.l2cache.overall_mshr_misses::cpu.inst 710 # number of overall MSHR misses
659 system.cpu.l2cache.overall_mshr_misses::cpu.data 14805 # number of overall MSHR misses
660 system.cpu.l2cache.overall_mshr_misses::total 15515 # number of overall MSHR misses
661 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 23238000 # number of ReadReq MSHR miss cycles
662 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 9078500 # number of ReadReq MSHR miss cycles
663 system.cpu.l2cache.ReadReq_mshr_miss_latency::total 32316500 # number of ReadReq MSHR miss cycles
664 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 451969500 # number of ReadExReq MSHR miss cycles
665 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 451969500 # number of ReadExReq MSHR miss cycles
666 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23238000 # number of demand (read+write) MSHR miss cycles
667 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 461048000 # number of demand (read+write) MSHR miss cycles
668 system.cpu.l2cache.demand_mshr_miss_latency::total 484286000 # number of demand (read+write) MSHR miss cycles
669 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23238000 # number of overall MSHR miss cycles
670 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 461048000 # number of overall MSHR miss cycles
671 system.cpu.l2cache.overall_mshr_miss_latency::total 484286000 # number of overall MSHR miss cycles
672 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.962060 # mshr miss rate for ReadReq accesses
673 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000292 # mshr miss rate for ReadReq accesses
674 system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001069 # mshr miss rate for ReadReq accesses
675 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.419931 # mshr miss rate for ReadExReq accesses
676 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.419931 # mshr miss rate for ReadExReq accesses
677 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.962060 # mshr miss rate for demand accesses
678 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015622 # mshr miss rate for demand accesses
679 system.cpu.l2cache.demand_mshr_miss_rate::total 0.016358 # mshr miss rate for demand accesses
680 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.962060 # mshr miss rate for overall accesses
681 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015622 # mshr miss rate for overall accesses
682 system.cpu.l2cache.overall_mshr_miss_rate::total 0.016358 # mshr miss rate for overall accesses
683 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32729.577465 # average ReadReq mshr miss latency
684 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 34001.872659 # average ReadReq mshr miss latency
685 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33077.277380 # average ReadReq mshr miss latency
686 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31088.836154 # average ReadExReq mshr miss latency
687 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31088.836154 # average ReadExReq mshr miss latency
688 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32729.577465 # average overall mshr miss latency
689 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31141.371158 # average overall mshr miss latency
690 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31214.050918 # average overall mshr miss latency
691 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32729.577465 # average overall mshr miss latency
692 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31141.371158 # average overall mshr miss latency
693 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31214.050918 # average overall mshr miss latency
694 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
696 ---------- End Simulation Statistics ----------
projects / gem5.git / blob