2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.026894 # Number of seconds simulated
4 sim_ticks 26894328500 # Number of ticks simulated
5 final_tick 26894328500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 165934 # Simulator instruction rate (inst/s)
8 host_op_rate 167125 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 49262466 # Simulator tick rate (ticks/s)
10 host_mem_usage 394132 # Number of bytes of host memory used
11 host_seconds 545.94 # Real time elapsed on the host
12 sim_insts 90589798 # Number of instructions simulated
13 sim_ops 91240351 # Number of ops (including micro ops) simulated
14 system.voltage_domain.voltage 1 # Voltage in Volts
15 system.clk_domain.clock 1000 # Clock period in ticks
16 system.physmem.bytes_read::cpu.inst 45184 # Number of bytes read from this memory
17 system.physmem.bytes_read::cpu.data 947456 # Number of bytes read from this memory
18 system.physmem.bytes_read::total 992640 # Number of bytes read from this memory
19 system.physmem.bytes_inst_read::cpu.inst 45184 # Number of instructions bytes read from this memory
20 system.physmem.bytes_inst_read::total 45184 # Number of instructions bytes read from this memory
21 system.physmem.num_reads::cpu.inst 706 # Number of read requests responded to by this memory
22 system.physmem.num_reads::cpu.data 14804 # Number of read requests responded to by this memory
23 system.physmem.num_reads::total 15510 # Number of read requests responded to by this memory
24 system.physmem.bw_read::cpu.inst 1680057 # Total read bandwidth from this memory (bytes/s)
25 system.physmem.bw_read::cpu.data 35228840 # Total read bandwidth from this memory (bytes/s)
26 system.physmem.bw_read::total 36908897 # Total read bandwidth from this memory (bytes/s)
27 system.physmem.bw_inst_read::cpu.inst 1680057 # Instruction read bandwidth from this memory (bytes/s)
28 system.physmem.bw_inst_read::total 1680057 # Instruction read bandwidth from this memory (bytes/s)
29 system.physmem.bw_total::cpu.inst 1680057 # Total bandwidth to/from this memory (bytes/s)
30 system.physmem.bw_total::cpu.data 35228840 # Total bandwidth to/from this memory (bytes/s)
31 system.physmem.bw_total::total 36908897 # Total bandwidth to/from this memory (bytes/s)
32 system.physmem.readReqs 15510 # Number of read requests accepted
33 system.physmem.writeReqs 0 # Number of write requests accepted
34 system.physmem.readBursts 15510 # Number of DRAM read bursts, including those serviced by the write queue
35 system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
36 system.physmem.bytesReadDRAM 992640 # Total number of bytes read from DRAM
37 system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
38 system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
39 system.physmem.bytesReadSys 992640 # Total read bytes from the system interface side
40 system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
41 system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
42 system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
43 system.physmem.neitherReadNorWriteReqs 1 # Number of requests that are neither read nor write
44 system.physmem.perBankRdBursts::0 987 # Per bank write bursts
45 system.physmem.perBankRdBursts::1 885 # Per bank write bursts
46 system.physmem.perBankRdBursts::2 942 # Per bank write bursts
47 system.physmem.perBankRdBursts::3 1029 # Per bank write bursts
48 system.physmem.perBankRdBursts::4 1048 # Per bank write bursts
49 system.physmem.perBankRdBursts::5 1105 # Per bank write bursts
50 system.physmem.perBankRdBursts::6 1078 # Per bank write bursts
51 system.physmem.perBankRdBursts::7 1080 # Per bank write bursts
52 system.physmem.perBankRdBursts::8 1024 # Per bank write bursts
53 system.physmem.perBankRdBursts::9 957 # Per bank write bursts
54 system.physmem.perBankRdBursts::10 936 # Per bank write bursts
55 system.physmem.perBankRdBursts::11 899 # Per bank write bursts
56 system.physmem.perBankRdBursts::12 905 # Per bank write bursts
57 system.physmem.perBankRdBursts::13 863 # Per bank write bursts
58 system.physmem.perBankRdBursts::14 876 # Per bank write bursts
59 system.physmem.perBankRdBursts::15 896 # Per bank write bursts
60 system.physmem.perBankWrBursts::0 0 # Per bank write bursts
61 system.physmem.perBankWrBursts::1 0 # Per bank write bursts
62 system.physmem.perBankWrBursts::2 0 # Per bank write bursts
63 system.physmem.perBankWrBursts::3 0 # Per bank write bursts
64 system.physmem.perBankWrBursts::4 0 # Per bank write bursts
65 system.physmem.perBankWrBursts::5 0 # Per bank write bursts
66 system.physmem.perBankWrBursts::6 0 # Per bank write bursts
67 system.physmem.perBankWrBursts::7 0 # Per bank write bursts
68 system.physmem.perBankWrBursts::8 0 # Per bank write bursts
69 system.physmem.perBankWrBursts::9 0 # Per bank write bursts
70 system.physmem.perBankWrBursts::10 0 # Per bank write bursts
71 system.physmem.perBankWrBursts::11 0 # Per bank write bursts
72 system.physmem.perBankWrBursts::12 0 # Per bank write bursts
73 system.physmem.perBankWrBursts::13 0 # Per bank write bursts
74 system.physmem.perBankWrBursts::14 0 # Per bank write bursts
75 system.physmem.perBankWrBursts::15 0 # Per bank write bursts
76 system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
77 system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
78 system.physmem.totGap 26894128500 # Total gap between requests
79 system.physmem.readPktSize::0 0 # Read request sizes (log2)
80 system.physmem.readPktSize::1 0 # Read request sizes (log2)
81 system.physmem.readPktSize::2 0 # Read request sizes (log2)
82 system.physmem.readPktSize::3 0 # Read request sizes (log2)
83 system.physmem.readPktSize::4 0 # Read request sizes (log2)
84 system.physmem.readPktSize::5 0 # Read request sizes (log2)
85 system.physmem.readPktSize::6 15510 # Read request sizes (log2)
86 system.physmem.writePktSize::0 0 # Write request sizes (log2)
87 system.physmem.writePktSize::1 0 # Write request sizes (log2)
88 system.physmem.writePktSize::2 0 # Write request sizes (log2)
89 system.physmem.writePktSize::3 0 # Write request sizes (log2)
90 system.physmem.writePktSize::4 0 # Write request sizes (log2)
91 system.physmem.writePktSize::5 0 # Write request sizes (log2)
92 system.physmem.writePktSize::6 0 # Write request sizes (log2)
93 system.physmem.rdQLenPdf::0 10369 # What read queue length does an incoming req see
94 system.physmem.rdQLenPdf::1 4857 # What read queue length does an incoming req see
95 system.physmem.rdQLenPdf::2 264 # What read queue length does an incoming req see
96 system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see
97 system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see
98 system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see
99 system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
100 system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
101 system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
102 system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
103 system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
104 system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
105 system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
106 system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
107 system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
108 system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
109 system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
110 system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
111 system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
112 system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
113 system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
114 system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
115 system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
116 system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
117 system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
118 system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
119 system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
120 system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
121 system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
122 system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
123 system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
124 system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
125 system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
126 system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
127 system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
128 system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
129 system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
130 system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
131 system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
132 system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
133 system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
134 system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
135 system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
136 system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
137 system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
138 system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
139 system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
140 system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
141 system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
142 system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
143 system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
144 system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
145 system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
146 system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
147 system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
148 system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
149 system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
150 system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
151 system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
152 system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
153 system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
154 system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
155 system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
156 system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
157 system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
158 system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
159 system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
160 system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
161 system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
162 system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
163 system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
164 system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
165 system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
166 system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
167 system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
168 system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
169 system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
170 system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
171 system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
172 system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
173 system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
174 system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
175 system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
176 system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
177 system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
178 system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
179 system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
180 system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
181 system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
182 system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
183 system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
184 system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
185 system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
186 system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
187 system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
188 system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
189 system.physmem.bytesPerActivate::samples 1366 # Bytes accessed per row activation
190 system.physmem.bytesPerActivate::mean 726.489019 # Bytes accessed per row activation
191 system.physmem.bytesPerActivate::gmean 530.637647 # Bytes accessed per row activation
192 system.physmem.bytesPerActivate::stdev 387.552146 # Bytes accessed per row activation
193 system.physmem.bytesPerActivate::0-127 153 11.20% 11.20% # Bytes accessed per row activation
194 system.physmem.bytesPerActivate::128-255 146 10.69% 21.89% # Bytes accessed per row activation
195 system.physmem.bytesPerActivate::256-383 54 3.95% 25.84% # Bytes accessed per row activation
196 system.physmem.bytesPerActivate::384-511 65 4.76% 30.60% # Bytes accessed per row activation
197 system.physmem.bytesPerActivate::512-639 57 4.17% 34.77% # Bytes accessed per row activation
198 system.physmem.bytesPerActivate::640-767 41 3.00% 37.77% # Bytes accessed per row activation
199 system.physmem.bytesPerActivate::768-895 35 2.56% 40.34% # Bytes accessed per row activation
200 system.physmem.bytesPerActivate::896-1023 33 2.42% 42.75% # Bytes accessed per row activation
201 system.physmem.bytesPerActivate::1024-1151 782 57.25% 100.00% # Bytes accessed per row activation
202 system.physmem.bytesPerActivate::total 1366 # Bytes accessed per row activation
203 system.physmem.totQLat 88775250 # Total ticks spent queuing
204 system.physmem.totMemAccLat 379587750 # Total ticks spent from burst creation until serviced by the DRAM
205 system.physmem.totBusLat 77550000 # Total ticks spent in databus transfers
206 system.physmem.avgQLat 5723.74 # Average queueing delay per DRAM burst
207 system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
208 system.physmem.avgMemAccLat 24473.74 # Average memory access latency per DRAM burst
209 system.physmem.avgRdBW 36.91 # Average DRAM read bandwidth in MiByte/s
210 system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
211 system.physmem.avgRdBWSys 36.91 # Average system read bandwidth in MiByte/s
212 system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
213 system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
214 system.physmem.busUtil 0.29 # Data bus utilization in percentage
215 system.physmem.busUtilRead 0.29 # Data bus utilization in percentage for reads
216 system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
217 system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing
218 system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
219 system.physmem.readRowHits 14143 # Number of row buffer hits during reads
220 system.physmem.writeRowHits 0 # Number of row buffer hits during writes
221 system.physmem.readRowHitRate 91.19 # Row buffer hit rate for reads
222 system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
223 system.physmem.avgGap 1733986.36 # Average gap between requests
224 system.physmem.pageHitRate 91.19 # Row buffer hit rate, read and write combined
225 system.physmem.memoryStateTime::IDLE 24303280500 # Time in different power states
226 system.physmem.memoryStateTime::REF 898040000 # Time in different power states
227 system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
228 system.physmem.memoryStateTime::ACT 1692660750 # Time in different power states
229 system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
230 system.membus.throughput 36908897 # Throughput (bytes/s)
231 system.membus.trans_dist::ReadReq 972 # Transaction distribution
232 system.membus.trans_dist::ReadResp 972 # Transaction distribution
233 system.membus.trans_dist::UpgradeReq 1 # Transaction distribution
234 system.membus.trans_dist::UpgradeResp 1 # Transaction distribution
235 system.membus.trans_dist::ReadExReq 14538 # Transaction distribution
236 system.membus.trans_dist::ReadExResp 14538 # Transaction distribution
237 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31022 # Packet count per connected master and slave (bytes)
238 system.membus.pkt_count::total 31022 # Packet count per connected master and slave (bytes)
239 system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 992640 # Cumulative packet size per connected master and slave (bytes)
240 system.membus.tot_pkt_size::total 992640 # Cumulative packet size per connected master and slave (bytes)
241 system.membus.data_through_bus 992640 # Total data (bytes)
242 system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
243 system.membus.reqLayer0.occupancy 18401000 # Layer occupancy (ticks)
244 system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
245 system.membus.respLayer1.occupancy 145166999 # Layer occupancy (ticks)
246 system.membus.respLayer1.utilization 0.5 # Layer utilization (%)
247 system.cpu_clk_domain.clock 500 # Clock period in ticks
248 system.cpu.branchPred.lookups 27364118 # Number of BP lookups
249 system.cpu.branchPred.condPredicted 22575249 # Number of conditional branches predicted
250 system.cpu.branchPred.condIncorrect 843312 # Number of conditional branches incorrect
251 system.cpu.branchPred.BTBLookups 11626081 # Number of BTB lookups
252 system.cpu.branchPred.BTBHits 11546341 # Number of BTB hits
253 system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
254 system.cpu.branchPred.BTBHitPct 99.314128 # BTB Hit Percentage
255 system.cpu.branchPred.usedRAS 70079 # Number of times the RAS was used to get a target.
256 system.cpu.branchPred.RASInCorrect 187 # Number of incorrect RAS predictions.
257 system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
258 system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
259 system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
260 system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
261 system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
262 system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
263 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
264 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
265 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
266 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
267 system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
268 system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
269 system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
270 system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
271 system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
272 system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
273 system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
274 system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
275 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
276 system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
277 system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
278 system.cpu.dtb.inst_hits 0 # ITB inst hits
279 system.cpu.dtb.inst_misses 0 # ITB inst misses
280 system.cpu.dtb.read_hits 0 # DTB read hits
281 system.cpu.dtb.read_misses 0 # DTB read misses
282 system.cpu.dtb.write_hits 0 # DTB write hits
283 system.cpu.dtb.write_misses 0 # DTB write misses
284 system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
285 system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
286 system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
287 system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
288 system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
289 system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
290 system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
291 system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
292 system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
293 system.cpu.dtb.read_accesses 0 # DTB read accesses
294 system.cpu.dtb.write_accesses 0 # DTB write accesses
295 system.cpu.dtb.inst_accesses 0 # ITB inst accesses
296 system.cpu.dtb.hits 0 # DTB hits
297 system.cpu.dtb.misses 0 # DTB misses
298 system.cpu.dtb.accesses 0 # DTB accesses
299 system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
300 system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
301 system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
302 system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
303 system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
304 system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
305 system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
306 system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
307 system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
308 system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
309 system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
310 system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
311 system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
312 system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
313 system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
314 system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
315 system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
316 system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
317 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
318 system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
319 system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
320 system.cpu.itb.inst_hits 0 # ITB inst hits
321 system.cpu.itb.inst_misses 0 # ITB inst misses
322 system.cpu.itb.read_hits 0 # DTB read hits
323 system.cpu.itb.read_misses 0 # DTB read misses
324 system.cpu.itb.write_hits 0 # DTB write hits
325 system.cpu.itb.write_misses 0 # DTB write misses
326 system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
327 system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
328 system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
329 system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
330 system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
331 system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
332 system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
333 system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
334 system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
335 system.cpu.itb.read_accesses 0 # DTB read accesses
336 system.cpu.itb.write_accesses 0 # DTB write accesses
337 system.cpu.itb.inst_accesses 0 # ITB inst accesses
338 system.cpu.itb.hits 0 # DTB hits
339 system.cpu.itb.misses 0 # DTB misses
340 system.cpu.itb.accesses 0 # DTB accesses
341 system.cpu.workload.num_syscalls 442 # Number of system calls
342 system.cpu.numCycles 53788658 # number of cpu cycles simulated
343 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
344 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
345 system.cpu.fetch.icacheStallCycles 14474692 # Number of cycles fetch is stalled on an Icache miss
346 system.cpu.fetch.Insts 130915195 # Number of instructions fetch has processed
347 system.cpu.fetch.Branches 27364118 # Number of branches that fetch encountered
348 system.cpu.fetch.predictedBranches 11616420 # Number of branches that fetch has predicted taken
349 system.cpu.fetch.Cycles 24576695 # Number of cycles fetch has run and was not squashing or blocked
350 system.cpu.fetch.SquashCycles 5106515 # Number of cycles fetch has spent squashing
351 system.cpu.fetch.BlockedCycles 9886759 # Number of cycles fetch has spent blocked
352 system.cpu.fetch.MiscStallCycles 107 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
353 system.cpu.fetch.PendingTrapStallCycles 8 # Number of stall cycles due to pending traps
354 system.cpu.fetch.IcacheWaitRetryStallCycles 29 # Number of stall cycles due to full MSHR
355 system.cpu.fetch.CacheLines 14156505 # Number of cache lines fetched
356 system.cpu.fetch.IcacheSquashes 349331 # Number of outstanding Icache misses that were squashed
357 system.cpu.fetch.rateDist::samples 53187301 # Number of instructions fetched each cycle (Total)
358 system.cpu.fetch.rateDist::mean 2.478661 # Number of instructions fetched each cycle (Total)
359 system.cpu.fetch.rateDist::stdev 3.235073 # Number of instructions fetched each cycle (Total)
360 system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
361 system.cpu.fetch.rateDist::0 28648969 53.86% 53.86% # Number of instructions fetched each cycle (Total)
362 system.cpu.fetch.rateDist::1 3469200 6.52% 60.39% # Number of instructions fetched each cycle (Total)
363 system.cpu.fetch.rateDist::2 2052434 3.86% 64.25% # Number of instructions fetched each cycle (Total)
364 system.cpu.fetch.rateDist::3 1567853 2.95% 67.19% # Number of instructions fetched each cycle (Total)
365 system.cpu.fetch.rateDist::4 1679873 3.16% 70.35% # Number of instructions fetched each cycle (Total)
366 system.cpu.fetch.rateDist::5 3021837 5.68% 76.03% # Number of instructions fetched each cycle (Total)
367 system.cpu.fetch.rateDist::6 1566641 2.95% 78.98% # Number of instructions fetched each cycle (Total)
368 system.cpu.fetch.rateDist::7 1116795 2.10% 81.08% # Number of instructions fetched each cycle (Total)
369 system.cpu.fetch.rateDist::8 10063699 18.92% 100.00% # Number of instructions fetched each cycle (Total)
370 system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
371 system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
372 system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
373 system.cpu.fetch.rateDist::total 53187301 # Number of instructions fetched each cycle (Total)
374 system.cpu.fetch.branchRate 0.508734 # Number of branch fetches per cycle
375 system.cpu.fetch.rate 2.433881 # Number of inst fetches per cycle
376 system.cpu.decode.IdleCycles 16310855 # Number of cycles decode is idle
377 system.cpu.decode.BlockedCycles 8657573 # Number of cycles decode is blocked
378 system.cpu.decode.RunCycles 23455900 # Number of cycles decode is running
379 system.cpu.decode.UnblockCycles 522552 # Number of cycles decode is unblocking
380 system.cpu.decode.SquashCycles 4240421 # Number of cycles decode is squashing
381 system.cpu.decode.BranchResolved 4543490 # Number of times decode resolved a branch
382 system.cpu.decode.BranchMispred 8671 # Number of times decode detected a branch misprediction
383 system.cpu.decode.DecodedInsts 129206748 # Number of instructions handled by decode
384 system.cpu.decode.SquashedInsts 42514 # Number of squashed instructions handled by decode
385 system.cpu.rename.SquashCycles 4240421 # Number of cycles rename is squashing
386 system.cpu.rename.IdleCycles 17921369 # Number of cycles rename is idle
387 system.cpu.rename.BlockCycles 2850180 # Number of cycles rename is blocking
388 system.cpu.rename.serializeStallCycles 191379 # count of cycles rename stalled for serializing inst
389 system.cpu.rename.RunCycles 22351654 # Number of cycles rename is running
390 system.cpu.rename.UnblockCycles 5632298 # Number of cycles rename is unblocking
391 system.cpu.rename.RenamedInsts 126131712 # Number of instructions processed by rename
392 system.cpu.rename.ROBFullEvents 134 # Number of times rename has blocked due to ROB full
393 system.cpu.rename.IQFullEvents 1889841 # Number of times rename has blocked due to IQ full
394 system.cpu.rename.LQFullEvents 3251328 # Number of times rename has blocked due to LQ full
395 system.cpu.rename.SQFullEvents 563418 # Number of times rename has blocked due to SQ full
396 system.cpu.rename.FullRegisterEvents 3246 # Number of times there has been no free registers
397 system.cpu.rename.RenamedOperands 146876533 # Number of destination operands rename has renamed
398 system.cpu.rename.RenameLookups 549573070 # Number of register rename lookups that rename has made
399 system.cpu.rename.int_rename_lookups 512042051 # Number of integer rename lookups
400 system.cpu.rename.fp_rename_lookups 826 # Number of floating rename lookups
401 system.cpu.rename.CommittedMaps 107414186 # Number of HB maps that are committed
402 system.cpu.rename.UndoneMaps 39462347 # Number of HB maps that are undone due to squashing
403 system.cpu.rename.serializingInsts 4633 # count of serializing insts renamed
404 system.cpu.rename.tempSerializingInsts 4631 # count of temporary serializing insts renamed
405 system.cpu.rename.skidInsts 9072079 # count of insts added to the skid buffer
406 system.cpu.memDep0.insertedLoads 30275485 # Number of loads inserted to the mem dependence unit.
407 system.cpu.memDep0.insertedStores 5599467 # Number of stores inserted to the mem dependence unit.
408 system.cpu.memDep0.conflictingLoads 2184620 # Number of conflicting loads.
409 system.cpu.memDep0.conflictingStores 1363504 # Number of conflicting stores.
410 system.cpu.iq.iqInstsAdded 120806561 # Number of instructions added to the IQ (excludes non-spec)
411 system.cpu.iq.iqNonSpecInstsAdded 8485 # Number of non-speculative instructions added to the IQ
412 system.cpu.iq.iqInstsIssued 105954089 # Number of instructions issued
413 system.cpu.iq.iqSquashedInstsIssued 91175 # Number of squashed instructions issued
414 system.cpu.iq.iqSquashedInstsExamined 29372689 # Number of squashed instructions iterated over during squash; mainly for profiling
415 system.cpu.iq.iqSquashedOperandsExamined 73925597 # Number of squashed operands that are examined and possibly removed from graph
416 system.cpu.iq.iqSquashedNonSpecRemoved 267 # Number of squashed non-spec instructions that were removed
417 system.cpu.iq.issued_per_cycle::samples 53187301 # Number of insts issued each cycle
418 system.cpu.iq.issued_per_cycle::mean 1.992094 # Number of insts issued each cycle
419 system.cpu.iq.issued_per_cycle::stdev 1.919550 # Number of insts issued each cycle
420 system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
421 system.cpu.iq.issued_per_cycle::0 15526622 29.19% 29.19% # Number of insts issued each cycle
422 system.cpu.iq.issued_per_cycle::1 10753574 20.22% 49.41% # Number of insts issued each cycle
423 system.cpu.iq.issued_per_cycle::2 8641028 16.25% 65.66% # Number of insts issued each cycle
424 system.cpu.iq.issued_per_cycle::3 6157106 11.58% 77.23% # Number of insts issued each cycle
425 system.cpu.iq.issued_per_cycle::4 5949684 11.19% 88.42% # Number of insts issued each cycle
426 system.cpu.iq.issued_per_cycle::5 2742880 5.16% 93.58% # Number of insts issued each cycle
427 system.cpu.iq.issued_per_cycle::6 2429206 4.57% 98.14% # Number of insts issued each cycle
428 system.cpu.iq.issued_per_cycle::7 538839 1.01% 99.16% # Number of insts issued each cycle
429 system.cpu.iq.issued_per_cycle::8 448362 0.84% 100.00% # Number of insts issued each cycle
430 system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
431 system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
432 system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
433 system.cpu.iq.issued_per_cycle::total 53187301 # Number of insts issued each cycle
434 system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
435 system.cpu.iq.fu_full::IntAlu 44574 8.99% 8.99% # attempts to use FU when none available
436 system.cpu.iq.fu_full::IntMult 27 0.01% 8.99% # attempts to use FU when none available
437 system.cpu.iq.fu_full::IntDiv 0 0.00% 8.99% # attempts to use FU when none available
438 system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.99% # attempts to use FU when none available
439 system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.99% # attempts to use FU when none available
440 system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.99% # attempts to use FU when none available
441 system.cpu.iq.fu_full::FloatMult 0 0.00% 8.99% # attempts to use FU when none available
442 system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.99% # attempts to use FU when none available
443 system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.99% # attempts to use FU when none available
444 system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.99% # attempts to use FU when none available
445 system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.99% # attempts to use FU when none available
446 system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.99% # attempts to use FU when none available
447 system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.99% # attempts to use FU when none available
448 system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.99% # attempts to use FU when none available
449 system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.99% # attempts to use FU when none available
450 system.cpu.iq.fu_full::SimdMult 0 0.00% 8.99% # attempts to use FU when none available
451 system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.99% # attempts to use FU when none available
452 system.cpu.iq.fu_full::SimdShift 0 0.00% 8.99% # attempts to use FU when none available
453 system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.99% # attempts to use FU when none available
454 system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.99% # attempts to use FU when none available
455 system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.99% # attempts to use FU when none available
456 system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.99% # attempts to use FU when none available
457 system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.99% # attempts to use FU when none available
458 system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.99% # attempts to use FU when none available
459 system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.99% # attempts to use FU when none available
460 system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.99% # attempts to use FU when none available
461 system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.99% # attempts to use FU when none available
462 system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.99% # attempts to use FU when none available
463 system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.99% # attempts to use FU when none available
464 system.cpu.iq.fu_full::MemRead 174239 35.13% 44.13% # attempts to use FU when none available
465 system.cpu.iq.fu_full::MemWrite 277108 55.87% 100.00% # attempts to use FU when none available
466 system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
467 system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
468 system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
469 system.cpu.iq.FU_type_0::IntAlu 75094311 70.87% 70.87% # Type of FU issued
470 system.cpu.iq.FU_type_0::IntMult 10550 0.01% 70.88% # Type of FU issued
471 system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.88% # Type of FU issued
472 system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.88% # Type of FU issued
473 system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.88% # Type of FU issued
474 system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.88% # Type of FU issued
475 system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.88% # Type of FU issued
476 system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.88% # Type of FU issued
477 system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.88% # Type of FU issued
478 system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.88% # Type of FU issued
479 system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.88% # Type of FU issued
480 system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.88% # Type of FU issued
481 system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.88% # Type of FU issued
482 system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.88% # Type of FU issued
483 system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.88% # Type of FU issued
484 system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.88% # Type of FU issued
485 system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.88% # Type of FU issued
486 system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.88% # Type of FU issued
487 system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.88% # Type of FU issued
488 system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.88% # Type of FU issued
489 system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.88% # Type of FU issued
490 system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.88% # Type of FU issued
491 system.cpu.iq.FU_type_0::SimdFloatCmp 1 0.00% 70.88% # Type of FU issued
492 system.cpu.iq.FU_type_0::SimdFloatCvt 140 0.00% 70.88% # Type of FU issued
493 system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.88% # Type of FU issued
494 system.cpu.iq.FU_type_0::SimdFloatMisc 196 0.00% 70.88% # Type of FU issued
495 system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.88% # Type of FU issued
496 system.cpu.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 70.88% # Type of FU issued
497 system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.88% # Type of FU issued
498 system.cpu.iq.FU_type_0::MemRead 25720178 24.27% 95.16% # Type of FU issued
499 system.cpu.iq.FU_type_0::MemWrite 5128709 4.84% 100.00% # Type of FU issued
500 system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
501 system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
502 system.cpu.iq.FU_type_0::total 105954089 # Type of FU issued
503 system.cpu.iq.rate 1.969822 # Inst issue rate
504 system.cpu.iq.fu_busy_cnt 495948 # FU busy when requested
505 system.cpu.iq.fu_busy_rate 0.004681 # FU busy rate (busy events/executed inst)
506 system.cpu.iq.int_inst_queue_reads 265681854 # Number of integer instruction queue reads
507 system.cpu.iq.int_inst_queue_writes 150192687 # Number of integer instruction queue writes
508 system.cpu.iq.int_inst_queue_wakeup_accesses 103425723 # Number of integer instruction queue wakeup accesses
509 system.cpu.iq.fp_inst_queue_reads 748 # Number of floating instruction queue reads
510 system.cpu.iq.fp_inst_queue_writes 1061 # Number of floating instruction queue writes
511 system.cpu.iq.fp_inst_queue_wakeup_accesses 319 # Number of floating instruction queue wakeup accesses
512 system.cpu.iq.int_alu_accesses 106449666 # Number of integer alu accesses
513 system.cpu.iq.fp_alu_accesses 371 # Number of floating point alu accesses
514 system.cpu.iew.lsq.thread0.forwLoads 469381 # Number of loads that had data forwarded from stores
515 system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
516 system.cpu.iew.lsq.thread0.squashedLoads 7701519 # Number of loads squashed
517 system.cpu.iew.lsq.thread0.ignoredResponses 7870 # Number of memory responses ignored because the instruction is squashed
518 system.cpu.iew.lsq.thread0.memOrderViolation 6982 # Number of memory ordering violations
519 system.cpu.iew.lsq.thread0.squashedStores 854623 # Number of stores squashed
520 system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
521 system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
522 system.cpu.iew.lsq.thread0.rescheduledLoads 2 # Number of loads that were rescheduled
523 system.cpu.iew.lsq.thread0.cacheBlocked 30068 # Number of times an access to memory failed due to the cache being blocked
524 system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
525 system.cpu.iew.iewSquashCycles 4240421 # Number of cycles IEW is squashing
526 system.cpu.iew.iewBlockCycles 731718 # Number of cycles IEW is blocking
527 system.cpu.iew.iewUnblockCycles 478226 # Number of cycles IEW is unblocking
528 system.cpu.iew.iewDispatchedInsts 120827778 # Number of instructions dispatched to IQ
529 system.cpu.iew.iewDispSquashedInsts 309730 # Number of squashed instructions skipped by dispatch
530 system.cpu.iew.iewDispLoadInsts 30275485 # Number of dispatched load instructions
531 system.cpu.iew.iewDispStoreInsts 5599467 # Number of dispatched store instructions
532 system.cpu.iew.iewDispNonSpecInsts 4597 # Number of dispatched non-speculative instructions
533 system.cpu.iew.iewIQFullEvents 72415 # Number of times the IQ has become full, causing a stall
534 system.cpu.iew.iewLSQFullEvents 359917 # Number of times the LSQ has become full, causing a stall
535 system.cpu.iew.memOrderViolationEvents 6982 # Number of memory order violations
536 system.cpu.iew.predictedTakenIncorrect 447833 # Number of branches that were predicted taken incorrectly
537 system.cpu.iew.predictedNotTakenIncorrect 447193 # Number of branches that were predicted not taken incorrectly
538 system.cpu.iew.branchMispredicts 895026 # Number of branch mispredicts detected at execute
539 system.cpu.iew.iewExecutedInsts 104954211 # Number of executed instructions
540 system.cpu.iew.iewExecLoadInsts 25387781 # Number of load instructions executed
541 system.cpu.iew.iewExecSquashedInsts 999878 # Number of squashed instructions skipped in execute
542 system.cpu.iew.exec_swp 0 # number of swp insts executed
543 system.cpu.iew.exec_nop 12732 # number of nop insts executed
544 system.cpu.iew.exec_refs 30458601 # number of memory reference insts executed
545 system.cpu.iew.exec_branches 21526378 # Number of branches executed
546 system.cpu.iew.exec_stores 5070820 # Number of stores executed
547 system.cpu.iew.exec_rate 1.951233 # Inst execution rate
548 system.cpu.iew.wb_sent 103717343 # cumulative count of insts sent to commit
549 system.cpu.iew.wb_count 103426042 # cumulative count of insts written-back
550 system.cpu.iew.wb_producers 62672484 # num instructions producing a value
551 system.cpu.iew.wb_consumers 105780863 # num instructions consuming a value
552 system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
553 system.cpu.iew.wb_rate 1.922823 # insts written-back per cycle
554 system.cpu.iew.wb_fanout 0.592475 # average fanout of values written-back
555 system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
556 system.cpu.commit.commitSquashedInsts 29588025 # The number of squashed insts skipped by commit
557 system.cpu.commit.commitNonSpecStalls 8218 # The number of times commit has been forced to stall to communicate backwards
558 system.cpu.commit.branchMispredicts 834722 # The number of times a branch was mispredicted
559 system.cpu.commit.committed_per_cycle::samples 48946880 # Number of insts commited each cycle
560 system.cpu.commit.committed_per_cycle::mean 1.864326 # Number of insts commited each cycle
561 system.cpu.commit.committed_per_cycle::stdev 2.553843 # Number of insts commited each cycle
562 system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
563 system.cpu.commit.committed_per_cycle::0 19590544 40.02% 40.02% # Number of insts commited each cycle
564 system.cpu.commit.committed_per_cycle::1 13003525 26.57% 66.59% # Number of insts commited each cycle
565 system.cpu.commit.committed_per_cycle::2 4154420 8.49% 75.08% # Number of insts commited each cycle
566 system.cpu.commit.committed_per_cycle::3 3492472 7.14% 82.21% # Number of insts commited each cycle
567 system.cpu.commit.committed_per_cycle::4 1473630 3.01% 85.22% # Number of insts commited each cycle
568 system.cpu.commit.committed_per_cycle::5 727145 1.49% 86.71% # Number of insts commited each cycle
569 system.cpu.commit.committed_per_cycle::6 923215 1.89% 88.60% # Number of insts commited each cycle
570 system.cpu.commit.committed_per_cycle::7 261788 0.53% 89.13% # Number of insts commited each cycle
571 system.cpu.commit.committed_per_cycle::8 5320141 10.87% 100.00% # Number of insts commited each cycle
572 system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
573 system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
574 system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
575 system.cpu.commit.committed_per_cycle::total 48946880 # Number of insts commited each cycle
576 system.cpu.commit.committedInsts 90602407 # Number of instructions committed
577 system.cpu.commit.committedOps 91252960 # Number of ops (including micro ops) committed
578 system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
579 system.cpu.commit.refs 27318810 # Number of memory references committed
580 system.cpu.commit.loads 22573966 # Number of loads committed
581 system.cpu.commit.membars 3888 # Number of memory barriers committed
582 system.cpu.commit.branches 18732304 # Number of branches committed
583 system.cpu.commit.fp_insts 48 # Number of committed floating point instructions.
584 system.cpu.commit.int_insts 72525674 # Number of committed integer instructions.
585 system.cpu.commit.function_calls 56148 # Number of function calls committed.
586 system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
587 system.cpu.commit.op_class_0::IntAlu 63923653 70.05% 70.05% # Class of committed instruction
588 system.cpu.commit.op_class_0::IntMult 10474 0.01% 70.06% # Class of committed instruction
589 system.cpu.commit.op_class_0::IntDiv 0 0.00% 70.06% # Class of committed instruction
590 system.cpu.commit.op_class_0::FloatAdd 0 0.00% 70.06% # Class of committed instruction
591 system.cpu.commit.op_class_0::FloatCmp 0 0.00% 70.06% # Class of committed instruction
592 system.cpu.commit.op_class_0::FloatCvt 0 0.00% 70.06% # Class of committed instruction
593 system.cpu.commit.op_class_0::FloatMult 0 0.00% 70.06% # Class of committed instruction
594 system.cpu.commit.op_class_0::FloatDiv 0 0.00% 70.06% # Class of committed instruction
595 system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 70.06% # Class of committed instruction
596 system.cpu.commit.op_class_0::SimdAdd 0 0.00% 70.06% # Class of committed instruction
597 system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 70.06% # Class of committed instruction
598 system.cpu.commit.op_class_0::SimdAlu 0 0.00% 70.06% # Class of committed instruction
599 system.cpu.commit.op_class_0::SimdCmp 0 0.00% 70.06% # Class of committed instruction
600 system.cpu.commit.op_class_0::SimdCvt 0 0.00% 70.06% # Class of committed instruction
601 system.cpu.commit.op_class_0::SimdMisc 0 0.00% 70.06% # Class of committed instruction
602 system.cpu.commit.op_class_0::SimdMult 0 0.00% 70.06% # Class of committed instruction
603 system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 70.06% # Class of committed instruction
604 system.cpu.commit.op_class_0::SimdShift 0 0.00% 70.06% # Class of committed instruction
605 system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 70.06% # Class of committed instruction
606 system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 70.06% # Class of committed instruction
607 system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 70.06% # Class of committed instruction
608 system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 70.06% # Class of committed instruction
609 system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 70.06% # Class of committed instruction
610 system.cpu.commit.op_class_0::SimdFloatCvt 6 0.00% 70.06% # Class of committed instruction
611 system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 70.06% # Class of committed instruction
612 system.cpu.commit.op_class_0::SimdFloatMisc 15 0.00% 70.06% # Class of committed instruction
613 system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 70.06% # Class of committed instruction
614 system.cpu.commit.op_class_0::SimdFloatMultAcc 2 0.00% 70.06% # Class of committed instruction
615 system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.06% # Class of committed instruction
616 system.cpu.commit.op_class_0::MemRead 22573966 24.74% 94.80% # Class of committed instruction
617 system.cpu.commit.op_class_0::MemWrite 4744844 5.20% 100.00% # Class of committed instruction
618 system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
619 system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
620 system.cpu.commit.op_class_0::total 91252960 # Class of committed instruction
621 system.cpu.commit.bw_lim_events 5320141 # number cycles where commit BW limit reached
622 system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
623 system.cpu.rob.rob_reads 164461990 # The number of ROB reads
624 system.cpu.rob.rob_writes 245943119 # The number of ROB writes
625 system.cpu.timesIdled 58216 # Number of times that the entire CPU went into an idle state and unscheduled itself
626 system.cpu.idleCycles 601357 # Total number of cycles that the CPU has spent unscheduled due to idling
627 system.cpu.committedInsts 90589798 # Number of Instructions Simulated
628 system.cpu.committedOps 91240351 # Number of Ops (including micro ops) Simulated
629 system.cpu.cpi 0.593761 # CPI: Cycles Per Instruction
630 system.cpu.cpi_total 0.593761 # CPI: Total CPI of All Threads
631 system.cpu.ipc 1.684180 # IPC: Instructions Per Cycle
632 system.cpu.ipc_total 1.684180 # IPC: Total IPC of All Threads
633 system.cpu.int_regfile_reads 499033245 # number of integer regfile reads
634 system.cpu.int_regfile_writes 121427335 # number of integer regfile writes
635 system.cpu.fp_regfile_reads 166 # number of floating regfile reads
636 system.cpu.fp_regfile_writes 402 # number of floating regfile writes
637 system.cpu.misc_regfile_reads 29301616 # number of misc regfile reads
638 system.cpu.misc_regfile_writes 7784 # number of misc regfile writes
639 system.cpu.toL2Bus.throughput 4500548582 # Throughput (bytes/s)
640 system.cpu.toL2Bus.trans_dist::ReadReq 907410 # Transaction distribution
641 system.cpu.toL2Bus.trans_dist::ReadResp 907410 # Transaction distribution
642 system.cpu.toL2Bus.trans_dist::Writeback 942895 # Transaction distribution
643 system.cpu.toL2Bus.trans_dist::UpgradeReq 1 # Transaction distribution
644 system.cpu.toL2Bus.trans_dist::UpgradeResp 1 # Transaction distribution
645 system.cpu.toL2Bus.trans_dist::ReadExReq 40933 # Transaction distribution
646 system.cpu.toL2Bus.trans_dist::ReadExResp 40933 # Transaction distribution
647 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1463 # Packet count per connected master and slave (bytes)
648 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2838119 # Packet count per connected master and slave (bytes)
649 system.cpu.toL2Bus.pkt_count::total 2839582 # Packet count per connected master and slave (bytes)
650 system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 46784 # Cumulative packet size per connected master and slave (bytes)
651 system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 120992384 # Cumulative packet size per connected master and slave (bytes)
652 system.cpu.toL2Bus.tot_pkt_size::total 121039168 # Cumulative packet size per connected master and slave (bytes)
653 system.cpu.toL2Bus.data_through_bus 121039168 # Total data (bytes)
654 system.cpu.toL2Bus.snoop_data_through_bus 64 # Total snoop data (bytes)
655 system.cpu.toL2Bus.reqLayer0.occupancy 1888514500 # Layer occupancy (ticks)
656 system.cpu.toL2Bus.reqLayer0.utilization 7.0 # Layer utilization (%)
657 system.cpu.toL2Bus.respLayer0.occupancy 1215999 # Layer occupancy (ticks)
658 system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
659 system.cpu.toL2Bus.respLayer1.occupancy 1424171240 # Layer occupancy (ticks)
660 system.cpu.toL2Bus.respLayer1.utilization 5.3 # Layer utilization (%)
661 system.cpu.icache.tags.replacements 3 # number of replacements
662 system.cpu.icache.tags.tagsinuse 631.006365 # Cycle average of tags in use
663 system.cpu.icache.tags.total_refs 14155509 # Total number of references to valid blocks.
664 system.cpu.icache.tags.sampled_refs 731 # Sample count of references to valid blocks.
665 system.cpu.icache.tags.avg_refs 19364.581395 # Average number of references to valid blocks.
666 system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
667 system.cpu.icache.tags.occ_blocks::cpu.inst 631.006365 # Average occupied blocks per requestor
668 system.cpu.icache.tags.occ_percent::cpu.inst 0.308109 # Average percentage of cache occupancy
669 system.cpu.icache.tags.occ_percent::total 0.308109 # Average percentage of cache occupancy
670 system.cpu.icache.tags.occ_task_id_blocks::1024 728 # Occupied blocks per task id
671 system.cpu.icache.tags.age_task_id_blocks_1024::0 36 # Occupied blocks per task id
672 system.cpu.icache.tags.age_task_id_blocks_1024::2 13 # Occupied blocks per task id
673 system.cpu.icache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id
674 system.cpu.icache.tags.age_task_id_blocks_1024::4 673 # Occupied blocks per task id
675 system.cpu.icache.tags.occ_task_id_percent::1024 0.355469 # Percentage of cache occupancy per task id
676 system.cpu.icache.tags.tag_accesses 28313740 # Number of tag accesses
677 system.cpu.icache.tags.data_accesses 28313740 # Number of data accesses
678 system.cpu.icache.ReadReq_hits::cpu.inst 14155509 # number of ReadReq hits
679 system.cpu.icache.ReadReq_hits::total 14155509 # number of ReadReq hits
680 system.cpu.icache.demand_hits::cpu.inst 14155509 # number of demand (read+write) hits
681 system.cpu.icache.demand_hits::total 14155509 # number of demand (read+write) hits
682 system.cpu.icache.overall_hits::cpu.inst 14155509 # number of overall hits
683 system.cpu.icache.overall_hits::total 14155509 # number of overall hits
684 system.cpu.icache.ReadReq_misses::cpu.inst 995 # number of ReadReq misses
685 system.cpu.icache.ReadReq_misses::total 995 # number of ReadReq misses
686 system.cpu.icache.demand_misses::cpu.inst 995 # number of demand (read+write) misses
687 system.cpu.icache.demand_misses::total 995 # number of demand (read+write) misses
688 system.cpu.icache.overall_misses::cpu.inst 995 # number of overall misses
689 system.cpu.icache.overall_misses::total 995 # number of overall misses
690 system.cpu.icache.ReadReq_miss_latency::cpu.inst 67178998 # number of ReadReq miss cycles
691 system.cpu.icache.ReadReq_miss_latency::total 67178998 # number of ReadReq miss cycles
692 system.cpu.icache.demand_miss_latency::cpu.inst 67178998 # number of demand (read+write) miss cycles
693 system.cpu.icache.demand_miss_latency::total 67178998 # number of demand (read+write) miss cycles
694 system.cpu.icache.overall_miss_latency::cpu.inst 67178998 # number of overall miss cycles
695 system.cpu.icache.overall_miss_latency::total 67178998 # number of overall miss cycles
696 system.cpu.icache.ReadReq_accesses::cpu.inst 14156504 # number of ReadReq accesses(hits+misses)
697 system.cpu.icache.ReadReq_accesses::total 14156504 # number of ReadReq accesses(hits+misses)
698 system.cpu.icache.demand_accesses::cpu.inst 14156504 # number of demand (read+write) accesses
699 system.cpu.icache.demand_accesses::total 14156504 # number of demand (read+write) accesses
700 system.cpu.icache.overall_accesses::cpu.inst 14156504 # number of overall (read+write) accesses
701 system.cpu.icache.overall_accesses::total 14156504 # number of overall (read+write) accesses
702 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000070 # miss rate for ReadReq accesses
703 system.cpu.icache.ReadReq_miss_rate::total 0.000070 # miss rate for ReadReq accesses
704 system.cpu.icache.demand_miss_rate::cpu.inst 0.000070 # miss rate for demand accesses
705 system.cpu.icache.demand_miss_rate::total 0.000070 # miss rate for demand accesses
706 system.cpu.icache.overall_miss_rate::cpu.inst 0.000070 # miss rate for overall accesses
707 system.cpu.icache.overall_miss_rate::total 0.000070 # miss rate for overall accesses
708 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67516.580905 # average ReadReq miss latency
709 system.cpu.icache.ReadReq_avg_miss_latency::total 67516.580905 # average ReadReq miss latency
710 system.cpu.icache.demand_avg_miss_latency::cpu.inst 67516.580905 # average overall miss latency
711 system.cpu.icache.demand_avg_miss_latency::total 67516.580905 # average overall miss latency
712 system.cpu.icache.overall_avg_miss_latency::cpu.inst 67516.580905 # average overall miss latency
713 system.cpu.icache.overall_avg_miss_latency::total 67516.580905 # average overall miss latency
714 system.cpu.icache.blocked_cycles::no_mshrs 593 # number of cycles access was blocked
715 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
716 system.cpu.icache.blocked::no_mshrs 10 # number of cycles access was blocked
717 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
718 system.cpu.icache.avg_blocked_cycles::no_mshrs 59.300000 # average number of cycles each access was blocked
719 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
720 system.cpu.icache.fast_writes 0 # number of fast writes performed
721 system.cpu.icache.cache_copies 0 # number of cache copies performed
722 system.cpu.icache.ReadReq_mshr_hits::cpu.inst 263 # number of ReadReq MSHR hits
723 system.cpu.icache.ReadReq_mshr_hits::total 263 # number of ReadReq MSHR hits
724 system.cpu.icache.demand_mshr_hits::cpu.inst 263 # number of demand (read+write) MSHR hits
725 system.cpu.icache.demand_mshr_hits::total 263 # number of demand (read+write) MSHR hits
726 system.cpu.icache.overall_mshr_hits::cpu.inst 263 # number of overall MSHR hits
727 system.cpu.icache.overall_mshr_hits::total 263 # number of overall MSHR hits
728 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 732 # number of ReadReq MSHR misses
729 system.cpu.icache.ReadReq_mshr_misses::total 732 # number of ReadReq MSHR misses
730 system.cpu.icache.demand_mshr_misses::cpu.inst 732 # number of demand (read+write) MSHR misses
731 system.cpu.icache.demand_mshr_misses::total 732 # number of demand (read+write) MSHR misses
732 system.cpu.icache.overall_mshr_misses::cpu.inst 732 # number of overall MSHR misses
733 system.cpu.icache.overall_mshr_misses::total 732 # number of overall MSHR misses
734 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 50814250 # number of ReadReq MSHR miss cycles
735 system.cpu.icache.ReadReq_mshr_miss_latency::total 50814250 # number of ReadReq MSHR miss cycles
736 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 50814250 # number of demand (read+write) MSHR miss cycles
737 system.cpu.icache.demand_mshr_miss_latency::total 50814250 # number of demand (read+write) MSHR miss cycles
738 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 50814250 # number of overall MSHR miss cycles
739 system.cpu.icache.overall_mshr_miss_latency::total 50814250 # number of overall MSHR miss cycles
740 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000052 # mshr miss rate for ReadReq accesses
741 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000052 # mshr miss rate for ReadReq accesses
742 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000052 # mshr miss rate for demand accesses
743 system.cpu.icache.demand_mshr_miss_rate::total 0.000052 # mshr miss rate for demand accesses
744 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000052 # mshr miss rate for overall accesses
745 system.cpu.icache.overall_mshr_miss_rate::total 0.000052 # mshr miss rate for overall accesses
746 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69418.374317 # average ReadReq mshr miss latency
747 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69418.374317 # average ReadReq mshr miss latency
748 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69418.374317 # average overall mshr miss latency
749 system.cpu.icache.demand_avg_mshr_miss_latency::total 69418.374317 # average overall mshr miss latency
750 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69418.374317 # average overall mshr miss latency
751 system.cpu.icache.overall_avg_mshr_miss_latency::total 69418.374317 # average overall mshr miss latency
752 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
753 system.cpu.l2cache.tags.replacements 0 # number of replacements
754 system.cpu.l2cache.tags.tagsinuse 10751.524012 # Cycle average of tags in use
755 system.cpu.l2cache.tags.total_refs 1834202 # Total number of references to valid blocks.
756 system.cpu.l2cache.tags.sampled_refs 15494 # Sample count of references to valid blocks.
757 system.cpu.l2cache.tags.avg_refs 118.381438 # Average number of references to valid blocks.
758 system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
759 system.cpu.l2cache.tags.occ_blocks::writebacks 9904.575959 # Average occupied blocks per requestor
760 system.cpu.l2cache.tags.occ_blocks::cpu.inst 617.996997 # Average occupied blocks per requestor
761 system.cpu.l2cache.tags.occ_blocks::cpu.data 228.951056 # Average occupied blocks per requestor
762 system.cpu.l2cache.tags.occ_percent::writebacks 0.302264 # Average percentage of cache occupancy
763 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.018860 # Average percentage of cache occupancy
764 system.cpu.l2cache.tags.occ_percent::cpu.data 0.006987 # Average percentage of cache occupancy
765 system.cpu.l2cache.tags.occ_percent::total 0.328110 # Average percentage of cache occupancy
766 system.cpu.l2cache.tags.occ_task_id_blocks::1024 15494 # Occupied blocks per task id
767 system.cpu.l2cache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id
768 system.cpu.l2cache.tags.age_task_id_blocks_1024::1 27 # Occupied blocks per task id
769 system.cpu.l2cache.tags.age_task_id_blocks_1024::2 509 # Occupied blocks per task id
770 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1306 # Occupied blocks per task id
771 system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13614 # Occupied blocks per task id
772 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.472839 # Percentage of cache occupancy per task id
773 system.cpu.l2cache.tags.tag_accesses 15186331 # Number of tag accesses
774 system.cpu.l2cache.tags.data_accesses 15186331 # Number of data accesses
775 system.cpu.l2cache.ReadReq_hits::cpu.inst 24 # number of ReadReq hits
776 system.cpu.l2cache.ReadReq_hits::cpu.data 906402 # number of ReadReq hits
777 system.cpu.l2cache.ReadReq_hits::total 906426 # number of ReadReq hits
778 system.cpu.l2cache.Writeback_hits::writebacks 942895 # number of Writeback hits
779 system.cpu.l2cache.Writeback_hits::total 942895 # number of Writeback hits
780 system.cpu.l2cache.ReadExReq_hits::cpu.data 26395 # number of ReadExReq hits
781 system.cpu.l2cache.ReadExReq_hits::total 26395 # number of ReadExReq hits
782 system.cpu.l2cache.demand_hits::cpu.inst 24 # number of demand (read+write) hits
783 system.cpu.l2cache.demand_hits::cpu.data 932797 # number of demand (read+write) hits
784 system.cpu.l2cache.demand_hits::total 932821 # number of demand (read+write) hits
785 system.cpu.l2cache.overall_hits::cpu.inst 24 # number of overall hits
786 system.cpu.l2cache.overall_hits::cpu.data 932797 # number of overall hits
787 system.cpu.l2cache.overall_hits::total 932821 # number of overall hits
788 system.cpu.l2cache.ReadReq_misses::cpu.inst 707 # number of ReadReq misses
789 system.cpu.l2cache.ReadReq_misses::cpu.data 276 # number of ReadReq misses
790 system.cpu.l2cache.ReadReq_misses::total 983 # number of ReadReq misses
791 system.cpu.l2cache.UpgradeReq_misses::cpu.data 1 # number of UpgradeReq misses
792 system.cpu.l2cache.UpgradeReq_misses::total 1 # number of UpgradeReq misses
793 system.cpu.l2cache.ReadExReq_misses::cpu.data 14538 # number of ReadExReq misses
794 system.cpu.l2cache.ReadExReq_misses::total 14538 # number of ReadExReq misses
795 system.cpu.l2cache.demand_misses::cpu.inst 707 # number of demand (read+write) misses
796 system.cpu.l2cache.demand_misses::cpu.data 14814 # number of demand (read+write) misses
797 system.cpu.l2cache.demand_misses::total 15521 # number of demand (read+write) misses
798 system.cpu.l2cache.overall_misses::cpu.inst 707 # number of overall misses
799 system.cpu.l2cache.overall_misses::cpu.data 14814 # number of overall misses
800 system.cpu.l2cache.overall_misses::total 15521 # number of overall misses
801 system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 49834500 # number of ReadReq miss cycles
802 system.cpu.l2cache.ReadReq_miss_latency::cpu.data 21050250 # number of ReadReq miss cycles
803 system.cpu.l2cache.ReadReq_miss_latency::total 70884750 # number of ReadReq miss cycles
804 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 978125750 # number of ReadExReq miss cycles
805 system.cpu.l2cache.ReadExReq_miss_latency::total 978125750 # number of ReadExReq miss cycles
806 system.cpu.l2cache.demand_miss_latency::cpu.inst 49834500 # number of demand (read+write) miss cycles
807 system.cpu.l2cache.demand_miss_latency::cpu.data 999176000 # number of demand (read+write) miss cycles
808 system.cpu.l2cache.demand_miss_latency::total 1049010500 # number of demand (read+write) miss cycles
809 system.cpu.l2cache.overall_miss_latency::cpu.inst 49834500 # number of overall miss cycles
810 system.cpu.l2cache.overall_miss_latency::cpu.data 999176000 # number of overall miss cycles
811 system.cpu.l2cache.overall_miss_latency::total 1049010500 # number of overall miss cycles
812 system.cpu.l2cache.ReadReq_accesses::cpu.inst 731 # number of ReadReq accesses(hits+misses)
813 system.cpu.l2cache.ReadReq_accesses::cpu.data 906678 # number of ReadReq accesses(hits+misses)
814 system.cpu.l2cache.ReadReq_accesses::total 907409 # number of ReadReq accesses(hits+misses)
815 system.cpu.l2cache.Writeback_accesses::writebacks 942895 # number of Writeback accesses(hits+misses)
816 system.cpu.l2cache.Writeback_accesses::total 942895 # number of Writeback accesses(hits+misses)
817 system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1 # number of UpgradeReq accesses(hits+misses)
818 system.cpu.l2cache.UpgradeReq_accesses::total 1 # number of UpgradeReq accesses(hits+misses)
819 system.cpu.l2cache.ReadExReq_accesses::cpu.data 40933 # number of ReadExReq accesses(hits+misses)
820 system.cpu.l2cache.ReadExReq_accesses::total 40933 # number of ReadExReq accesses(hits+misses)
821 system.cpu.l2cache.demand_accesses::cpu.inst 731 # number of demand (read+write) accesses
822 system.cpu.l2cache.demand_accesses::cpu.data 947611 # number of demand (read+write) accesses
823 system.cpu.l2cache.demand_accesses::total 948342 # number of demand (read+write) accesses
824 system.cpu.l2cache.overall_accesses::cpu.inst 731 # number of overall (read+write) accesses
825 system.cpu.l2cache.overall_accesses::cpu.data 947611 # number of overall (read+write) accesses
826 system.cpu.l2cache.overall_accesses::total 948342 # number of overall (read+write) accesses
827 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.967168 # miss rate for ReadReq accesses
828 system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000304 # miss rate for ReadReq accesses
829 system.cpu.l2cache.ReadReq_miss_rate::total 0.001083 # miss rate for ReadReq accesses
830 system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses
831 system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses
832 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.355166 # miss rate for ReadExReq accesses
833 system.cpu.l2cache.ReadExReq_miss_rate::total 0.355166 # miss rate for ReadExReq accesses
834 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.967168 # miss rate for demand accesses
835 system.cpu.l2cache.demand_miss_rate::cpu.data 0.015633 # miss rate for demand accesses
836 system.cpu.l2cache.demand_miss_rate::total 0.016366 # miss rate for demand accesses
837 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.967168 # miss rate for overall accesses
838 system.cpu.l2cache.overall_miss_rate::cpu.data 0.015633 # miss rate for overall accesses
839 system.cpu.l2cache.overall_miss_rate::total 0.016366 # miss rate for overall accesses
840 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70487.270156 # average ReadReq miss latency
841 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76269.021739 # average ReadReq miss latency
842 system.cpu.l2cache.ReadReq_avg_miss_latency::total 72110.630722 # average ReadReq miss latency
843 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 67280.626634 # average ReadExReq miss latency
844 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67280.626634 # average ReadExReq miss latency
845 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70487.270156 # average overall miss latency
846 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 67448.089645 # average overall miss latency
847 system.cpu.l2cache.demand_avg_miss_latency::total 67586.527930 # average overall miss latency
848 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70487.270156 # average overall miss latency
849 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 67448.089645 # average overall miss latency
850 system.cpu.l2cache.overall_avg_miss_latency::total 67586.527930 # average overall miss latency
851 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
852 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
853 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
854 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
855 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
856 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
857 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
858 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
859 system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits
860 system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 10 # number of ReadReq MSHR hits
861 system.cpu.l2cache.ReadReq_mshr_hits::total 11 # number of ReadReq MSHR hits
862 system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
863 system.cpu.l2cache.demand_mshr_hits::cpu.data 10 # number of demand (read+write) MSHR hits
864 system.cpu.l2cache.demand_mshr_hits::total 11 # number of demand (read+write) MSHR hits
865 system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
866 system.cpu.l2cache.overall_mshr_hits::cpu.data 10 # number of overall MSHR hits
867 system.cpu.l2cache.overall_mshr_hits::total 11 # number of overall MSHR hits
868 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 706 # number of ReadReq MSHR misses
869 system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 266 # number of ReadReq MSHR misses
870 system.cpu.l2cache.ReadReq_mshr_misses::total 972 # number of ReadReq MSHR misses
871 system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1 # number of UpgradeReq MSHR misses
872 system.cpu.l2cache.UpgradeReq_mshr_misses::total 1 # number of UpgradeReq MSHR misses
873 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14538 # number of ReadExReq MSHR misses
874 system.cpu.l2cache.ReadExReq_mshr_misses::total 14538 # number of ReadExReq MSHR misses
875 system.cpu.l2cache.demand_mshr_misses::cpu.inst 706 # number of demand (read+write) MSHR misses
876 system.cpu.l2cache.demand_mshr_misses::cpu.data 14804 # number of demand (read+write) MSHR misses
877 system.cpu.l2cache.demand_mshr_misses::total 15510 # number of demand (read+write) MSHR misses
878 system.cpu.l2cache.overall_mshr_misses::cpu.inst 706 # number of overall MSHR misses
879 system.cpu.l2cache.overall_mshr_misses::cpu.data 14804 # number of overall MSHR misses
880 system.cpu.l2cache.overall_mshr_misses::total 15510 # number of overall MSHR misses
881 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 40933250 # number of ReadReq MSHR miss cycles
882 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 17118000 # number of ReadReq MSHR miss cycles
883 system.cpu.l2cache.ReadReq_mshr_miss_latency::total 58051250 # number of ReadReq MSHR miss cycles
884 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 10001 # number of UpgradeReq MSHR miss cycles
885 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 10001 # number of UpgradeReq MSHR miss cycles
886 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 795610750 # number of ReadExReq MSHR miss cycles
887 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 795610750 # number of ReadExReq MSHR miss cycles
888 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 40933250 # number of demand (read+write) MSHR miss cycles
889 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 812728750 # number of demand (read+write) MSHR miss cycles
890 system.cpu.l2cache.demand_mshr_miss_latency::total 853662000 # number of demand (read+write) MSHR miss cycles
891 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 40933250 # number of overall MSHR miss cycles
892 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 812728750 # number of overall MSHR miss cycles
893 system.cpu.l2cache.overall_mshr_miss_latency::total 853662000 # number of overall MSHR miss cycles
894 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.965800 # mshr miss rate for ReadReq accesses
895 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000293 # mshr miss rate for ReadReq accesses
896 system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001071 # mshr miss rate for ReadReq accesses
897 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses
898 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
899 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.355166 # mshr miss rate for ReadExReq accesses
900 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.355166 # mshr miss rate for ReadExReq accesses
901 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.965800 # mshr miss rate for demand accesses
902 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015622 # mshr miss rate for demand accesses
903 system.cpu.l2cache.demand_mshr_miss_rate::total 0.016355 # mshr miss rate for demand accesses
904 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965800 # mshr miss rate for overall accesses
905 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015622 # mshr miss rate for overall accesses
906 system.cpu.l2cache.overall_mshr_miss_rate::total 0.016355 # mshr miss rate for overall accesses
907 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57979.107649 # average ReadReq mshr miss latency
908 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64353.383459 # average ReadReq mshr miss latency
909 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59723.508230 # average ReadReq mshr miss latency
910 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency
911 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency
912 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54726.286284 # average ReadExReq mshr miss latency
913 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54726.286284 # average ReadExReq mshr miss latency
914 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57979.107649 # average overall mshr miss latency
915 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 54899.267090 # average overall mshr miss latency
916 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55039.458414 # average overall mshr miss latency
917 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57979.107649 # average overall mshr miss latency
918 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 54899.267090 # average overall mshr miss latency
919 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55039.458414 # average overall mshr miss latency
920 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
921 system.cpu.dcache.tags.replacements 943515 # number of replacements
922 system.cpu.dcache.tags.tagsinuse 3673.207831 # Cycle average of tags in use
923 system.cpu.dcache.tags.total_refs 28229578 # Total number of references to valid blocks.
924 system.cpu.dcache.tags.sampled_refs 947611 # Sample count of references to valid blocks.
925 system.cpu.dcache.tags.avg_refs 29.790260 # Average number of references to valid blocks.
926 system.cpu.dcache.tags.warmup_cycle 7976079250 # Cycle when the warmup percentage was hit.
927 system.cpu.dcache.tags.occ_blocks::cpu.data 3673.207831 # Average occupied blocks per requestor
928 system.cpu.dcache.tags.occ_percent::cpu.data 0.896779 # Average percentage of cache occupancy
929 system.cpu.dcache.tags.occ_percent::total 0.896779 # Average percentage of cache occupancy
930 system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
931 system.cpu.dcache.tags.age_task_id_blocks_1024::0 452 # Occupied blocks per task id
932 system.cpu.dcache.tags.age_task_id_blocks_1024::1 3133 # Occupied blocks per task id
933 system.cpu.dcache.tags.age_task_id_blocks_1024::2 511 # Occupied blocks per task id
934 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
935 system.cpu.dcache.tags.tag_accesses 60126081 # Number of tag accesses
936 system.cpu.dcache.tags.data_accesses 60126081 # Number of data accesses
937 system.cpu.dcache.ReadReq_hits::cpu.data 23676805 # number of ReadReq hits
938 system.cpu.dcache.ReadReq_hits::total 23676805 # number of ReadReq hits
939 system.cpu.dcache.WriteReq_hits::cpu.data 4544974 # number of WriteReq hits
940 system.cpu.dcache.WriteReq_hits::total 4544974 # number of WriteReq hits
941 system.cpu.dcache.LoadLockedReq_hits::cpu.data 3910 # number of LoadLockedReq hits
942 system.cpu.dcache.LoadLockedReq_hits::total 3910 # number of LoadLockedReq hits
943 system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits
944 system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits
945 system.cpu.dcache.demand_hits::cpu.data 28221779 # number of demand (read+write) hits
946 system.cpu.dcache.demand_hits::total 28221779 # number of demand (read+write) hits
947 system.cpu.dcache.overall_hits::cpu.data 28221779 # number of overall hits
948 system.cpu.dcache.overall_hits::total 28221779 # number of overall hits
949 system.cpu.dcache.ReadReq_misses::cpu.data 1169644 # number of ReadReq misses
950 system.cpu.dcache.ReadReq_misses::total 1169644 # number of ReadReq misses
951 system.cpu.dcache.WriteReq_misses::cpu.data 190007 # number of WriteReq misses
952 system.cpu.dcache.WriteReq_misses::total 190007 # number of WriteReq misses
953 system.cpu.dcache.LoadLockedReq_misses::cpu.data 8 # number of LoadLockedReq misses
954 system.cpu.dcache.LoadLockedReq_misses::total 8 # number of LoadLockedReq misses
955 system.cpu.dcache.demand_misses::cpu.data 1359651 # number of demand (read+write) misses
956 system.cpu.dcache.demand_misses::total 1359651 # number of demand (read+write) misses
957 system.cpu.dcache.overall_misses::cpu.data 1359651 # number of overall misses
958 system.cpu.dcache.overall_misses::total 1359651 # number of overall misses
959 system.cpu.dcache.ReadReq_miss_latency::cpu.data 13867675477 # number of ReadReq miss cycles
960 system.cpu.dcache.ReadReq_miss_latency::total 13867675477 # number of ReadReq miss cycles
961 system.cpu.dcache.WriteReq_miss_latency::cpu.data 8610605390 # number of WriteReq miss cycles
962 system.cpu.dcache.WriteReq_miss_latency::total 8610605390 # number of WriteReq miss cycles
963 system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 264500 # number of LoadLockedReq miss cycles
964 system.cpu.dcache.LoadLockedReq_miss_latency::total 264500 # number of LoadLockedReq miss cycles
965 system.cpu.dcache.demand_miss_latency::cpu.data 22478280867 # number of demand (read+write) miss cycles
966 system.cpu.dcache.demand_miss_latency::total 22478280867 # number of demand (read+write) miss cycles
967 system.cpu.dcache.overall_miss_latency::cpu.data 22478280867 # number of overall miss cycles
968 system.cpu.dcache.overall_miss_latency::total 22478280867 # number of overall miss cycles
969 system.cpu.dcache.ReadReq_accesses::cpu.data 24846449 # number of ReadReq accesses(hits+misses)
970 system.cpu.dcache.ReadReq_accesses::total 24846449 # number of ReadReq accesses(hits+misses)
971 system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses)
972 system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses)
973 system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3918 # number of LoadLockedReq accesses(hits+misses)
974 system.cpu.dcache.LoadLockedReq_accesses::total 3918 # number of LoadLockedReq accesses(hits+misses)
975 system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses)
976 system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses)
977 system.cpu.dcache.demand_accesses::cpu.data 29581430 # number of demand (read+write) accesses
978 system.cpu.dcache.demand_accesses::total 29581430 # number of demand (read+write) accesses
979 system.cpu.dcache.overall_accesses::cpu.data 29581430 # number of overall (read+write) accesses
980 system.cpu.dcache.overall_accesses::total 29581430 # number of overall (read+write) accesses
981 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.047075 # miss rate for ReadReq accesses
982 system.cpu.dcache.ReadReq_miss_rate::total 0.047075 # miss rate for ReadReq accesses
983 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.040128 # miss rate for WriteReq accesses
984 system.cpu.dcache.WriteReq_miss_rate::total 0.040128 # miss rate for WriteReq accesses
985 system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002042 # miss rate for LoadLockedReq accesses
986 system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002042 # miss rate for LoadLockedReq accesses
987 system.cpu.dcache.demand_miss_rate::cpu.data 0.045963 # miss rate for demand accesses
988 system.cpu.dcache.demand_miss_rate::total 0.045963 # miss rate for demand accesses
989 system.cpu.dcache.overall_miss_rate::cpu.data 0.045963 # miss rate for overall accesses
990 system.cpu.dcache.overall_miss_rate::total 0.045963 # miss rate for overall accesses
991 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11856.321647 # average ReadReq miss latency
992 system.cpu.dcache.ReadReq_avg_miss_latency::total 11856.321647 # average ReadReq miss latency
993 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 45317.306152 # average WriteReq miss latency
994 system.cpu.dcache.WriteReq_avg_miss_latency::total 45317.306152 # average WriteReq miss latency
995 system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 33062.500000 # average LoadLockedReq miss latency
996 system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 33062.500000 # average LoadLockedReq miss latency
997 system.cpu.dcache.demand_avg_miss_latency::cpu.data 16532.390199 # average overall miss latency
998 system.cpu.dcache.demand_avg_miss_latency::total 16532.390199 # average overall miss latency
999 system.cpu.dcache.overall_avg_miss_latency::cpu.data 16532.390199 # average overall miss latency
1000 system.cpu.dcache.overall_avg_miss_latency::total 16532.390199 # average overall miss latency
1001 system.cpu.dcache.blocked_cycles::no_mshrs 136970 # number of cycles access was blocked
1002 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1003 system.cpu.dcache.blocked::no_mshrs 24472 # number of cycles access was blocked
1004 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
1005 system.cpu.dcache.avg_blocked_cycles::no_mshrs 5.597009 # average number of cycles each access was blocked
1006 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1007 system.cpu.dcache.fast_writes 0 # number of fast writes performed
1008 system.cpu.dcache.cache_copies 0 # number of cache copies performed
1009 system.cpu.dcache.writebacks::writebacks 942895 # number of writebacks
1010 system.cpu.dcache.writebacks::total 942895 # number of writebacks
1011 system.cpu.dcache.ReadReq_mshr_hits::cpu.data 262958 # number of ReadReq MSHR hits
1012 system.cpu.dcache.ReadReq_mshr_hits::total 262958 # number of ReadReq MSHR hits
1013 system.cpu.dcache.WriteReq_mshr_hits::cpu.data 149081 # number of WriteReq MSHR hits
1014 system.cpu.dcache.WriteReq_mshr_hits::total 149081 # number of WriteReq MSHR hits
1015 system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 8 # number of LoadLockedReq MSHR hits
1016 system.cpu.dcache.LoadLockedReq_mshr_hits::total 8 # number of LoadLockedReq MSHR hits
1017 system.cpu.dcache.demand_mshr_hits::cpu.data 412039 # number of demand (read+write) MSHR hits
1018 system.cpu.dcache.demand_mshr_hits::total 412039 # number of demand (read+write) MSHR hits
1019 system.cpu.dcache.overall_mshr_hits::cpu.data 412039 # number of overall MSHR hits
1020 system.cpu.dcache.overall_mshr_hits::total 412039 # number of overall MSHR hits
1021 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 906686 # number of ReadReq MSHR misses
1022 system.cpu.dcache.ReadReq_mshr_misses::total 906686 # number of ReadReq MSHR misses
1023 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 40926 # number of WriteReq MSHR misses
1024 system.cpu.dcache.WriteReq_mshr_misses::total 40926 # number of WriteReq MSHR misses
1025 system.cpu.dcache.demand_mshr_misses::cpu.data 947612 # number of demand (read+write) MSHR misses
1026 system.cpu.dcache.demand_mshr_misses::total 947612 # number of demand (read+write) MSHR misses
1027 system.cpu.dcache.overall_mshr_misses::cpu.data 947612 # number of overall MSHR misses
1028 system.cpu.dcache.overall_mshr_misses::total 947612 # number of overall MSHR misses
1029 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10019308761 # number of ReadReq MSHR miss cycles
1030 system.cpu.dcache.ReadReq_mshr_miss_latency::total 10019308761 # number of ReadReq MSHR miss cycles
1031 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1304642257 # number of WriteReq MSHR miss cycles
1032 system.cpu.dcache.WriteReq_mshr_miss_latency::total 1304642257 # number of WriteReq MSHR miss cycles
1033 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11323951018 # number of demand (read+write) MSHR miss cycles
1034 system.cpu.dcache.demand_mshr_miss_latency::total 11323951018 # number of demand (read+write) MSHR miss cycles
1035 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11323951018 # number of overall MSHR miss cycles
1036 system.cpu.dcache.overall_mshr_miss_latency::total 11323951018 # number of overall MSHR miss cycles
1037 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036492 # mshr miss rate for ReadReq accesses
1038 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036492 # mshr miss rate for ReadReq accesses
1039 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.008643 # mshr miss rate for WriteReq accesses
1040 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.008643 # mshr miss rate for WriteReq accesses
1041 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032034 # mshr miss rate for demand accesses
1042 system.cpu.dcache.demand_mshr_miss_rate::total 0.032034 # mshr miss rate for demand accesses
1043 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032034 # mshr miss rate for overall accesses
1044 system.cpu.dcache.overall_mshr_miss_rate::total 0.032034 # mshr miss rate for overall accesses
1045 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11050.472557 # average ReadReq mshr miss latency
1046 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11050.472557 # average ReadReq mshr miss latency
1047 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31878.078898 # average WriteReq mshr miss latency
1048 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31878.078898 # average WriteReq mshr miss latency
1049 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11949.986933 # average overall mshr miss latency
1050 system.cpu.dcache.demand_avg_mshr_miss_latency::total 11949.986933 # average overall mshr miss latency
1051 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11949.986933 # average overall mshr miss latency
1052 system.cpu.dcache.overall_avg_mshr_miss_latency::total 11949.986933 # average overall mshr miss latency
1053 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1055 ---------- End Simulation Statistics ----------
projects / gem5.git / blob