2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.058203 # Number of seconds simulated
4 sim_ticks 58203290500 # Number of ticks simulated
5 final_tick 58203290500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 131910 # Simulator instruction rate (inst/s)
8 host_op_rate 132567 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 84750962 # Simulator tick rate (ticks/s)
10 host_mem_usage 445160 # Number of bytes of host memory used
11 host_seconds 686.76 # Real time elapsed on the host
12 sim_insts 90589799 # Number of instructions simulated
13 sim_ops 91041030 # Number of ops (including micro ops) simulated
14 system.voltage_domain.voltage 1 # Voltage in Volts
15 system.clk_domain.clock 1000 # Clock period in ticks
16 system.physmem.bytes_read::cpu.inst 44544 # Number of bytes read from this memory
17 system.physmem.bytes_read::cpu.data 48256 # Number of bytes read from this memory
18 system.physmem.bytes_read::cpu.l2cache.prefetcher 930624 # Number of bytes read from this memory
19 system.physmem.bytes_read::total 1023424 # Number of bytes read from this memory
20 system.physmem.bytes_inst_read::cpu.inst 44544 # Number of instructions bytes read from this memory
21 system.physmem.bytes_inst_read::total 44544 # Number of instructions bytes read from this memory
22 system.physmem.bytes_written::writebacks 25536 # Number of bytes written to this memory
23 system.physmem.bytes_written::total 25536 # Number of bytes written to this memory
24 system.physmem.num_reads::cpu.inst 696 # Number of read requests responded to by this memory
25 system.physmem.num_reads::cpu.data 754 # Number of read requests responded to by this memory
26 system.physmem.num_reads::cpu.l2cache.prefetcher 14541 # Number of read requests responded to by this memory
27 system.physmem.num_reads::total 15991 # Number of read requests responded to by this memory
28 system.physmem.num_writes::writebacks 399 # Number of write requests responded to by this memory
29 system.physmem.num_writes::total 399 # Number of write requests responded to by this memory
30 system.physmem.bw_read::cpu.inst 765318 # Total read bandwidth from this memory (bytes/s)
31 system.physmem.bw_read::cpu.data 829094 # Total read bandwidth from this memory (bytes/s)
32 system.physmem.bw_read::cpu.l2cache.prefetcher 15989199 # Total read bandwidth from this memory (bytes/s)
33 system.physmem.bw_read::total 17583611 # Total read bandwidth from this memory (bytes/s)
34 system.physmem.bw_inst_read::cpu.inst 765318 # Instruction read bandwidth from this memory (bytes/s)
35 system.physmem.bw_inst_read::total 765318 # Instruction read bandwidth from this memory (bytes/s)
36 system.physmem.bw_write::writebacks 438738 # Write bandwidth from this memory (bytes/s)
37 system.physmem.bw_write::total 438738 # Write bandwidth from this memory (bytes/s)
38 system.physmem.bw_total::writebacks 438738 # Total bandwidth to/from this memory (bytes/s)
39 system.physmem.bw_total::cpu.inst 765318 # Total bandwidth to/from this memory (bytes/s)
40 system.physmem.bw_total::cpu.data 829094 # Total bandwidth to/from this memory (bytes/s)
41 system.physmem.bw_total::cpu.l2cache.prefetcher 15989199 # Total bandwidth to/from this memory (bytes/s)
42 system.physmem.bw_total::total 18022349 # Total bandwidth to/from this memory (bytes/s)
43 system.physmem.readReqs 15991 # Number of read requests accepted
44 system.physmem.writeReqs 399 # Number of write requests accepted
45 system.physmem.readBursts 15991 # Number of DRAM read bursts, including those serviced by the write queue
46 system.physmem.writeBursts 399 # Number of DRAM write bursts, including those merged in the write queue
47 system.physmem.bytesReadDRAM 1010944 # Total number of bytes read from DRAM
48 system.physmem.bytesReadWrQ 12480 # Total number of bytes read from write queue
49 system.physmem.bytesWritten 24064 # Total number of bytes written to DRAM
50 system.physmem.bytesReadSys 1023424 # Total read bytes from the system interface side
51 system.physmem.bytesWrittenSys 25536 # Total written bytes from the system interface side
52 system.physmem.servicedByWrQ 195 # Number of DRAM read bursts serviced by the write queue
53 system.physmem.mergedWrBursts 3 # Number of DRAM write bursts merged with an existing one
54 system.physmem.neitherReadNorWriteReqs 2 # Number of requests that are neither read nor write
55 system.physmem.perBankRdBursts::0 1015 # Per bank write bursts
56 system.physmem.perBankRdBursts::1 876 # Per bank write bursts
57 system.physmem.perBankRdBursts::2 963 # Per bank write bursts
58 system.physmem.perBankRdBursts::3 1023 # Per bank write bursts
59 system.physmem.perBankRdBursts::4 1065 # Per bank write bursts
60 system.physmem.perBankRdBursts::5 1139 # Per bank write bursts
61 system.physmem.perBankRdBursts::6 1118 # Per bank write bursts
62 system.physmem.perBankRdBursts::7 1101 # Per bank write bursts
63 system.physmem.perBankRdBursts::8 1044 # Per bank write bursts
64 system.physmem.perBankRdBursts::9 962 # Per bank write bursts
65 system.physmem.perBankRdBursts::10 939 # Per bank write bursts
66 system.physmem.perBankRdBursts::11 899 # Per bank write bursts
67 system.physmem.perBankRdBursts::12 905 # Per bank write bursts
68 system.physmem.perBankRdBursts::13 898 # Per bank write bursts
69 system.physmem.perBankRdBursts::14 928 # Per bank write bursts
70 system.physmem.perBankRdBursts::15 921 # Per bank write bursts
71 system.physmem.perBankWrBursts::0 32 # Per bank write bursts
72 system.physmem.perBankWrBursts::1 0 # Per bank write bursts
73 system.physmem.perBankWrBursts::2 16 # Per bank write bursts
74 system.physmem.perBankWrBursts::3 0 # Per bank write bursts
75 system.physmem.perBankWrBursts::4 9 # Per bank write bursts
76 system.physmem.perBankWrBursts::5 45 # Per bank write bursts
77 system.physmem.perBankWrBursts::6 72 # Per bank write bursts
78 system.physmem.perBankWrBursts::7 35 # Per bank write bursts
79 system.physmem.perBankWrBursts::8 36 # Per bank write bursts
80 system.physmem.perBankWrBursts::9 0 # Per bank write bursts
81 system.physmem.perBankWrBursts::10 13 # Per bank write bursts
82 system.physmem.perBankWrBursts::11 2 # Per bank write bursts
83 system.physmem.perBankWrBursts::12 5 # Per bank write bursts
84 system.physmem.perBankWrBursts::13 37 # Per bank write bursts
85 system.physmem.perBankWrBursts::14 47 # Per bank write bursts
86 system.physmem.perBankWrBursts::15 27 # Per bank write bursts
87 system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
88 system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
89 system.physmem.totGap 58203132500 # Total gap between requests
90 system.physmem.readPktSize::0 0 # Read request sizes (log2)
91 system.physmem.readPktSize::1 0 # Read request sizes (log2)
92 system.physmem.readPktSize::2 0 # Read request sizes (log2)
93 system.physmem.readPktSize::3 0 # Read request sizes (log2)
94 system.physmem.readPktSize::4 0 # Read request sizes (log2)
95 system.physmem.readPktSize::5 0 # Read request sizes (log2)
96 system.physmem.readPktSize::6 15991 # Read request sizes (log2)
97 system.physmem.writePktSize::0 0 # Write request sizes (log2)
98 system.physmem.writePktSize::1 0 # Write request sizes (log2)
99 system.physmem.writePktSize::2 0 # Write request sizes (log2)
100 system.physmem.writePktSize::3 0 # Write request sizes (log2)
101 system.physmem.writePktSize::4 0 # Write request sizes (log2)
102 system.physmem.writePktSize::5 0 # Write request sizes (log2)
103 system.physmem.writePktSize::6 399 # Write request sizes (log2)
104 system.physmem.rdQLenPdf::0 10953 # What read queue length does an incoming req see
105 system.physmem.rdQLenPdf::1 2399 # What read queue length does an incoming req see
106 system.physmem.rdQLenPdf::2 519 # What read queue length does an incoming req see
107 system.physmem.rdQLenPdf::3 359 # What read queue length does an incoming req see
108 system.physmem.rdQLenPdf::4 309 # What read queue length does an incoming req see
109 system.physmem.rdQLenPdf::5 297 # What read queue length does an incoming req see
110 system.physmem.rdQLenPdf::6 305 # What read queue length does an incoming req see
111 system.physmem.rdQLenPdf::7 289 # What read queue length does an incoming req see
112 system.physmem.rdQLenPdf::8 304 # What read queue length does an incoming req see
113 system.physmem.rdQLenPdf::9 62 # What read queue length does an incoming req see
114 system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
115 system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
116 system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
117 system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
118 system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
119 system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
120 system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
121 system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
122 system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
123 system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
124 system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
125 system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
126 system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
127 system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
128 system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
129 system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
130 system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
131 system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
132 system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
133 system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
134 system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
135 system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
136 system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
137 system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
138 system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
139 system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
140 system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
141 system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
142 system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
143 system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
144 system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
145 system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
146 system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
147 system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
148 system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
149 system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
150 system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
151 system.physmem.wrQLenPdf::15 20 # What write queue length does an incoming req see
152 system.physmem.wrQLenPdf::16 20 # What write queue length does an incoming req see
153 system.physmem.wrQLenPdf::17 22 # What write queue length does an incoming req see
154 system.physmem.wrQLenPdf::18 22 # What write queue length does an incoming req see
155 system.physmem.wrQLenPdf::19 22 # What write queue length does an incoming req see
156 system.physmem.wrQLenPdf::20 21 # What write queue length does an incoming req see
157 system.physmem.wrQLenPdf::21 21 # What write queue length does an incoming req see
158 system.physmem.wrQLenPdf::22 21 # What write queue length does an incoming req see
159 system.physmem.wrQLenPdf::23 21 # What write queue length does an incoming req see
160 system.physmem.wrQLenPdf::24 21 # What write queue length does an incoming req see
161 system.physmem.wrQLenPdf::25 21 # What write queue length does an incoming req see
162 system.physmem.wrQLenPdf::26 21 # What write queue length does an incoming req see
163 system.physmem.wrQLenPdf::27 21 # What write queue length does an incoming req see
164 system.physmem.wrQLenPdf::28 21 # What write queue length does an incoming req see
165 system.physmem.wrQLenPdf::29 23 # What write queue length does an incoming req see
166 system.physmem.wrQLenPdf::30 21 # What write queue length does an incoming req see
167 system.physmem.wrQLenPdf::31 21 # What write queue length does an incoming req see
168 system.physmem.wrQLenPdf::32 21 # What write queue length does an incoming req see
169 system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
170 system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
171 system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
172 system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
173 system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
174 system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
175 system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
176 system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
177 system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
178 system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
179 system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
180 system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
181 system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
182 system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
183 system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
184 system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
185 system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
186 system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
187 system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
188 system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
189 system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
190 system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
191 system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
192 system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
193 system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
194 system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
195 system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
196 system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
197 system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
198 system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
199 system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
200 system.physmem.bytesPerActivate::samples 1905 # Bytes accessed per row activation
201 system.physmem.bytesPerActivate::mean 542.975328 # Bytes accessed per row activation
202 system.physmem.bytesPerActivate::gmean 308.892213 # Bytes accessed per row activation
203 system.physmem.bytesPerActivate::stdev 434.261771 # Bytes accessed per row activation
204 system.physmem.bytesPerActivate::0-127 566 29.71% 29.71% # Bytes accessed per row activation
205 system.physmem.bytesPerActivate::128-255 241 12.65% 42.36% # Bytes accessed per row activation
206 system.physmem.bytesPerActivate::256-383 93 4.88% 47.24% # Bytes accessed per row activation
207 system.physmem.bytesPerActivate::384-511 55 2.89% 50.13% # Bytes accessed per row activation
208 system.physmem.bytesPerActivate::512-639 58 3.04% 53.18% # Bytes accessed per row activation
209 system.physmem.bytesPerActivate::640-767 46 2.41% 55.59% # Bytes accessed per row activation
210 system.physmem.bytesPerActivate::768-895 56 2.94% 58.53% # Bytes accessed per row activation
211 system.physmem.bytesPerActivate::896-1023 43 2.26% 60.79% # Bytes accessed per row activation
212 system.physmem.bytesPerActivate::1024-1151 747 39.21% 100.00% # Bytes accessed per row activation
213 system.physmem.bytesPerActivate::total 1905 # Bytes accessed per row activation
214 system.physmem.rdPerTurnAround::samples 21 # Reads before turning the bus around for writes
215 system.physmem.rdPerTurnAround::mean 751.047619 # Reads before turning the bus around for writes
216 system.physmem.rdPerTurnAround::gmean 33.268614 # Reads before turning the bus around for writes
217 system.physmem.rdPerTurnAround::stdev 3285.704681 # Reads before turning the bus around for writes
218 system.physmem.rdPerTurnAround::0-511 20 95.24% 95.24% # Reads before turning the bus around for writes
219 system.physmem.rdPerTurnAround::14848-15359 1 4.76% 100.00% # Reads before turning the bus around for writes
220 system.physmem.rdPerTurnAround::total 21 # Reads before turning the bus around for writes
221 system.physmem.wrPerTurnAround::samples 21 # Writes before turning the bus around for reads
222 system.physmem.wrPerTurnAround::mean 17.904762 # Writes before turning the bus around for reads
223 system.physmem.wrPerTurnAround::gmean 17.888741 # Writes before turning the bus around for reads
224 system.physmem.wrPerTurnAround::stdev 0.768424 # Writes before turning the bus around for reads
225 system.physmem.wrPerTurnAround::16 2 9.52% 9.52% # Writes before turning the bus around for reads
226 system.physmem.wrPerTurnAround::18 18 85.71% 95.24% # Writes before turning the bus around for reads
227 system.physmem.wrPerTurnAround::20 1 4.76% 100.00% # Writes before turning the bus around for reads
228 system.physmem.wrPerTurnAround::total 21 # Writes before turning the bus around for reads
229 system.physmem.totQLat 171453784 # Total ticks spent queuing
230 system.physmem.totMemAccLat 467628784 # Total ticks spent from burst creation until serviced by the DRAM
231 system.physmem.totBusLat 78980000 # Total ticks spent in databus transfers
232 system.physmem.avgQLat 10854.25 # Average queueing delay per DRAM burst
233 system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
234 system.physmem.avgMemAccLat 29604.25 # Average memory access latency per DRAM burst
235 system.physmem.avgRdBW 17.37 # Average DRAM read bandwidth in MiByte/s
236 system.physmem.avgWrBW 0.41 # Average achieved write bandwidth in MiByte/s
237 system.physmem.avgRdBWSys 17.58 # Average system read bandwidth in MiByte/s
238 system.physmem.avgWrBWSys 0.44 # Average system write bandwidth in MiByte/s
239 system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
240 system.physmem.busUtil 0.14 # Data bus utilization in percentage
241 system.physmem.busUtilRead 0.14 # Data bus utilization in percentage for reads
242 system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
243 system.physmem.avgRdQLen 1.12 # Average read queue length when enqueuing
244 system.physmem.avgWrQLen 19.75 # Average write queue length when enqueuing
245 system.physmem.readRowHits 14158 # Number of row buffer hits during reads
246 system.physmem.writeRowHits 107 # Number of row buffer hits during writes
247 system.physmem.readRowHitRate 89.63 # Row buffer hit rate for reads
248 system.physmem.writeRowHitRate 27.02 # Row buffer hit rate for writes
249 system.physmem.avgGap 3551136.82 # Average gap between requests
250 system.physmem.pageHitRate 88.10 # Row buffer hit rate, read and write combined
251 system.physmem_0.actEnergy 7854840 # Energy for activate commands per rank (pJ)
252 system.physmem_0.preEnergy 4285875 # Energy for precharge commands per rank (pJ)
253 system.physmem_0.readEnergy 64662000 # Energy for read commands per rank (pJ)
254 system.physmem_0.writeEnergy 1354320 # Energy for write commands per rank (pJ)
255 system.physmem_0.refreshEnergy 3801486000 # Energy for refresh commands per rank (pJ)
256 system.physmem_0.actBackEnergy 2465906355 # Energy for active background per rank (pJ)
257 system.physmem_0.preBackEnergy 32758411500 # Energy for precharge background per rank (pJ)
258 system.physmem_0.totalEnergy 39103960890 # Total energy per rank (pJ)
259 system.physmem_0.averagePower 671.860748 # Core power per rank (mW)
260 system.physmem_0.memoryStateTime::IDLE 54486158959 # Time in different power states
261 system.physmem_0.memoryStateTime::REF 1943500000 # Time in different power states
262 system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
263 system.physmem_0.memoryStateTime::ACT 1772833541 # Time in different power states
264 system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
265 system.physmem_1.actEnergy 6546960 # Energy for activate commands per rank (pJ)
266 system.physmem_1.preEnergy 3572250 # Energy for precharge commands per rank (pJ)
267 system.physmem_1.readEnergy 58468800 # Energy for read commands per rank (pJ)
268 system.physmem_1.writeEnergy 1082160 # Energy for write commands per rank (pJ)
269 system.physmem_1.refreshEnergy 3801486000 # Energy for refresh commands per rank (pJ)
270 system.physmem_1.actBackEnergy 2423272635 # Energy for active background per rank (pJ)
271 system.physmem_1.preBackEnergy 32795809500 # Energy for precharge background per rank (pJ)
272 system.physmem_1.totalEnergy 39090238305 # Total energy per rank (pJ)
273 system.physmem_1.averagePower 671.624974 # Core power per rank (mW)
274 system.physmem_1.memoryStateTime::IDLE 54548877915 # Time in different power states
275 system.physmem_1.memoryStateTime::REF 1943500000 # Time in different power states
276 system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
277 system.physmem_1.memoryStateTime::ACT 1710114585 # Time in different power states
278 system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
279 system.cpu.branchPred.lookups 28259243 # Number of BP lookups
280 system.cpu.branchPred.condPredicted 23281231 # Number of conditional branches predicted
281 system.cpu.branchPred.condIncorrect 837964 # Number of conditional branches incorrect
282 system.cpu.branchPred.BTBLookups 11853879 # Number of BTB lookups
283 system.cpu.branchPred.BTBHits 11785418 # Number of BTB hits
284 system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
285 system.cpu.branchPred.BTBHitPct 99.422459 # BTB Hit Percentage
286 system.cpu.branchPred.usedRAS 75772 # Number of times the RAS was used to get a target.
287 system.cpu.branchPred.RASInCorrect 89 # Number of incorrect RAS predictions.
288 system.cpu_clk_domain.clock 500 # Clock period in ticks
289 system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
290 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
291 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
292 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
293 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
294 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
295 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
296 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
297 system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
298 system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
299 system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
300 system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
301 system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
302 system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
303 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
304 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
305 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
306 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
307 system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
308 system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
309 system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
310 system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
311 system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
312 system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
313 system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
314 system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
315 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
316 system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
317 system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
318 system.cpu.dtb.walker.walks 0 # Table walker walks requested
319 system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
320 system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
321 system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
322 system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
323 system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
324 system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
325 system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
326 system.cpu.dtb.inst_hits 0 # ITB inst hits
327 system.cpu.dtb.inst_misses 0 # ITB inst misses
328 system.cpu.dtb.read_hits 0 # DTB read hits
329 system.cpu.dtb.read_misses 0 # DTB read misses
330 system.cpu.dtb.write_hits 0 # DTB write hits
331 system.cpu.dtb.write_misses 0 # DTB write misses
332 system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
333 system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
334 system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
335 system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
336 system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
337 system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
338 system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
339 system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
340 system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
341 system.cpu.dtb.read_accesses 0 # DTB read accesses
342 system.cpu.dtb.write_accesses 0 # DTB write accesses
343 system.cpu.dtb.inst_accesses 0 # ITB inst accesses
344 system.cpu.dtb.hits 0 # DTB hits
345 system.cpu.dtb.misses 0 # DTB misses
346 system.cpu.dtb.accesses 0 # DTB accesses
347 system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
348 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
349 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
350 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
351 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
352 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
353 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
354 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
355 system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
356 system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
357 system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
358 system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
359 system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
360 system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
361 system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
362 system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
363 system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
364 system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
365 system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
366 system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
367 system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
368 system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
369 system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
370 system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
371 system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
372 system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
373 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
374 system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
375 system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
376 system.cpu.itb.walker.walks 0 # Table walker walks requested
377 system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
378 system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
379 system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
380 system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
381 system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
382 system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
383 system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
384 system.cpu.itb.inst_hits 0 # ITB inst hits
385 system.cpu.itb.inst_misses 0 # ITB inst misses
386 system.cpu.itb.read_hits 0 # DTB read hits
387 system.cpu.itb.read_misses 0 # DTB read misses
388 system.cpu.itb.write_hits 0 # DTB write hits
389 system.cpu.itb.write_misses 0 # DTB write misses
390 system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
391 system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
392 system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
393 system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
394 system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
395 system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
396 system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
397 system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
398 system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
399 system.cpu.itb.read_accesses 0 # DTB read accesses
400 system.cpu.itb.write_accesses 0 # DTB write accesses
401 system.cpu.itb.inst_accesses 0 # ITB inst accesses
402 system.cpu.itb.hits 0 # DTB hits
403 system.cpu.itb.misses 0 # DTB misses
404 system.cpu.itb.accesses 0 # DTB accesses
405 system.cpu.workload.num_syscalls 442 # Number of system calls
406 system.cpu.numCycles 116406582 # number of cpu cycles simulated
407 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
408 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
409 system.cpu.fetch.icacheStallCycles 748963 # Number of cycles fetch is stalled on an Icache miss
410 system.cpu.fetch.Insts 134993544 # Number of instructions fetch has processed
411 system.cpu.fetch.Branches 28259243 # Number of branches that fetch encountered
412 system.cpu.fetch.predictedBranches 11861190 # Number of branches that fetch has predicted taken
413 system.cpu.fetch.Cycles 114762985 # Number of cycles fetch has run and was not squashing or blocked
414 system.cpu.fetch.SquashCycles 1679231 # Number of cycles fetch has spent squashing
415 system.cpu.fetch.MiscStallCycles 934 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
416 system.cpu.fetch.IcacheWaitRetryStallCycles 807 # Number of stall cycles due to full MSHR
417 system.cpu.fetch.CacheLines 32304048 # Number of cache lines fetched
418 system.cpu.fetch.IcacheSquashes 578 # Number of outstanding Icache misses that were squashed
419 system.cpu.fetch.rateDist::samples 116353304 # Number of instructions fetched each cycle (Total)
420 system.cpu.fetch.rateDist::mean 1.165458 # Number of instructions fetched each cycle (Total)
421 system.cpu.fetch.rateDist::stdev 1.319046 # Number of instructions fetched each cycle (Total)
422 system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
423 system.cpu.fetch.rateDist::0 58781536 50.52% 50.52% # Number of instructions fetched each cycle (Total)
424 system.cpu.fetch.rateDist::1 13944543 11.98% 62.50% # Number of instructions fetched each cycle (Total)
425 system.cpu.fetch.rateDist::2 9221339 7.93% 70.43% # Number of instructions fetched each cycle (Total)
426 system.cpu.fetch.rateDist::3 34405886 29.57% 100.00% # Number of instructions fetched each cycle (Total)
427 system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
428 system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
429 system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
430 system.cpu.fetch.rateDist::total 116353304 # Number of instructions fetched each cycle (Total)
431 system.cpu.fetch.branchRate 0.242763 # Number of branch fetches per cycle
432 system.cpu.fetch.rate 1.159673 # Number of inst fetches per cycle
433 system.cpu.decode.IdleCycles 8844047 # Number of cycles decode is idle
434 system.cpu.decode.BlockedCycles 64088450 # Number of cycles decode is blocked
435 system.cpu.decode.RunCycles 33032847 # Number of cycles decode is running
436 system.cpu.decode.UnblockCycles 9560591 # Number of cycles decode is unblocking
437 system.cpu.decode.SquashCycles 827369 # Number of cycles decode is squashing
438 system.cpu.decode.BranchResolved 4101287 # Number of times decode resolved a branch
439 system.cpu.decode.BranchMispred 12347 # Number of times decode detected a branch misprediction
440 system.cpu.decode.DecodedInsts 114434695 # Number of instructions handled by decode
441 system.cpu.decode.SquashedInsts 1995559 # Number of squashed instructions handled by decode
442 system.cpu.rename.SquashCycles 827369 # Number of cycles rename is squashing
443 system.cpu.rename.IdleCycles 15306268 # Number of cycles rename is idle
444 system.cpu.rename.BlockCycles 49839660 # Number of cycles rename is blocking
445 system.cpu.rename.serializeStallCycles 109196 # count of cycles rename stalled for serializing inst
446 system.cpu.rename.RunCycles 35408210 # Number of cycles rename is running
447 system.cpu.rename.UnblockCycles 14862601 # Number of cycles rename is unblocking
448 system.cpu.rename.RenamedInsts 110902627 # Number of instructions processed by rename
449 system.cpu.rename.SquashedInsts 1415209 # Number of squashed instructions processed by rename
450 system.cpu.rename.ROBFullEvents 11132813 # Number of times rename has blocked due to ROB full
451 system.cpu.rename.IQFullEvents 1143128 # Number of times rename has blocked due to IQ full
452 system.cpu.rename.LQFullEvents 1515839 # Number of times rename has blocked due to LQ full
453 system.cpu.rename.SQFullEvents 570040 # Number of times rename has blocked due to SQ full
454 system.cpu.rename.RenamedOperands 129962079 # Number of destination operands rename has renamed
455 system.cpu.rename.RenameLookups 483289738 # Number of register rename lookups that rename has made
456 system.cpu.rename.int_rename_lookups 119478423 # Number of integer rename lookups
457 system.cpu.rename.fp_rename_lookups 422 # Number of floating rename lookups
458 system.cpu.rename.CommittedMaps 107312919 # Number of HB maps that are committed
459 system.cpu.rename.UndoneMaps 22649160 # Number of HB maps that are undone due to squashing
460 system.cpu.rename.serializingInsts 4363 # count of serializing insts renamed
461 system.cpu.rename.tempSerializingInsts 4358 # count of temporary serializing insts renamed
462 system.cpu.rename.skidInsts 21571738 # count of insts added to the skid buffer
463 system.cpu.memDep0.insertedLoads 26814245 # Number of loads inserted to the mem dependence unit.
464 system.cpu.memDep0.insertedStores 5349583 # Number of stores inserted to the mem dependence unit.
465 system.cpu.memDep0.conflictingLoads 611820 # Number of conflicting loads.
466 system.cpu.memDep0.conflictingStores 348925 # Number of conflicting stores.
467 system.cpu.iq.iqInstsAdded 109694682 # Number of instructions added to the IQ (excludes non-spec)
468 system.cpu.iq.iqNonSpecInstsAdded 8246 # Number of non-speculative instructions added to the IQ
469 system.cpu.iq.iqInstsIssued 101389793 # Number of instructions issued
470 system.cpu.iq.iqSquashedInstsIssued 1073874 # Number of squashed instructions issued
471 system.cpu.iq.iqSquashedInstsExamined 18661898 # Number of squashed instructions iterated over during squash; mainly for profiling
472 system.cpu.iq.iqSquashedOperandsExamined 41702987 # Number of squashed operands that are examined and possibly removed from graph
473 system.cpu.iq.iqSquashedNonSpecRemoved 28 # Number of squashed non-spec instructions that were removed
474 system.cpu.iq.issued_per_cycle::samples 116353304 # Number of insts issued each cycle
475 system.cpu.iq.issued_per_cycle::mean 0.871396 # Number of insts issued each cycle
476 system.cpu.iq.issued_per_cycle::stdev 0.988581 # Number of insts issued each cycle
477 system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
478 system.cpu.iq.issued_per_cycle::0 54657362 46.98% 46.98% # Number of insts issued each cycle
479 system.cpu.iq.issued_per_cycle::1 31448211 27.03% 74.00% # Number of insts issued each cycle
480 system.cpu.iq.issued_per_cycle::2 21997386 18.91% 92.91% # Number of insts issued each cycle
481 system.cpu.iq.issued_per_cycle::3 7054887 6.06% 98.97% # Number of insts issued each cycle
482 system.cpu.iq.issued_per_cycle::4 1195141 1.03% 100.00% # Number of insts issued each cycle
483 system.cpu.iq.issued_per_cycle::5 317 0.00% 100.00% # Number of insts issued each cycle
484 system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
485 system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
486 system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
487 system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
488 system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
489 system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
490 system.cpu.iq.issued_per_cycle::total 116353304 # Number of insts issued each cycle
491 system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
492 system.cpu.iq.fu_full::IntAlu 9796132 48.71% 48.71% # attempts to use FU when none available
493 system.cpu.iq.fu_full::IntMult 50 0.00% 48.71% # attempts to use FU when none available
494 system.cpu.iq.fu_full::IntDiv 0 0.00% 48.71% # attempts to use FU when none available
495 system.cpu.iq.fu_full::FloatAdd 0 0.00% 48.71% # attempts to use FU when none available
496 system.cpu.iq.fu_full::FloatCmp 0 0.00% 48.71% # attempts to use FU when none available
497 system.cpu.iq.fu_full::FloatCvt 0 0.00% 48.71% # attempts to use FU when none available
498 system.cpu.iq.fu_full::FloatMult 0 0.00% 48.71% # attempts to use FU when none available
499 system.cpu.iq.fu_full::FloatDiv 0 0.00% 48.71% # attempts to use FU when none available
500 system.cpu.iq.fu_full::FloatSqrt 0 0.00% 48.71% # attempts to use FU when none available
501 system.cpu.iq.fu_full::SimdAdd 0 0.00% 48.71% # attempts to use FU when none available
502 system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 48.71% # attempts to use FU when none available
503 system.cpu.iq.fu_full::SimdAlu 0 0.00% 48.71% # attempts to use FU when none available
504 system.cpu.iq.fu_full::SimdCmp 0 0.00% 48.71% # attempts to use FU when none available
505 system.cpu.iq.fu_full::SimdCvt 0 0.00% 48.71% # attempts to use FU when none available
506 system.cpu.iq.fu_full::SimdMisc 0 0.00% 48.71% # attempts to use FU when none available
507 system.cpu.iq.fu_full::SimdMult 0 0.00% 48.71% # attempts to use FU when none available
508 system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 48.71% # attempts to use FU when none available
509 system.cpu.iq.fu_full::SimdShift 0 0.00% 48.71% # attempts to use FU when none available
510 system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 48.71% # attempts to use FU when none available
511 system.cpu.iq.fu_full::SimdSqrt 0 0.00% 48.71% # attempts to use FU when none available
512 system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 48.71% # attempts to use FU when none available
513 system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 48.71% # attempts to use FU when none available
514 system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 48.71% # attempts to use FU when none available
515 system.cpu.iq.fu_full::SimdFloatCvt 12 0.00% 48.71% # attempts to use FU when none available
516 system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 48.71% # attempts to use FU when none available
517 system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 48.71% # attempts to use FU when none available
518 system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 48.71% # attempts to use FU when none available
519 system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 48.71% # attempts to use FU when none available
520 system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 48.71% # attempts to use FU when none available
521 system.cpu.iq.fu_full::MemRead 9605412 47.76% 96.48% # attempts to use FU when none available
522 system.cpu.iq.fu_full::MemWrite 708293 3.52% 100.00% # attempts to use FU when none available
523 system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
524 system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
525 system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
526 system.cpu.iq.FU_type_0::IntAlu 71985396 71.00% 71.00% # Type of FU issued
527 system.cpu.iq.FU_type_0::IntMult 10710 0.01% 71.01% # Type of FU issued
528 system.cpu.iq.FU_type_0::IntDiv 0 0.00% 71.01% # Type of FU issued
529 system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 71.01% # Type of FU issued
530 system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 71.01% # Type of FU issued
531 system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 71.01% # Type of FU issued
532 system.cpu.iq.FU_type_0::FloatMult 0 0.00% 71.01% # Type of FU issued
533 system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 71.01% # Type of FU issued
534 system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 71.01% # Type of FU issued
535 system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 71.01% # Type of FU issued
536 system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 71.01% # Type of FU issued
537 system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 71.01% # Type of FU issued
538 system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 71.01% # Type of FU issued
539 system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 71.01% # Type of FU issued
540 system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 71.01% # Type of FU issued
541 system.cpu.iq.FU_type_0::SimdMult 0 0.00% 71.01% # Type of FU issued
542 system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 71.01% # Type of FU issued
543 system.cpu.iq.FU_type_0::SimdShift 0 0.00% 71.01% # Type of FU issued
544 system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 71.01% # Type of FU issued
545 system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 71.01% # Type of FU issued
546 system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 71.01% # Type of FU issued
547 system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 71.01% # Type of FU issued
548 system.cpu.iq.FU_type_0::SimdFloatCmp 2 0.00% 71.01% # Type of FU issued
549 system.cpu.iq.FU_type_0::SimdFloatCvt 56 0.00% 71.01% # Type of FU issued
550 system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 71.01% # Type of FU issued
551 system.cpu.iq.FU_type_0::SimdFloatMisc 123 0.00% 71.01% # Type of FU issued
552 system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 71.01% # Type of FU issued
553 system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 71.01% # Type of FU issued
554 system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 71.01% # Type of FU issued
555 system.cpu.iq.FU_type_0::MemRead 24344165 24.01% 95.02% # Type of FU issued
556 system.cpu.iq.FU_type_0::MemWrite 5049339 4.98% 100.00% # Type of FU issued
557 system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
558 system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
559 system.cpu.iq.FU_type_0::total 101389793 # Type of FU issued
560 system.cpu.iq.rate 0.870997 # Inst issue rate
561 system.cpu.iq.fu_busy_cnt 20109899 # FU busy when requested
562 system.cpu.iq.fu_busy_rate 0.198342 # FU busy rate (busy events/executed inst)
563 system.cpu.iq.int_inst_queue_reads 340316208 # Number of integer instruction queue reads
564 system.cpu.iq.int_inst_queue_writes 128365476 # Number of integer instruction queue writes
565 system.cpu.iq.int_inst_queue_wakeup_accesses 99625945 # Number of integer instruction queue wakeup accesses
566 system.cpu.iq.fp_inst_queue_reads 455 # Number of floating instruction queue reads
567 system.cpu.iq.fp_inst_queue_writes 608 # Number of floating instruction queue writes
568 system.cpu.iq.fp_inst_queue_wakeup_accesses 113 # Number of floating instruction queue wakeup accesses
569 system.cpu.iq.int_alu_accesses 121499455 # Number of integer alu accesses
570 system.cpu.iq.fp_alu_accesses 237 # Number of floating point alu accesses
571 system.cpu.iew.lsq.thread0.forwLoads 282715 # Number of loads that had data forwarded from stores
572 system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
573 system.cpu.iew.lsq.thread0.squashedLoads 4338334 # Number of loads squashed
574 system.cpu.iew.lsq.thread0.ignoredResponses 1512 # Number of memory responses ignored because the instruction is squashed
575 system.cpu.iew.lsq.thread0.memOrderViolation 1293 # Number of memory ordering violations
576 system.cpu.iew.lsq.thread0.squashedStores 604739 # Number of stores squashed
577 system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
578 system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
579 system.cpu.iew.lsq.thread0.rescheduledLoads 7563 # Number of loads that were rescheduled
580 system.cpu.iew.lsq.thread0.cacheBlocked 130432 # Number of times an access to memory failed due to the cache being blocked
581 system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
582 system.cpu.iew.iewSquashCycles 827369 # Number of cycles IEW is squashing
583 system.cpu.iew.iewBlockCycles 8116840 # Number of cycles IEW is blocking
584 system.cpu.iew.iewUnblockCycles 661308 # Number of cycles IEW is unblocking
585 system.cpu.iew.iewDispatchedInsts 109715594 # Number of instructions dispatched to IQ
586 system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
587 system.cpu.iew.iewDispLoadInsts 26814245 # Number of dispatched load instructions
588 system.cpu.iew.iewDispStoreInsts 5349583 # Number of dispatched store instructions
589 system.cpu.iew.iewDispNonSpecInsts 4358 # Number of dispatched non-speculative instructions
590 system.cpu.iew.iewIQFullEvents 178503 # Number of times the IQ has become full, causing a stall
591 system.cpu.iew.iewLSQFullEvents 319361 # Number of times the LSQ has become full, causing a stall
592 system.cpu.iew.memOrderViolationEvents 1293 # Number of memory order violations
593 system.cpu.iew.predictedTakenIncorrect 436568 # Number of branches that were predicted taken incorrectly
594 system.cpu.iew.predictedNotTakenIncorrect 412973 # Number of branches that were predicted not taken incorrectly
595 system.cpu.iew.branchMispredicts 849541 # Number of branch mispredicts detected at execute
596 system.cpu.iew.iewExecutedInsts 100128175 # Number of executed instructions
597 system.cpu.iew.iewExecLoadInsts 23807340 # Number of load instructions executed
598 system.cpu.iew.iewExecSquashedInsts 1261618 # Number of squashed instructions skipped in execute
599 system.cpu.iew.exec_swp 0 # number of swp insts executed
600 system.cpu.iew.exec_nop 12666 # number of nop insts executed
601 system.cpu.iew.exec_refs 28725211 # number of memory reference insts executed
602 system.cpu.iew.exec_branches 20624854 # Number of branches executed
603 system.cpu.iew.exec_stores 4917871 # Number of stores executed
604 system.cpu.iew.exec_rate 0.860159 # Inst execution rate
605 system.cpu.iew.wb_sent 99711063 # cumulative count of insts sent to commit
606 system.cpu.iew.wb_count 99626058 # cumulative count of insts written-back
607 system.cpu.iew.wb_producers 59706030 # num instructions producing a value
608 system.cpu.iew.wb_consumers 95562635 # num instructions consuming a value
609 system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
610 system.cpu.iew.wb_rate 0.855846 # insts written-back per cycle
611 system.cpu.iew.wb_fanout 0.624784 # average fanout of values written-back
612 system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
613 system.cpu.commit.commitSquashedInsts 17389920 # The number of squashed insts skipped by commit
614 system.cpu.commit.commitNonSpecStalls 8218 # The number of times commit has been forced to stall to communicate backwards
615 system.cpu.commit.branchMispredicts 825718 # The number of times a branch was mispredicted
616 system.cpu.commit.committed_per_cycle::samples 113660326 # Number of insts commited each cycle
617 system.cpu.commit.committed_per_cycle::mean 0.801103 # Number of insts commited each cycle
618 system.cpu.commit.committed_per_cycle::stdev 1.737104 # Number of insts commited each cycle
619 system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
620 system.cpu.commit.committed_per_cycle::0 77212273 67.93% 67.93% # Number of insts commited each cycle
621 system.cpu.commit.committed_per_cycle::1 18641375 16.40% 84.33% # Number of insts commited each cycle
622 system.cpu.commit.committed_per_cycle::2 7152706 6.29% 90.63% # Number of insts commited each cycle
623 system.cpu.commit.committed_per_cycle::3 3462873 3.05% 93.67% # Number of insts commited each cycle
624 system.cpu.commit.committed_per_cycle::4 1652643 1.45% 95.13% # Number of insts commited each cycle
625 system.cpu.commit.committed_per_cycle::5 524647 0.46% 95.59% # Number of insts commited each cycle
626 system.cpu.commit.committed_per_cycle::6 723706 0.64% 96.23% # Number of insts commited each cycle
627 system.cpu.commit.committed_per_cycle::7 178634 0.16% 96.38% # Number of insts commited each cycle
628 system.cpu.commit.committed_per_cycle::8 4111469 3.62% 100.00% # Number of insts commited each cycle
629 system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
630 system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
631 system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
632 system.cpu.commit.committed_per_cycle::total 113660326 # Number of insts commited each cycle
633 system.cpu.commit.committedInsts 90602408 # Number of instructions committed
634 system.cpu.commit.committedOps 91053639 # Number of ops (including micro ops) committed
635 system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
636 system.cpu.commit.refs 27220755 # Number of memory references committed
637 system.cpu.commit.loads 22475911 # Number of loads committed
638 system.cpu.commit.membars 3888 # Number of memory barriers committed
639 system.cpu.commit.branches 18732305 # Number of branches committed
640 system.cpu.commit.fp_insts 48 # Number of committed floating point instructions.
641 system.cpu.commit.int_insts 72326352 # Number of committed integer instructions.
642 system.cpu.commit.function_calls 56148 # Number of function calls committed.
643 system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
644 system.cpu.commit.op_class_0::IntAlu 63822387 70.09% 70.09% # Class of committed instruction
645 system.cpu.commit.op_class_0::IntMult 10474 0.01% 70.10% # Class of committed instruction
646 system.cpu.commit.op_class_0::IntDiv 0 0.00% 70.10% # Class of committed instruction
647 system.cpu.commit.op_class_0::FloatAdd 0 0.00% 70.10% # Class of committed instruction
648 system.cpu.commit.op_class_0::FloatCmp 0 0.00% 70.10% # Class of committed instruction
649 system.cpu.commit.op_class_0::FloatCvt 0 0.00% 70.10% # Class of committed instruction
650 system.cpu.commit.op_class_0::FloatMult 0 0.00% 70.10% # Class of committed instruction
651 system.cpu.commit.op_class_0::FloatDiv 0 0.00% 70.10% # Class of committed instruction
652 system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 70.10% # Class of committed instruction
653 system.cpu.commit.op_class_0::SimdAdd 0 0.00% 70.10% # Class of committed instruction
654 system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 70.10% # Class of committed instruction
655 system.cpu.commit.op_class_0::SimdAlu 0 0.00% 70.10% # Class of committed instruction
656 system.cpu.commit.op_class_0::SimdCmp 0 0.00% 70.10% # Class of committed instruction
657 system.cpu.commit.op_class_0::SimdCvt 0 0.00% 70.10% # Class of committed instruction
658 system.cpu.commit.op_class_0::SimdMisc 0 0.00% 70.10% # Class of committed instruction
659 system.cpu.commit.op_class_0::SimdMult 0 0.00% 70.10% # Class of committed instruction
660 system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 70.10% # Class of committed instruction
661 system.cpu.commit.op_class_0::SimdShift 0 0.00% 70.10% # Class of committed instruction
662 system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 70.10% # Class of committed instruction
663 system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 70.10% # Class of committed instruction
664 system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 70.10% # Class of committed instruction
665 system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 70.10% # Class of committed instruction
666 system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 70.10% # Class of committed instruction
667 system.cpu.commit.op_class_0::SimdFloatCvt 6 0.00% 70.10% # Class of committed instruction
668 system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 70.10% # Class of committed instruction
669 system.cpu.commit.op_class_0::SimdFloatMisc 15 0.00% 70.10% # Class of committed instruction
670 system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 70.10% # Class of committed instruction
671 system.cpu.commit.op_class_0::SimdFloatMultAcc 2 0.00% 70.10% # Class of committed instruction
672 system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.10% # Class of committed instruction
673 system.cpu.commit.op_class_0::MemRead 22475911 24.68% 94.79% # Class of committed instruction
674 system.cpu.commit.op_class_0::MemWrite 4744844 5.21% 100.00% # Class of committed instruction
675 system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
676 system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
677 system.cpu.commit.op_class_0::total 91053639 # Class of committed instruction
678 system.cpu.commit.bw_lim_events 4111469 # number cycles where commit BW limit reached
679 system.cpu.rob.rob_reads 217986682 # The number of ROB reads
680 system.cpu.rob.rob_writes 219580711 # The number of ROB writes
681 system.cpu.timesIdled 588 # Number of times that the entire CPU went into an idle state and unscheduled itself
682 system.cpu.idleCycles 53278 # Total number of cycles that the CPU has spent unscheduled due to idling
683 system.cpu.committedInsts 90589799 # Number of Instructions Simulated
684 system.cpu.committedOps 91041030 # Number of Ops (including micro ops) Simulated
685 system.cpu.cpi 1.284986 # CPI: Cycles Per Instruction
686 system.cpu.cpi_total 1.284986 # CPI: Total CPI of All Threads
687 system.cpu.ipc 0.778219 # IPC: Instructions Per Cycle
688 system.cpu.ipc_total 0.778219 # IPC: Total IPC of All Threads
689 system.cpu.int_regfile_reads 108112805 # number of integer regfile reads
690 system.cpu.int_regfile_writes 58701882 # number of integer regfile writes
691 system.cpu.fp_regfile_reads 58 # number of floating regfile reads
692 system.cpu.fp_regfile_writes 93 # number of floating regfile writes
693 system.cpu.cc_regfile_reads 369068913 # number of cc regfile reads
694 system.cpu.cc_regfile_writes 58692415 # number of cc regfile writes
695 system.cpu.misc_regfile_reads 28415527 # number of misc regfile reads
696 system.cpu.misc_regfile_writes 7784 # number of misc regfile writes
697 system.cpu.dcache.tags.replacements 5469565 # number of replacements
698 system.cpu.dcache.tags.tagsinuse 511.787779 # Cycle average of tags in use
699 system.cpu.dcache.tags.total_refs 18297385 # Total number of references to valid blocks.
700 system.cpu.dcache.tags.sampled_refs 5470077 # Sample count of references to valid blocks.
701 system.cpu.dcache.tags.avg_refs 3.344996 # Average number of references to valid blocks.
702 system.cpu.dcache.tags.warmup_cycle 35255000 # Cycle when the warmup percentage was hit.
703 system.cpu.dcache.tags.occ_blocks::cpu.data 511.787779 # Average occupied blocks per requestor
704 system.cpu.dcache.tags.occ_percent::cpu.data 0.999586 # Average percentage of cache occupancy
705 system.cpu.dcache.tags.occ_percent::total 0.999586 # Average percentage of cache occupancy
706 system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
707 system.cpu.dcache.tags.age_task_id_blocks_1024::0 341 # Occupied blocks per task id
708 system.cpu.dcache.tags.age_task_id_blocks_1024::1 171 # Occupied blocks per task id
709 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
710 system.cpu.dcache.tags.tag_accesses 61924887 # Number of tag accesses
711 system.cpu.dcache.tags.data_accesses 61924887 # Number of data accesses
712 system.cpu.dcache.ReadReq_hits::cpu.data 13934133 # number of ReadReq hits
713 system.cpu.dcache.ReadReq_hits::total 13934133 # number of ReadReq hits
714 system.cpu.dcache.WriteReq_hits::cpu.data 4354955 # number of WriteReq hits
715 system.cpu.dcache.WriteReq_hits::total 4354955 # number of WriteReq hits
716 system.cpu.dcache.SoftPFReq_hits::cpu.data 522 # number of SoftPFReq hits
717 system.cpu.dcache.SoftPFReq_hits::total 522 # number of SoftPFReq hits
718 system.cpu.dcache.LoadLockedReq_hits::cpu.data 3872 # number of LoadLockedReq hits
719 system.cpu.dcache.LoadLockedReq_hits::total 3872 # number of LoadLockedReq hits
720 system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits
721 system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits
722 system.cpu.dcache.demand_hits::cpu.data 18289088 # number of demand (read+write) hits
723 system.cpu.dcache.demand_hits::total 18289088 # number of demand (read+write) hits
724 system.cpu.dcache.overall_hits::cpu.data 18289610 # number of overall hits
725 system.cpu.dcache.overall_hits::total 18289610 # number of overall hits
726 system.cpu.dcache.ReadReq_misses::cpu.data 9549988 # number of ReadReq misses
727 system.cpu.dcache.ReadReq_misses::total 9549988 # number of ReadReq misses
728 system.cpu.dcache.WriteReq_misses::cpu.data 380026 # number of WriteReq misses
729 system.cpu.dcache.WriteReq_misses::total 380026 # number of WriteReq misses
730 system.cpu.dcache.SoftPFReq_misses::cpu.data 7 # number of SoftPFReq misses
731 system.cpu.dcache.SoftPFReq_misses::total 7 # number of SoftPFReq misses
732 system.cpu.dcache.LoadLockedReq_misses::cpu.data 15 # number of LoadLockedReq misses
733 system.cpu.dcache.LoadLockedReq_misses::total 15 # number of LoadLockedReq misses
734 system.cpu.dcache.demand_misses::cpu.data 9930014 # number of demand (read+write) misses
735 system.cpu.dcache.demand_misses::total 9930014 # number of demand (read+write) misses
736 system.cpu.dcache.overall_misses::cpu.data 9930021 # number of overall misses
737 system.cpu.dcache.overall_misses::total 9930021 # number of overall misses
738 system.cpu.dcache.ReadReq_miss_latency::cpu.data 88444420972 # number of ReadReq miss cycles
739 system.cpu.dcache.ReadReq_miss_latency::total 88444420972 # number of ReadReq miss cycles
740 system.cpu.dcache.WriteReq_miss_latency::cpu.data 3962617493 # number of WriteReq miss cycles
741 system.cpu.dcache.WriteReq_miss_latency::total 3962617493 # number of WriteReq miss cycles
742 system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 297000 # number of LoadLockedReq miss cycles
743 system.cpu.dcache.LoadLockedReq_miss_latency::total 297000 # number of LoadLockedReq miss cycles
744 system.cpu.dcache.demand_miss_latency::cpu.data 92407038465 # number of demand (read+write) miss cycles
745 system.cpu.dcache.demand_miss_latency::total 92407038465 # number of demand (read+write) miss cycles
746 system.cpu.dcache.overall_miss_latency::cpu.data 92407038465 # number of overall miss cycles
747 system.cpu.dcache.overall_miss_latency::total 92407038465 # number of overall miss cycles
748 system.cpu.dcache.ReadReq_accesses::cpu.data 23484121 # number of ReadReq accesses(hits+misses)
749 system.cpu.dcache.ReadReq_accesses::total 23484121 # number of ReadReq accesses(hits+misses)
750 system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses)
751 system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses)
752 system.cpu.dcache.SoftPFReq_accesses::cpu.data 529 # number of SoftPFReq accesses(hits+misses)
753 system.cpu.dcache.SoftPFReq_accesses::total 529 # number of SoftPFReq accesses(hits+misses)
754 system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 # number of LoadLockedReq accesses(hits+misses)
755 system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses)
756 system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses)
757 system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses)
758 system.cpu.dcache.demand_accesses::cpu.data 28219102 # number of demand (read+write) accesses
759 system.cpu.dcache.demand_accesses::total 28219102 # number of demand (read+write) accesses
760 system.cpu.dcache.overall_accesses::cpu.data 28219631 # number of overall (read+write) accesses
761 system.cpu.dcache.overall_accesses::total 28219631 # number of overall (read+write) accesses
762 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.406657 # miss rate for ReadReq accesses
763 system.cpu.dcache.ReadReq_miss_rate::total 0.406657 # miss rate for ReadReq accesses
764 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.080259 # miss rate for WriteReq accesses
765 system.cpu.dcache.WriteReq_miss_rate::total 0.080259 # miss rate for WriteReq accesses
766 system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.013233 # miss rate for SoftPFReq accesses
767 system.cpu.dcache.SoftPFReq_miss_rate::total 0.013233 # miss rate for SoftPFReq accesses
768 system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.003859 # miss rate for LoadLockedReq accesses
769 system.cpu.dcache.LoadLockedReq_miss_rate::total 0.003859 # miss rate for LoadLockedReq accesses
770 system.cpu.dcache.demand_miss_rate::cpu.data 0.351890 # miss rate for demand accesses
771 system.cpu.dcache.demand_miss_rate::total 0.351890 # miss rate for demand accesses
772 system.cpu.dcache.overall_miss_rate::cpu.data 0.351883 # miss rate for overall accesses
773 system.cpu.dcache.overall_miss_rate::total 0.351883 # miss rate for overall accesses
774 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9261.207550 # average ReadReq miss latency
775 system.cpu.dcache.ReadReq_avg_miss_latency::total 9261.207550 # average ReadReq miss latency
776 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10427.227329 # average WriteReq miss latency
777 system.cpu.dcache.WriteReq_avg_miss_latency::total 10427.227329 # average WriteReq miss latency
778 system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 19800 # average LoadLockedReq miss latency
779 system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 19800 # average LoadLockedReq miss latency
780 system.cpu.dcache.demand_avg_miss_latency::cpu.data 9305.831640 # average overall miss latency
781 system.cpu.dcache.demand_avg_miss_latency::total 9305.831640 # average overall miss latency
782 system.cpu.dcache.overall_avg_miss_latency::cpu.data 9305.825080 # average overall miss latency
783 system.cpu.dcache.overall_avg_miss_latency::total 9305.825080 # average overall miss latency
784 system.cpu.dcache.blocked_cycles::no_mshrs 306116 # number of cycles access was blocked
785 system.cpu.dcache.blocked_cycles::no_targets 36058 # number of cycles access was blocked
786 system.cpu.dcache.blocked::no_mshrs 120736 # number of cycles access was blocked
787 system.cpu.dcache.blocked::no_targets 2278 # number of cycles access was blocked
788 system.cpu.dcache.avg_blocked_cycles::no_mshrs 2.535416 # average number of cycles each access was blocked
789 system.cpu.dcache.avg_blocked_cycles::no_targets 15.828797 # average number of cycles each access was blocked
790 system.cpu.dcache.fast_writes 0 # number of fast writes performed
791 system.cpu.dcache.cache_copies 0 # number of cache copies performed
792 system.cpu.dcache.writebacks::writebacks 5437967 # number of writebacks
793 system.cpu.dcache.writebacks::total 5437967 # number of writebacks
794 system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4312992 # number of ReadReq MSHR hits
795 system.cpu.dcache.ReadReq_mshr_hits::total 4312992 # number of ReadReq MSHR hits
796 system.cpu.dcache.WriteReq_mshr_hits::cpu.data 146947 # number of WriteReq MSHR hits
797 system.cpu.dcache.WriteReq_mshr_hits::total 146947 # number of WriteReq MSHR hits
798 system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 15 # number of LoadLockedReq MSHR hits
799 system.cpu.dcache.LoadLockedReq_mshr_hits::total 15 # number of LoadLockedReq MSHR hits
800 system.cpu.dcache.demand_mshr_hits::cpu.data 4459939 # number of demand (read+write) MSHR hits
801 system.cpu.dcache.demand_mshr_hits::total 4459939 # number of demand (read+write) MSHR hits
802 system.cpu.dcache.overall_mshr_hits::cpu.data 4459939 # number of overall MSHR hits
803 system.cpu.dcache.overall_mshr_hits::total 4459939 # number of overall MSHR hits
804 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5236996 # number of ReadReq MSHR misses
805 system.cpu.dcache.ReadReq_mshr_misses::total 5236996 # number of ReadReq MSHR misses
806 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 233079 # number of WriteReq MSHR misses
807 system.cpu.dcache.WriteReq_mshr_misses::total 233079 # number of WriteReq MSHR misses
808 system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 4 # number of SoftPFReq MSHR misses
809 system.cpu.dcache.SoftPFReq_mshr_misses::total 4 # number of SoftPFReq MSHR misses
810 system.cpu.dcache.demand_mshr_misses::cpu.data 5470075 # number of demand (read+write) MSHR misses
811 system.cpu.dcache.demand_mshr_misses::total 5470075 # number of demand (read+write) MSHR misses
812 system.cpu.dcache.overall_mshr_misses::cpu.data 5470079 # number of overall MSHR misses
813 system.cpu.dcache.overall_mshr_misses::total 5470079 # number of overall MSHR misses
814 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 40520727758 # number of ReadReq MSHR miss cycles
815 system.cpu.dcache.ReadReq_mshr_miss_latency::total 40520727758 # number of ReadReq MSHR miss cycles
816 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2294964437 # number of WriteReq MSHR miss cycles
817 system.cpu.dcache.WriteReq_mshr_miss_latency::total 2294964437 # number of WriteReq MSHR miss cycles
818 system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 213000 # number of SoftPFReq MSHR miss cycles
819 system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 213000 # number of SoftPFReq MSHR miss cycles
820 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 42815692195 # number of demand (read+write) MSHR miss cycles
821 system.cpu.dcache.demand_mshr_miss_latency::total 42815692195 # number of demand (read+write) MSHR miss cycles
822 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 42815905195 # number of overall MSHR miss cycles
823 system.cpu.dcache.overall_mshr_miss_latency::total 42815905195 # number of overall MSHR miss cycles
824 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.223002 # mshr miss rate for ReadReq accesses
825 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.223002 # mshr miss rate for ReadReq accesses
826 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049225 # mshr miss rate for WriteReq accesses
827 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049225 # mshr miss rate for WriteReq accesses
828 system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.007561 # mshr miss rate for SoftPFReq accesses
829 system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.007561 # mshr miss rate for SoftPFReq accesses
830 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.193843 # mshr miss rate for demand accesses
831 system.cpu.dcache.demand_mshr_miss_rate::total 0.193843 # mshr miss rate for demand accesses
832 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.193839 # mshr miss rate for overall accesses
833 system.cpu.dcache.overall_mshr_miss_rate::total 0.193839 # mshr miss rate for overall accesses
834 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7737.399028 # average ReadReq mshr miss latency
835 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 7737.399028 # average ReadReq mshr miss latency
836 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 9846.294334 # average WriteReq mshr miss latency
837 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 9846.294334 # average WriteReq mshr miss latency
838 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53250 # average SoftPFReq mshr miss latency
839 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53250 # average SoftPFReq mshr miss latency
840 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 7827.258711 # average overall mshr miss latency
841 system.cpu.dcache.demand_avg_mshr_miss_latency::total 7827.258711 # average overall mshr miss latency
842 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 7827.291927 # average overall mshr miss latency
843 system.cpu.dcache.overall_avg_mshr_miss_latency::total 7827.291927 # average overall mshr miss latency
844 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
845 system.cpu.icache.tags.replacements 449 # number of replacements
846 system.cpu.icache.tags.tagsinuse 428.262881 # Cycle average of tags in use
847 system.cpu.icache.tags.total_refs 32302878 # Total number of references to valid blocks.
848 system.cpu.icache.tags.sampled_refs 908 # Sample count of references to valid blocks.
849 system.cpu.icache.tags.avg_refs 35575.856828 # Average number of references to valid blocks.
850 system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
851 system.cpu.icache.tags.occ_blocks::cpu.inst 428.262881 # Average occupied blocks per requestor
852 system.cpu.icache.tags.occ_percent::cpu.inst 0.836451 # Average percentage of cache occupancy
853 system.cpu.icache.tags.occ_percent::total 0.836451 # Average percentage of cache occupancy
854 system.cpu.icache.tags.occ_task_id_blocks::1024 459 # Occupied blocks per task id
855 system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id
856 system.cpu.icache.tags.age_task_id_blocks_1024::2 51 # Occupied blocks per task id
857 system.cpu.icache.tags.age_task_id_blocks_1024::3 21 # Occupied blocks per task id
858 system.cpu.icache.tags.age_task_id_blocks_1024::4 332 # Occupied blocks per task id
859 system.cpu.icache.tags.occ_task_id_percent::1024 0.896484 # Percentage of cache occupancy per task id
860 system.cpu.icache.tags.tag_accesses 64608978 # Number of tag accesses
861 system.cpu.icache.tags.data_accesses 64608978 # Number of data accesses
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863 system.cpu.icache.ReadReq_hits::total 32302878 # number of ReadReq hits
864 system.cpu.icache.demand_hits::cpu.inst 32302878 # number of demand (read+write) hits
865 system.cpu.icache.demand_hits::total 32302878 # number of demand (read+write) hits
866 system.cpu.icache.overall_hits::cpu.inst 32302878 # number of overall hits
867 system.cpu.icache.overall_hits::total 32302878 # number of overall hits
868 system.cpu.icache.ReadReq_misses::cpu.inst 1157 # number of ReadReq misses
869 system.cpu.icache.ReadReq_misses::total 1157 # number of ReadReq misses
870 system.cpu.icache.demand_misses::cpu.inst 1157 # number of demand (read+write) misses
871 system.cpu.icache.demand_misses::total 1157 # number of demand (read+write) misses
872 system.cpu.icache.overall_misses::cpu.inst 1157 # number of overall misses
873 system.cpu.icache.overall_misses::total 1157 # number of overall misses
874 system.cpu.icache.ReadReq_miss_latency::cpu.inst 62067238 # number of ReadReq miss cycles
875 system.cpu.icache.ReadReq_miss_latency::total 62067238 # number of ReadReq miss cycles
876 system.cpu.icache.demand_miss_latency::cpu.inst 62067238 # number of demand (read+write) miss cycles
877 system.cpu.icache.demand_miss_latency::total 62067238 # number of demand (read+write) miss cycles
878 system.cpu.icache.overall_miss_latency::cpu.inst 62067238 # number of overall miss cycles
879 system.cpu.icache.overall_miss_latency::total 62067238 # number of overall miss cycles
880 system.cpu.icache.ReadReq_accesses::cpu.inst 32304035 # number of ReadReq accesses(hits+misses)
881 system.cpu.icache.ReadReq_accesses::total 32304035 # number of ReadReq accesses(hits+misses)
882 system.cpu.icache.demand_accesses::cpu.inst 32304035 # number of demand (read+write) accesses
883 system.cpu.icache.demand_accesses::total 32304035 # number of demand (read+write) accesses
884 system.cpu.icache.overall_accesses::cpu.inst 32304035 # number of overall (read+write) accesses
885 system.cpu.icache.overall_accesses::total 32304035 # number of overall (read+write) accesses
886 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000036 # miss rate for ReadReq accesses
887 system.cpu.icache.ReadReq_miss_rate::total 0.000036 # miss rate for ReadReq accesses
888 system.cpu.icache.demand_miss_rate::cpu.inst 0.000036 # miss rate for demand accesses
889 system.cpu.icache.demand_miss_rate::total 0.000036 # miss rate for demand accesses
890 system.cpu.icache.overall_miss_rate::cpu.inst 0.000036 # miss rate for overall accesses
891 system.cpu.icache.overall_miss_rate::total 0.000036 # miss rate for overall accesses
892 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53644.976664 # average ReadReq miss latency
893 system.cpu.icache.ReadReq_avg_miss_latency::total 53644.976664 # average ReadReq miss latency
894 system.cpu.icache.demand_avg_miss_latency::cpu.inst 53644.976664 # average overall miss latency
895 system.cpu.icache.demand_avg_miss_latency::total 53644.976664 # average overall miss latency
896 system.cpu.icache.overall_avg_miss_latency::cpu.inst 53644.976664 # average overall miss latency
897 system.cpu.icache.overall_avg_miss_latency::total 53644.976664 # average overall miss latency
898 system.cpu.icache.blocked_cycles::no_mshrs 18268 # number of cycles access was blocked
899 system.cpu.icache.blocked_cycles::no_targets 134 # number of cycles access was blocked
900 system.cpu.icache.blocked::no_mshrs 226 # number of cycles access was blocked
901 system.cpu.icache.blocked::no_targets 5 # number of cycles access was blocked
902 system.cpu.icache.avg_blocked_cycles::no_mshrs 80.831858 # average number of cycles each access was blocked
903 system.cpu.icache.avg_blocked_cycles::no_targets 26.800000 # average number of cycles each access was blocked
904 system.cpu.icache.fast_writes 0 # number of fast writes performed
905 system.cpu.icache.cache_copies 0 # number of cache copies performed
906 system.cpu.icache.ReadReq_mshr_hits::cpu.inst 249 # number of ReadReq MSHR hits
907 system.cpu.icache.ReadReq_mshr_hits::total 249 # number of ReadReq MSHR hits
908 system.cpu.icache.demand_mshr_hits::cpu.inst 249 # number of demand (read+write) MSHR hits
909 system.cpu.icache.demand_mshr_hits::total 249 # number of demand (read+write) MSHR hits
910 system.cpu.icache.overall_mshr_hits::cpu.inst 249 # number of overall MSHR hits
911 system.cpu.icache.overall_mshr_hits::total 249 # number of overall MSHR hits
912 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 908 # number of ReadReq MSHR misses
913 system.cpu.icache.ReadReq_mshr_misses::total 908 # number of ReadReq MSHR misses
914 system.cpu.icache.demand_mshr_misses::cpu.inst 908 # number of demand (read+write) MSHR misses
915 system.cpu.icache.demand_mshr_misses::total 908 # number of demand (read+write) MSHR misses
916 system.cpu.icache.overall_mshr_misses::cpu.inst 908 # number of overall MSHR misses
917 system.cpu.icache.overall_mshr_misses::total 908 # number of overall MSHR misses
918 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 49773732 # number of ReadReq MSHR miss cycles
919 system.cpu.icache.ReadReq_mshr_miss_latency::total 49773732 # number of ReadReq MSHR miss cycles
920 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 49773732 # number of demand (read+write) MSHR miss cycles
921 system.cpu.icache.demand_mshr_miss_latency::total 49773732 # number of demand (read+write) MSHR miss cycles
922 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 49773732 # number of overall MSHR miss cycles
923 system.cpu.icache.overall_mshr_miss_latency::total 49773732 # number of overall MSHR miss cycles
924 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for ReadReq accesses
925 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000028 # mshr miss rate for ReadReq accesses
926 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for demand accesses
927 system.cpu.icache.demand_mshr_miss_rate::total 0.000028 # mshr miss rate for demand accesses
928 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for overall accesses
929 system.cpu.icache.overall_mshr_miss_rate::total 0.000028 # mshr miss rate for overall accesses
930 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54816.885463 # average ReadReq mshr miss latency
931 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54816.885463 # average ReadReq mshr miss latency
932 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54816.885463 # average overall mshr miss latency
933 system.cpu.icache.demand_avg_mshr_miss_latency::total 54816.885463 # average overall mshr miss latency
934 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54816.885463 # average overall mshr miss latency
935 system.cpu.icache.overall_avg_mshr_miss_latency::total 54816.885463 # average overall mshr miss latency
936 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
937 system.cpu.l2cache.prefetcher.num_hwpf_issued 4492873 # number of hwpf issued
938 system.cpu.l2cache.prefetcher.pfIdentified 5289387 # number of prefetch candidates identified
939 system.cpu.l2cache.prefetcher.pfBufferHit 687833 # number of redundant prefetches already in prefetch queue
940 system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
941 system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
942 system.cpu.l2cache.prefetcher.pfSpanPage 14073797 # number of prefetches not generated due to page crossing
943 system.cpu.l2cache.tags.replacements 562 # number of replacements
944 system.cpu.l2cache.tags.tagsinuse 12069.997275 # Cycle average of tags in use
945 system.cpu.l2cache.tags.total_refs 10652240 # Total number of references to valid blocks.
946 system.cpu.l2cache.tags.sampled_refs 15999 # Sample count of references to valid blocks.
947 system.cpu.l2cache.tags.avg_refs 665.806613 # Average number of references to valid blocks.
948 system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
949 system.cpu.l2cache.tags.occ_blocks::writebacks 11108.777118 # Average occupied blocks per requestor
950 system.cpu.l2cache.tags.occ_blocks::cpu.inst 571.857159 # Average occupied blocks per requestor
951 system.cpu.l2cache.tags.occ_blocks::cpu.data 208.039641 # Average occupied blocks per requestor
952 system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 181.323358 # Average occupied blocks per requestor
953 system.cpu.l2cache.tags.occ_percent::writebacks 0.678026 # Average percentage of cache occupancy
954 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.034903 # Average percentage of cache occupancy
955 system.cpu.l2cache.tags.occ_percent::cpu.data 0.012698 # Average percentage of cache occupancy
956 system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.011067 # Average percentage of cache occupancy
957 system.cpu.l2cache.tags.occ_percent::total 0.736694 # Average percentage of cache occupancy
958 system.cpu.l2cache.tags.occ_task_id_blocks::1022 237 # Occupied blocks per task id
959 system.cpu.l2cache.tags.occ_task_id_blocks::1024 15200 # Occupied blocks per task id
960 system.cpu.l2cache.tags.age_task_id_blocks_1022::0 2 # Occupied blocks per task id
961 system.cpu.l2cache.tags.age_task_id_blocks_1022::1 9 # Occupied blocks per task id
962 system.cpu.l2cache.tags.age_task_id_blocks_1022::2 30 # Occupied blocks per task id
963 system.cpu.l2cache.tags.age_task_id_blocks_1022::3 6 # Occupied blocks per task id
964 system.cpu.l2cache.tags.age_task_id_blocks_1022::4 190 # Occupied blocks per task id
965 system.cpu.l2cache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id
966 system.cpu.l2cache.tags.age_task_id_blocks_1024::1 36 # Occupied blocks per task id
967 system.cpu.l2cache.tags.age_task_id_blocks_1024::2 976 # Occupied blocks per task id
968 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1058 # Occupied blocks per task id
969 system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13088 # Occupied blocks per task id
970 system.cpu.l2cache.tags.occ_task_id_percent::1022 0.014465 # Percentage of cache occupancy per task id
971 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.927734 # Percentage of cache occupancy per task id
972 system.cpu.l2cache.tags.tag_accesses 174792474 # Number of tag accesses
973 system.cpu.l2cache.tags.data_accesses 174792474 # Number of data accesses
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976 system.cpu.l2cache.ReadReq_hits::total 5236612 # number of ReadReq hits
977 system.cpu.l2cache.Writeback_hits::writebacks 5437967 # number of Writeback hits
978 system.cpu.l2cache.Writeback_hits::total 5437967 # number of Writeback hits
979 system.cpu.l2cache.ReadExReq_hits::cpu.data 232700 # number of ReadExReq hits
980 system.cpu.l2cache.ReadExReq_hits::total 232700 # number of ReadExReq hits
981 system.cpu.l2cache.demand_hits::cpu.inst 211 # number of demand (read+write) hits
982 system.cpu.l2cache.demand_hits::cpu.data 5469101 # number of demand (read+write) hits
983 system.cpu.l2cache.demand_hits::total 5469312 # number of demand (read+write) hits
984 system.cpu.l2cache.overall_hits::cpu.inst 211 # number of overall hits
985 system.cpu.l2cache.overall_hits::cpu.data 5469101 # number of overall hits
986 system.cpu.l2cache.overall_hits::total 5469312 # number of overall hits
987 system.cpu.l2cache.ReadReq_misses::cpu.inst 697 # number of ReadReq misses
988 system.cpu.l2cache.ReadReq_misses::cpu.data 467 # number of ReadReq misses
989 system.cpu.l2cache.ReadReq_misses::total 1164 # number of ReadReq misses
990 system.cpu.l2cache.UpgradeReq_misses::cpu.data 2 # number of UpgradeReq misses
991 system.cpu.l2cache.UpgradeReq_misses::total 2 # number of UpgradeReq misses
992 system.cpu.l2cache.ReadExReq_misses::cpu.data 509 # number of ReadExReq misses
993 system.cpu.l2cache.ReadExReq_misses::total 509 # number of ReadExReq misses
994 system.cpu.l2cache.demand_misses::cpu.inst 697 # number of demand (read+write) misses
995 system.cpu.l2cache.demand_misses::cpu.data 976 # number of demand (read+write) misses
996 system.cpu.l2cache.demand_misses::total 1673 # number of demand (read+write) misses
997 system.cpu.l2cache.overall_misses::cpu.inst 697 # number of overall misses
998 system.cpu.l2cache.overall_misses::cpu.data 976 # number of overall misses
999 system.cpu.l2cache.overall_misses::total 1673 # number of overall misses
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1003 system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 46498 # number of UpgradeReq miss cycles
1004 system.cpu.l2cache.UpgradeReq_miss_latency::total 46498 # number of UpgradeReq miss cycles
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1012 system.cpu.l2cache.overall_miss_latency::total 113442306 # number of overall miss cycles
1013 system.cpu.l2cache.ReadReq_accesses::cpu.inst 908 # number of ReadReq accesses(hits+misses)
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1015 system.cpu.l2cache.ReadReq_accesses::total 5237776 # number of ReadReq accesses(hits+misses)
1016 system.cpu.l2cache.Writeback_accesses::writebacks 5437967 # number of Writeback accesses(hits+misses)
1017 system.cpu.l2cache.Writeback_accesses::total 5437967 # number of Writeback accesses(hits+misses)
1018 system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2 # number of UpgradeReq accesses(hits+misses)
1019 system.cpu.l2cache.UpgradeReq_accesses::total 2 # number of UpgradeReq accesses(hits+misses)
1020 system.cpu.l2cache.ReadExReq_accesses::cpu.data 233209 # number of ReadExReq accesses(hits+misses)
1021 system.cpu.l2cache.ReadExReq_accesses::total 233209 # number of ReadExReq accesses(hits+misses)
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1025 system.cpu.l2cache.overall_accesses::cpu.inst 908 # number of overall (read+write) accesses
1026 system.cpu.l2cache.overall_accesses::cpu.data 5470077 # number of overall (read+write) accesses
1027 system.cpu.l2cache.overall_accesses::total 5470985 # number of overall (read+write) accesses
1028 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.767621 # miss rate for ReadReq accesses
1029 system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000089 # miss rate for ReadReq accesses
1030 system.cpu.l2cache.ReadReq_miss_rate::total 0.000222 # miss rate for ReadReq accesses
1031 system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses
1032 system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses
1033 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.002183 # miss rate for ReadExReq accesses
1034 system.cpu.l2cache.ReadExReq_miss_rate::total 0.002183 # miss rate for ReadExReq accesses
1035 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.767621 # miss rate for demand accesses
1036 system.cpu.l2cache.demand_miss_rate::cpu.data 0.000178 # miss rate for demand accesses
1037 system.cpu.l2cache.demand_miss_rate::total 0.000306 # miss rate for demand accesses
1038 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.767621 # miss rate for overall accesses
1039 system.cpu.l2cache.overall_miss_rate::cpu.data 0.000178 # miss rate for overall accesses
1040 system.cpu.l2cache.overall_miss_rate::total 0.000306 # miss rate for overall accesses
1041 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68760.391679 # average ReadReq miss latency
1042 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 62336.723769 # average ReadReq miss latency
1043 system.cpu.l2cache.ReadReq_avg_miss_latency::total 66183.198454 # average ReadReq miss latency
1044 system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 23249 # average UpgradeReq miss latency
1045 system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 23249 # average UpgradeReq miss latency
1046 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71522.717092 # average ReadExReq miss latency
1047 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71522.717092 # average ReadExReq miss latency
1048 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68760.391679 # average overall miss latency
1049 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 67127.369877 # average overall miss latency
1050 system.cpu.l2cache.demand_avg_miss_latency::total 67807.714286 # average overall miss latency
1051 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68760.391679 # average overall miss latency
1052 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 67127.369877 # average overall miss latency
1053 system.cpu.l2cache.overall_avg_miss_latency::total 67807.714286 # average overall miss latency
1054 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1055 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1056 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
1057 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1058 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1059 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1060 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
1061 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
1062 system.cpu.l2cache.writebacks::writebacks 399 # number of writebacks
1063 system.cpu.l2cache.writebacks::total 399 # number of writebacks
1064 system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits
1065 system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 52 # number of ReadReq MSHR hits
1066 system.cpu.l2cache.ReadReq_mshr_hits::total 53 # number of ReadReq MSHR hits
1067 system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 170 # number of ReadExReq MSHR hits
1068 system.cpu.l2cache.ReadExReq_mshr_hits::total 170 # number of ReadExReq MSHR hits
1069 system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
1070 system.cpu.l2cache.demand_mshr_hits::cpu.data 222 # number of demand (read+write) MSHR hits
1071 system.cpu.l2cache.demand_mshr_hits::total 223 # number of demand (read+write) MSHR hits
1072 system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
1073 system.cpu.l2cache.overall_mshr_hits::cpu.data 222 # number of overall MSHR hits
1074 system.cpu.l2cache.overall_mshr_hits::total 223 # number of overall MSHR hits
1075 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 696 # number of ReadReq MSHR misses
1076 system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 415 # number of ReadReq MSHR misses
1077 system.cpu.l2cache.ReadReq_mshr_misses::total 1111 # number of ReadReq MSHR misses
1078 system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 20227 # number of HardPFReq MSHR misses
1079 system.cpu.l2cache.HardPFReq_mshr_misses::total 20227 # number of HardPFReq MSHR misses
1080 system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2 # number of UpgradeReq MSHR misses
1081 system.cpu.l2cache.UpgradeReq_mshr_misses::total 2 # number of UpgradeReq MSHR misses
1082 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 339 # number of ReadExReq MSHR misses
1083 system.cpu.l2cache.ReadExReq_mshr_misses::total 339 # number of ReadExReq MSHR misses
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1087 system.cpu.l2cache.overall_mshr_misses::cpu.inst 696 # number of overall MSHR misses
1088 system.cpu.l2cache.overall_mshr_misses::cpu.data 754 # number of overall MSHR misses
1089 system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 20227 # number of overall MSHR misses
1090 system.cpu.l2cache.overall_mshr_misses::total 21677 # number of overall MSHR misses
1091 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 41955257 # number of ReadReq MSHR miss cycles
1092 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 23172750 # number of ReadReq MSHR miss cycles
1093 system.cpu.l2cache.ReadReq_mshr_miss_latency::total 65128007 # number of ReadReq MSHR miss cycles
1094 system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 829862007 # number of HardPFReq MSHR miss cycles
1095 system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 829862007 # number of HardPFReq MSHR miss cycles
1096 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 27502 # number of UpgradeReq MSHR miss cycles
1097 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 27502 # number of UpgradeReq MSHR miss cycles
1098 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 25379758 # number of ReadExReq MSHR miss cycles
1099 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 25379758 # number of ReadExReq MSHR miss cycles
1100 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 41955257 # number of demand (read+write) MSHR miss cycles
1101 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 48552508 # number of demand (read+write) MSHR miss cycles
1102 system.cpu.l2cache.demand_mshr_miss_latency::total 90507765 # number of demand (read+write) MSHR miss cycles
1103 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 41955257 # number of overall MSHR miss cycles
1104 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 48552508 # number of overall MSHR miss cycles
1105 system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 829862007 # number of overall MSHR miss cycles
1106 system.cpu.l2cache.overall_mshr_miss_latency::total 920369772 # number of overall MSHR miss cycles
1107 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.766520 # mshr miss rate for ReadReq accesses
1108 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000079 # mshr miss rate for ReadReq accesses
1109 system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000212 # mshr miss rate for ReadReq accesses
1110 system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
1111 system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
1112 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses
1113 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
1114 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001454 # mshr miss rate for ReadExReq accesses
1115 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001454 # mshr miss rate for ReadExReq accesses
1116 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.766520 # mshr miss rate for demand accesses
1117 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.000138 # mshr miss rate for demand accesses
1118 system.cpu.l2cache.demand_mshr_miss_rate::total 0.000265 # mshr miss rate for demand accesses
1119 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.766520 # mshr miss rate for overall accesses
1120 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.000138 # mshr miss rate for overall accesses
1121 system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses
1122 system.cpu.l2cache.overall_mshr_miss_rate::total 0.003962 # mshr miss rate for overall accesses
1123 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60280.541667 # average ReadReq mshr miss latency
1124 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 55837.951807 # average ReadReq mshr miss latency
1125 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58621.068407 # average ReadReq mshr miss latency
1126 system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 41027.438918 # average HardPFReq mshr miss latency
1127 system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 41027.438918 # average HardPFReq mshr miss latency
1128 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 13751 # average UpgradeReq mshr miss latency
1129 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 13751 # average UpgradeReq mshr miss latency
1130 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 74866.542773 # average ReadExReq mshr miss latency
1131 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 74866.542773 # average ReadExReq mshr miss latency
1132 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60280.541667 # average overall mshr miss latency
1133 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64393.246684 # average overall mshr miss latency
1134 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62419.148276 # average overall mshr miss latency
1135 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60280.541667 # average overall mshr miss latency
1136 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64393.246684 # average overall mshr miss latency
1137 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 41027.438918 # average overall mshr miss latency
1138 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42458.355492 # average overall mshr miss latency
1139 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
1140 system.cpu.toL2Bus.trans_dist::ReadReq 5237776 # Transaction distribution
1141 system.cpu.toL2Bus.trans_dist::ReadResp 5237776 # Transaction distribution
1142 system.cpu.toL2Bus.trans_dist::Writeback 5437967 # Transaction distribution
1143 system.cpu.toL2Bus.trans_dist::HardPFReq 22114 # Transaction distribution
1144 system.cpu.toL2Bus.trans_dist::HardPFResp 2 # Transaction distribution
1145 system.cpu.toL2Bus.trans_dist::UpgradeReq 2 # Transaction distribution
1146 system.cpu.toL2Bus.trans_dist::UpgradeResp 2 # Transaction distribution
1147 system.cpu.toL2Bus.trans_dist::ReadExReq 233209 # Transaction distribution
1148 system.cpu.toL2Bus.trans_dist::ReadExResp 233209 # Transaction distribution
1149 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1816 # Packet count per connected master and slave (bytes)
1150 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 16378127 # Packet count per connected master and slave (bytes)
1151 system.cpu.toL2Bus.pkt_count::total 16379943 # Packet count per connected master and slave (bytes)
1152 system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 58112 # Cumulative packet size per connected master and slave (bytes)
1153 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 698114944 # Cumulative packet size per connected master and slave (bytes)
1154 system.cpu.toL2Bus.pkt_size::total 698173056 # Cumulative packet size per connected master and slave (bytes)
1155 system.cpu.toL2Bus.snoops 22116 # Total snoops (count)
1156 system.cpu.toL2Bus.snoop_fanout::samples 10931068 # Request fanout histogram
1157 system.cpu.toL2Bus.snoop_fanout::mean 1.002023 # Request fanout histogram
1158 system.cpu.toL2Bus.snoop_fanout::stdev 0.044933 # Request fanout histogram
1159 system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1160 system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
1161 system.cpu.toL2Bus.snoop_fanout::1 10908954 99.80% 99.80% # Request fanout histogram
1162 system.cpu.toL2Bus.snoop_fanout::2 22114 0.20% 100.00% # Request fanout histogram
1163 system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1164 system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
1165 system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
1166 system.cpu.toL2Bus.snoop_fanout::total 10931068 # Request fanout histogram
1167 system.cpu.toL2Bus.reqLayer0.occupancy 10892444998 # Layer occupancy (ticks)
1168 system.cpu.toL2Bus.reqLayer0.utilization 18.7 # Layer utilization (%)
1169 system.cpu.toL2Bus.snoopLayer0.occupancy 3000 # Layer occupancy (ticks)
1170 system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
1171 system.cpu.toL2Bus.respLayer0.occupancy 1495005 # Layer occupancy (ticks)
1172 system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
1173 system.cpu.toL2Bus.respLayer1.occupancy 8205165681 # Layer occupancy (ticks)
1174 system.cpu.toL2Bus.respLayer1.utilization 14.1 # Layer utilization (%)
1175 system.membus.trans_dist::ReadReq 15652 # Transaction distribution
1176 system.membus.trans_dist::ReadResp 15652 # Transaction distribution
1177 system.membus.trans_dist::Writeback 399 # Transaction distribution
1178 system.membus.trans_dist::UpgradeReq 2 # Transaction distribution
1179 system.membus.trans_dist::UpgradeResp 2 # Transaction distribution
1180 system.membus.trans_dist::ReadExReq 339 # Transaction distribution
1181 system.membus.trans_dist::ReadExResp 339 # Transaction distribution
1182 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 32385 # Packet count per connected master and slave (bytes)
1183 system.membus.pkt_count::total 32385 # Packet count per connected master and slave (bytes)
1184 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1048960 # Cumulative packet size per connected master and slave (bytes)
1185 system.membus.pkt_size::total 1048960 # Cumulative packet size per connected master and slave (bytes)
1186 system.membus.snoops 0 # Total snoops (count)
1187 system.membus.snoop_fanout::samples 16392 # Request fanout histogram
1188 system.membus.snoop_fanout::mean 0 # Request fanout histogram
1189 system.membus.snoop_fanout::stdev 0 # Request fanout histogram
1190 system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1191 system.membus.snoop_fanout::0 16392 100.00% 100.00% # Request fanout histogram
1192 system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
1193 system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1194 system.membus.snoop_fanout::min_value 0 # Request fanout histogram
1195 system.membus.snoop_fanout::max_value 0 # Request fanout histogram
1196 system.membus.snoop_fanout::total 16392 # Request fanout histogram
1197 system.membus.reqLayer0.occupancy 27168735 # Layer occupancy (ticks)
1198 system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
1199 system.membus.respLayer1.occupancy 83645045 # Layer occupancy (ticks)
1200 system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
1202 ---------- End Simulation Statistics ----------
projects / gem5.git / blob