2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.058199 # Number of seconds simulated
4 sim_ticks 58199030500 # Number of ticks simulated
5 final_tick 58199030500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 123305 # Simulator instruction rate (inst/s)
8 host_op_rate 123919 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 79216719 # Simulator tick rate (ticks/s)
10 host_mem_usage 487100 # Number of bytes of host memory used
11 host_seconds 734.68 # Real time elapsed on the host
12 sim_insts 90589799 # Number of instructions simulated
13 sim_ops 91041030 # Number of ops (including micro ops) simulated
14 system.voltage_domain.voltage 1 # Voltage in Volts
15 system.clk_domain.clock 1000 # Clock period in ticks
16 system.physmem.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states
17 system.physmem.bytes_read::cpu.inst 44352 # Number of bytes read from this memory
18 system.physmem.bytes_read::cpu.data 87616 # Number of bytes read from this memory
19 system.physmem.bytes_read::cpu.l2cache.prefetcher 925056 # Number of bytes read from this memory
20 system.physmem.bytes_read::total 1057024 # Number of bytes read from this memory
21 system.physmem.bytes_inst_read::cpu.inst 44352 # Number of instructions bytes read from this memory
22 system.physmem.bytes_inst_read::total 44352 # Number of instructions bytes read from this memory
23 system.physmem.bytes_written::writebacks 11200 # Number of bytes written to this memory
24 system.physmem.bytes_written::total 11200 # Number of bytes written to this memory
25 system.physmem.num_reads::cpu.inst 693 # Number of read requests responded to by this memory
26 system.physmem.num_reads::cpu.data 1369 # Number of read requests responded to by this memory
27 system.physmem.num_reads::cpu.l2cache.prefetcher 14454 # Number of read requests responded to by this memory
28 system.physmem.num_reads::total 16516 # Number of read requests responded to by this memory
29 system.physmem.num_writes::writebacks 175 # Number of write requests responded to by this memory
30 system.physmem.num_writes::total 175 # Number of write requests responded to by this memory
31 system.physmem.bw_read::cpu.inst 762075 # Total read bandwidth from this memory (bytes/s)
32 system.physmem.bw_read::cpu.data 1505455 # Total read bandwidth from this memory (bytes/s)
33 system.physmem.bw_read::cpu.l2cache.prefetcher 15894698 # Total read bandwidth from this memory (bytes/s)
34 system.physmem.bw_read::total 18162227 # Total read bandwidth from this memory (bytes/s)
35 system.physmem.bw_inst_read::cpu.inst 762075 # Instruction read bandwidth from this memory (bytes/s)
36 system.physmem.bw_inst_read::total 762075 # Instruction read bandwidth from this memory (bytes/s)
37 system.physmem.bw_write::writebacks 192443 # Write bandwidth from this memory (bytes/s)
38 system.physmem.bw_write::total 192443 # Write bandwidth from this memory (bytes/s)
39 system.physmem.bw_total::writebacks 192443 # Total bandwidth to/from this memory (bytes/s)
40 system.physmem.bw_total::cpu.inst 762075 # Total bandwidth to/from this memory (bytes/s)
41 system.physmem.bw_total::cpu.data 1505455 # Total bandwidth to/from this memory (bytes/s)
42 system.physmem.bw_total::cpu.l2cache.prefetcher 15894698 # Total bandwidth to/from this memory (bytes/s)
43 system.physmem.bw_total::total 18354670 # Total bandwidth to/from this memory (bytes/s)
44 system.physmem.readReqs 16517 # Number of read requests accepted
45 system.physmem.writeReqs 175 # Number of write requests accepted
46 system.physmem.readBursts 16517 # Number of DRAM read bursts, including those serviced by the write queue
47 system.physmem.writeBursts 175 # Number of DRAM write bursts, including those merged in the write queue
48 system.physmem.bytesReadDRAM 1048320 # Total number of bytes read from DRAM
49 system.physmem.bytesReadWrQ 8768 # Total number of bytes read from write queue
50 system.physmem.bytesWritten 9216 # Total number of bytes written to DRAM
51 system.physmem.bytesReadSys 1057088 # Total read bytes from the system interface side
52 system.physmem.bytesWrittenSys 11200 # Total written bytes from the system interface side
53 system.physmem.servicedByWrQ 137 # Number of DRAM read bursts serviced by the write queue
54 system.physmem.mergedWrBursts 4 # Number of DRAM write bursts merged with an existing one
55 system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
56 system.physmem.perBankRdBursts::0 1166 # Per bank write bursts
57 system.physmem.perBankRdBursts::1 920 # Per bank write bursts
58 system.physmem.perBankRdBursts::2 953 # Per bank write bursts
59 system.physmem.perBankRdBursts::3 1031 # Per bank write bursts
60 system.physmem.perBankRdBursts::4 1061 # Per bank write bursts
61 system.physmem.perBankRdBursts::5 1122 # Per bank write bursts
62 system.physmem.perBankRdBursts::6 1094 # Per bank write bursts
63 system.physmem.perBankRdBursts::7 1089 # Per bank write bursts
64 system.physmem.perBankRdBursts::8 1025 # Per bank write bursts
65 system.physmem.perBankRdBursts::9 962 # Per bank write bursts
66 system.physmem.perBankRdBursts::10 933 # Per bank write bursts
67 system.physmem.perBankRdBursts::11 900 # Per bank write bursts
68 system.physmem.perBankRdBursts::12 903 # Per bank write bursts
69 system.physmem.perBankRdBursts::13 900 # Per bank write bursts
70 system.physmem.perBankRdBursts::14 1411 # Per bank write bursts
71 system.physmem.perBankRdBursts::15 910 # Per bank write bursts
72 system.physmem.perBankWrBursts::0 2 # Per bank write bursts
73 system.physmem.perBankWrBursts::1 0 # Per bank write bursts
74 system.physmem.perBankWrBursts::2 6 # Per bank write bursts
75 system.physmem.perBankWrBursts::3 1 # Per bank write bursts
76 system.physmem.perBankWrBursts::4 3 # Per bank write bursts
77 system.physmem.perBankWrBursts::5 16 # Per bank write bursts
78 system.physmem.perBankWrBursts::6 40 # Per bank write bursts
79 system.physmem.perBankWrBursts::7 7 # Per bank write bursts
80 system.physmem.perBankWrBursts::8 2 # Per bank write bursts
81 system.physmem.perBankWrBursts::9 0 # Per bank write bursts
82 system.physmem.perBankWrBursts::10 2 # Per bank write bursts
83 system.physmem.perBankWrBursts::11 2 # Per bank write bursts
84 system.physmem.perBankWrBursts::12 2 # Per bank write bursts
85 system.physmem.perBankWrBursts::13 17 # Per bank write bursts
86 system.physmem.perBankWrBursts::14 37 # Per bank write bursts
87 system.physmem.perBankWrBursts::15 7 # Per bank write bursts
88 system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
89 system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
90 system.physmem.totGap 58199022000 # Total gap between requests
91 system.physmem.readPktSize::0 0 # Read request sizes (log2)
92 system.physmem.readPktSize::1 0 # Read request sizes (log2)
93 system.physmem.readPktSize::2 0 # Read request sizes (log2)
94 system.physmem.readPktSize::3 0 # Read request sizes (log2)
95 system.physmem.readPktSize::4 0 # Read request sizes (log2)
96 system.physmem.readPktSize::5 0 # Read request sizes (log2)
97 system.physmem.readPktSize::6 16517 # Read request sizes (log2)
98 system.physmem.writePktSize::0 0 # Write request sizes (log2)
99 system.physmem.writePktSize::1 0 # Write request sizes (log2)
100 system.physmem.writePktSize::2 0 # Write request sizes (log2)
101 system.physmem.writePktSize::3 0 # Write request sizes (log2)
102 system.physmem.writePktSize::4 0 # Write request sizes (log2)
103 system.physmem.writePktSize::5 0 # Write request sizes (log2)
104 system.physmem.writePktSize::6 175 # Write request sizes (log2)
105 system.physmem.rdQLenPdf::0 11454 # What read queue length does an incoming req see
106 system.physmem.rdQLenPdf::1 2521 # What read queue length does an incoming req see
107 system.physmem.rdQLenPdf::2 462 # What read queue length does an incoming req see
108 system.physmem.rdQLenPdf::3 397 # What read queue length does an incoming req see
109 system.physmem.rdQLenPdf::4 296 # What read queue length does an incoming req see
110 system.physmem.rdQLenPdf::5 296 # What read queue length does an incoming req see
111 system.physmem.rdQLenPdf::6 316 # What read queue length does an incoming req see
112 system.physmem.rdQLenPdf::7 292 # What read queue length does an incoming req see
113 system.physmem.rdQLenPdf::8 292 # What read queue length does an incoming req see
114 system.physmem.rdQLenPdf::9 54 # What read queue length does an incoming req see
115 system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
116 system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
117 system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
118 system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
119 system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
120 system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
121 system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
122 system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
123 system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
124 system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
125 system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
126 system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
127 system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
128 system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
129 system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
130 system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
131 system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
132 system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
133 system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
134 system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
135 system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
136 system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
137 system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
138 system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
139 system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
140 system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
141 system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
142 system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
143 system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
144 system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
145 system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
146 system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
147 system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
148 system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
149 system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
150 system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
151 system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
152 system.physmem.wrQLenPdf::15 9 # What write queue length does an incoming req see
153 system.physmem.wrQLenPdf::16 9 # What write queue length does an incoming req see
154 system.physmem.wrQLenPdf::17 9 # What write queue length does an incoming req see
155 system.physmem.wrQLenPdf::18 9 # What write queue length does an incoming req see
156 system.physmem.wrQLenPdf::19 9 # What write queue length does an incoming req see
157 system.physmem.wrQLenPdf::20 9 # What write queue length does an incoming req see
158 system.physmem.wrQLenPdf::21 9 # What write queue length does an incoming req see
159 system.physmem.wrQLenPdf::22 9 # What write queue length does an incoming req see
160 system.physmem.wrQLenPdf::23 9 # What write queue length does an incoming req see
161 system.physmem.wrQLenPdf::24 9 # What write queue length does an incoming req see
162 system.physmem.wrQLenPdf::25 9 # What write queue length does an incoming req see
163 system.physmem.wrQLenPdf::26 9 # What write queue length does an incoming req see
164 system.physmem.wrQLenPdf::27 8 # What write queue length does an incoming req see
165 system.physmem.wrQLenPdf::28 8 # What write queue length does an incoming req see
166 system.physmem.wrQLenPdf::29 8 # What write queue length does an incoming req see
167 system.physmem.wrQLenPdf::30 8 # What write queue length does an incoming req see
168 system.physmem.wrQLenPdf::31 8 # What write queue length does an incoming req see
169 system.physmem.wrQLenPdf::32 8 # What write queue length does an incoming req see
170 system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
171 system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
172 system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
173 system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
174 system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
175 system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
176 system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
177 system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
178 system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
179 system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
180 system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
181 system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
182 system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
183 system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
184 system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
185 system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
186 system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
187 system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
188 system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
189 system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
190 system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
191 system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
192 system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
193 system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
194 system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
195 system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
196 system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
197 system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
198 system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
199 system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
200 system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
201 system.physmem.bytesPerActivate::samples 1812 # Bytes accessed per row activation
202 system.physmem.bytesPerActivate::mean 582.746137 # Bytes accessed per row activation
203 system.physmem.bytesPerActivate::gmean 353.648277 # Bytes accessed per row activation
204 system.physmem.bytesPerActivate::stdev 424.722034 # Bytes accessed per row activation
205 system.physmem.bytesPerActivate::0-127 448 24.72% 24.72% # Bytes accessed per row activation
206 system.physmem.bytesPerActivate::128-255 213 11.75% 36.48% # Bytes accessed per row activation
207 system.physmem.bytesPerActivate::256-383 96 5.30% 41.78% # Bytes accessed per row activation
208 system.physmem.bytesPerActivate::384-511 72 3.97% 45.75% # Bytes accessed per row activation
209 system.physmem.bytesPerActivate::512-639 56 3.09% 48.84% # Bytes accessed per row activation
210 system.physmem.bytesPerActivate::640-767 67 3.70% 52.54% # Bytes accessed per row activation
211 system.physmem.bytesPerActivate::768-895 61 3.37% 55.91% # Bytes accessed per row activation
212 system.physmem.bytesPerActivate::896-1023 48 2.65% 58.55% # Bytes accessed per row activation
213 system.physmem.bytesPerActivate::1024-1151 751 41.45% 100.00% # Bytes accessed per row activation
214 system.physmem.bytesPerActivate::total 1812 # Bytes accessed per row activation
215 system.physmem.rdPerTurnAround::samples 8 # Reads before turning the bus around for writes
216 system.physmem.rdPerTurnAround::mean 2016.250000 # Reads before turning the bus around for writes
217 system.physmem.rdPerTurnAround::gmean 98.342741 # Reads before turning the bus around for writes
218 system.physmem.rdPerTurnAround::stdev 5441.040729 # Reads before turning the bus around for writes
219 system.physmem.rdPerTurnAround::0-511 7 87.50% 87.50% # Reads before turning the bus around for writes
220 system.physmem.rdPerTurnAround::15360-15871 1 12.50% 100.00% # Reads before turning the bus around for writes
221 system.physmem.rdPerTurnAround::total 8 # Reads before turning the bus around for writes
222 system.physmem.wrPerTurnAround::samples 8 # Writes before turning the bus around for reads
223 system.physmem.wrPerTurnAround::mean 18 # Writes before turning the bus around for reads
224 system.physmem.wrPerTurnAround::gmean 18.000000 # Writes before turning the bus around for reads
225 system.physmem.wrPerTurnAround::18 8 100.00% 100.00% # Writes before turning the bus around for reads
226 system.physmem.wrPerTurnAround::total 8 # Writes before turning the bus around for reads
227 system.physmem.totQLat 175730624 # Total ticks spent queuing
228 system.physmem.totMemAccLat 482855624 # Total ticks spent from burst creation until serviced by the DRAM
229 system.physmem.totBusLat 81900000 # Total ticks spent in databus transfers
230 system.physmem.avgQLat 10728.37 # Average queueing delay per DRAM burst
231 system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
232 system.physmem.avgMemAccLat 29478.37 # Average memory access latency per DRAM burst
233 system.physmem.avgRdBW 18.01 # Average DRAM read bandwidth in MiByte/s
234 system.physmem.avgWrBW 0.16 # Average achieved write bandwidth in MiByte/s
235 system.physmem.avgRdBWSys 18.16 # Average system read bandwidth in MiByte/s
236 system.physmem.avgWrBWSys 0.19 # Average system write bandwidth in MiByte/s
237 system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
238 system.physmem.busUtil 0.14 # Data bus utilization in percentage
239 system.physmem.busUtilRead 0.14 # Data bus utilization in percentage for reads
240 system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
241 system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing
242 system.physmem.avgWrQLen 14.75 # Average write queue length when enqueuing
243 system.physmem.readRowHits 14651 # Number of row buffer hits during reads
244 system.physmem.writeRowHits 51 # Number of row buffer hits during writes
245 system.physmem.readRowHitRate 89.44 # Row buffer hit rate for reads
246 system.physmem.writeRowHitRate 29.82 # Row buffer hit rate for writes
247 system.physmem.avgGap 3486641.62 # Average gap between requests
248 system.physmem.pageHitRate 88.83 # Row buffer hit rate, read and write combined
249 system.physmem_0.actEnergy 7658280 # Energy for activate commands per rank (pJ)
250 system.physmem_0.preEnergy 4178625 # Energy for precharge commands per rank (pJ)
251 system.physmem_0.readEnergy 65512200 # Energy for read commands per rank (pJ)
252 system.physmem_0.writeEnergy 486000 # Energy for write commands per rank (pJ)
253 system.physmem_0.refreshEnergy 3800977440 # Energy for refresh commands per rank (pJ)
254 system.physmem_0.actBackEnergy 2714701095 # Energy for active background per rank (pJ)
255 system.physmem_0.preBackEnergy 32535498750 # Energy for precharge background per rank (pJ)
256 system.physmem_0.totalEnergy 39129012390 # Total energy per rank (pJ)
257 system.physmem_0.averagePower 672.381118 # Core power per rank (mW)
258 system.physmem_0.memoryStateTime::IDLE 54114607553 # Time in different power states
259 system.physmem_0.memoryStateTime::REF 1943240000 # Time in different power states
260 system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
261 system.physmem_0.memoryStateTime::ACT 2137743447 # Time in different power states
262 system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
263 system.physmem_1.actEnergy 6017760 # Energy for activate commands per rank (pJ)
264 system.physmem_1.preEnergy 3283500 # Energy for precharge commands per rank (pJ)
265 system.physmem_1.readEnergy 61916400 # Energy for read commands per rank (pJ)
266 system.physmem_1.writeEnergy 447120 # Energy for write commands per rank (pJ)
267 system.physmem_1.refreshEnergy 3800977440 # Energy for refresh commands per rank (pJ)
268 system.physmem_1.actBackEnergy 2480426820 # Energy for active background per rank (pJ)
269 system.physmem_1.preBackEnergy 32741002500 # Energy for precharge background per rank (pJ)
270 system.physmem_1.totalEnergy 39094071540 # Total energy per rank (pJ)
271 system.physmem_1.averagePower 671.780705 # Core power per rank (mW)
272 system.physmem_1.memoryStateTime::IDLE 54458056984 # Time in different power states
273 system.physmem_1.memoryStateTime::REF 1943240000 # Time in different power states
274 system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
275 system.physmem_1.memoryStateTime::ACT 1793992016 # Time in different power states
276 system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
277 system.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states
278 system.cpu.branchPred.lookups 28233538 # Number of BP lookups
279 system.cpu.branchPred.condPredicted 23266052 # Number of conditional branches predicted
280 system.cpu.branchPred.condIncorrect 835390 # Number of conditional branches incorrect
281 system.cpu.branchPred.BTBLookups 11829354 # Number of BTB lookups
282 system.cpu.branchPred.BTBHits 11747655 # Number of BTB hits
283 system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
284 system.cpu.branchPred.BTBHitPct 99.309354 # BTB Hit Percentage
285 system.cpu.branchPred.usedRAS 74541 # Number of times the RAS was used to get a target.
286 system.cpu.branchPred.RASInCorrect 92 # Number of incorrect RAS predictions.
287 system.cpu.branchPred.indirectLookups 27216 # Number of indirect predictor lookups.
288 system.cpu.branchPred.indirectHits 25478 # Number of indirect target hits.
289 system.cpu.branchPred.indirectMisses 1738 # Number of indirect misses.
290 system.cpu.branchPredindirectMispredicted 245 # Number of mispredicted indirect branches.
291 system.cpu_clk_domain.clock 500 # Clock period in ticks
292 system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states
293 system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
294 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
295 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
296 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
297 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
298 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
299 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
300 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
301 system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
302 system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
303 system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
304 system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
305 system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
306 system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
307 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
308 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
309 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
310 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
311 system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
312 system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
313 system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
314 system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
315 system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
316 system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
317 system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
318 system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
319 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
320 system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
321 system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
322 system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states
323 system.cpu.dtb.walker.walks 0 # Table walker walks requested
324 system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
325 system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
326 system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
327 system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
328 system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
329 system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
330 system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
331 system.cpu.dtb.inst_hits 0 # ITB inst hits
332 system.cpu.dtb.inst_misses 0 # ITB inst misses
333 system.cpu.dtb.read_hits 0 # DTB read hits
334 system.cpu.dtb.read_misses 0 # DTB read misses
335 system.cpu.dtb.write_hits 0 # DTB write hits
336 system.cpu.dtb.write_misses 0 # DTB write misses
337 system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
338 system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
339 system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
340 system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
341 system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
342 system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
343 system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
344 system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
345 system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
346 system.cpu.dtb.read_accesses 0 # DTB read accesses
347 system.cpu.dtb.write_accesses 0 # DTB write accesses
348 system.cpu.dtb.inst_accesses 0 # ITB inst accesses
349 system.cpu.dtb.hits 0 # DTB hits
350 system.cpu.dtb.misses 0 # DTB misses
351 system.cpu.dtb.accesses 0 # DTB accesses
352 system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states
353 system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
354 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
355 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
356 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
357 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
358 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
359 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
360 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
361 system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
362 system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
363 system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
364 system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
365 system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
366 system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
367 system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
368 system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
369 system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
370 system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
371 system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
372 system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
373 system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
374 system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
375 system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
376 system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
377 system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
378 system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
379 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
380 system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
381 system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
382 system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states
383 system.cpu.itb.walker.walks 0 # Table walker walks requested
384 system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
385 system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
386 system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
387 system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
388 system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
389 system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
390 system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
391 system.cpu.itb.inst_hits 0 # ITB inst hits
392 system.cpu.itb.inst_misses 0 # ITB inst misses
393 system.cpu.itb.read_hits 0 # DTB read hits
394 system.cpu.itb.read_misses 0 # DTB read misses
395 system.cpu.itb.write_hits 0 # DTB write hits
396 system.cpu.itb.write_misses 0 # DTB write misses
397 system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
398 system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
399 system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
400 system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
401 system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
402 system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
403 system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
404 system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
405 system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
406 system.cpu.itb.read_accesses 0 # DTB read accesses
407 system.cpu.itb.write_accesses 0 # DTB write accesses
408 system.cpu.itb.inst_accesses 0 # ITB inst accesses
409 system.cpu.itb.hits 0 # DTB hits
410 system.cpu.itb.misses 0 # DTB misses
411 system.cpu.itb.accesses 0 # DTB accesses
412 system.cpu.workload.num_syscalls 442 # Number of system calls
413 system.cpu.pwrStateResidencyTicks::ON 58199030500 # Cumulative time (in ticks) in various power states
414 system.cpu.numCycles 116398062 # number of cpu cycles simulated
415 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
416 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
417 system.cpu.fetch.icacheStallCycles 746143 # Number of cycles fetch is stalled on an Icache miss
418 system.cpu.fetch.Insts 134906479 # Number of instructions fetch has processed
419 system.cpu.fetch.Branches 28233538 # Number of branches that fetch encountered
420 system.cpu.fetch.predictedBranches 11847674 # Number of branches that fetch has predicted taken
421 system.cpu.fetch.Cycles 114760827 # Number of cycles fetch has run and was not squashing or blocked
422 system.cpu.fetch.SquashCycles 1674187 # Number of cycles fetch has spent squashing
423 system.cpu.fetch.MiscStallCycles 911 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
424 system.cpu.fetch.IcacheWaitRetryStallCycles 805 # Number of stall cycles due to full MSHR
425 system.cpu.fetch.CacheLines 32275055 # Number of cache lines fetched
426 system.cpu.fetch.IcacheSquashes 562 # Number of outstanding Icache misses that were squashed
427 system.cpu.fetch.rateDist::samples 116345779 # Number of instructions fetched each cycle (Total)
428 system.cpu.fetch.rateDist::mean 1.164712 # Number of instructions fetched each cycle (Total)
429 system.cpu.fetch.rateDist::stdev 1.318875 # Number of instructions fetched each cycle (Total)
430 system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
431 system.cpu.fetch.rateDist::0 58810972 50.55% 50.55% # Number of instructions fetched each cycle (Total)
432 system.cpu.fetch.rateDist::1 13933527 11.98% 62.52% # Number of instructions fetched each cycle (Total)
433 system.cpu.fetch.rateDist::2 9228064 7.93% 70.46% # Number of instructions fetched each cycle (Total)
434 system.cpu.fetch.rateDist::3 34373216 29.54% 100.00% # Number of instructions fetched each cycle (Total)
435 system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
436 system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
437 system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
438 system.cpu.fetch.rateDist::total 116345779 # Number of instructions fetched each cycle (Total)
439 system.cpu.fetch.branchRate 0.242560 # Number of branch fetches per cycle
440 system.cpu.fetch.rate 1.159010 # Number of inst fetches per cycle
441 system.cpu.decode.IdleCycles 8834252 # Number of cycles decode is idle
442 system.cpu.decode.BlockedCycles 64111694 # Number of cycles decode is blocked
443 system.cpu.decode.RunCycles 33013656 # Number of cycles decode is running
444 system.cpu.decode.UnblockCycles 9560800 # Number of cycles decode is unblocking
445 system.cpu.decode.SquashCycles 825377 # Number of cycles decode is squashing
446 system.cpu.decode.BranchResolved 4097950 # Number of times decode resolved a branch
447 system.cpu.decode.BranchMispred 11817 # Number of times decode detected a branch misprediction
448 system.cpu.decode.DecodedInsts 114395383 # Number of instructions handled by decode
449 system.cpu.decode.SquashedInsts 1985420 # Number of squashed instructions handled by decode
450 system.cpu.rename.SquashCycles 825377 # Number of cycles rename is squashing
451 system.cpu.rename.IdleCycles 15270485 # Number of cycles rename is idle
452 system.cpu.rename.BlockCycles 49952350 # Number of cycles rename is blocking
453 system.cpu.rename.serializeStallCycles 109536 # count of cycles rename stalled for serializing inst
454 system.cpu.rename.RunCycles 35410349 # Number of cycles rename is running
455 system.cpu.rename.UnblockCycles 14777682 # Number of cycles rename is unblocking
456 system.cpu.rename.RenamedInsts 110872417 # Number of instructions processed by rename
457 system.cpu.rename.SquashedInsts 1412237 # Number of squashed instructions processed by rename
458 system.cpu.rename.ROBFullEvents 11132933 # Number of times rename has blocked due to ROB full
459 system.cpu.rename.IQFullEvents 1144918 # Number of times rename has blocked due to IQ full
460 system.cpu.rename.LQFullEvents 1526969 # Number of times rename has blocked due to LQ full
461 system.cpu.rename.SQFullEvents 486977 # Number of times rename has blocked due to SQ full
462 system.cpu.rename.RenamedOperands 129945519 # Number of destination operands rename has renamed
463 system.cpu.rename.RenameLookups 483152587 # Number of register rename lookups that rename has made
464 system.cpu.rename.int_rename_lookups 119447216 # Number of integer rename lookups
465 system.cpu.rename.fp_rename_lookups 432 # Number of floating rename lookups
466 system.cpu.rename.CommittedMaps 107312919 # Number of HB maps that are committed
467 system.cpu.rename.UndoneMaps 22632600 # Number of HB maps that are undone due to squashing
468 system.cpu.rename.serializingInsts 4409 # count of serializing insts renamed
469 system.cpu.rename.tempSerializingInsts 4401 # count of temporary serializing insts renamed
470 system.cpu.rename.skidInsts 21510749 # count of insts added to the skid buffer
471 system.cpu.memDep0.insertedLoads 26805153 # Number of loads inserted to the mem dependence unit.
472 system.cpu.memDep0.insertedStores 5347343 # Number of stores inserted to the mem dependence unit.
473 system.cpu.memDep0.conflictingLoads 519410 # Number of conflicting loads.
474 system.cpu.memDep0.conflictingStores 254099 # Number of conflicting stores.
475 system.cpu.iq.iqInstsAdded 109667150 # Number of instructions added to the IQ (excludes non-spec)
476 system.cpu.iq.iqNonSpecInstsAdded 8283 # Number of non-speculative instructions added to the IQ
477 system.cpu.iq.iqInstsIssued 101366848 # Number of instructions issued
478 system.cpu.iq.iqSquashedInstsIssued 1074801 # Number of squashed instructions issued
479 system.cpu.iq.iqSquashedInstsExamined 18634403 # Number of squashed instructions iterated over during squash; mainly for profiling
480 system.cpu.iq.iqSquashedOperandsExamined 41667039 # Number of squashed operands that are examined and possibly removed from graph
481 system.cpu.iq.iqSquashedNonSpecRemoved 65 # Number of squashed non-spec instructions that were removed
482 system.cpu.iq.issued_per_cycle::samples 116345779 # Number of insts issued each cycle
483 system.cpu.iq.issued_per_cycle::mean 0.871255 # Number of insts issued each cycle
484 system.cpu.iq.issued_per_cycle::stdev 0.989200 # Number of insts issued each cycle
485 system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
486 system.cpu.iq.issued_per_cycle::0 54714850 47.03% 47.03% # Number of insts issued each cycle
487 system.cpu.iq.issued_per_cycle::1 31358235 26.95% 73.98% # Number of insts issued each cycle
488 system.cpu.iq.issued_per_cycle::2 22007860 18.92% 92.90% # Number of insts issued each cycle
489 system.cpu.iq.issued_per_cycle::3 7066756 6.07% 98.97% # Number of insts issued each cycle
490 system.cpu.iq.issued_per_cycle::4 1197765 1.03% 100.00% # Number of insts issued each cycle
491 system.cpu.iq.issued_per_cycle::5 313 0.00% 100.00% # Number of insts issued each cycle
492 system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
493 system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
494 system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
495 system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
496 system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
497 system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
498 system.cpu.iq.issued_per_cycle::total 116345779 # Number of insts issued each cycle
499 system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
500 system.cpu.iq.fu_full::IntAlu 9784213 48.67% 48.67% # attempts to use FU when none available
501 system.cpu.iq.fu_full::IntMult 50 0.00% 48.67% # attempts to use FU when none available
502 system.cpu.iq.fu_full::IntDiv 0 0.00% 48.67% # attempts to use FU when none available
503 system.cpu.iq.fu_full::FloatAdd 0 0.00% 48.67% # attempts to use FU when none available
504 system.cpu.iq.fu_full::FloatCmp 0 0.00% 48.67% # attempts to use FU when none available
505 system.cpu.iq.fu_full::FloatCvt 0 0.00% 48.67% # attempts to use FU when none available
506 system.cpu.iq.fu_full::FloatMult 0 0.00% 48.67% # attempts to use FU when none available
507 system.cpu.iq.fu_full::FloatDiv 0 0.00% 48.67% # attempts to use FU when none available
508 system.cpu.iq.fu_full::FloatSqrt 0 0.00% 48.67% # attempts to use FU when none available
509 system.cpu.iq.fu_full::SimdAdd 0 0.00% 48.67% # attempts to use FU when none available
510 system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 48.67% # attempts to use FU when none available
511 system.cpu.iq.fu_full::SimdAlu 0 0.00% 48.67% # attempts to use FU when none available
512 system.cpu.iq.fu_full::SimdCmp 0 0.00% 48.67% # attempts to use FU when none available
513 system.cpu.iq.fu_full::SimdCvt 0 0.00% 48.67% # attempts to use FU when none available
514 system.cpu.iq.fu_full::SimdMisc 0 0.00% 48.67% # attempts to use FU when none available
515 system.cpu.iq.fu_full::SimdMult 0 0.00% 48.67% # attempts to use FU when none available
516 system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 48.67% # attempts to use FU when none available
517 system.cpu.iq.fu_full::SimdShift 0 0.00% 48.67% # attempts to use FU when none available
518 system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 48.67% # attempts to use FU when none available
519 system.cpu.iq.fu_full::SimdSqrt 0 0.00% 48.67% # attempts to use FU when none available
520 system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 48.67% # attempts to use FU when none available
521 system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 48.67% # attempts to use FU when none available
522 system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 48.67% # attempts to use FU when none available
523 system.cpu.iq.fu_full::SimdFloatCvt 13 0.00% 48.67% # attempts to use FU when none available
524 system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 48.67% # attempts to use FU when none available
525 system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 48.67% # attempts to use FU when none available
526 system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 48.67% # attempts to use FU when none available
527 system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 48.67% # attempts to use FU when none available
528 system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 48.67% # attempts to use FU when none available
529 system.cpu.iq.fu_full::MemRead 9614548 47.83% 96.50% # attempts to use FU when none available
530 system.cpu.iq.fu_full::MemWrite 702998 3.50% 100.00% # attempts to use FU when none available
531 system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
532 system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
533 system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
534 system.cpu.iq.FU_type_0::IntAlu 71970791 71.00% 71.00% # Type of FU issued
535 system.cpu.iq.FU_type_0::IntMult 10698 0.01% 71.01% # Type of FU issued
536 system.cpu.iq.FU_type_0::IntDiv 0 0.00% 71.01% # Type of FU issued
537 system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 71.01% # Type of FU issued
538 system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 71.01% # Type of FU issued
539 system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 71.01% # Type of FU issued
540 system.cpu.iq.FU_type_0::FloatMult 0 0.00% 71.01% # Type of FU issued
541 system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 71.01% # Type of FU issued
542 system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 71.01% # Type of FU issued
543 system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 71.01% # Type of FU issued
544 system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 71.01% # Type of FU issued
545 system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 71.01% # Type of FU issued
546 system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 71.01% # Type of FU issued
547 system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 71.01% # Type of FU issued
548 system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 71.01% # Type of FU issued
549 system.cpu.iq.FU_type_0::SimdMult 0 0.00% 71.01% # Type of FU issued
550 system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 71.01% # Type of FU issued
551 system.cpu.iq.FU_type_0::SimdShift 0 0.00% 71.01% # Type of FU issued
552 system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 71.01% # Type of FU issued
553 system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 71.01% # Type of FU issued
554 system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 71.01% # Type of FU issued
555 system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 71.01% # Type of FU issued
556 system.cpu.iq.FU_type_0::SimdFloatCmp 2 0.00% 71.01% # Type of FU issued
557 system.cpu.iq.FU_type_0::SimdFloatCvt 54 0.00% 71.01% # Type of FU issued
558 system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 71.01% # Type of FU issued
559 system.cpu.iq.FU_type_0::SimdFloatMisc 124 0.00% 71.01% # Type of FU issued
560 system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 71.01% # Type of FU issued
561 system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 71.01% # Type of FU issued
562 system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 71.01% # Type of FU issued
563 system.cpu.iq.FU_type_0::MemRead 24337715 24.01% 95.02% # Type of FU issued
564 system.cpu.iq.FU_type_0::MemWrite 5047462 4.98% 100.00% # Type of FU issued
565 system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
566 system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
567 system.cpu.iq.FU_type_0::total 101366848 # Type of FU issued
568 system.cpu.iq.rate 0.870864 # Inst issue rate
569 system.cpu.iq.fu_busy_cnt 20101822 # FU busy when requested
570 system.cpu.iq.fu_busy_rate 0.198308 # FU busy rate (busy events/executed inst)
571 system.cpu.iq.int_inst_queue_reads 340255638 # Number of integer instruction queue reads
572 system.cpu.iq.int_inst_queue_writes 128310520 # Number of integer instruction queue writes
573 system.cpu.iq.int_inst_queue_wakeup_accesses 99608490 # Number of integer instruction queue wakeup accesses
574 system.cpu.iq.fp_inst_queue_reads 460 # Number of floating instruction queue reads
575 system.cpu.iq.fp_inst_queue_writes 624 # Number of floating instruction queue writes
576 system.cpu.iq.fp_inst_queue_wakeup_accesses 115 # Number of floating instruction queue wakeup accesses
577 system.cpu.iq.int_alu_accesses 121468430 # Number of integer alu accesses
578 system.cpu.iq.fp_alu_accesses 240 # Number of floating point alu accesses
579 system.cpu.iew.lsq.thread0.forwLoads 288068 # Number of loads that had data forwarded from stores
580 system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
581 system.cpu.iew.lsq.thread0.squashedLoads 4329242 # Number of loads squashed
582 system.cpu.iew.lsq.thread0.ignoredResponses 1500 # Number of memory responses ignored because the instruction is squashed
583 system.cpu.iew.lsq.thread0.memOrderViolation 1342 # Number of memory ordering violations
584 system.cpu.iew.lsq.thread0.squashedStores 602499 # Number of stores squashed
585 system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
586 system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
587 system.cpu.iew.lsq.thread0.rescheduledLoads 7579 # Number of loads that were rescheduled
588 system.cpu.iew.lsq.thread0.cacheBlocked 130663 # Number of times an access to memory failed due to the cache being blocked
589 system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
590 system.cpu.iew.iewSquashCycles 825377 # Number of cycles IEW is squashing
591 system.cpu.iew.iewBlockCycles 8119454 # Number of cycles IEW is blocking
592 system.cpu.iew.iewUnblockCycles 685980 # Number of cycles IEW is unblocking
593 system.cpu.iew.iewDispatchedInsts 109688255 # Number of instructions dispatched to IQ
594 system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
595 system.cpu.iew.iewDispLoadInsts 26805153 # Number of dispatched load instructions
596 system.cpu.iew.iewDispStoreInsts 5347343 # Number of dispatched store instructions
597 system.cpu.iew.iewDispNonSpecInsts 4395 # Number of dispatched non-speculative instructions
598 system.cpu.iew.iewIQFullEvents 180270 # Number of times the IQ has become full, causing a stall
599 system.cpu.iew.iewLSQFullEvents 342292 # Number of times the LSQ has become full, causing a stall
600 system.cpu.iew.memOrderViolationEvents 1342 # Number of memory order violations
601 system.cpu.iew.predictedTakenIncorrect 435059 # Number of branches that were predicted taken incorrectly
602 system.cpu.iew.predictedNotTakenIncorrect 412404 # Number of branches that were predicted not taken incorrectly
603 system.cpu.iew.branchMispredicts 847463 # Number of branch mispredicts detected at execute
604 system.cpu.iew.iewExecutedInsts 100109842 # Number of executed instructions
605 system.cpu.iew.iewExecLoadInsts 23803071 # Number of load instructions executed
606 system.cpu.iew.iewExecSquashedInsts 1257006 # Number of squashed instructions skipped in execute
607 system.cpu.iew.exec_swp 0 # number of swp insts executed
608 system.cpu.iew.exec_nop 12822 # number of nop insts executed
609 system.cpu.iew.exec_refs 28718921 # number of memory reference insts executed
610 system.cpu.iew.exec_branches 20621209 # Number of branches executed
611 system.cpu.iew.exec_stores 4915850 # Number of stores executed
612 system.cpu.iew.exec_rate 0.860065 # Inst execution rate
613 system.cpu.iew.wb_sent 99693752 # cumulative count of insts sent to commit
614 system.cpu.iew.wb_count 99608605 # cumulative count of insts written-back
615 system.cpu.iew.wb_producers 59691637 # num instructions producing a value
616 system.cpu.iew.wb_consumers 95527463 # num instructions consuming a value
617 system.cpu.iew.wb_rate 0.855758 # insts written-back per cycle
618 system.cpu.iew.wb_fanout 0.624864 # average fanout of values written-back
619 system.cpu.commit.commitSquashedInsts 17362842 # The number of squashed insts skipped by commit
620 system.cpu.commit.commitNonSpecStalls 8218 # The number of times commit has been forced to stall to communicate backwards
621 system.cpu.commit.branchMispredicts 823674 # The number of times a branch was mispredicted
622 system.cpu.commit.committed_per_cycle::samples 113658017 # Number of insts commited each cycle
623 system.cpu.commit.committed_per_cycle::mean 0.801119 # Number of insts commited each cycle
624 system.cpu.commit.committed_per_cycle::stdev 1.737711 # Number of insts commited each cycle
625 system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
626 system.cpu.commit.committed_per_cycle::0 77235221 67.95% 67.95% # Number of insts commited each cycle
627 system.cpu.commit.committed_per_cycle::1 18611593 16.38% 84.33% # Number of insts commited each cycle
628 system.cpu.commit.committed_per_cycle::2 7151823 6.29% 90.62% # Number of insts commited each cycle
629 system.cpu.commit.committed_per_cycle::3 3469408 3.05% 93.67% # Number of insts commited each cycle
630 system.cpu.commit.committed_per_cycle::4 1644636 1.45% 95.12% # Number of insts commited each cycle
631 system.cpu.commit.committed_per_cycle::5 541902 0.48% 95.60% # Number of insts commited each cycle
632 system.cpu.commit.committed_per_cycle::6 703188 0.62% 96.22% # Number of insts commited each cycle
633 system.cpu.commit.committed_per_cycle::7 178974 0.16% 96.37% # Number of insts commited each cycle
634 system.cpu.commit.committed_per_cycle::8 4121272 3.63% 100.00% # Number of insts commited each cycle
635 system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
636 system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
637 system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
638 system.cpu.commit.committed_per_cycle::total 113658017 # Number of insts commited each cycle
639 system.cpu.commit.committedInsts 90602408 # Number of instructions committed
640 system.cpu.commit.committedOps 91053639 # Number of ops (including micro ops) committed
641 system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
642 system.cpu.commit.refs 27220755 # Number of memory references committed
643 system.cpu.commit.loads 22475911 # Number of loads committed
644 system.cpu.commit.membars 3888 # Number of memory barriers committed
645 system.cpu.commit.branches 18732305 # Number of branches committed
646 system.cpu.commit.fp_insts 48 # Number of committed floating point instructions.
647 system.cpu.commit.int_insts 72326352 # Number of committed integer instructions.
648 system.cpu.commit.function_calls 56148 # Number of function calls committed.
649 system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
650 system.cpu.commit.op_class_0::IntAlu 63822387 70.09% 70.09% # Class of committed instruction
651 system.cpu.commit.op_class_0::IntMult 10474 0.01% 70.10% # Class of committed instruction
652 system.cpu.commit.op_class_0::IntDiv 0 0.00% 70.10% # Class of committed instruction
653 system.cpu.commit.op_class_0::FloatAdd 0 0.00% 70.10% # Class of committed instruction
654 system.cpu.commit.op_class_0::FloatCmp 0 0.00% 70.10% # Class of committed instruction
655 system.cpu.commit.op_class_0::FloatCvt 0 0.00% 70.10% # Class of committed instruction
656 system.cpu.commit.op_class_0::FloatMult 0 0.00% 70.10% # Class of committed instruction
657 system.cpu.commit.op_class_0::FloatDiv 0 0.00% 70.10% # Class of committed instruction
658 system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 70.10% # Class of committed instruction
659 system.cpu.commit.op_class_0::SimdAdd 0 0.00% 70.10% # Class of committed instruction
660 system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 70.10% # Class of committed instruction
661 system.cpu.commit.op_class_0::SimdAlu 0 0.00% 70.10% # Class of committed instruction
662 system.cpu.commit.op_class_0::SimdCmp 0 0.00% 70.10% # Class of committed instruction
663 system.cpu.commit.op_class_0::SimdCvt 0 0.00% 70.10% # Class of committed instruction
664 system.cpu.commit.op_class_0::SimdMisc 0 0.00% 70.10% # Class of committed instruction
665 system.cpu.commit.op_class_0::SimdMult 0 0.00% 70.10% # Class of committed instruction
666 system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 70.10% # Class of committed instruction
667 system.cpu.commit.op_class_0::SimdShift 0 0.00% 70.10% # Class of committed instruction
668 system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 70.10% # Class of committed instruction
669 system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 70.10% # Class of committed instruction
670 system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 70.10% # Class of committed instruction
671 system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 70.10% # Class of committed instruction
672 system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 70.10% # Class of committed instruction
673 system.cpu.commit.op_class_0::SimdFloatCvt 6 0.00% 70.10% # Class of committed instruction
674 system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 70.10% # Class of committed instruction
675 system.cpu.commit.op_class_0::SimdFloatMisc 15 0.00% 70.10% # Class of committed instruction
676 system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 70.10% # Class of committed instruction
677 system.cpu.commit.op_class_0::SimdFloatMultAcc 2 0.00% 70.10% # Class of committed instruction
678 system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.10% # Class of committed instruction
679 system.cpu.commit.op_class_0::MemRead 22475911 24.68% 94.79% # Class of committed instruction
680 system.cpu.commit.op_class_0::MemWrite 4744844 5.21% 100.00% # Class of committed instruction
681 system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
682 system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
683 system.cpu.commit.op_class_0::total 91053639 # Class of committed instruction
684 system.cpu.commit.bw_lim_events 4121272 # number cycles where commit BW limit reached
685 system.cpu.rob.rob_reads 217947492 # The number of ROB reads
686 system.cpu.rob.rob_writes 219521309 # The number of ROB writes
687 system.cpu.timesIdled 570 # Number of times that the entire CPU went into an idle state and unscheduled itself
688 system.cpu.idleCycles 52283 # Total number of cycles that the CPU has spent unscheduled due to idling
689 system.cpu.committedInsts 90589799 # Number of Instructions Simulated
690 system.cpu.committedOps 91041030 # Number of Ops (including micro ops) Simulated
691 system.cpu.cpi 1.284891 # CPI: Cycles Per Instruction
692 system.cpu.cpi_total 1.284891 # CPI: Total CPI of All Threads
693 system.cpu.ipc 0.778276 # IPC: Instructions Per Cycle
694 system.cpu.ipc_total 0.778276 # IPC: Total IPC of All Threads
695 system.cpu.int_regfile_reads 108097873 # number of integer regfile reads
696 system.cpu.int_regfile_writes 58692304 # number of integer regfile writes
697 system.cpu.fp_regfile_reads 59 # number of floating regfile reads
698 system.cpu.fp_regfile_writes 96 # number of floating regfile writes
699 system.cpu.cc_regfile_reads 369004699 # number of cc regfile reads
700 system.cpu.cc_regfile_writes 58686555 # number of cc regfile writes
701 system.cpu.misc_regfile_reads 28410103 # number of misc regfile reads
702 system.cpu.misc_regfile_writes 7784 # number of misc regfile writes
703 system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states
704 system.cpu.dcache.tags.replacements 5470634 # number of replacements
705 system.cpu.dcache.tags.tagsinuse 511.784091 # Cycle average of tags in use
706 system.cpu.dcache.tags.total_refs 18249365 # Total number of references to valid blocks.
707 system.cpu.dcache.tags.sampled_refs 5471146 # Sample count of references to valid blocks.
708 system.cpu.dcache.tags.avg_refs 3.335565 # Average number of references to valid blocks.
709 system.cpu.dcache.tags.warmup_cycle 35796500 # Cycle when the warmup percentage was hit.
710 system.cpu.dcache.tags.occ_blocks::cpu.data 511.784091 # Average occupied blocks per requestor
711 system.cpu.dcache.tags.occ_percent::cpu.data 0.999578 # Average percentage of cache occupancy
712 system.cpu.dcache.tags.occ_percent::total 0.999578 # Average percentage of cache occupancy
713 system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
714 system.cpu.dcache.tags.age_task_id_blocks_1024::0 344 # Occupied blocks per task id
715 system.cpu.dcache.tags.age_task_id_blocks_1024::1 168 # Occupied blocks per task id
716 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
717 system.cpu.dcache.tags.tag_accesses 61906904 # Number of tag accesses
718 system.cpu.dcache.tags.data_accesses 61906904 # Number of data accesses
719 system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states
720 system.cpu.dcache.ReadReq_hits::cpu.data 13887331 # number of ReadReq hits
721 system.cpu.dcache.ReadReq_hits::total 13887331 # number of ReadReq hits
722 system.cpu.dcache.WriteReq_hits::cpu.data 4353747 # number of WriteReq hits
723 system.cpu.dcache.WriteReq_hits::total 4353747 # number of WriteReq hits
724 system.cpu.dcache.SoftPFReq_hits::cpu.data 522 # number of SoftPFReq hits
725 system.cpu.dcache.SoftPFReq_hits::total 522 # number of SoftPFReq hits
726 system.cpu.dcache.LoadLockedReq_hits::cpu.data 3872 # number of LoadLockedReq hits
727 system.cpu.dcache.LoadLockedReq_hits::total 3872 # number of LoadLockedReq hits
728 system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits
729 system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits
730 system.cpu.dcache.demand_hits::cpu.data 18241078 # number of demand (read+write) hits
731 system.cpu.dcache.demand_hits::total 18241078 # number of demand (read+write) hits
732 system.cpu.dcache.overall_hits::cpu.data 18241600 # number of overall hits
733 system.cpu.dcache.overall_hits::total 18241600 # number of overall hits
734 system.cpu.dcache.ReadReq_misses::cpu.data 9587264 # number of ReadReq misses
735 system.cpu.dcache.ReadReq_misses::total 9587264 # number of ReadReq misses
736 system.cpu.dcache.WriteReq_misses::cpu.data 381234 # number of WriteReq misses
737 system.cpu.dcache.WriteReq_misses::total 381234 # number of WriteReq misses
738 system.cpu.dcache.SoftPFReq_misses::cpu.data 7 # number of SoftPFReq misses
739 system.cpu.dcache.SoftPFReq_misses::total 7 # number of SoftPFReq misses
740 system.cpu.dcache.LoadLockedReq_misses::cpu.data 15 # number of LoadLockedReq misses
741 system.cpu.dcache.LoadLockedReq_misses::total 15 # number of LoadLockedReq misses
742 system.cpu.dcache.demand_misses::cpu.data 9968498 # number of demand (read+write) misses
743 system.cpu.dcache.demand_misses::total 9968498 # number of demand (read+write) misses
744 system.cpu.dcache.overall_misses::cpu.data 9968505 # number of overall misses
745 system.cpu.dcache.overall_misses::total 9968505 # number of overall misses
746 system.cpu.dcache.ReadReq_miss_latency::cpu.data 88773272500 # number of ReadReq miss cycles
747 system.cpu.dcache.ReadReq_miss_latency::total 88773272500 # number of ReadReq miss cycles
748 system.cpu.dcache.WriteReq_miss_latency::cpu.data 4000795875 # number of WriteReq miss cycles
749 system.cpu.dcache.WriteReq_miss_latency::total 4000795875 # number of WriteReq miss cycles
750 system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 291000 # number of LoadLockedReq miss cycles
751 system.cpu.dcache.LoadLockedReq_miss_latency::total 291000 # number of LoadLockedReq miss cycles
752 system.cpu.dcache.demand_miss_latency::cpu.data 92774068375 # number of demand (read+write) miss cycles
753 system.cpu.dcache.demand_miss_latency::total 92774068375 # number of demand (read+write) miss cycles
754 system.cpu.dcache.overall_miss_latency::cpu.data 92774068375 # number of overall miss cycles
755 system.cpu.dcache.overall_miss_latency::total 92774068375 # number of overall miss cycles
756 system.cpu.dcache.ReadReq_accesses::cpu.data 23474595 # number of ReadReq accesses(hits+misses)
757 system.cpu.dcache.ReadReq_accesses::total 23474595 # number of ReadReq accesses(hits+misses)
758 system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses)
759 system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses)
760 system.cpu.dcache.SoftPFReq_accesses::cpu.data 529 # number of SoftPFReq accesses(hits+misses)
761 system.cpu.dcache.SoftPFReq_accesses::total 529 # number of SoftPFReq accesses(hits+misses)
762 system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 # number of LoadLockedReq accesses(hits+misses)
763 system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses)
764 system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses)
765 system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses)
766 system.cpu.dcache.demand_accesses::cpu.data 28209576 # number of demand (read+write) accesses
767 system.cpu.dcache.demand_accesses::total 28209576 # number of demand (read+write) accesses
768 system.cpu.dcache.overall_accesses::cpu.data 28210105 # number of overall (read+write) accesses
769 system.cpu.dcache.overall_accesses::total 28210105 # number of overall (read+write) accesses
770 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.408410 # miss rate for ReadReq accesses
771 system.cpu.dcache.ReadReq_miss_rate::total 0.408410 # miss rate for ReadReq accesses
772 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.080514 # miss rate for WriteReq accesses
773 system.cpu.dcache.WriteReq_miss_rate::total 0.080514 # miss rate for WriteReq accesses
774 system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.013233 # miss rate for SoftPFReq accesses
775 system.cpu.dcache.SoftPFReq_miss_rate::total 0.013233 # miss rate for SoftPFReq accesses
776 system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.003859 # miss rate for LoadLockedReq accesses
777 system.cpu.dcache.LoadLockedReq_miss_rate::total 0.003859 # miss rate for LoadLockedReq accesses
778 system.cpu.dcache.demand_miss_rate::cpu.data 0.353373 # miss rate for demand accesses
779 system.cpu.dcache.demand_miss_rate::total 0.353373 # miss rate for demand accesses
780 system.cpu.dcache.overall_miss_rate::cpu.data 0.353366 # miss rate for overall accesses
781 system.cpu.dcache.overall_miss_rate::total 0.353366 # miss rate for overall accesses
782 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9259.500156 # average ReadReq miss latency
783 system.cpu.dcache.ReadReq_avg_miss_latency::total 9259.500156 # average ReadReq miss latency
784 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10494.331238 # average WriteReq miss latency
785 system.cpu.dcache.WriteReq_avg_miss_latency::total 10494.331238 # average WriteReq miss latency
786 system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 19400 # average LoadLockedReq miss latency
787 system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 19400 # average LoadLockedReq miss latency
788 system.cpu.dcache.demand_avg_miss_latency::cpu.data 9306.724882 # average overall miss latency
789 system.cpu.dcache.demand_avg_miss_latency::total 9306.724882 # average overall miss latency
790 system.cpu.dcache.overall_avg_miss_latency::cpu.data 9306.718347 # average overall miss latency
791 system.cpu.dcache.overall_avg_miss_latency::total 9306.718347 # average overall miss latency
792 system.cpu.dcache.blocked_cycles::no_mshrs 329915 # number of cycles access was blocked
793 system.cpu.dcache.blocked_cycles::no_targets 108865 # number of cycles access was blocked
794 system.cpu.dcache.blocked::no_mshrs 121409 # number of cycles access was blocked
795 system.cpu.dcache.blocked::no_targets 12838 # number of cycles access was blocked
796 system.cpu.dcache.avg_blocked_cycles::no_mshrs 2.717385 # average number of cycles each access was blocked
797 system.cpu.dcache.avg_blocked_cycles::no_targets 8.479903 # average number of cycles each access was blocked
798 system.cpu.dcache.writebacks::writebacks 5470634 # number of writebacks
799 system.cpu.dcache.writebacks::total 5470634 # number of writebacks
800 system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4338603 # number of ReadReq MSHR hits
801 system.cpu.dcache.ReadReq_mshr_hits::total 4338603 # number of ReadReq MSHR hits
802 system.cpu.dcache.WriteReq_mshr_hits::cpu.data 158750 # number of WriteReq MSHR hits
803 system.cpu.dcache.WriteReq_mshr_hits::total 158750 # number of WriteReq MSHR hits
804 system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 15 # number of LoadLockedReq MSHR hits
805 system.cpu.dcache.LoadLockedReq_mshr_hits::total 15 # number of LoadLockedReq MSHR hits
806 system.cpu.dcache.demand_mshr_hits::cpu.data 4497353 # number of demand (read+write) MSHR hits
807 system.cpu.dcache.demand_mshr_hits::total 4497353 # number of demand (read+write) MSHR hits
808 system.cpu.dcache.overall_mshr_hits::cpu.data 4497353 # number of overall MSHR hits
809 system.cpu.dcache.overall_mshr_hits::total 4497353 # number of overall MSHR hits
810 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5248661 # number of ReadReq MSHR misses
811 system.cpu.dcache.ReadReq_mshr_misses::total 5248661 # number of ReadReq MSHR misses
812 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 222484 # number of WriteReq MSHR misses
813 system.cpu.dcache.WriteReq_mshr_misses::total 222484 # number of WriteReq MSHR misses
814 system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 4 # number of SoftPFReq MSHR misses
815 system.cpu.dcache.SoftPFReq_mshr_misses::total 4 # number of SoftPFReq MSHR misses
816 system.cpu.dcache.demand_mshr_misses::cpu.data 5471145 # number of demand (read+write) MSHR misses
817 system.cpu.dcache.demand_mshr_misses::total 5471145 # number of demand (read+write) MSHR misses
818 system.cpu.dcache.overall_mshr_misses::cpu.data 5471149 # number of overall MSHR misses
819 system.cpu.dcache.overall_mshr_misses::total 5471149 # number of overall MSHR misses
820 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 43288788000 # number of ReadReq MSHR miss cycles
821 system.cpu.dcache.ReadReq_mshr_miss_latency::total 43288788000 # number of ReadReq MSHR miss cycles
822 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2285573254 # number of WriteReq MSHR miss cycles
823 system.cpu.dcache.WriteReq_mshr_miss_latency::total 2285573254 # number of WriteReq MSHR miss cycles
824 system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 214500 # number of SoftPFReq MSHR miss cycles
825 system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 214500 # number of SoftPFReq MSHR miss cycles
826 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 45574361254 # number of demand (read+write) MSHR miss cycles
827 system.cpu.dcache.demand_mshr_miss_latency::total 45574361254 # number of demand (read+write) MSHR miss cycles
828 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 45574575754 # number of overall MSHR miss cycles
829 system.cpu.dcache.overall_mshr_miss_latency::total 45574575754 # number of overall MSHR miss cycles
830 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.223589 # mshr miss rate for ReadReq accesses
831 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.223589 # mshr miss rate for ReadReq accesses
832 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046987 # mshr miss rate for WriteReq accesses
833 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046987 # mshr miss rate for WriteReq accesses
834 system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.007561 # mshr miss rate for SoftPFReq accesses
835 system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.007561 # mshr miss rate for SoftPFReq accesses
836 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.193946 # mshr miss rate for demand accesses
837 system.cpu.dcache.demand_mshr_miss_rate::total 0.193946 # mshr miss rate for demand accesses
838 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.193943 # mshr miss rate for overall accesses
839 system.cpu.dcache.overall_mshr_miss_rate::total 0.193943 # mshr miss rate for overall accesses
840 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8247.586956 # average ReadReq mshr miss latency
841 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 8247.586956 # average ReadReq mshr miss latency
842 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10272.978075 # average WriteReq mshr miss latency
843 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10272.978075 # average WriteReq mshr miss latency
844 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53625 # average SoftPFReq mshr miss latency
845 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53625 # average SoftPFReq mshr miss latency
846 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8329.949445 # average overall mshr miss latency
847 system.cpu.dcache.demand_avg_mshr_miss_latency::total 8329.949445 # average overall mshr miss latency
848 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8329.982560 # average overall mshr miss latency
849 system.cpu.dcache.overall_avg_mshr_miss_latency::total 8329.982560 # average overall mshr miss latency
850 system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states
851 system.cpu.icache.tags.replacements 447 # number of replacements
852 system.cpu.icache.tags.tagsinuse 427.448157 # Cycle average of tags in use
853 system.cpu.icache.tags.total_refs 32273898 # Total number of references to valid blocks.
854 system.cpu.icache.tags.sampled_refs 904 # Sample count of references to valid blocks.
855 system.cpu.icache.tags.avg_refs 35701.214602 # Average number of references to valid blocks.
856 system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
857 system.cpu.icache.tags.occ_blocks::cpu.inst 427.448157 # Average occupied blocks per requestor
858 system.cpu.icache.tags.occ_percent::cpu.inst 0.834860 # Average percentage of cache occupancy
859 system.cpu.icache.tags.occ_percent::total 0.834860 # Average percentage of cache occupancy
860 system.cpu.icache.tags.occ_task_id_blocks::1024 457 # Occupied blocks per task id
861 system.cpu.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id
862 system.cpu.icache.tags.age_task_id_blocks_1024::2 51 # Occupied blocks per task id
863 system.cpu.icache.tags.age_task_id_blocks_1024::3 18 # Occupied blocks per task id
864 system.cpu.icache.tags.age_task_id_blocks_1024::4 335 # Occupied blocks per task id
865 system.cpu.icache.tags.occ_task_id_percent::1024 0.892578 # Percentage of cache occupancy per task id
866 system.cpu.icache.tags.tag_accesses 64550990 # Number of tag accesses
867 system.cpu.icache.tags.data_accesses 64550990 # Number of data accesses
868 system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states
869 system.cpu.icache.ReadReq_hits::cpu.inst 32273898 # number of ReadReq hits
870 system.cpu.icache.ReadReq_hits::total 32273898 # number of ReadReq hits
871 system.cpu.icache.demand_hits::cpu.inst 32273898 # number of demand (read+write) hits
872 system.cpu.icache.demand_hits::total 32273898 # number of demand (read+write) hits
873 system.cpu.icache.overall_hits::cpu.inst 32273898 # number of overall hits
874 system.cpu.icache.overall_hits::total 32273898 # number of overall hits
875 system.cpu.icache.ReadReq_misses::cpu.inst 1145 # number of ReadReq misses
876 system.cpu.icache.ReadReq_misses::total 1145 # number of ReadReq misses
877 system.cpu.icache.demand_misses::cpu.inst 1145 # number of demand (read+write) misses
878 system.cpu.icache.demand_misses::total 1145 # number of demand (read+write) misses
879 system.cpu.icache.overall_misses::cpu.inst 1145 # number of overall misses
880 system.cpu.icache.overall_misses::total 1145 # number of overall misses
881 system.cpu.icache.ReadReq_miss_latency::cpu.inst 60302481 # number of ReadReq miss cycles
882 system.cpu.icache.ReadReq_miss_latency::total 60302481 # number of ReadReq miss cycles
883 system.cpu.icache.demand_miss_latency::cpu.inst 60302481 # number of demand (read+write) miss cycles
884 system.cpu.icache.demand_miss_latency::total 60302481 # number of demand (read+write) miss cycles
885 system.cpu.icache.overall_miss_latency::cpu.inst 60302481 # number of overall miss cycles
886 system.cpu.icache.overall_miss_latency::total 60302481 # number of overall miss cycles
887 system.cpu.icache.ReadReq_accesses::cpu.inst 32275043 # number of ReadReq accesses(hits+misses)
888 system.cpu.icache.ReadReq_accesses::total 32275043 # number of ReadReq accesses(hits+misses)
889 system.cpu.icache.demand_accesses::cpu.inst 32275043 # number of demand (read+write) accesses
890 system.cpu.icache.demand_accesses::total 32275043 # number of demand (read+write) accesses
891 system.cpu.icache.overall_accesses::cpu.inst 32275043 # number of overall (read+write) accesses
892 system.cpu.icache.overall_accesses::total 32275043 # number of overall (read+write) accesses
893 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000035 # miss rate for ReadReq accesses
894 system.cpu.icache.ReadReq_miss_rate::total 0.000035 # miss rate for ReadReq accesses
895 system.cpu.icache.demand_miss_rate::cpu.inst 0.000035 # miss rate for demand accesses
896 system.cpu.icache.demand_miss_rate::total 0.000035 # miss rate for demand accesses
897 system.cpu.icache.overall_miss_rate::cpu.inst 0.000035 # miss rate for overall accesses
898 system.cpu.icache.overall_miss_rate::total 0.000035 # miss rate for overall accesses
899 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52665.922271 # average ReadReq miss latency
900 system.cpu.icache.ReadReq_avg_miss_latency::total 52665.922271 # average ReadReq miss latency
901 system.cpu.icache.demand_avg_miss_latency::cpu.inst 52665.922271 # average overall miss latency
902 system.cpu.icache.demand_avg_miss_latency::total 52665.922271 # average overall miss latency
903 system.cpu.icache.overall_avg_miss_latency::cpu.inst 52665.922271 # average overall miss latency
904 system.cpu.icache.overall_avg_miss_latency::total 52665.922271 # average overall miss latency
905 system.cpu.icache.blocked_cycles::no_mshrs 18953 # number of cycles access was blocked
906 system.cpu.icache.blocked_cycles::no_targets 107 # number of cycles access was blocked
907 system.cpu.icache.blocked::no_mshrs 219 # number of cycles access was blocked
908 system.cpu.icache.blocked::no_targets 5 # number of cycles access was blocked
909 system.cpu.icache.avg_blocked_cycles::no_mshrs 86.543379 # average number of cycles each access was blocked
910 system.cpu.icache.avg_blocked_cycles::no_targets 21.400000 # average number of cycles each access was blocked
911 system.cpu.icache.writebacks::writebacks 447 # number of writebacks
912 system.cpu.icache.writebacks::total 447 # number of writebacks
913 system.cpu.icache.ReadReq_mshr_hits::cpu.inst 240 # number of ReadReq MSHR hits
914 system.cpu.icache.ReadReq_mshr_hits::total 240 # number of ReadReq MSHR hits
915 system.cpu.icache.demand_mshr_hits::cpu.inst 240 # number of demand (read+write) MSHR hits
916 system.cpu.icache.demand_mshr_hits::total 240 # number of demand (read+write) MSHR hits
917 system.cpu.icache.overall_mshr_hits::cpu.inst 240 # number of overall MSHR hits
918 system.cpu.icache.overall_mshr_hits::total 240 # number of overall MSHR hits
919 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 905 # number of ReadReq MSHR misses
920 system.cpu.icache.ReadReq_mshr_misses::total 905 # number of ReadReq MSHR misses
921 system.cpu.icache.demand_mshr_misses::cpu.inst 905 # number of demand (read+write) MSHR misses
922 system.cpu.icache.demand_mshr_misses::total 905 # number of demand (read+write) MSHR misses
923 system.cpu.icache.overall_mshr_misses::cpu.inst 905 # number of overall MSHR misses
924 system.cpu.icache.overall_mshr_misses::total 905 # number of overall MSHR misses
925 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 49734485 # number of ReadReq MSHR miss cycles
926 system.cpu.icache.ReadReq_mshr_miss_latency::total 49734485 # number of ReadReq MSHR miss cycles
927 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 49734485 # number of demand (read+write) MSHR miss cycles
928 system.cpu.icache.demand_mshr_miss_latency::total 49734485 # number of demand (read+write) MSHR miss cycles
929 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 49734485 # number of overall MSHR miss cycles
930 system.cpu.icache.overall_mshr_miss_latency::total 49734485 # number of overall MSHR miss cycles
931 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for ReadReq accesses
932 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000028 # mshr miss rate for ReadReq accesses
933 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for demand accesses
934 system.cpu.icache.demand_mshr_miss_rate::total 0.000028 # mshr miss rate for demand accesses
935 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for overall accesses
936 system.cpu.icache.overall_mshr_miss_rate::total 0.000028 # mshr miss rate for overall accesses
937 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54955.232044 # average ReadReq mshr miss latency
938 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54955.232044 # average ReadReq mshr miss latency
939 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54955.232044 # average overall mshr miss latency
940 system.cpu.icache.demand_avg_mshr_miss_latency::total 54955.232044 # average overall mshr miss latency
941 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54955.232044 # average overall mshr miss latency
942 system.cpu.icache.overall_avg_mshr_miss_latency::total 54955.232044 # average overall mshr miss latency
943 system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states
944 system.cpu.l2cache.prefetcher.num_hwpf_issued 4981065 # number of hwpf issued
945 system.cpu.l2cache.prefetcher.pfIdentified 5296247 # number of prefetch candidates identified
946 system.cpu.l2cache.prefetcher.pfBufferHit 274020 # number of redundant prefetches already in prefetch queue
947 system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
948 system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
949 system.cpu.l2cache.prefetcher.pfSpanPage 14074841 # number of prefetches not generated due to page crossing
950 system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states
951 system.cpu.l2cache.tags.replacements 248 # number of replacements
952 system.cpu.l2cache.tags.tagsinuse 11235.818499 # Cycle average of tags in use
953 system.cpu.l2cache.tags.total_refs 5318374 # Total number of references to valid blocks.
954 system.cpu.l2cache.tags.sampled_refs 14915 # Sample count of references to valid blocks.
955 system.cpu.l2cache.tags.avg_refs 356.578880 # Average number of references to valid blocks.
956 system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
957 system.cpu.l2cache.tags.occ_blocks::writebacks 11061.516911 # Average occupied blocks per requestor
958 system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 174.301588 # Average occupied blocks per requestor
959 system.cpu.l2cache.tags.occ_percent::writebacks 0.675141 # Average percentage of cache occupancy
960 system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.010639 # Average percentage of cache occupancy
961 system.cpu.l2cache.tags.occ_percent::total 0.685780 # Average percentage of cache occupancy
962 system.cpu.l2cache.tags.occ_task_id_blocks::1022 181 # Occupied blocks per task id
963 system.cpu.l2cache.tags.occ_task_id_blocks::1024 14486 # Occupied blocks per task id
964 system.cpu.l2cache.tags.age_task_id_blocks_1022::1 8 # Occupied blocks per task id
965 system.cpu.l2cache.tags.age_task_id_blocks_1022::2 3 # Occupied blocks per task id
966 system.cpu.l2cache.tags.age_task_id_blocks_1022::3 2 # Occupied blocks per task id
967 system.cpu.l2cache.tags.age_task_id_blocks_1022::4 168 # Occupied blocks per task id
968 system.cpu.l2cache.tags.age_task_id_blocks_1024::0 469 # Occupied blocks per task id
969 system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3489 # Occupied blocks per task id
970 system.cpu.l2cache.tags.age_task_id_blocks_1024::2 9544 # Occupied blocks per task id
971 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 100 # Occupied blocks per task id
972 system.cpu.l2cache.tags.age_task_id_blocks_1024::4 884 # Occupied blocks per task id
973 system.cpu.l2cache.tags.occ_task_id_percent::1022 0.011047 # Percentage of cache occupancy per task id
974 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.884155 # Percentage of cache occupancy per task id
975 system.cpu.l2cache.tags.tag_accesses 180510207 # Number of tag accesses
976 system.cpu.l2cache.tags.data_accesses 180510207 # Number of data accesses
977 system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states
978 system.cpu.l2cache.WritebackDirty_hits::writebacks 5451171 # number of WritebackDirty hits
979 system.cpu.l2cache.WritebackDirty_hits::total 5451171 # number of WritebackDirty hits
980 system.cpu.l2cache.WritebackClean_hits::writebacks 17033 # number of WritebackClean hits
981 system.cpu.l2cache.WritebackClean_hits::total 17033 # number of WritebackClean hits
982 system.cpu.l2cache.ReadExReq_hits::cpu.data 226019 # number of ReadExReq hits
983 system.cpu.l2cache.ReadExReq_hits::total 226019 # number of ReadExReq hits
984 system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 210 # number of ReadCleanReq hits
985 system.cpu.l2cache.ReadCleanReq_hits::total 210 # number of ReadCleanReq hits
986 system.cpu.l2cache.ReadSharedReq_hits::cpu.data 5243562 # number of ReadSharedReq hits
987 system.cpu.l2cache.ReadSharedReq_hits::total 5243562 # number of ReadSharedReq hits
988 system.cpu.l2cache.demand_hits::cpu.inst 210 # number of demand (read+write) hits
989 system.cpu.l2cache.demand_hits::cpu.data 5469581 # number of demand (read+write) hits
990 system.cpu.l2cache.demand_hits::total 5469791 # number of demand (read+write) hits
991 system.cpu.l2cache.overall_hits::cpu.inst 210 # number of overall hits
992 system.cpu.l2cache.overall_hits::cpu.data 5469581 # number of overall hits
993 system.cpu.l2cache.overall_hits::total 5469791 # number of overall hits
994 system.cpu.l2cache.UpgradeReq_misses::cpu.data 3 # number of UpgradeReq misses
995 system.cpu.l2cache.UpgradeReq_misses::total 3 # number of UpgradeReq misses
996 system.cpu.l2cache.ReadExReq_misses::cpu.data 500 # number of ReadExReq misses
997 system.cpu.l2cache.ReadExReq_misses::total 500 # number of ReadExReq misses
998 system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 695 # number of ReadCleanReq misses
999 system.cpu.l2cache.ReadCleanReq_misses::total 695 # number of ReadCleanReq misses
1000 system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1065 # number of ReadSharedReq misses
1001 system.cpu.l2cache.ReadSharedReq_misses::total 1065 # number of ReadSharedReq misses
1002 system.cpu.l2cache.demand_misses::cpu.inst 695 # number of demand (read+write) misses
1003 system.cpu.l2cache.demand_misses::cpu.data 1565 # number of demand (read+write) misses
1004 system.cpu.l2cache.demand_misses::total 2260 # number of demand (read+write) misses
1005 system.cpu.l2cache.overall_misses::cpu.inst 695 # number of overall misses
1006 system.cpu.l2cache.overall_misses::cpu.data 1565 # number of overall misses
1007 system.cpu.l2cache.overall_misses::total 2260 # number of overall misses
1008 system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 59500 # number of UpgradeReq miss cycles
1009 system.cpu.l2cache.UpgradeReq_miss_latency::total 59500 # number of UpgradeReq miss cycles
1010 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 41259500 # number of ReadExReq miss cycles
1011 system.cpu.l2cache.ReadExReq_miss_latency::total 41259500 # number of ReadExReq miss cycles
1012 system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 47414000 # number of ReadCleanReq miss cycles
1013 system.cpu.l2cache.ReadCleanReq_miss_latency::total 47414000 # number of ReadCleanReq miss cycles
1014 system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 71274500 # number of ReadSharedReq miss cycles
1015 system.cpu.l2cache.ReadSharedReq_miss_latency::total 71274500 # number of ReadSharedReq miss cycles
1016 system.cpu.l2cache.demand_miss_latency::cpu.inst 47414000 # number of demand (read+write) miss cycles
1017 system.cpu.l2cache.demand_miss_latency::cpu.data 112534000 # number of demand (read+write) miss cycles
1018 system.cpu.l2cache.demand_miss_latency::total 159948000 # number of demand (read+write) miss cycles
1019 system.cpu.l2cache.overall_miss_latency::cpu.inst 47414000 # number of overall miss cycles
1020 system.cpu.l2cache.overall_miss_latency::cpu.data 112534000 # number of overall miss cycles
1021 system.cpu.l2cache.overall_miss_latency::total 159948000 # number of overall miss cycles
1022 system.cpu.l2cache.WritebackDirty_accesses::writebacks 5451171 # number of WritebackDirty accesses(hits+misses)
1023 system.cpu.l2cache.WritebackDirty_accesses::total 5451171 # number of WritebackDirty accesses(hits+misses)
1024 system.cpu.l2cache.WritebackClean_accesses::writebacks 17033 # number of WritebackClean accesses(hits+misses)
1025 system.cpu.l2cache.WritebackClean_accesses::total 17033 # number of WritebackClean accesses(hits+misses)
1026 system.cpu.l2cache.UpgradeReq_accesses::cpu.data 3 # number of UpgradeReq accesses(hits+misses)
1027 system.cpu.l2cache.UpgradeReq_accesses::total 3 # number of UpgradeReq accesses(hits+misses)
1028 system.cpu.l2cache.ReadExReq_accesses::cpu.data 226519 # number of ReadExReq accesses(hits+misses)
1029 system.cpu.l2cache.ReadExReq_accesses::total 226519 # number of ReadExReq accesses(hits+misses)
1030 system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 905 # number of ReadCleanReq accesses(hits+misses)
1031 system.cpu.l2cache.ReadCleanReq_accesses::total 905 # number of ReadCleanReq accesses(hits+misses)
1032 system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 5244627 # number of ReadSharedReq accesses(hits+misses)
1033 system.cpu.l2cache.ReadSharedReq_accesses::total 5244627 # number of ReadSharedReq accesses(hits+misses)
1034 system.cpu.l2cache.demand_accesses::cpu.inst 905 # number of demand (read+write) accesses
1035 system.cpu.l2cache.demand_accesses::cpu.data 5471146 # number of demand (read+write) accesses
1036 system.cpu.l2cache.demand_accesses::total 5472051 # number of demand (read+write) accesses
1037 system.cpu.l2cache.overall_accesses::cpu.inst 905 # number of overall (read+write) accesses
1038 system.cpu.l2cache.overall_accesses::cpu.data 5471146 # number of overall (read+write) accesses
1039 system.cpu.l2cache.overall_accesses::total 5472051 # number of overall (read+write) accesses
1040 system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses
1041 system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses
1042 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.002207 # miss rate for ReadExReq accesses
1043 system.cpu.l2cache.ReadExReq_miss_rate::total 0.002207 # miss rate for ReadExReq accesses
1044 system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.767956 # miss rate for ReadCleanReq accesses
1045 system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.767956 # miss rate for ReadCleanReq accesses
1046 system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000203 # miss rate for ReadSharedReq accesses
1047 system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000203 # miss rate for ReadSharedReq accesses
1048 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.767956 # miss rate for demand accesses
1049 system.cpu.l2cache.demand_miss_rate::cpu.data 0.000286 # miss rate for demand accesses
1050 system.cpu.l2cache.demand_miss_rate::total 0.000413 # miss rate for demand accesses
1051 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.767956 # miss rate for overall accesses
1052 system.cpu.l2cache.overall_miss_rate::cpu.data 0.000286 # miss rate for overall accesses
1053 system.cpu.l2cache.overall_miss_rate::total 0.000413 # miss rate for overall accesses
1054 system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 19833.333333 # average UpgradeReq miss latency
1055 system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 19833.333333 # average UpgradeReq miss latency
1056 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 82519 # average ReadExReq miss latency
1057 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 82519 # average ReadExReq miss latency
1058 system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 68221.582734 # average ReadCleanReq miss latency
1059 system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 68221.582734 # average ReadCleanReq miss latency
1060 system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 66924.413146 # average ReadSharedReq miss latency
1061 system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 66924.413146 # average ReadSharedReq miss latency
1062 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68221.582734 # average overall miss latency
1063 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71906.709265 # average overall miss latency
1064 system.cpu.l2cache.demand_avg_miss_latency::total 70773.451327 # average overall miss latency
1065 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68221.582734 # average overall miss latency
1066 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71906.709265 # average overall miss latency
1067 system.cpu.l2cache.overall_avg_miss_latency::total 70773.451327 # average overall miss latency
1068 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1069 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1070 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
1071 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1072 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1073 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1074 system.cpu.l2cache.unused_prefetches 7 # number of HardPF blocks evicted w/o reference
1075 system.cpu.l2cache.writebacks::writebacks 175 # number of writebacks
1076 system.cpu.l2cache.writebacks::total 175 # number of writebacks
1077 system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 158 # number of ReadExReq MSHR hits
1078 system.cpu.l2cache.ReadExReq_mshr_hits::total 158 # number of ReadExReq MSHR hits
1079 system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits
1080 system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits
1081 system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 37 # number of ReadSharedReq MSHR hits
1082 system.cpu.l2cache.ReadSharedReq_mshr_hits::total 37 # number of ReadSharedReq MSHR hits
1083 system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
1084 system.cpu.l2cache.demand_mshr_hits::cpu.data 195 # number of demand (read+write) MSHR hits
1085 system.cpu.l2cache.demand_mshr_hits::total 196 # number of demand (read+write) MSHR hits
1086 system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
1087 system.cpu.l2cache.overall_mshr_hits::cpu.data 195 # number of overall MSHR hits
1088 system.cpu.l2cache.overall_mshr_hits::total 196 # number of overall MSHR hits
1089 system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 316084 # number of HardPFReq MSHR misses
1090 system.cpu.l2cache.HardPFReq_mshr_misses::total 316084 # number of HardPFReq MSHR misses
1091 system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 3 # number of UpgradeReq MSHR misses
1092 system.cpu.l2cache.UpgradeReq_mshr_misses::total 3 # number of UpgradeReq MSHR misses
1093 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 342 # number of ReadExReq MSHR misses
1094 system.cpu.l2cache.ReadExReq_mshr_misses::total 342 # number of ReadExReq MSHR misses
1095 system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 694 # number of ReadCleanReq MSHR misses
1096 system.cpu.l2cache.ReadCleanReq_mshr_misses::total 694 # number of ReadCleanReq MSHR misses
1097 system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1028 # number of ReadSharedReq MSHR misses
1098 system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1028 # number of ReadSharedReq MSHR misses
1099 system.cpu.l2cache.demand_mshr_misses::cpu.inst 694 # number of demand (read+write) MSHR misses
1100 system.cpu.l2cache.demand_mshr_misses::cpu.data 1370 # number of demand (read+write) MSHR misses
1101 system.cpu.l2cache.demand_mshr_misses::total 2064 # number of demand (read+write) MSHR misses
1102 system.cpu.l2cache.overall_mshr_misses::cpu.inst 694 # number of overall MSHR misses
1103 system.cpu.l2cache.overall_mshr_misses::cpu.data 1370 # number of overall MSHR misses
1104 system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 316084 # number of overall MSHR misses
1105 system.cpu.l2cache.overall_mshr_misses::total 318148 # number of overall MSHR misses
1106 system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 852614747 # number of HardPFReq MSHR miss cycles
1107 system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 852614747 # number of HardPFReq MSHR miss cycles
1108 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 41500 # number of UpgradeReq MSHR miss cycles
1109 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 41500 # number of UpgradeReq MSHR miss cycles
1110 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 32745000 # number of ReadExReq MSHR miss cycles
1111 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 32745000 # number of ReadExReq MSHR miss cycles
1112 system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 43196500 # number of ReadCleanReq MSHR miss cycles
1113 system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 43196500 # number of ReadCleanReq MSHR miss cycles
1114 system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 63614500 # number of ReadSharedReq MSHR miss cycles
1115 system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 63614500 # number of ReadSharedReq MSHR miss cycles
1116 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 43196500 # number of demand (read+write) MSHR miss cycles
1117 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 96359500 # number of demand (read+write) MSHR miss cycles
1118 system.cpu.l2cache.demand_mshr_miss_latency::total 139556000 # number of demand (read+write) MSHR miss cycles
1119 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 43196500 # number of overall MSHR miss cycles
1120 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 96359500 # number of overall MSHR miss cycles
1121 system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 852614747 # number of overall MSHR miss cycles
1122 system.cpu.l2cache.overall_mshr_miss_latency::total 992170747 # number of overall MSHR miss cycles
1123 system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
1124 system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
1125 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses
1126 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
1127 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001510 # mshr miss rate for ReadExReq accesses
1128 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001510 # mshr miss rate for ReadExReq accesses
1129 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.766851 # mshr miss rate for ReadCleanReq accesses
1130 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.766851 # mshr miss rate for ReadCleanReq accesses
1131 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000196 # mshr miss rate for ReadSharedReq accesses
1132 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000196 # mshr miss rate for ReadSharedReq accesses
1133 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.766851 # mshr miss rate for demand accesses
1134 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.000250 # mshr miss rate for demand accesses
1135 system.cpu.l2cache.demand_mshr_miss_rate::total 0.000377 # mshr miss rate for demand accesses
1136 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.766851 # mshr miss rate for overall accesses
1137 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.000250 # mshr miss rate for overall accesses
1138 system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses
1139 system.cpu.l2cache.overall_mshr_miss_rate::total 0.058141 # mshr miss rate for overall accesses
1140 system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 2697.430895 # average HardPFReq mshr miss latency
1141 system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 2697.430895 # average HardPFReq mshr miss latency
1142 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 13833.333333 # average UpgradeReq mshr miss latency
1143 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 13833.333333 # average UpgradeReq mshr miss latency
1144 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 95745.614035 # average ReadExReq mshr miss latency
1145 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 95745.614035 # average ReadExReq mshr miss latency
1146 system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 62242.795389 # average ReadCleanReq mshr miss latency
1147 system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 62242.795389 # average ReadCleanReq mshr miss latency
1148 system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 61881.809339 # average ReadSharedReq mshr miss latency
1149 system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 61881.809339 # average ReadSharedReq mshr miss latency
1150 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62242.795389 # average overall mshr miss latency
1151 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70335.401460 # average overall mshr miss latency
1152 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67614.341085 # average overall mshr miss latency
1153 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62242.795389 # average overall mshr miss latency
1154 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70335.401460 # average overall mshr miss latency
1155 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 2697.430895 # average overall mshr miss latency
1156 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 3118.582380 # average overall mshr miss latency
1157 system.cpu.toL2Bus.snoop_filter.tot_requests 10943135 # Total number of requests made to the snoop filter.
1158 system.cpu.toL2Bus.snoop_filter.hit_single_requests 5471097 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1159 system.cpu.toL2Bus.snoop_filter.hit_multi_requests 2877 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1160 system.cpu.toL2Bus.snoop_filter.tot_snoops 303361 # Total number of snoops made to the snoop filter.
1161 system.cpu.toL2Bus.snoop_filter.hit_single_snoops 302576 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1162 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 785 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
1163 system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states
1164 system.cpu.toL2Bus.trans_dist::ReadResp 5245531 # Transaction distribution
1165 system.cpu.toL2Bus.trans_dist::WritebackDirty 5451346 # Transaction distribution
1166 system.cpu.toL2Bus.trans_dist::WritebackClean 19910 # Transaction distribution
1167 system.cpu.toL2Bus.trans_dist::CleanEvict 1794 # Transaction distribution
1168 system.cpu.toL2Bus.trans_dist::HardPFReq 317966 # Transaction distribution
1169 system.cpu.toL2Bus.trans_dist::HardPFResp 4 # Transaction distribution
1170 system.cpu.toL2Bus.trans_dist::UpgradeReq 3 # Transaction distribution
1171 system.cpu.toL2Bus.trans_dist::UpgradeResp 3 # Transaction distribution
1172 system.cpu.toL2Bus.trans_dist::ReadExReq 226519 # Transaction distribution
1173 system.cpu.toL2Bus.trans_dist::ReadExResp 226519 # Transaction distribution
1174 system.cpu.toL2Bus.trans_dist::ReadCleanReq 905 # Transaction distribution
1175 system.cpu.toL2Bus.trans_dist::ReadSharedReq 5244627 # Transaction distribution
1176 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2256 # Packet count per connected master and slave (bytes)
1177 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 16412936 # Packet count per connected master and slave (bytes)
1178 system.cpu.toL2Bus.pkt_count::total 16415192 # Packet count per connected master and slave (bytes)
1179 system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 86464 # Cumulative packet size per connected master and slave (bytes)
1180 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 700274176 # Cumulative packet size per connected master and slave (bytes)
1181 system.cpu.toL2Bus.pkt_size::total 700360640 # Cumulative packet size per connected master and slave (bytes)
1182 system.cpu.toL2Bus.snoops 319939 # Total snoops (count)
1183 system.cpu.toL2Bus.snoopTraffic 11456 # Total snoop traffic (bytes)
1184 system.cpu.toL2Bus.snoop_fanout::samples 5791989 # Request fanout histogram
1185 system.cpu.toL2Bus.snoop_fanout::mean 0.053010 # Request fanout histogram
1186 system.cpu.toL2Bus.snoop_fanout::stdev 0.224658 # Request fanout histogram
1187 system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1188 system.cpu.toL2Bus.snoop_fanout::0 5485738 94.71% 94.71% # Request fanout histogram
1189 system.cpu.toL2Bus.snoop_fanout::1 305466 5.27% 99.99% # Request fanout histogram
1190 system.cpu.toL2Bus.snoop_fanout::2 785 0.01% 100.00% # Request fanout histogram
1191 system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1192 system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
1193 system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
1194 system.cpu.toL2Bus.snoop_fanout::total 5791989 # Request fanout histogram
1195 system.cpu.toL2Bus.reqLayer0.occupancy 10942648515 # Layer occupancy (ticks)
1196 system.cpu.toL2Bus.reqLayer0.utilization 18.8 # Layer utilization (%)
1197 system.cpu.toL2Bus.snoopLayer0.occupancy 6019 # Layer occupancy (ticks)
1198 system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
1199 system.cpu.toL2Bus.respLayer0.occupancy 1357497 # Layer occupancy (ticks)
1200 system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
1201 system.cpu.toL2Bus.respLayer1.occupancy 8206724991 # Layer occupancy (ticks)
1202 system.cpu.toL2Bus.respLayer1.utilization 14.1 # Layer utilization (%)
1203 system.membus.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states
1204 system.membus.trans_dist::ReadResp 16175 # Transaction distribution
1205 system.membus.trans_dist::WritebackDirty 175 # Transaction distribution
1206 system.membus.trans_dist::CleanEvict 63 # Transaction distribution
1207 system.membus.trans_dist::UpgradeReq 4 # Transaction distribution
1208 system.membus.trans_dist::ReadExReq 341 # Transaction distribution
1209 system.membus.trans_dist::ReadExResp 341 # Transaction distribution
1210 system.membus.trans_dist::ReadSharedReq 16176 # Transaction distribution
1211 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 33275 # Packet count per connected master and slave (bytes)
1212 system.membus.pkt_count::total 33275 # Packet count per connected master and slave (bytes)
1213 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1068224 # Cumulative packet size per connected master and slave (bytes)
1214 system.membus.pkt_size::total 1068224 # Cumulative packet size per connected master and slave (bytes)
1215 system.membus.snoops 0 # Total snoops (count)
1216 system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
1217 system.membus.snoop_fanout::samples 16759 # Request fanout histogram
1218 system.membus.snoop_fanout::mean 0 # Request fanout histogram
1219 system.membus.snoop_fanout::stdev 0 # Request fanout histogram
1220 system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1221 system.membus.snoop_fanout::0 16759 100.00% 100.00% # Request fanout histogram
1222 system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
1223 system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1224 system.membus.snoop_fanout::min_value 0 # Request fanout histogram
1225 system.membus.snoop_fanout::max_value 0 # Request fanout histogram
1226 system.membus.snoop_fanout::total 16759 # Request fanout histogram
1227 system.membus.reqLayer0.occupancy 27529285 # Layer occupancy (ticks)
1228 system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
1229 system.membus.respLayer1.occupancy 86434816 # Layer occupancy (ticks)
1230 system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
1232 ---------- End Simulation Statistics ----------
projects / gem5.git / blob