2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.026923 # Number of seconds simulated
4 sim_ticks 26922512500 # Number of ticks simulated
5 final_tick 26922512500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 143955 # Simulator instruction rate (inst/s)
8 host_op_rate 144989 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 42782119 # Simulator tick rate (ticks/s)
10 host_mem_usage 446112 # Number of bytes of host memory used
11 host_seconds 629.29 # Real time elapsed on the host
12 sim_insts 90589798 # Number of instructions simulated
13 sim_ops 91240351 # Number of ops (including micro ops) simulated
14 system.voltage_domain.voltage 1 # Voltage in Volts
15 system.clk_domain.clock 1000 # Clock period in ticks
16 system.physmem.bytes_read::cpu.inst 45248 # Number of bytes read from this memory
17 system.physmem.bytes_read::cpu.data 947648 # Number of bytes read from this memory
18 system.physmem.bytes_read::total 992896 # Number of bytes read from this memory
19 system.physmem.bytes_inst_read::cpu.inst 45248 # Number of instructions bytes read from this memory
20 system.physmem.bytes_inst_read::total 45248 # Number of instructions bytes read from this memory
21 system.physmem.num_reads::cpu.inst 707 # Number of read requests responded to by this memory
22 system.physmem.num_reads::cpu.data 14807 # Number of read requests responded to by this memory
23 system.physmem.num_reads::total 15514 # Number of read requests responded to by this memory
24 system.physmem.bw_read::cpu.inst 1680675 # Total read bandwidth from this memory (bytes/s)
25 system.physmem.bw_read::cpu.data 35199092 # Total read bandwidth from this memory (bytes/s)
26 system.physmem.bw_read::total 36879767 # Total read bandwidth from this memory (bytes/s)
27 system.physmem.bw_inst_read::cpu.inst 1680675 # Instruction read bandwidth from this memory (bytes/s)
28 system.physmem.bw_inst_read::total 1680675 # Instruction read bandwidth from this memory (bytes/s)
29 system.physmem.bw_total::cpu.inst 1680675 # Total bandwidth to/from this memory (bytes/s)
30 system.physmem.bw_total::cpu.data 35199092 # Total bandwidth to/from this memory (bytes/s)
31 system.physmem.bw_total::total 36879767 # Total bandwidth to/from this memory (bytes/s)
32 system.physmem.readReqs 15514 # Number of read requests accepted
33 system.physmem.writeReqs 0 # Number of write requests accepted
34 system.physmem.readBursts 15514 # Number of DRAM read bursts, including those serviced by the write queue
35 system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
36 system.physmem.bytesReadDRAM 992896 # Total number of bytes read from DRAM
37 system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
38 system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
39 system.physmem.bytesReadSys 992896 # Total read bytes from the system interface side
40 system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
41 system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
42 system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
43 system.physmem.neitherReadNorWriteReqs 1 # Number of requests that are neither read nor write
44 system.physmem.perBankRdBursts::0 988 # Per bank write bursts
45 system.physmem.perBankRdBursts::1 886 # Per bank write bursts
46 system.physmem.perBankRdBursts::2 942 # Per bank write bursts
47 system.physmem.perBankRdBursts::3 1028 # Per bank write bursts
48 system.physmem.perBankRdBursts::4 1050 # Per bank write bursts
49 system.physmem.perBankRdBursts::5 1105 # Per bank write bursts
50 system.physmem.perBankRdBursts::6 1078 # Per bank write bursts
51 system.physmem.perBankRdBursts::7 1078 # Per bank write bursts
52 system.physmem.perBankRdBursts::8 1024 # Per bank write bursts
53 system.physmem.perBankRdBursts::9 956 # Per bank write bursts
54 system.physmem.perBankRdBursts::10 938 # Per bank write bursts
55 system.physmem.perBankRdBursts::11 899 # Per bank write bursts
56 system.physmem.perBankRdBursts::12 904 # Per bank write bursts
57 system.physmem.perBankRdBursts::13 865 # Per bank write bursts
58 system.physmem.perBankRdBursts::14 877 # Per bank write bursts
59 system.physmem.perBankRdBursts::15 896 # Per bank write bursts
60 system.physmem.perBankWrBursts::0 0 # Per bank write bursts
61 system.physmem.perBankWrBursts::1 0 # Per bank write bursts
62 system.physmem.perBankWrBursts::2 0 # Per bank write bursts
63 system.physmem.perBankWrBursts::3 0 # Per bank write bursts
64 system.physmem.perBankWrBursts::4 0 # Per bank write bursts
65 system.physmem.perBankWrBursts::5 0 # Per bank write bursts
66 system.physmem.perBankWrBursts::6 0 # Per bank write bursts
67 system.physmem.perBankWrBursts::7 0 # Per bank write bursts
68 system.physmem.perBankWrBursts::8 0 # Per bank write bursts
69 system.physmem.perBankWrBursts::9 0 # Per bank write bursts
70 system.physmem.perBankWrBursts::10 0 # Per bank write bursts
71 system.physmem.perBankWrBursts::11 0 # Per bank write bursts
72 system.physmem.perBankWrBursts::12 0 # Per bank write bursts
73 system.physmem.perBankWrBursts::13 0 # Per bank write bursts
74 system.physmem.perBankWrBursts::14 0 # Per bank write bursts
75 system.physmem.perBankWrBursts::15 0 # Per bank write bursts
76 system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
77 system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
78 system.physmem.totGap 26922312500 # Total gap between requests
79 system.physmem.readPktSize::0 0 # Read request sizes (log2)
80 system.physmem.readPktSize::1 0 # Read request sizes (log2)
81 system.physmem.readPktSize::2 0 # Read request sizes (log2)
82 system.physmem.readPktSize::3 0 # Read request sizes (log2)
83 system.physmem.readPktSize::4 0 # Read request sizes (log2)
84 system.physmem.readPktSize::5 0 # Read request sizes (log2)
85 system.physmem.readPktSize::6 15514 # Read request sizes (log2)
86 system.physmem.writePktSize::0 0 # Write request sizes (log2)
87 system.physmem.writePktSize::1 0 # Write request sizes (log2)
88 system.physmem.writePktSize::2 0 # Write request sizes (log2)
89 system.physmem.writePktSize::3 0 # Write request sizes (log2)
90 system.physmem.writePktSize::4 0 # Write request sizes (log2)
91 system.physmem.writePktSize::5 0 # Write request sizes (log2)
92 system.physmem.writePktSize::6 0 # Write request sizes (log2)
93 system.physmem.rdQLenPdf::0 10767 # What read queue length does an incoming req see
94 system.physmem.rdQLenPdf::1 4517 # What read queue length does an incoming req see
95 system.physmem.rdQLenPdf::2 211 # What read queue length does an incoming req see
96 system.physmem.rdQLenPdf::3 12 # What read queue length does an incoming req see
97 system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see
98 system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see
99 system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
100 system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
101 system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
102 system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
103 system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
104 system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
105 system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
106 system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
107 system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
108 system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
109 system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
110 system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
111 system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
112 system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
113 system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
114 system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
115 system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
116 system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
117 system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
118 system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
119 system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
120 system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
121 system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
122 system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
123 system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
124 system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
125 system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
126 system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
127 system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
128 system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
129 system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
130 system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
131 system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
132 system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
133 system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
134 system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
135 system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
136 system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
137 system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
138 system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
139 system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
140 system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
141 system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
142 system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
143 system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
144 system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
145 system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
146 system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
147 system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
148 system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
149 system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
150 system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
151 system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
152 system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
153 system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
154 system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
155 system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
156 system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
157 system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
158 system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
159 system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
160 system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
161 system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
162 system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
163 system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
164 system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
165 system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
166 system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
167 system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
168 system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
169 system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
170 system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
171 system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
172 system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
173 system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
174 system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
175 system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
176 system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
177 system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
178 system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
179 system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
180 system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
181 system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
182 system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
183 system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
184 system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
185 system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
186 system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
187 system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
188 system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
189 system.physmem.bytesPerActivate::samples 880 # Bytes accessed per row activation
190 system.physmem.bytesPerActivate::mean 935.927273 # Bytes accessed per row activation
191 system.physmem.bytesPerActivate::gmean 827.602742 # Bytes accessed per row activation
192 system.physmem.bytesPerActivate::stdev 262.440032 # Bytes accessed per row activation
193 system.physmem.bytesPerActivate::0-127 41 4.66% 4.66% # Bytes accessed per row activation
194 system.physmem.bytesPerActivate::128-255 26 2.95% 7.61% # Bytes accessed per row activation
195 system.physmem.bytesPerActivate::256-383 13 1.48% 9.09% # Bytes accessed per row activation
196 system.physmem.bytesPerActivate::384-511 4 0.45% 9.55% # Bytes accessed per row activation
197 system.physmem.bytesPerActivate::512-639 5 0.57% 10.11% # Bytes accessed per row activation
198 system.physmem.bytesPerActivate::640-767 2 0.23% 10.34% # Bytes accessed per row activation
199 system.physmem.bytesPerActivate::768-895 2 0.23% 10.57% # Bytes accessed per row activation
200 system.physmem.bytesPerActivate::896-1023 1 0.11% 10.68% # Bytes accessed per row activation
201 system.physmem.bytesPerActivate::1024-1151 786 89.32% 100.00% # Bytes accessed per row activation
202 system.physmem.bytesPerActivate::total 880 # Bytes accessed per row activation
203 system.physmem.totQLat 108095000 # Total ticks spent queuing
204 system.physmem.totMemAccLat 369557500 # Total ticks spent from burst creation until serviced by the DRAM
205 system.physmem.totBusLat 77570000 # Total ticks spent in databus transfers
206 system.physmem.totBankLat 183892500 # Total ticks spent accessing banks
207 system.physmem.avgQLat 6967.58 # Average queueing delay per DRAM burst
208 system.physmem.avgBankLat 11853.33 # Average bank access latency per DRAM burst
209 system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
210 system.physmem.avgMemAccLat 23820.90 # Average memory access latency per DRAM burst
211 system.physmem.avgRdBW 36.88 # Average DRAM read bandwidth in MiByte/s
212 system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
213 system.physmem.avgRdBWSys 36.88 # Average system read bandwidth in MiByte/s
214 system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
215 system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
216 system.physmem.busUtil 0.29 # Data bus utilization in percentage
217 system.physmem.busUtilRead 0.29 # Data bus utilization in percentage for reads
218 system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
219 system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing
220 system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
221 system.physmem.readRowHits 14141 # Number of row buffer hits during reads
222 system.physmem.writeRowHits 0 # Number of row buffer hits during writes
223 system.physmem.readRowHitRate 91.15 # Row buffer hit rate for reads
224 system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
225 system.physmem.avgGap 1735355.97 # Average gap between requests
226 system.physmem.pageHitRate 91.15 # Row buffer hit rate, read and write combined
227 system.physmem.prechargeAllPercent 1.09 # Percentage of time for which DRAM has all the banks in precharge state
228 system.membus.throughput 36879767 # Throughput (bytes/s)
229 system.membus.trans_dist::ReadReq 976 # Transaction distribution
230 system.membus.trans_dist::ReadResp 976 # Transaction distribution
231 system.membus.trans_dist::UpgradeReq 1 # Transaction distribution
232 system.membus.trans_dist::UpgradeResp 1 # Transaction distribution
233 system.membus.trans_dist::ReadExReq 14538 # Transaction distribution
234 system.membus.trans_dist::ReadExResp 14538 # Transaction distribution
235 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31030 # Packet count per connected master and slave (bytes)
236 system.membus.pkt_count::total 31030 # Packet count per connected master and slave (bytes)
237 system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 992896 # Cumulative packet size per connected master and slave (bytes)
238 system.membus.tot_pkt_size::total 992896 # Cumulative packet size per connected master and slave (bytes)
239 system.membus.data_through_bus 992896 # Total data (bytes)
240 system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
241 system.membus.reqLayer0.occupancy 19225500 # Layer occupancy (ticks)
242 system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
243 system.membus.respLayer1.occupancy 144897999 # Layer occupancy (ticks)
244 system.membus.respLayer1.utilization 0.5 # Layer utilization (%)
245 system.cpu_clk_domain.clock 500 # Clock period in ticks
246 system.cpu.branchPred.lookups 26688187 # Number of BP lookups
247 system.cpu.branchPred.condPredicted 22005801 # Number of conditional branches predicted
248 system.cpu.branchPred.condIncorrect 842567 # Number of conditional branches incorrect
249 system.cpu.branchPred.BTBLookups 11378681 # Number of BTB lookups
250 system.cpu.branchPred.BTBHits 11285656 # Number of BTB hits
251 system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
252 system.cpu.branchPred.BTBHitPct 99.182462 # BTB Hit Percentage
253 system.cpu.branchPred.usedRAS 69960 # Number of times the RAS was used to get a target.
254 system.cpu.branchPred.RASInCorrect 176 # Number of incorrect RAS predictions.
255 system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
256 system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
257 system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
258 system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
259 system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
260 system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
261 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
262 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
263 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
264 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
265 system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
266 system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
267 system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
268 system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
269 system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
270 system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
271 system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
272 system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
273 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
274 system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
275 system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
276 system.cpu.dtb.inst_hits 0 # ITB inst hits
277 system.cpu.dtb.inst_misses 0 # ITB inst misses
278 system.cpu.dtb.read_hits 0 # DTB read hits
279 system.cpu.dtb.read_misses 0 # DTB read misses
280 system.cpu.dtb.write_hits 0 # DTB write hits
281 system.cpu.dtb.write_misses 0 # DTB write misses
282 system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
283 system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
284 system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
285 system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
286 system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
287 system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
288 system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
289 system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
290 system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
291 system.cpu.dtb.read_accesses 0 # DTB read accesses
292 system.cpu.dtb.write_accesses 0 # DTB write accesses
293 system.cpu.dtb.inst_accesses 0 # ITB inst accesses
294 system.cpu.dtb.hits 0 # DTB hits
295 system.cpu.dtb.misses 0 # DTB misses
296 system.cpu.dtb.accesses 0 # DTB accesses
297 system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
298 system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
299 system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
300 system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
301 system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
302 system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
303 system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
304 system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
305 system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
306 system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
307 system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
308 system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
309 system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
310 system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
311 system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
312 system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
313 system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
314 system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
315 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
316 system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
317 system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
318 system.cpu.itb.inst_hits 0 # ITB inst hits
319 system.cpu.itb.inst_misses 0 # ITB inst misses
320 system.cpu.itb.read_hits 0 # DTB read hits
321 system.cpu.itb.read_misses 0 # DTB read misses
322 system.cpu.itb.write_hits 0 # DTB write hits
323 system.cpu.itb.write_misses 0 # DTB write misses
324 system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
325 system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
326 system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
327 system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
328 system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
329 system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
330 system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
331 system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
332 system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
333 system.cpu.itb.read_accesses 0 # DTB read accesses
334 system.cpu.itb.write_accesses 0 # DTB write accesses
335 system.cpu.itb.inst_accesses 0 # ITB inst accesses
336 system.cpu.itb.hits 0 # DTB hits
337 system.cpu.itb.misses 0 # DTB misses
338 system.cpu.itb.accesses 0 # DTB accesses
339 system.cpu.workload.num_syscalls 442 # Number of system calls
340 system.cpu.numCycles 53845026 # number of cpu cycles simulated
341 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
342 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
343 system.cpu.fetch.icacheStallCycles 14173388 # Number of cycles fetch is stalled on an Icache miss
344 system.cpu.fetch.Insts 127901014 # Number of instructions fetch has processed
345 system.cpu.fetch.Branches 26688187 # Number of branches that fetch encountered
346 system.cpu.fetch.predictedBranches 11355616 # Number of branches that fetch has predicted taken
347 system.cpu.fetch.Cycles 24038968 # Number of cycles fetch has run and was not squashing or blocked
348 system.cpu.fetch.SquashCycles 4766662 # Number of cycles fetch has spent squashing
349 system.cpu.fetch.BlockedCycles 11320590 # Number of cycles fetch has spent blocked
350 system.cpu.fetch.MiscStallCycles 107 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
351 system.cpu.fetch.PendingTrapStallCycles 8 # Number of stall cycles due to pending traps
352 system.cpu.fetch.IcacheWaitRetryStallCycles 29 # Number of stall cycles due to full MSHR
353 system.cpu.fetch.CacheLines 13845523 # Number of cache lines fetched
354 system.cpu.fetch.IcacheSquashes 330018 # Number of outstanding Icache misses that were squashed
355 system.cpu.fetch.rateDist::samples 53440501 # Number of instructions fetched each cycle (Total)
356 system.cpu.fetch.rateDist::mean 2.409803 # Number of instructions fetched each cycle (Total)
357 system.cpu.fetch.rateDist::stdev 3.214653 # Number of instructions fetched each cycle (Total)
358 system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
359 system.cpu.fetch.rateDist::0 29439765 55.09% 55.09% # Number of instructions fetched each cycle (Total)
360 system.cpu.fetch.rateDist::1 3390250 6.34% 61.43% # Number of instructions fetched each cycle (Total)
361 system.cpu.fetch.rateDist::2 2029247 3.80% 65.23% # Number of instructions fetched each cycle (Total)
362 system.cpu.fetch.rateDist::3 1554755 2.91% 68.14% # Number of instructions fetched each cycle (Total)
363 system.cpu.fetch.rateDist::4 1667292 3.12% 71.26% # Number of instructions fetched each cycle (Total)
364 system.cpu.fetch.rateDist::5 2920236 5.46% 76.72% # Number of instructions fetched each cycle (Total)
365 system.cpu.fetch.rateDist::6 1512043 2.83% 79.55% # Number of instructions fetched each cycle (Total)
366 system.cpu.fetch.rateDist::7 1089860 2.04% 81.59% # Number of instructions fetched each cycle (Total)
367 system.cpu.fetch.rateDist::8 9837053 18.41% 100.00% # Number of instructions fetched each cycle (Total)
368 system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
369 system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
370 system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
371 system.cpu.fetch.rateDist::total 53440501 # Number of instructions fetched each cycle (Total)
372 system.cpu.fetch.branchRate 0.495648 # Number of branch fetches per cycle
373 system.cpu.fetch.rate 2.375354 # Number of inst fetches per cycle
374 system.cpu.decode.IdleCycles 16937222 # Number of cycles decode is idle
375 system.cpu.decode.BlockedCycles 9166719 # Number of cycles decode is blocked
376 system.cpu.decode.RunCycles 22408314 # Number of cycles decode is running
377 system.cpu.decode.UnblockCycles 1029433 # Number of cycles decode is unblocking
378 system.cpu.decode.SquashCycles 3898813 # Number of cycles decode is squashing
379 system.cpu.decode.BranchResolved 4444354 # Number of times decode resolved a branch
380 system.cpu.decode.BranchMispred 8681 # Number of times decode detected a branch misprediction
381 system.cpu.decode.DecodedInsts 126084070 # Number of instructions handled by decode
382 system.cpu.decode.SquashedInsts 42675 # Number of squashed instructions handled by decode
383 system.cpu.rename.SquashCycles 3898813 # Number of cycles rename is squashing
384 system.cpu.rename.IdleCycles 18718559 # Number of cycles rename is idle
385 system.cpu.rename.BlockCycles 3593311 # Number of cycles rename is blocking
386 system.cpu.rename.serializeStallCycles 188330 # count of cycles rename stalled for serializing inst
387 system.cpu.rename.RunCycles 21554671 # Number of cycles rename is running
388 system.cpu.rename.UnblockCycles 5486817 # Number of cycles rename is unblocking
389 system.cpu.rename.RenamedInsts 123168222 # Number of instructions processed by rename
390 system.cpu.rename.ROBFullEvents 14 # Number of times rename has blocked due to ROB full
391 system.cpu.rename.IQFullEvents 424808 # Number of times rename has blocked due to IQ full
392 system.cpu.rename.LSQFullEvents 4599857 # Number of times rename has blocked due to LSQ full
393 system.cpu.rename.FullRegisterEvents 1460 # Number of times there has been no free registers
394 system.cpu.rename.RenamedOperands 143625263 # Number of destination operands rename has renamed
395 system.cpu.rename.RenameLookups 536555031 # Number of register rename lookups that rename has made
396 system.cpu.rename.int_rename_lookups 500037832 # Number of integer rename lookups
397 system.cpu.rename.fp_rename_lookups 718 # Number of floating rename lookups
398 system.cpu.rename.CommittedMaps 107414186 # Number of HB maps that are committed
399 system.cpu.rename.UndoneMaps 36211077 # Number of HB maps that are undone due to squashing
400 system.cpu.rename.serializingInsts 4609 # count of serializing insts renamed
401 system.cpu.rename.tempSerializingInsts 4607 # count of temporary serializing insts renamed
402 system.cpu.rename.skidInsts 12545622 # count of insts added to the skid buffer
403 system.cpu.memDep0.insertedLoads 29481569 # Number of loads inserted to the mem dependence unit.
404 system.cpu.memDep0.insertedStores 5520172 # Number of stores inserted to the mem dependence unit.
405 system.cpu.memDep0.conflictingLoads 2131780 # Number of conflicting loads.
406 system.cpu.memDep0.conflictingStores 1278964 # Number of conflicting stores.
407 system.cpu.iq.iqInstsAdded 118183319 # Number of instructions added to the IQ (excludes non-spec)
408 system.cpu.iq.iqNonSpecInstsAdded 8477 # Number of non-speculative instructions added to the IQ
409 system.cpu.iq.iqInstsIssued 105169429 # Number of instructions issued
410 system.cpu.iq.iqSquashedInstsIssued 79348 # Number of squashed instructions issued
411 system.cpu.iq.iqSquashedInstsExamined 26754797 # Number of squashed instructions iterated over during squash; mainly for profiling
412 system.cpu.iq.iqSquashedOperandsExamined 65616265 # Number of squashed operands that are examined and possibly removed from graph
413 system.cpu.iq.iqSquashedNonSpecRemoved 259 # Number of squashed non-spec instructions that were removed
414 system.cpu.iq.issued_per_cycle::samples 53440501 # Number of insts issued each cycle
415 system.cpu.iq.issued_per_cycle::mean 1.967972 # Number of insts issued each cycle
416 system.cpu.iq.issued_per_cycle::stdev 1.909350 # Number of insts issued each cycle
417 system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
418 system.cpu.iq.issued_per_cycle::0 15384800 28.79% 28.79% # Number of insts issued each cycle
419 system.cpu.iq.issued_per_cycle::1 11651642 21.80% 50.59% # Number of insts issued each cycle
420 system.cpu.iq.issued_per_cycle::2 8259769 15.46% 66.05% # Number of insts issued each cycle
421 system.cpu.iq.issued_per_cycle::3 6813523 12.75% 78.80% # Number of insts issued each cycle
422 system.cpu.iq.issued_per_cycle::4 4933870 9.23% 88.03% # Number of insts issued each cycle
423 system.cpu.iq.issued_per_cycle::5 2968386 5.55% 93.58% # Number of insts issued each cycle
424 system.cpu.iq.issued_per_cycle::6 2461371 4.61% 98.19% # Number of insts issued each cycle
425 system.cpu.iq.issued_per_cycle::7 525076 0.98% 99.17% # Number of insts issued each cycle
426 system.cpu.iq.issued_per_cycle::8 442064 0.83% 100.00% # Number of insts issued each cycle
427 system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
428 system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
429 system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
430 system.cpu.iq.issued_per_cycle::total 53440501 # Number of insts issued each cycle
431 system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
432 system.cpu.iq.fu_full::IntAlu 46222 6.98% 6.98% # attempts to use FU when none available
433 system.cpu.iq.fu_full::IntMult 26 0.00% 6.98% # attempts to use FU when none available
434 system.cpu.iq.fu_full::IntDiv 0 0.00% 6.98% # attempts to use FU when none available
435 system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.98% # attempts to use FU when none available
436 system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.98% # attempts to use FU when none available
437 system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.98% # attempts to use FU when none available
438 system.cpu.iq.fu_full::FloatMult 0 0.00% 6.98% # attempts to use FU when none available
439 system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.98% # attempts to use FU when none available
440 system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.98% # attempts to use FU when none available
441 system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.98% # attempts to use FU when none available
442 system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.98% # attempts to use FU when none available
443 system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.98% # attempts to use FU when none available
444 system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.98% # attempts to use FU when none available
445 system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.98% # attempts to use FU when none available
446 system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.98% # attempts to use FU when none available
447 system.cpu.iq.fu_full::SimdMult 0 0.00% 6.98% # attempts to use FU when none available
448 system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.98% # attempts to use FU when none available
449 system.cpu.iq.fu_full::SimdShift 0 0.00% 6.98% # attempts to use FU when none available
450 system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.98% # attempts to use FU when none available
451 system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.98% # attempts to use FU when none available
452 system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.98% # attempts to use FU when none available
453 system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.98% # attempts to use FU when none available
454 system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.98% # attempts to use FU when none available
455 system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.98% # attempts to use FU when none available
456 system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.98% # attempts to use FU when none available
457 system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.98% # attempts to use FU when none available
458 system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.98% # attempts to use FU when none available
459 system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.98% # attempts to use FU when none available
460 system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.98% # attempts to use FU when none available
461 system.cpu.iq.fu_full::MemRead 339934 51.34% 58.33% # attempts to use FU when none available
462 system.cpu.iq.fu_full::MemWrite 275932 41.67% 100.00% # attempts to use FU when none available
463 system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
464 system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
465 system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
466 system.cpu.iq.FU_type_0::IntAlu 74431142 70.77% 70.77% # Type of FU issued
467 system.cpu.iq.FU_type_0::IntMult 10980 0.01% 70.78% # Type of FU issued
468 system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.78% # Type of FU issued
469 system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.78% # Type of FU issued
470 system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.78% # Type of FU issued
471 system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.78% # Type of FU issued
472 system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.78% # Type of FU issued
473 system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.78% # Type of FU issued
474 system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.78% # Type of FU issued
475 system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.78% # Type of FU issued
476 system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.78% # Type of FU issued
477 system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.78% # Type of FU issued
478 system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.78% # Type of FU issued
479 system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.78% # Type of FU issued
480 system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.78% # Type of FU issued
481 system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.78% # Type of FU issued
482 system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.78% # Type of FU issued
483 system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.78% # Type of FU issued
484 system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.78% # Type of FU issued
485 system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.78% # Type of FU issued
486 system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.78% # Type of FU issued
487 system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.78% # Type of FU issued
488 system.cpu.iq.FU_type_0::SimdFloatCmp 1 0.00% 70.78% # Type of FU issued
489 system.cpu.iq.FU_type_0::SimdFloatCvt 132 0.00% 70.78% # Type of FU issued
490 system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.78% # Type of FU issued
491 system.cpu.iq.FU_type_0::SimdFloatMisc 172 0.00% 70.78% # Type of FU issued
492 system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.78% # Type of FU issued
493 system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 70.78% # Type of FU issued
494 system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.78% # Type of FU issued
495 system.cpu.iq.FU_type_0::MemRead 25611933 24.35% 95.14% # Type of FU issued
496 system.cpu.iq.FU_type_0::MemWrite 5115067 4.86% 100.00% # Type of FU issued
497 system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
498 system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
499 system.cpu.iq.FU_type_0::total 105169429 # Type of FU issued
500 system.cpu.iq.rate 1.953187 # Inst issue rate
501 system.cpu.iq.fu_busy_cnt 662114 # FU busy when requested
502 system.cpu.iq.fu_busy_rate 0.006296 # FU busy rate (busy events/executed inst)
503 system.cpu.iq.int_inst_queue_reads 264520145 # Number of integer instruction queue reads
504 system.cpu.iq.int_inst_queue_writes 144951370 # Number of integer instruction queue writes
505 system.cpu.iq.int_inst_queue_wakeup_accesses 102696867 # Number of integer instruction queue wakeup accesses
506 system.cpu.iq.fp_inst_queue_reads 676 # Number of floating instruction queue reads
507 system.cpu.iq.fp_inst_queue_writes 925 # Number of floating instruction queue writes
508 system.cpu.iq.fp_inst_queue_wakeup_accesses 287 # Number of floating instruction queue wakeup accesses
509 system.cpu.iq.int_alu_accesses 105831206 # Number of integer alu accesses
510 system.cpu.iq.fp_alu_accesses 337 # Number of floating point alu accesses
511 system.cpu.iew.lsq.thread0.forwLoads 441415 # Number of loads that had data forwarded from stores
512 system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
513 system.cpu.iew.lsq.thread0.squashedLoads 6907603 # Number of loads squashed
514 system.cpu.iew.lsq.thread0.ignoredResponses 6432 # Number of memory responses ignored because the instruction is squashed
515 system.cpu.iew.lsq.thread0.memOrderViolation 6446 # Number of memory ordering violations
516 system.cpu.iew.lsq.thread0.squashedStores 775328 # Number of stores squashed
517 system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
518 system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
519 system.cpu.iew.lsq.thread0.rescheduledLoads 2 # Number of loads that were rescheduled
520 system.cpu.iew.lsq.thread0.cacheBlocked 31602 # Number of times an access to memory failed due to the cache being blocked
521 system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
522 system.cpu.iew.iewSquashCycles 3898813 # Number of cycles IEW is squashing
523 system.cpu.iew.iewBlockCycles 959371 # Number of cycles IEW is blocking
524 system.cpu.iew.iewUnblockCycles 127029 # Number of cycles IEW is unblocking
525 system.cpu.iew.iewDispatchedInsts 118204490 # Number of instructions dispatched to IQ
526 system.cpu.iew.iewDispSquashedInsts 309594 # Number of squashed instructions skipped by dispatch
527 system.cpu.iew.iewDispLoadInsts 29481569 # Number of dispatched load instructions
528 system.cpu.iew.iewDispStoreInsts 5520172 # Number of dispatched store instructions
529 system.cpu.iew.iewDispNonSpecInsts 4589 # Number of dispatched non-speculative instructions
530 system.cpu.iew.iewIQFullEvents 66074 # Number of times the IQ has become full, causing a stall
531 system.cpu.iew.iewLSQFullEvents 6711 # Number of times the LSQ has become full, causing a stall
532 system.cpu.iew.memOrderViolationEvents 6446 # Number of memory order violations
533 system.cpu.iew.predictedTakenIncorrect 446623 # Number of branches that were predicted taken incorrectly
534 system.cpu.iew.predictedNotTakenIncorrect 445838 # Number of branches that were predicted not taken incorrectly
535 system.cpu.iew.branchMispredicts 892461 # Number of branch mispredicts detected at execute
536 system.cpu.iew.iewExecutedInsts 104194994 # Number of executed instructions
537 system.cpu.iew.iewExecLoadInsts 25292197 # Number of load instructions executed
538 system.cpu.iew.iewExecSquashedInsts 974435 # Number of squashed instructions skipped in execute
539 system.cpu.iew.exec_swp 0 # number of swp insts executed
540 system.cpu.iew.exec_nop 12694 # number of nop insts executed
541 system.cpu.iew.exec_refs 30350924 # number of memory reference insts executed
542 system.cpu.iew.exec_branches 21328461 # Number of branches executed
543 system.cpu.iew.exec_stores 5058727 # Number of stores executed
544 system.cpu.iew.exec_rate 1.935090 # Inst execution rate
545 system.cpu.iew.wb_sent 102975092 # cumulative count of insts sent to commit
546 system.cpu.iew.wb_count 102697154 # cumulative count of insts written-back
547 system.cpu.iew.wb_producers 62242577 # num instructions producing a value
548 system.cpu.iew.wb_consumers 104291686 # num instructions consuming a value
549 system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
550 system.cpu.iew.wb_rate 1.907273 # insts written-back per cycle
551 system.cpu.iew.wb_fanout 0.596812 # average fanout of values written-back
552 system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
553 system.cpu.commit.commitSquashedInsts 26954537 # The number of squashed insts skipped by commit
554 system.cpu.commit.commitNonSpecStalls 8218 # The number of times commit has been forced to stall to communicate backwards
555 system.cpu.commit.branchMispredicts 833969 # The number of times a branch was mispredicted
556 system.cpu.commit.committed_per_cycle::samples 49541688 # Number of insts commited each cycle
557 system.cpu.commit.committed_per_cycle::mean 1.841943 # Number of insts commited each cycle
558 system.cpu.commit.committed_per_cycle::stdev 2.539958 # Number of insts commited each cycle
559 system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
560 system.cpu.commit.committed_per_cycle::0 20036957 40.44% 40.44% # Number of insts commited each cycle
561 system.cpu.commit.committed_per_cycle::1 13159597 26.56% 67.01% # Number of insts commited each cycle
562 system.cpu.commit.committed_per_cycle::2 4169965 8.42% 75.42% # Number of insts commited each cycle
563 system.cpu.commit.committed_per_cycle::3 3431804 6.93% 82.35% # Number of insts commited each cycle
564 system.cpu.commit.committed_per_cycle::4 1536139 3.10% 85.45% # Number of insts commited each cycle
565 system.cpu.commit.committed_per_cycle::5 734203 1.48% 86.93% # Number of insts commited each cycle
566 system.cpu.commit.committed_per_cycle::6 944467 1.91% 88.84% # Number of insts commited each cycle
567 system.cpu.commit.committed_per_cycle::7 252800 0.51% 89.35% # Number of insts commited each cycle
568 system.cpu.commit.committed_per_cycle::8 5275756 10.65% 100.00% # Number of insts commited each cycle
569 system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
570 system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
571 system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
572 system.cpu.commit.committed_per_cycle::total 49541688 # Number of insts commited each cycle
573 system.cpu.commit.committedInsts 90602407 # Number of instructions committed
574 system.cpu.commit.committedOps 91252960 # Number of ops (including micro ops) committed
575 system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
576 system.cpu.commit.refs 27318810 # Number of memory references committed
577 system.cpu.commit.loads 22573966 # Number of loads committed
578 system.cpu.commit.membars 3888 # Number of memory barriers committed
579 system.cpu.commit.branches 18732304 # Number of branches committed
580 system.cpu.commit.fp_insts 48 # Number of committed floating point instructions.
581 system.cpu.commit.int_insts 72525674 # Number of committed integer instructions.
582 system.cpu.commit.function_calls 56148 # Number of function calls committed.
583 system.cpu.commit.bw_lim_events 5275756 # number cycles where commit BW limit reached
584 system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
585 system.cpu.rob.rob_reads 162467695 # The number of ROB reads
586 system.cpu.rob.rob_writes 240333520 # The number of ROB writes
587 system.cpu.timesIdled 46195 # Number of times that the entire CPU went into an idle state and unscheduled itself
588 system.cpu.idleCycles 404525 # Total number of cycles that the CPU has spent unscheduled due to idling
589 system.cpu.committedInsts 90589798 # Number of Instructions Simulated
590 system.cpu.committedOps 91240351 # Number of Ops (including micro ops) Simulated
591 system.cpu.committedInsts_total 90589798 # Number of Instructions Simulated
592 system.cpu.cpi 0.594383 # CPI: Cycles Per Instruction
593 system.cpu.cpi_total 0.594383 # CPI: Total CPI of All Threads
594 system.cpu.ipc 1.682417 # IPC: Instructions Per Cycle
595 system.cpu.ipc_total 1.682417 # IPC: Total IPC of All Threads
596 system.cpu.int_regfile_reads 495621667 # number of integer regfile reads
597 system.cpu.int_regfile_writes 120557380 # number of integer regfile writes
598 system.cpu.fp_regfile_reads 149 # number of floating regfile reads
599 system.cpu.fp_regfile_writes 361 # number of floating regfile writes
600 system.cpu.misc_regfile_reads 29211256 # number of misc regfile reads
601 system.cpu.misc_regfile_writes 7784 # number of misc regfile writes
602 system.cpu.toL2Bus.throughput 4495994050 # Throughput (bytes/s)
603 system.cpu.toL2Bus.trans_dist::ReadReq 904654 # Transaction distribution
604 system.cpu.toL2Bus.trans_dist::ReadResp 904654 # Transaction distribution
605 system.cpu.toL2Bus.trans_dist::Writeback 942932 # Transaction distribution
606 system.cpu.toL2Bus.trans_dist::UpgradeReq 1 # Transaction distribution
607 system.cpu.toL2Bus.trans_dist::UpgradeResp 1 # Transaction distribution
608 system.cpu.toL2Bus.trans_dist::ReadExReq 43718 # Transaction distribution
609 system.cpu.toL2Bus.trans_dist::ReadExResp 43718 # Transaction distribution
610 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1467 # Packet count per connected master and slave (bytes)
611 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2838210 # Packet count per connected master and slave (bytes)
612 system.cpu.toL2Bus.pkt_count::total 2839677 # Packet count per connected master and slave (bytes)
613 system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 46912 # Cumulative packet size per connected master and slave (bytes)
614 system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 120996480 # Cumulative packet size per connected master and slave (bytes)
615 system.cpu.toL2Bus.tot_pkt_size::total 121043392 # Cumulative packet size per connected master and slave (bytes)
616 system.cpu.toL2Bus.data_through_bus 121043392 # Total data (bytes)
617 system.cpu.toL2Bus.snoop_data_through_bus 64 # Total snoop data (bytes)
618 system.cpu.toL2Bus.reqLayer0.occupancy 1888584500 # Layer occupancy (ticks)
619 system.cpu.toL2Bus.reqLayer0.utilization 7.0 # Layer utilization (%)
620 system.cpu.toL2Bus.respLayer0.occupancy 1216499 # Layer occupancy (ticks)
621 system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
622 system.cpu.toL2Bus.respLayer1.occupancy 1423941741 # Layer occupancy (ticks)
623 system.cpu.toL2Bus.respLayer1.utilization 5.3 # Layer utilization (%)
624 system.cpu.icache.tags.replacements 3 # number of replacements
625 system.cpu.icache.tags.tagsinuse 632.458088 # Cycle average of tags in use
626 system.cpu.icache.tags.total_refs 13844537 # Total number of references to valid blocks.
627 system.cpu.icache.tags.sampled_refs 733 # Sample count of references to valid blocks.
628 system.cpu.icache.tags.avg_refs 18887.499318 # Average number of references to valid blocks.
629 system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
630 system.cpu.icache.tags.occ_blocks::cpu.inst 632.458088 # Average occupied blocks per requestor
631 system.cpu.icache.tags.occ_percent::cpu.inst 0.308817 # Average percentage of cache occupancy
632 system.cpu.icache.tags.occ_percent::total 0.308817 # Average percentage of cache occupancy
633 system.cpu.icache.tags.occ_task_id_blocks::1024 730 # Occupied blocks per task id
634 system.cpu.icache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id
635 system.cpu.icache.tags.age_task_id_blocks_1024::2 14 # Occupied blocks per task id
636 system.cpu.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id
637 system.cpu.icache.tags.age_task_id_blocks_1024::4 676 # Occupied blocks per task id
638 system.cpu.icache.tags.occ_task_id_percent::1024 0.356445 # Percentage of cache occupancy per task id
639 system.cpu.icache.tags.tag_accesses 27691778 # Number of tag accesses
640 system.cpu.icache.tags.data_accesses 27691778 # Number of data accesses
641 system.cpu.icache.ReadReq_hits::cpu.inst 13844537 # number of ReadReq hits
642 system.cpu.icache.ReadReq_hits::total 13844537 # number of ReadReq hits
643 system.cpu.icache.demand_hits::cpu.inst 13844537 # number of demand (read+write) hits
644 system.cpu.icache.demand_hits::total 13844537 # number of demand (read+write) hits
645 system.cpu.icache.overall_hits::cpu.inst 13844537 # number of overall hits
646 system.cpu.icache.overall_hits::total 13844537 # number of overall hits
647 system.cpu.icache.ReadReq_misses::cpu.inst 985 # number of ReadReq misses
648 system.cpu.icache.ReadReq_misses::total 985 # number of ReadReq misses
649 system.cpu.icache.demand_misses::cpu.inst 985 # number of demand (read+write) misses
650 system.cpu.icache.demand_misses::total 985 # number of demand (read+write) misses
651 system.cpu.icache.overall_misses::cpu.inst 985 # number of overall misses
652 system.cpu.icache.overall_misses::total 985 # number of overall misses
653 system.cpu.icache.ReadReq_miss_latency::cpu.inst 65965748 # number of ReadReq miss cycles
654 system.cpu.icache.ReadReq_miss_latency::total 65965748 # number of ReadReq miss cycles
655 system.cpu.icache.demand_miss_latency::cpu.inst 65965748 # number of demand (read+write) miss cycles
656 system.cpu.icache.demand_miss_latency::total 65965748 # number of demand (read+write) miss cycles
657 system.cpu.icache.overall_miss_latency::cpu.inst 65965748 # number of overall miss cycles
658 system.cpu.icache.overall_miss_latency::total 65965748 # number of overall miss cycles
659 system.cpu.icache.ReadReq_accesses::cpu.inst 13845522 # number of ReadReq accesses(hits+misses)
660 system.cpu.icache.ReadReq_accesses::total 13845522 # number of ReadReq accesses(hits+misses)
661 system.cpu.icache.demand_accesses::cpu.inst 13845522 # number of demand (read+write) accesses
662 system.cpu.icache.demand_accesses::total 13845522 # number of demand (read+write) accesses
663 system.cpu.icache.overall_accesses::cpu.inst 13845522 # number of overall (read+write) accesses
664 system.cpu.icache.overall_accesses::total 13845522 # number of overall (read+write) accesses
665 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000071 # miss rate for ReadReq accesses
666 system.cpu.icache.ReadReq_miss_rate::total 0.000071 # miss rate for ReadReq accesses
667 system.cpu.icache.demand_miss_rate::cpu.inst 0.000071 # miss rate for demand accesses
668 system.cpu.icache.demand_miss_rate::total 0.000071 # miss rate for demand accesses
669 system.cpu.icache.overall_miss_rate::cpu.inst 0.000071 # miss rate for overall accesses
670 system.cpu.icache.overall_miss_rate::total 0.000071 # miss rate for overall accesses
671 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 66970.302538 # average ReadReq miss latency
672 system.cpu.icache.ReadReq_avg_miss_latency::total 66970.302538 # average ReadReq miss latency
673 system.cpu.icache.demand_avg_miss_latency::cpu.inst 66970.302538 # average overall miss latency
674 system.cpu.icache.demand_avg_miss_latency::total 66970.302538 # average overall miss latency
675 system.cpu.icache.overall_avg_miss_latency::cpu.inst 66970.302538 # average overall miss latency
676 system.cpu.icache.overall_avg_miss_latency::total 66970.302538 # average overall miss latency
677 system.cpu.icache.blocked_cycles::no_mshrs 596 # number of cycles access was blocked
678 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
679 system.cpu.icache.blocked::no_mshrs 12 # number of cycles access was blocked
680 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
681 system.cpu.icache.avg_blocked_cycles::no_mshrs 49.666667 # average number of cycles each access was blocked
682 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
683 system.cpu.icache.fast_writes 0 # number of fast writes performed
684 system.cpu.icache.cache_copies 0 # number of cache copies performed
685 system.cpu.icache.ReadReq_mshr_hits::cpu.inst 251 # number of ReadReq MSHR hits
686 system.cpu.icache.ReadReq_mshr_hits::total 251 # number of ReadReq MSHR hits
687 system.cpu.icache.demand_mshr_hits::cpu.inst 251 # number of demand (read+write) MSHR hits
688 system.cpu.icache.demand_mshr_hits::total 251 # number of demand (read+write) MSHR hits
689 system.cpu.icache.overall_mshr_hits::cpu.inst 251 # number of overall MSHR hits
690 system.cpu.icache.overall_mshr_hits::total 251 # number of overall MSHR hits
691 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 734 # number of ReadReq MSHR misses
692 system.cpu.icache.ReadReq_mshr_misses::total 734 # number of ReadReq MSHR misses
693 system.cpu.icache.demand_mshr_misses::cpu.inst 734 # number of demand (read+write) MSHR misses
694 system.cpu.icache.demand_mshr_misses::total 734 # number of demand (read+write) MSHR misses
695 system.cpu.icache.overall_mshr_misses::cpu.inst 734 # number of overall MSHR misses
696 system.cpu.icache.overall_mshr_misses::total 734 # number of overall MSHR misses
697 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 51030750 # number of ReadReq MSHR miss cycles
698 system.cpu.icache.ReadReq_mshr_miss_latency::total 51030750 # number of ReadReq MSHR miss cycles
699 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 51030750 # number of demand (read+write) MSHR miss cycles
700 system.cpu.icache.demand_mshr_miss_latency::total 51030750 # number of demand (read+write) MSHR miss cycles
701 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 51030750 # number of overall MSHR miss cycles
702 system.cpu.icache.overall_mshr_miss_latency::total 51030750 # number of overall MSHR miss cycles
703 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for ReadReq accesses
704 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000053 # mshr miss rate for ReadReq accesses
705 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for demand accesses
706 system.cpu.icache.demand_mshr_miss_rate::total 0.000053 # mshr miss rate for demand accesses
707 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for overall accesses
708 system.cpu.icache.overall_mshr_miss_rate::total 0.000053 # mshr miss rate for overall accesses
709 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69524.182561 # average ReadReq mshr miss latency
710 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69524.182561 # average ReadReq mshr miss latency
711 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69524.182561 # average overall mshr miss latency
712 system.cpu.icache.demand_avg_mshr_miss_latency::total 69524.182561 # average overall mshr miss latency
713 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69524.182561 # average overall mshr miss latency
714 system.cpu.icache.overall_avg_mshr_miss_latency::total 69524.182561 # average overall mshr miss latency
715 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
716 system.cpu.l2cache.tags.replacements 0 # number of replacements
717 system.cpu.l2cache.tags.tagsinuse 10726.796939 # Cycle average of tags in use
718 system.cpu.l2cache.tags.total_refs 1831454 # Total number of references to valid blocks.
719 system.cpu.l2cache.tags.sampled_refs 15497 # Sample count of references to valid blocks.
720 system.cpu.l2cache.tags.avg_refs 118.181196 # Average number of references to valid blocks.
721 system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
722 system.cpu.l2cache.tags.occ_blocks::writebacks 9879.688406 # Average occupied blocks per requestor
723 system.cpu.l2cache.tags.occ_blocks::cpu.inst 618.475949 # Average occupied blocks per requestor
724 system.cpu.l2cache.tags.occ_blocks::cpu.data 228.632584 # Average occupied blocks per requestor
725 system.cpu.l2cache.tags.occ_percent::writebacks 0.301504 # Average percentage of cache occupancy
726 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.018874 # Average percentage of cache occupancy
727 system.cpu.l2cache.tags.occ_percent::cpu.data 0.006977 # Average percentage of cache occupancy
728 system.cpu.l2cache.tags.occ_percent::total 0.327356 # Average percentage of cache occupancy
729 system.cpu.l2cache.tags.occ_task_id_blocks::1024 15497 # Occupied blocks per task id
730 system.cpu.l2cache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id
731 system.cpu.l2cache.tags.age_task_id_blocks_1024::1 27 # Occupied blocks per task id
732 system.cpu.l2cache.tags.age_task_id_blocks_1024::2 514 # Occupied blocks per task id
733 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1300 # Occupied blocks per task id
734 system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13616 # Occupied blocks per task id
735 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.472931 # Percentage of cache occupancy per task id
736 system.cpu.l2cache.tags.tag_accesses 15189647 # Number of tag accesses
737 system.cpu.l2cache.tags.data_accesses 15189647 # Number of data accesses
738 system.cpu.l2cache.ReadReq_hits::cpu.inst 25 # number of ReadReq hits
739 system.cpu.l2cache.ReadReq_hits::cpu.data 903641 # number of ReadReq hits
740 system.cpu.l2cache.ReadReq_hits::total 903666 # number of ReadReq hits
741 system.cpu.l2cache.Writeback_hits::writebacks 942932 # number of Writeback hits
742 system.cpu.l2cache.Writeback_hits::total 942932 # number of Writeback hits
743 system.cpu.l2cache.ReadExReq_hits::cpu.data 29180 # number of ReadExReq hits
744 system.cpu.l2cache.ReadExReq_hits::total 29180 # number of ReadExReq hits
745 system.cpu.l2cache.demand_hits::cpu.inst 25 # number of demand (read+write) hits
746 system.cpu.l2cache.demand_hits::cpu.data 932821 # number of demand (read+write) hits
747 system.cpu.l2cache.demand_hits::total 932846 # number of demand (read+write) hits
748 system.cpu.l2cache.overall_hits::cpu.inst 25 # number of overall hits
749 system.cpu.l2cache.overall_hits::cpu.data 932821 # number of overall hits
750 system.cpu.l2cache.overall_hits::total 932846 # number of overall hits
751 system.cpu.l2cache.ReadReq_misses::cpu.inst 708 # number of ReadReq misses
752 system.cpu.l2cache.ReadReq_misses::cpu.data 279 # number of ReadReq misses
753 system.cpu.l2cache.ReadReq_misses::total 987 # number of ReadReq misses
754 system.cpu.l2cache.UpgradeReq_misses::cpu.data 1 # number of UpgradeReq misses
755 system.cpu.l2cache.UpgradeReq_misses::total 1 # number of UpgradeReq misses
756 system.cpu.l2cache.ReadExReq_misses::cpu.data 14538 # number of ReadExReq misses
757 system.cpu.l2cache.ReadExReq_misses::total 14538 # number of ReadExReq misses
758 system.cpu.l2cache.demand_misses::cpu.inst 708 # number of demand (read+write) misses
759 system.cpu.l2cache.demand_misses::cpu.data 14817 # number of demand (read+write) misses
760 system.cpu.l2cache.demand_misses::total 15525 # number of demand (read+write) misses
761 system.cpu.l2cache.overall_misses::cpu.inst 708 # number of overall misses
762 system.cpu.l2cache.overall_misses::cpu.data 14817 # number of overall misses
763 system.cpu.l2cache.overall_misses::total 15525 # number of overall misses
764 system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 50040500 # number of ReadReq miss cycles
765 system.cpu.l2cache.ReadReq_miss_latency::cpu.data 21343000 # number of ReadReq miss cycles
766 system.cpu.l2cache.ReadReq_miss_latency::total 71383500 # number of ReadReq miss cycles
767 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 975716500 # number of ReadExReq miss cycles
768 system.cpu.l2cache.ReadExReq_miss_latency::total 975716500 # number of ReadExReq miss cycles
769 system.cpu.l2cache.demand_miss_latency::cpu.inst 50040500 # number of demand (read+write) miss cycles
770 system.cpu.l2cache.demand_miss_latency::cpu.data 997059500 # number of demand (read+write) miss cycles
771 system.cpu.l2cache.demand_miss_latency::total 1047100000 # number of demand (read+write) miss cycles
772 system.cpu.l2cache.overall_miss_latency::cpu.inst 50040500 # number of overall miss cycles
773 system.cpu.l2cache.overall_miss_latency::cpu.data 997059500 # number of overall miss cycles
774 system.cpu.l2cache.overall_miss_latency::total 1047100000 # number of overall miss cycles
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776 system.cpu.l2cache.ReadReq_accesses::cpu.data 903920 # number of ReadReq accesses(hits+misses)
777 system.cpu.l2cache.ReadReq_accesses::total 904653 # number of ReadReq accesses(hits+misses)
778 system.cpu.l2cache.Writeback_accesses::writebacks 942932 # number of Writeback accesses(hits+misses)
779 system.cpu.l2cache.Writeback_accesses::total 942932 # number of Writeback accesses(hits+misses)
780 system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1 # number of UpgradeReq accesses(hits+misses)
781 system.cpu.l2cache.UpgradeReq_accesses::total 1 # number of UpgradeReq accesses(hits+misses)
782 system.cpu.l2cache.ReadExReq_accesses::cpu.data 43718 # number of ReadExReq accesses(hits+misses)
783 system.cpu.l2cache.ReadExReq_accesses::total 43718 # number of ReadExReq accesses(hits+misses)
784 system.cpu.l2cache.demand_accesses::cpu.inst 733 # number of demand (read+write) accesses
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788 system.cpu.l2cache.overall_accesses::cpu.data 947638 # number of overall (read+write) accesses
789 system.cpu.l2cache.overall_accesses::total 948371 # number of overall (read+write) accesses
790 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.965894 # miss rate for ReadReq accesses
791 system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000309 # miss rate for ReadReq accesses
792 system.cpu.l2cache.ReadReq_miss_rate::total 0.001091 # miss rate for ReadReq accesses
793 system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses
794 system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses
795 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.332540 # miss rate for ReadExReq accesses
796 system.cpu.l2cache.ReadExReq_miss_rate::total 0.332540 # miss rate for ReadExReq accesses
797 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.965894 # miss rate for demand accesses
798 system.cpu.l2cache.demand_miss_rate::cpu.data 0.015636 # miss rate for demand accesses
799 system.cpu.l2cache.demand_miss_rate::total 0.016370 # miss rate for demand accesses
800 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.965894 # miss rate for overall accesses
801 system.cpu.l2cache.overall_miss_rate::cpu.data 0.015636 # miss rate for overall accesses
802 system.cpu.l2cache.overall_miss_rate::total 0.016370 # miss rate for overall accesses
803 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70678.672316 # average ReadReq miss latency
804 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76498.207885 # average ReadReq miss latency
805 system.cpu.l2cache.ReadReq_avg_miss_latency::total 72323.708207 # average ReadReq miss latency
806 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 67114.905764 # average ReadExReq miss latency
807 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67114.905764 # average ReadExReq miss latency
808 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70678.672316 # average overall miss latency
809 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 67291.590740 # average overall miss latency
810 system.cpu.l2cache.demand_avg_miss_latency::total 67446.054750 # average overall miss latency
811 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70678.672316 # average overall miss latency
812 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 67291.590740 # average overall miss latency
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814 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
815 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
816 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
817 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
818 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
819 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
820 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
821 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
822 system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits
823 system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 10 # number of ReadReq MSHR hits
824 system.cpu.l2cache.ReadReq_mshr_hits::total 11 # number of ReadReq MSHR hits
825 system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
826 system.cpu.l2cache.demand_mshr_hits::cpu.data 10 # number of demand (read+write) MSHR hits
827 system.cpu.l2cache.demand_mshr_hits::total 11 # number of demand (read+write) MSHR hits
828 system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
829 system.cpu.l2cache.overall_mshr_hits::cpu.data 10 # number of overall MSHR hits
830 system.cpu.l2cache.overall_mshr_hits::total 11 # number of overall MSHR hits
831 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 707 # number of ReadReq MSHR misses
832 system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 269 # number of ReadReq MSHR misses
833 system.cpu.l2cache.ReadReq_mshr_misses::total 976 # number of ReadReq MSHR misses
834 system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1 # number of UpgradeReq MSHR misses
835 system.cpu.l2cache.UpgradeReq_mshr_misses::total 1 # number of UpgradeReq MSHR misses
836 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14538 # number of ReadExReq MSHR misses
837 system.cpu.l2cache.ReadExReq_mshr_misses::total 14538 # number of ReadExReq MSHR misses
838 system.cpu.l2cache.demand_mshr_misses::cpu.inst 707 # number of demand (read+write) MSHR misses
839 system.cpu.l2cache.demand_mshr_misses::cpu.data 14807 # number of demand (read+write) MSHR misses
840 system.cpu.l2cache.demand_mshr_misses::total 15514 # number of demand (read+write) MSHR misses
841 system.cpu.l2cache.overall_mshr_misses::cpu.inst 707 # number of overall MSHR misses
842 system.cpu.l2cache.overall_mshr_misses::cpu.data 14807 # number of overall MSHR misses
843 system.cpu.l2cache.overall_mshr_misses::total 15514 # number of overall MSHR misses
844 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 41129750 # number of ReadReq MSHR miss cycles
845 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 17372750 # number of ReadReq MSHR miss cycles
846 system.cpu.l2cache.ReadReq_mshr_miss_latency::total 58502500 # number of ReadReq MSHR miss cycles
847 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 10001 # number of UpgradeReq MSHR miss cycles
848 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 10001 # number of UpgradeReq MSHR miss cycles
849 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 793837000 # number of ReadExReq MSHR miss cycles
850 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 793837000 # number of ReadExReq MSHR miss cycles
851 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 41129750 # number of demand (read+write) MSHR miss cycles
852 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 811209750 # number of demand (read+write) MSHR miss cycles
853 system.cpu.l2cache.demand_mshr_miss_latency::total 852339500 # number of demand (read+write) MSHR miss cycles
854 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 41129750 # number of overall MSHR miss cycles
855 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 811209750 # number of overall MSHR miss cycles
856 system.cpu.l2cache.overall_mshr_miss_latency::total 852339500 # number of overall MSHR miss cycles
857 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.964529 # mshr miss rate for ReadReq accesses
858 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000298 # mshr miss rate for ReadReq accesses
859 system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001079 # mshr miss rate for ReadReq accesses
860 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses
861 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
862 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.332540 # mshr miss rate for ReadExReq accesses
863 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.332540 # mshr miss rate for ReadExReq accesses
864 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.964529 # mshr miss rate for demand accesses
865 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015625 # mshr miss rate for demand accesses
866 system.cpu.l2cache.demand_mshr_miss_rate::total 0.016359 # mshr miss rate for demand accesses
867 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.964529 # mshr miss rate for overall accesses
868 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015625 # mshr miss rate for overall accesses
869 system.cpu.l2cache.overall_mshr_miss_rate::total 0.016359 # mshr miss rate for overall accesses
870 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58175.035361 # average ReadReq mshr miss latency
871 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64582.713755 # average ReadReq mshr miss latency
872 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59941.086066 # average ReadReq mshr miss latency
873 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency
874 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency
875 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54604.278443 # average ReadExReq mshr miss latency
876 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54604.278443 # average ReadExReq mshr miss latency
877 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58175.035361 # average overall mshr miss latency
878 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 54785.557507 # average overall mshr miss latency
879 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54940.021916 # average overall mshr miss latency
880 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58175.035361 # average overall mshr miss latency
881 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 54785.557507 # average overall mshr miss latency
882 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54940.021916 # average overall mshr miss latency
883 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
884 system.cpu.dcache.tags.replacements 943542 # number of replacements
885 system.cpu.dcache.tags.tagsinuse 3671.682953 # Cycle average of tags in use
886 system.cpu.dcache.tags.total_refs 28143982 # Total number of references to valid blocks.
887 system.cpu.dcache.tags.sampled_refs 947638 # Sample count of references to valid blocks.
888 system.cpu.dcache.tags.avg_refs 29.699086 # Average number of references to valid blocks.
889 system.cpu.dcache.tags.warmup_cycle 8008531250 # Cycle when the warmup percentage was hit.
890 system.cpu.dcache.tags.occ_blocks::cpu.data 3671.682953 # Average occupied blocks per requestor
891 system.cpu.dcache.tags.occ_percent::cpu.data 0.896407 # Average percentage of cache occupancy
892 system.cpu.dcache.tags.occ_percent::total 0.896407 # Average percentage of cache occupancy
893 system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
894 system.cpu.dcache.tags.age_task_id_blocks_1024::0 464 # Occupied blocks per task id
895 system.cpu.dcache.tags.age_task_id_blocks_1024::1 3129 # Occupied blocks per task id
896 system.cpu.dcache.tags.age_task_id_blocks_1024::2 503 # Occupied blocks per task id
897 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
898 system.cpu.dcache.tags.tag_accesses 59988388 # Number of tag accesses
899 system.cpu.dcache.tags.data_accesses 59988388 # Number of data accesses
900 system.cpu.dcache.ReadReq_hits::cpu.data 23603660 # number of ReadReq hits
901 system.cpu.dcache.ReadReq_hits::total 23603660 # number of ReadReq hits
902 system.cpu.dcache.WriteReq_hits::cpu.data 4532519 # number of WriteReq hits
903 system.cpu.dcache.WriteReq_hits::total 4532519 # number of WriteReq hits
904 system.cpu.dcache.LoadLockedReq_hits::cpu.data 3912 # number of LoadLockedReq hits
905 system.cpu.dcache.LoadLockedReq_hits::total 3912 # number of LoadLockedReq hits
906 system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits
907 system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits
908 system.cpu.dcache.demand_hits::cpu.data 28136179 # number of demand (read+write) hits
909 system.cpu.dcache.demand_hits::total 28136179 # number of demand (read+write) hits
910 system.cpu.dcache.overall_hits::cpu.data 28136179 # number of overall hits
911 system.cpu.dcache.overall_hits::total 28136179 # number of overall hits
912 system.cpu.dcache.ReadReq_misses::cpu.data 1173928 # number of ReadReq misses
913 system.cpu.dcache.ReadReq_misses::total 1173928 # number of ReadReq misses
914 system.cpu.dcache.WriteReq_misses::cpu.data 202462 # number of WriteReq misses
915 system.cpu.dcache.WriteReq_misses::total 202462 # number of WriteReq misses
916 system.cpu.dcache.LoadLockedReq_misses::cpu.data 7 # number of LoadLockedReq misses
917 system.cpu.dcache.LoadLockedReq_misses::total 7 # number of LoadLockedReq misses
918 system.cpu.dcache.demand_misses::cpu.data 1376390 # number of demand (read+write) misses
919 system.cpu.dcache.demand_misses::total 1376390 # number of demand (read+write) misses
920 system.cpu.dcache.overall_misses::cpu.data 1376390 # number of overall misses
921 system.cpu.dcache.overall_misses::total 1376390 # number of overall misses
922 system.cpu.dcache.ReadReq_miss_latency::cpu.data 13893768230 # number of ReadReq miss cycles
923 system.cpu.dcache.ReadReq_miss_latency::total 13893768230 # number of ReadReq miss cycles
924 system.cpu.dcache.WriteReq_miss_latency::cpu.data 8571552365 # number of WriteReq miss cycles
925 system.cpu.dcache.WriteReq_miss_latency::total 8571552365 # number of WriteReq miss cycles
926 system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 251500 # number of LoadLockedReq miss cycles
927 system.cpu.dcache.LoadLockedReq_miss_latency::total 251500 # number of LoadLockedReq miss cycles
928 system.cpu.dcache.demand_miss_latency::cpu.data 22465320595 # number of demand (read+write) miss cycles
929 system.cpu.dcache.demand_miss_latency::total 22465320595 # number of demand (read+write) miss cycles
930 system.cpu.dcache.overall_miss_latency::cpu.data 22465320595 # number of overall miss cycles
931 system.cpu.dcache.overall_miss_latency::total 22465320595 # number of overall miss cycles
932 system.cpu.dcache.ReadReq_accesses::cpu.data 24777588 # number of ReadReq accesses(hits+misses)
933 system.cpu.dcache.ReadReq_accesses::total 24777588 # number of ReadReq accesses(hits+misses)
934 system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses)
935 system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses)
936 system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3919 # number of LoadLockedReq accesses(hits+misses)
937 system.cpu.dcache.LoadLockedReq_accesses::total 3919 # number of LoadLockedReq accesses(hits+misses)
938 system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses)
939 system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses)
940 system.cpu.dcache.demand_accesses::cpu.data 29512569 # number of demand (read+write) accesses
941 system.cpu.dcache.demand_accesses::total 29512569 # number of demand (read+write) accesses
942 system.cpu.dcache.overall_accesses::cpu.data 29512569 # number of overall (read+write) accesses
943 system.cpu.dcache.overall_accesses::total 29512569 # number of overall (read+write) accesses
944 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.047379 # miss rate for ReadReq accesses
945 system.cpu.dcache.ReadReq_miss_rate::total 0.047379 # miss rate for ReadReq accesses
946 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.042759 # miss rate for WriteReq accesses
947 system.cpu.dcache.WriteReq_miss_rate::total 0.042759 # miss rate for WriteReq accesses
948 system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001786 # miss rate for LoadLockedReq accesses
949 system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001786 # miss rate for LoadLockedReq accesses
950 system.cpu.dcache.demand_miss_rate::cpu.data 0.046637 # miss rate for demand accesses
951 system.cpu.dcache.demand_miss_rate::total 0.046637 # miss rate for demand accesses
952 system.cpu.dcache.overall_miss_rate::cpu.data 0.046637 # miss rate for overall accesses
953 system.cpu.dcache.overall_miss_rate::total 0.046637 # miss rate for overall accesses
954 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11835.281406 # average ReadReq miss latency
955 system.cpu.dcache.ReadReq_avg_miss_latency::total 11835.281406 # average ReadReq miss latency
956 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42336.598300 # average WriteReq miss latency
957 system.cpu.dcache.WriteReq_avg_miss_latency::total 42336.598300 # average WriteReq miss latency
958 system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 35928.571429 # average LoadLockedReq miss latency
959 system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 35928.571429 # average LoadLockedReq miss latency
960 system.cpu.dcache.demand_avg_miss_latency::cpu.data 16321.915006 # average overall miss latency
961 system.cpu.dcache.demand_avg_miss_latency::total 16321.915006 # average overall miss latency
962 system.cpu.dcache.overall_avg_miss_latency::cpu.data 16321.915006 # average overall miss latency
963 system.cpu.dcache.overall_avg_miss_latency::total 16321.915006 # average overall miss latency
964 system.cpu.dcache.blocked_cycles::no_mshrs 154484 # number of cycles access was blocked
965 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
966 system.cpu.dcache.blocked::no_mshrs 23933 # number of cycles access was blocked
967 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
968 system.cpu.dcache.avg_blocked_cycles::no_mshrs 6.454853 # average number of cycles each access was blocked
969 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
970 system.cpu.dcache.fast_writes 0 # number of fast writes performed
971 system.cpu.dcache.cache_copies 0 # number of cache copies performed
972 system.cpu.dcache.writebacks::writebacks 942932 # number of writebacks
973 system.cpu.dcache.writebacks::total 942932 # number of writebacks
974 system.cpu.dcache.ReadReq_mshr_hits::cpu.data 269988 # number of ReadReq MSHR hits
975 system.cpu.dcache.ReadReq_mshr_hits::total 269988 # number of ReadReq MSHR hits
976 system.cpu.dcache.WriteReq_mshr_hits::cpu.data 158763 # number of WriteReq MSHR hits
977 system.cpu.dcache.WriteReq_mshr_hits::total 158763 # number of WriteReq MSHR hits
978 system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 7 # number of LoadLockedReq MSHR hits
979 system.cpu.dcache.LoadLockedReq_mshr_hits::total 7 # number of LoadLockedReq MSHR hits
980 system.cpu.dcache.demand_mshr_hits::cpu.data 428751 # number of demand (read+write) MSHR hits
981 system.cpu.dcache.demand_mshr_hits::total 428751 # number of demand (read+write) MSHR hits
982 system.cpu.dcache.overall_mshr_hits::cpu.data 428751 # number of overall MSHR hits
983 system.cpu.dcache.overall_mshr_hits::total 428751 # number of overall MSHR hits
984 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 903940 # number of ReadReq MSHR misses
985 system.cpu.dcache.ReadReq_mshr_misses::total 903940 # number of ReadReq MSHR misses
986 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43699 # number of WriteReq MSHR misses
987 system.cpu.dcache.WriteReq_mshr_misses::total 43699 # number of WriteReq MSHR misses
988 system.cpu.dcache.demand_mshr_misses::cpu.data 947639 # number of demand (read+write) MSHR misses
989 system.cpu.dcache.demand_mshr_misses::total 947639 # number of demand (read+write) MSHR misses
990 system.cpu.dcache.overall_mshr_misses::cpu.data 947639 # number of overall MSHR misses
991 system.cpu.dcache.overall_mshr_misses::total 947639 # number of overall MSHR misses
992 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9994791010 # number of ReadReq MSHR miss cycles
993 system.cpu.dcache.ReadReq_mshr_miss_latency::total 9994791010 # number of ReadReq MSHR miss cycles
994 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1332397702 # number of WriteReq MSHR miss cycles
995 system.cpu.dcache.WriteReq_mshr_miss_latency::total 1332397702 # number of WriteReq MSHR miss cycles
996 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11327188712 # number of demand (read+write) MSHR miss cycles
997 system.cpu.dcache.demand_mshr_miss_latency::total 11327188712 # number of demand (read+write) MSHR miss cycles
998 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11327188712 # number of overall MSHR miss cycles
999 system.cpu.dcache.overall_mshr_miss_latency::total 11327188712 # number of overall MSHR miss cycles
1000 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036482 # mshr miss rate for ReadReq accesses
1001 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036482 # mshr miss rate for ReadReq accesses
1002 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009229 # mshr miss rate for WriteReq accesses
1003 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009229 # mshr miss rate for WriteReq accesses
1004 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032110 # mshr miss rate for demand accesses
1005 system.cpu.dcache.demand_mshr_miss_rate::total 0.032110 # mshr miss rate for demand accesses
1006 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032110 # mshr miss rate for overall accesses
1007 system.cpu.dcache.overall_mshr_miss_rate::total 0.032110 # mshr miss rate for overall accesses
1008 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11056.918612 # average ReadReq mshr miss latency
1009 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11056.918612 # average ReadReq mshr miss latency
1010 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30490.347651 # average WriteReq mshr miss latency
1011 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30490.347651 # average WriteReq mshr miss latency
1012 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11953.063046 # average overall mshr miss latency
1013 system.cpu.dcache.demand_avg_mshr_miss_latency::total 11953.063046 # average overall mshr miss latency
1014 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11953.063046 # average overall mshr miss latency
1015 system.cpu.dcache.overall_avg_mshr_miss_latency::total 11953.063046 # average overall mshr miss latency
1016 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1018 ---------- End Simulation Statistics ----------
projects / gem5.git / blob