2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.058179 # Number of seconds simulated
4 sim_ticks 58178990500 # Number of ticks simulated
5 final_tick 58178990500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 60429 # Simulator instruction rate (inst/s)
8 host_op_rate 60730 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 38808737 # Simulator tick rate (ticks/s)
10 host_mem_usage 520460 # Number of bytes of host memory used
11 host_seconds 1499.12 # Real time elapsed on the host
12 sim_insts 90589799 # Number of instructions simulated
13 sim_ops 91041030 # Number of ops (including micro ops) simulated
14 system.voltage_domain.voltage 1 # Voltage in Volts
15 system.clk_domain.clock 1000 # Clock period in ticks
16 system.physmem.bytes_read::cpu.inst 44864 # Number of bytes read from this memory
17 system.physmem.bytes_read::cpu.data 57344 # Number of bytes read from this memory
18 system.physmem.bytes_read::cpu.l2cache.prefetcher 923968 # Number of bytes read from this memory
19 system.physmem.bytes_read::total 1026176 # Number of bytes read from this memory
20 system.physmem.bytes_inst_read::cpu.inst 44864 # Number of instructions bytes read from this memory
21 system.physmem.bytes_inst_read::total 44864 # Number of instructions bytes read from this memory
22 system.physmem.bytes_written::writebacks 10880 # Number of bytes written to this memory
23 system.physmem.bytes_written::total 10880 # Number of bytes written to this memory
24 system.physmem.num_reads::cpu.inst 701 # Number of read requests responded to by this memory
25 system.physmem.num_reads::cpu.data 896 # Number of read requests responded to by this memory
26 system.physmem.num_reads::cpu.l2cache.prefetcher 14437 # Number of read requests responded to by this memory
27 system.physmem.num_reads::total 16034 # Number of read requests responded to by this memory
28 system.physmem.num_writes::writebacks 170 # Number of write requests responded to by this memory
29 system.physmem.num_writes::total 170 # Number of write requests responded to by this memory
30 system.physmem.bw_read::cpu.inst 771137 # Total read bandwidth from this memory (bytes/s)
31 system.physmem.bw_read::cpu.data 985648 # Total read bandwidth from this memory (bytes/s)
32 system.physmem.bw_read::cpu.l2cache.prefetcher 15881472 # Total read bandwidth from this memory (bytes/s)
33 system.physmem.bw_read::total 17638257 # Total read bandwidth from this memory (bytes/s)
34 system.physmem.bw_inst_read::cpu.inst 771137 # Instruction read bandwidth from this memory (bytes/s)
35 system.physmem.bw_inst_read::total 771137 # Instruction read bandwidth from this memory (bytes/s)
36 system.physmem.bw_write::writebacks 187009 # Write bandwidth from this memory (bytes/s)
37 system.physmem.bw_write::total 187009 # Write bandwidth from this memory (bytes/s)
38 system.physmem.bw_total::writebacks 187009 # Total bandwidth to/from this memory (bytes/s)
39 system.physmem.bw_total::cpu.inst 771137 # Total bandwidth to/from this memory (bytes/s)
40 system.physmem.bw_total::cpu.data 985648 # Total bandwidth to/from this memory (bytes/s)
41 system.physmem.bw_total::cpu.l2cache.prefetcher 15881472 # Total bandwidth to/from this memory (bytes/s)
42 system.physmem.bw_total::total 17825266 # Total bandwidth to/from this memory (bytes/s)
43 system.physmem.readReqs 16035 # Number of read requests accepted
44 system.physmem.writeReqs 170 # Number of write requests accepted
45 system.physmem.readBursts 16035 # Number of DRAM read bursts, including those serviced by the write queue
46 system.physmem.writeBursts 170 # Number of DRAM write bursts, including those merged in the write queue
47 system.physmem.bytesReadDRAM 1017600 # Total number of bytes read from DRAM
48 system.physmem.bytesReadWrQ 8576 # Total number of bytes read from write queue
49 system.physmem.bytesWritten 9088 # Total number of bytes written to DRAM
50 system.physmem.bytesReadSys 1026240 # Total read bytes from the system interface side
51 system.physmem.bytesWrittenSys 10880 # Total written bytes from the system interface side
52 system.physmem.servicedByWrQ 134 # Number of DRAM read bursts serviced by the write queue
53 system.physmem.mergedWrBursts 4 # Number of DRAM write bursts merged with an existing one
54 system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
55 system.physmem.perBankRdBursts::0 1166 # Per bank write bursts
56 system.physmem.perBankRdBursts::1 919 # Per bank write bursts
57 system.physmem.perBankRdBursts::2 953 # Per bank write bursts
58 system.physmem.perBankRdBursts::3 1033 # Per bank write bursts
59 system.physmem.perBankRdBursts::4 1062 # Per bank write bursts
60 system.physmem.perBankRdBursts::5 1116 # Per bank write bursts
61 system.physmem.perBankRdBursts::6 1091 # Per bank write bursts
62 system.physmem.perBankRdBursts::7 1089 # Per bank write bursts
63 system.physmem.perBankRdBursts::8 1024 # Per bank write bursts
64 system.physmem.perBankRdBursts::9 962 # Per bank write bursts
65 system.physmem.perBankRdBursts::10 937 # Per bank write bursts
66 system.physmem.perBankRdBursts::11 900 # Per bank write bursts
67 system.physmem.perBankRdBursts::12 906 # Per bank write bursts
68 system.physmem.perBankRdBursts::13 899 # Per bank write bursts
69 system.physmem.perBankRdBursts::14 910 # Per bank write bursts
70 system.physmem.perBankRdBursts::15 933 # Per bank write bursts
71 system.physmem.perBankWrBursts::0 7 # Per bank write bursts
72 system.physmem.perBankWrBursts::1 0 # Per bank write bursts
73 system.physmem.perBankWrBursts::2 12 # Per bank write bursts
74 system.physmem.perBankWrBursts::3 4 # Per bank write bursts
75 system.physmem.perBankWrBursts::4 3 # Per bank write bursts
76 system.physmem.perBankWrBursts::5 12 # Per bank write bursts
77 system.physmem.perBankWrBursts::6 37 # Per bank write bursts
78 system.physmem.perBankWrBursts::7 2 # Per bank write bursts
79 system.physmem.perBankWrBursts::8 2 # Per bank write bursts
80 system.physmem.perBankWrBursts::9 0 # Per bank write bursts
81 system.physmem.perBankWrBursts::10 6 # Per bank write bursts
82 system.physmem.perBankWrBursts::11 4 # Per bank write bursts
83 system.physmem.perBankWrBursts::12 7 # Per bank write bursts
84 system.physmem.perBankWrBursts::13 12 # Per bank write bursts
85 system.physmem.perBankWrBursts::14 33 # Per bank write bursts
86 system.physmem.perBankWrBursts::15 1 # Per bank write bursts
87 system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
88 system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
89 system.physmem.totGap 58178982000 # Total gap between requests
90 system.physmem.readPktSize::0 0 # Read request sizes (log2)
91 system.physmem.readPktSize::1 0 # Read request sizes (log2)
92 system.physmem.readPktSize::2 0 # Read request sizes (log2)
93 system.physmem.readPktSize::3 0 # Read request sizes (log2)
94 system.physmem.readPktSize::4 0 # Read request sizes (log2)
95 system.physmem.readPktSize::5 0 # Read request sizes (log2)
96 system.physmem.readPktSize::6 16035 # Read request sizes (log2)
97 system.physmem.writePktSize::0 0 # Write request sizes (log2)
98 system.physmem.writePktSize::1 0 # Write request sizes (log2)
99 system.physmem.writePktSize::2 0 # Write request sizes (log2)
100 system.physmem.writePktSize::3 0 # Write request sizes (log2)
101 system.physmem.writePktSize::4 0 # Write request sizes (log2)
102 system.physmem.writePktSize::5 0 # Write request sizes (log2)
103 system.physmem.writePktSize::6 170 # Write request sizes (log2)
104 system.physmem.rdQLenPdf::0 10985 # What read queue length does an incoming req see
105 system.physmem.rdQLenPdf::1 2530 # What read queue length does an incoming req see
106 system.physmem.rdQLenPdf::2 456 # What read queue length does an incoming req see
107 system.physmem.rdQLenPdf::3 393 # What read queue length does an incoming req see
108 system.physmem.rdQLenPdf::4 293 # What read queue length does an incoming req see
109 system.physmem.rdQLenPdf::5 292 # What read queue length does an incoming req see
110 system.physmem.rdQLenPdf::6 315 # What read queue length does an incoming req see
111 system.physmem.rdQLenPdf::7 291 # What read queue length does an incoming req see
112 system.physmem.rdQLenPdf::8 292 # What read queue length does an incoming req see
113 system.physmem.rdQLenPdf::9 54 # What read queue length does an incoming req see
114 system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
115 system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
116 system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
117 system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
118 system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
119 system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
120 system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
121 system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
122 system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
123 system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
124 system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
125 system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
126 system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
127 system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
128 system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
129 system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
130 system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
131 system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
132 system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
133 system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
134 system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
135 system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
136 system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
137 system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
138 system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
139 system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
140 system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
141 system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
142 system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
143 system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
144 system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
145 system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
146 system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
147 system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
148 system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
149 system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
150 system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
151 system.physmem.wrQLenPdf::15 8 # What write queue length does an incoming req see
152 system.physmem.wrQLenPdf::16 8 # What write queue length does an incoming req see
153 system.physmem.wrQLenPdf::17 9 # What write queue length does an incoming req see
154 system.physmem.wrQLenPdf::18 9 # What write queue length does an incoming req see
155 system.physmem.wrQLenPdf::19 9 # What write queue length does an incoming req see
156 system.physmem.wrQLenPdf::20 9 # What write queue length does an incoming req see
157 system.physmem.wrQLenPdf::21 9 # What write queue length does an incoming req see
158 system.physmem.wrQLenPdf::22 9 # What write queue length does an incoming req see
159 system.physmem.wrQLenPdf::23 9 # What write queue length does an incoming req see
160 system.physmem.wrQLenPdf::24 8 # What write queue length does an incoming req see
161 system.physmem.wrQLenPdf::25 8 # What write queue length does an incoming req see
162 system.physmem.wrQLenPdf::26 8 # What write queue length does an incoming req see
163 system.physmem.wrQLenPdf::27 8 # What write queue length does an incoming req see
164 system.physmem.wrQLenPdf::28 8 # What write queue length does an incoming req see
165 system.physmem.wrQLenPdf::29 8 # What write queue length does an incoming req see
166 system.physmem.wrQLenPdf::30 8 # What write queue length does an incoming req see
167 system.physmem.wrQLenPdf::31 8 # What write queue length does an incoming req see
168 system.physmem.wrQLenPdf::32 8 # What write queue length does an incoming req see
169 system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
170 system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
171 system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
172 system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
173 system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
174 system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
175 system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
176 system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
177 system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
178 system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
179 system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
180 system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
181 system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
182 system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
183 system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
184 system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
185 system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
186 system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
187 system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
188 system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
189 system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
190 system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
191 system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
192 system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
193 system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
194 system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
195 system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
196 system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
197 system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
198 system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
199 system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
200 system.physmem.bytesPerActivate::samples 1792 # Bytes accessed per row activation
201 system.physmem.bytesPerActivate::mean 572.928571 # Bytes accessed per row activation
202 system.physmem.bytesPerActivate::gmean 339.689561 # Bytes accessed per row activation
203 system.physmem.bytesPerActivate::stdev 430.205419 # Bytes accessed per row activation
204 system.physmem.bytesPerActivate::0-127 476 26.56% 26.56% # Bytes accessed per row activation
205 system.physmem.bytesPerActivate::128-255 210 11.72% 38.28% # Bytes accessed per row activation
206 system.physmem.bytesPerActivate::256-383 97 5.41% 43.69% # Bytes accessed per row activation
207 system.physmem.bytesPerActivate::384-511 63 3.52% 47.21% # Bytes accessed per row activation
208 system.physmem.bytesPerActivate::512-639 46 2.57% 49.78% # Bytes accessed per row activation
209 system.physmem.bytesPerActivate::640-767 57 3.18% 52.96% # Bytes accessed per row activation
210 system.physmem.bytesPerActivate::768-895 50 2.79% 55.75% # Bytes accessed per row activation
211 system.physmem.bytesPerActivate::896-1023 48 2.68% 58.43% # Bytes accessed per row activation
212 system.physmem.bytesPerActivate::1024-1151 745 41.57% 100.00% # Bytes accessed per row activation
213 system.physmem.bytesPerActivate::total 1792 # Bytes accessed per row activation
214 system.physmem.rdPerTurnAround::samples 8 # Reads before turning the bus around for writes
215 system.physmem.rdPerTurnAround::mean 1980.250000 # Reads before turning the bus around for writes
216 system.physmem.rdPerTurnAround::gmean 75.328493 # Reads before turning the bus around for writes
217 system.physmem.rdPerTurnAround::stdev 5451.280656 # Reads before turning the bus around for writes
218 system.physmem.rdPerTurnAround::0-511 7 87.50% 87.50% # Reads before turning the bus around for writes
219 system.physmem.rdPerTurnAround::15360-15871 1 12.50% 100.00% # Reads before turning the bus around for writes
220 system.physmem.rdPerTurnAround::total 8 # Reads before turning the bus around for writes
221 system.physmem.wrPerTurnAround::samples 8 # Writes before turning the bus around for reads
222 system.physmem.wrPerTurnAround::mean 17.750000 # Writes before turning the bus around for reads
223 system.physmem.wrPerTurnAround::gmean 17.736929 # Writes before turning the bus around for reads
224 system.physmem.wrPerTurnAround::stdev 0.707107 # Writes before turning the bus around for reads
225 system.physmem.wrPerTurnAround::16 1 12.50% 12.50% # Writes before turning the bus around for reads
226 system.physmem.wrPerTurnAround::18 7 87.50% 100.00% # Writes before turning the bus around for reads
227 system.physmem.wrPerTurnAround::total 8 # Writes before turning the bus around for reads
228 system.physmem.totQLat 173529353 # Total ticks spent queuing
229 system.physmem.totMemAccLat 471654353 # Total ticks spent from burst creation until serviced by the DRAM
230 system.physmem.totBusLat 79500000 # Total ticks spent in databus transfers
231 system.physmem.avgQLat 10913.11 # Average queueing delay per DRAM burst
232 system.physmem.avgBusLat 4999.69 # Average bus latency per DRAM burst
233 system.physmem.avgMemAccLat 29661.93 # Average memory access latency per DRAM burst
234 system.physmem.avgRdBW 17.49 # Average DRAM read bandwidth in MiByte/s
235 system.physmem.avgWrBW 0.16 # Average achieved write bandwidth in MiByte/s
236 system.physmem.avgRdBWSys 17.64 # Average system read bandwidth in MiByte/s
237 system.physmem.avgWrBWSys 0.19 # Average system write bandwidth in MiByte/s
238 system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
239 system.physmem.busUtil 0.14 # Data bus utilization in percentage
240 system.physmem.busUtilRead 0.14 # Data bus utilization in percentage for reads
241 system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
242 system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing
243 system.physmem.avgWrQLen 20.26 # Average write queue length when enqueuing
244 system.physmem.readRowHits 14205 # Number of row buffer hits during reads
245 system.physmem.writeRowHits 45 # Number of row buffer hits during writes
246 system.physmem.readRowHitRate 89.33 # Row buffer hit rate for reads
247 system.physmem.writeRowHitRate 27.11 # Row buffer hit rate for writes
248 system.physmem.avgGap 3590187.10 # Average gap between requests
249 system.physmem.pageHitRate 88.69 # Row buffer hit rate, read and write combined
250 system.physmem_0.actEnergy 7794360 # Energy for activate commands per rank (pJ)
251 system.physmem_0.preEnergy 4252875 # Energy for precharge commands per rank (pJ)
252 system.physmem_0.readEnergy 65746200 # Energy for read commands per rank (pJ)
253 system.physmem_0.writeEnergy 498960 # Energy for write commands per rank (pJ)
254 system.physmem_0.refreshEnergy 3799960320 # Energy for refresh commands per rank (pJ)
255 system.physmem_0.actBackEnergy 2649738195 # Energy for active background per rank (pJ)
256 system.physmem_0.preBackEnergy 32583140250 # Energy for precharge background per rank (pJ)
257 system.physmem_0.totalEnergy 39111131160 # Total energy per rank (pJ)
258 system.physmem_0.averagePower 672.253743 # Core power per rank (mW)
259 system.physmem_0.memoryStateTime::IDLE 54193285294 # Time in different power states
260 system.physmem_0.memoryStateTime::REF 1942460000 # Time in different power states
261 system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
262 system.physmem_0.memoryStateTime::ACT 2043128456 # Time in different power states
263 system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
264 system.physmem_1.actEnergy 5753160 # Energy for activate commands per rank (pJ)
265 system.physmem_1.preEnergy 3139125 # Energy for precharge commands per rank (pJ)
266 system.physmem_1.readEnergy 58273800 # Energy for read commands per rank (pJ)
267 system.physmem_1.writeEnergy 421200 # Energy for write commands per rank (pJ)
268 system.physmem_1.refreshEnergy 3799960320 # Energy for refresh commands per rank (pJ)
269 system.physmem_1.actBackEnergy 2342596545 # Energy for active background per rank (pJ)
270 system.physmem_1.preBackEnergy 32852562750 # Energy for precharge background per rank (pJ)
271 system.physmem_1.totalEnergy 39062706900 # Total energy per rank (pJ)
272 system.physmem_1.averagePower 671.421412 # Core power per rank (mW)
273 system.physmem_1.memoryStateTime::IDLE 54644034494 # Time in different power states
274 system.physmem_1.memoryStateTime::REF 1942460000 # Time in different power states
275 system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
276 system.physmem_1.memoryStateTime::ACT 1592379256 # Time in different power states
277 system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
278 system.cpu.branchPred.lookups 28257760 # Number of BP lookups
279 system.cpu.branchPred.condPredicted 23279733 # Number of conditional branches predicted
280 system.cpu.branchPred.condIncorrect 837848 # Number of conditional branches incorrect
281 system.cpu.branchPred.BTBLookups 11842330 # Number of BTB lookups
282 system.cpu.branchPred.BTBHits 11784674 # Number of BTB hits
283 system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
284 system.cpu.branchPred.BTBHitPct 99.513136 # BTB Hit Percentage
285 system.cpu.branchPred.usedRAS 75804 # Number of times the RAS was used to get a target.
286 system.cpu.branchPred.RASInCorrect 88 # Number of incorrect RAS predictions.
287 system.cpu_clk_domain.clock 500 # Clock period in ticks
288 system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
289 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
290 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
291 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
292 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
293 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
294 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
295 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
296 system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
297 system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
298 system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
299 system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
300 system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
301 system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
302 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
303 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
304 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
305 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
306 system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
307 system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
308 system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
309 system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
310 system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
311 system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
312 system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
313 system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
314 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
315 system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
316 system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
317 system.cpu.dtb.walker.walks 0 # Table walker walks requested
318 system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
319 system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
320 system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
321 system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
322 system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
323 system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
324 system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
325 system.cpu.dtb.inst_hits 0 # ITB inst hits
326 system.cpu.dtb.inst_misses 0 # ITB inst misses
327 system.cpu.dtb.read_hits 0 # DTB read hits
328 system.cpu.dtb.read_misses 0 # DTB read misses
329 system.cpu.dtb.write_hits 0 # DTB write hits
330 system.cpu.dtb.write_misses 0 # DTB write misses
331 system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
332 system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
333 system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
334 system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
335 system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
336 system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
337 system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
338 system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
339 system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
340 system.cpu.dtb.read_accesses 0 # DTB read accesses
341 system.cpu.dtb.write_accesses 0 # DTB write accesses
342 system.cpu.dtb.inst_accesses 0 # ITB inst accesses
343 system.cpu.dtb.hits 0 # DTB hits
344 system.cpu.dtb.misses 0 # DTB misses
345 system.cpu.dtb.accesses 0 # DTB accesses
346 system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
347 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
348 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
349 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
350 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
351 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
352 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
353 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
354 system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
355 system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
356 system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
357 system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
358 system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
359 system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
360 system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
361 system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
362 system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
363 system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
364 system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
365 system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
366 system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
367 system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
368 system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
369 system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
370 system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
371 system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
372 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
373 system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
374 system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
375 system.cpu.itb.walker.walks 0 # Table walker walks requested
376 system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
377 system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
378 system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
379 system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
380 system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
381 system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
382 system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
383 system.cpu.itb.inst_hits 0 # ITB inst hits
384 system.cpu.itb.inst_misses 0 # ITB inst misses
385 system.cpu.itb.read_hits 0 # DTB read hits
386 system.cpu.itb.read_misses 0 # DTB read misses
387 system.cpu.itb.write_hits 0 # DTB write hits
388 system.cpu.itb.write_misses 0 # DTB write misses
389 system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
390 system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
391 system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
392 system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
393 system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
394 system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
395 system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
396 system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
397 system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
398 system.cpu.itb.read_accesses 0 # DTB read accesses
399 system.cpu.itb.write_accesses 0 # DTB write accesses
400 system.cpu.itb.inst_accesses 0 # ITB inst accesses
401 system.cpu.itb.hits 0 # DTB hits
402 system.cpu.itb.misses 0 # DTB misses
403 system.cpu.itb.accesses 0 # DTB accesses
404 system.cpu.workload.num_syscalls 442 # Number of system calls
405 system.cpu.numCycles 116357982 # number of cpu cycles simulated
406 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
407 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
408 system.cpu.fetch.icacheStallCycles 748703 # Number of cycles fetch is stalled on an Icache miss
409 system.cpu.fetch.Insts 134988401 # Number of instructions fetch has processed
410 system.cpu.fetch.Branches 28257760 # Number of branches that fetch encountered
411 system.cpu.fetch.predictedBranches 11860478 # Number of branches that fetch has predicted taken
412 system.cpu.fetch.Cycles 114715121 # Number of cycles fetch has run and was not squashing or blocked
413 system.cpu.fetch.SquashCycles 1679113 # Number of cycles fetch has spent squashing
414 system.cpu.fetch.MiscStallCycles 977 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
415 system.cpu.fetch.IcacheWaitRetryStallCycles 833 # Number of stall cycles due to full MSHR
416 system.cpu.fetch.CacheLines 32302514 # Number of cache lines fetched
417 system.cpu.fetch.IcacheSquashes 574 # Number of outstanding Icache misses that were squashed
418 system.cpu.fetch.rateDist::samples 116305190 # Number of instructions fetched each cycle (Total)
419 system.cpu.fetch.rateDist::mean 1.165894 # Number of instructions fetched each cycle (Total)
420 system.cpu.fetch.rateDist::stdev 1.319044 # Number of instructions fetched each cycle (Total)
421 system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
422 system.cpu.fetch.rateDist::0 58733287 50.50% 50.50% # Number of instructions fetched each cycle (Total)
423 system.cpu.fetch.rateDist::1 13942631 11.99% 62.49% # Number of instructions fetched each cycle (Total)
424 system.cpu.fetch.rateDist::2 9230901 7.94% 70.42% # Number of instructions fetched each cycle (Total)
425 system.cpu.fetch.rateDist::3 34398371 29.58% 100.00% # Number of instructions fetched each cycle (Total)
426 system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
427 system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
428 system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
429 system.cpu.fetch.rateDist::total 116305190 # Number of instructions fetched each cycle (Total)
430 system.cpu.fetch.branchRate 0.242852 # Number of branch fetches per cycle
431 system.cpu.fetch.rate 1.160113 # Number of inst fetches per cycle
432 system.cpu.decode.IdleCycles 8839704 # Number of cycles decode is idle
433 system.cpu.decode.BlockedCycles 64044923 # Number of cycles decode is blocked
434 system.cpu.decode.RunCycles 33035218 # Number of cycles decode is running
435 system.cpu.decode.UnblockCycles 9558027 # Number of cycles decode is unblocking
436 system.cpu.decode.SquashCycles 827318 # Number of cycles decode is squashing
437 system.cpu.decode.BranchResolved 4101316 # Number of times decode resolved a branch
438 system.cpu.decode.BranchMispred 12341 # Number of times decode detected a branch misprediction
439 system.cpu.decode.DecodedInsts 114430969 # Number of instructions handled by decode
440 system.cpu.decode.SquashedInsts 1996281 # Number of squashed instructions handled by decode
441 system.cpu.rename.SquashCycles 827318 # Number of cycles rename is squashing
442 system.cpu.rename.IdleCycles 15281065 # Number of cycles rename is idle
443 system.cpu.rename.BlockCycles 49888125 # Number of cycles rename is blocking
444 system.cpu.rename.serializeStallCycles 109559 # count of cycles rename stalled for serializing inst
445 system.cpu.rename.RunCycles 35425090 # Number of cycles rename is running
446 system.cpu.rename.UnblockCycles 14774033 # Number of cycles rename is unblocking
447 system.cpu.rename.RenamedInsts 110899108 # Number of instructions processed by rename
448 system.cpu.rename.SquashedInsts 1414941 # Number of squashed instructions processed by rename
449 system.cpu.rename.ROBFullEvents 11132282 # Number of times rename has blocked due to ROB full
450 system.cpu.rename.IQFullEvents 1143663 # Number of times rename has blocked due to IQ full
451 system.cpu.rename.LQFullEvents 1527047 # Number of times rename has blocked due to LQ full
452 system.cpu.rename.SQFullEvents 487517 # Number of times rename has blocked due to SQ full
453 system.cpu.rename.RenamedOperands 129956871 # Number of destination operands rename has renamed
454 system.cpu.rename.RenameLookups 483273963 # Number of register rename lookups that rename has made
455 system.cpu.rename.int_rename_lookups 119474159 # Number of integer rename lookups
456 system.cpu.rename.fp_rename_lookups 431 # Number of floating rename lookups
457 system.cpu.rename.CommittedMaps 107312919 # Number of HB maps that are committed
458 system.cpu.rename.UndoneMaps 22643952 # Number of HB maps that are undone due to squashing
459 system.cpu.rename.serializingInsts 4364 # count of serializing insts renamed
460 system.cpu.rename.tempSerializingInsts 4359 # count of temporary serializing insts renamed
461 system.cpu.rename.skidInsts 21508074 # count of insts added to the skid buffer
462 system.cpu.memDep0.insertedLoads 26812702 # Number of loads inserted to the mem dependence unit.
463 system.cpu.memDep0.insertedStores 5350076 # Number of stores inserted to the mem dependence unit.
464 system.cpu.memDep0.conflictingLoads 518927 # Number of conflicting loads.
465 system.cpu.memDep0.conflictingStores 253927 # Number of conflicting stores.
466 system.cpu.iq.iqInstsAdded 109691489 # Number of instructions added to the IQ (excludes non-spec)
467 system.cpu.iq.iqNonSpecInstsAdded 8248 # Number of non-speculative instructions added to the IQ
468 system.cpu.iq.iqInstsIssued 101389067 # Number of instructions issued
469 system.cpu.iq.iqSquashedInstsIssued 1075877 # Number of squashed instructions issued
470 system.cpu.iq.iqSquashedInstsExamined 18658707 # Number of squashed instructions iterated over during squash; mainly for profiling
471 system.cpu.iq.iqSquashedOperandsExamined 41691247 # Number of squashed operands that are examined and possibly removed from graph
472 system.cpu.iq.iqSquashedNonSpecRemoved 30 # Number of squashed non-spec instructions that were removed
473 system.cpu.iq.issued_per_cycle::samples 116305190 # Number of insts issued each cycle
474 system.cpu.iq.issued_per_cycle::mean 0.871750 # Number of insts issued each cycle
475 system.cpu.iq.issued_per_cycle::stdev 0.989327 # Number of insts issued each cycle
476 system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
477 system.cpu.iq.issued_per_cycle::0 54664640 47.00% 47.00% # Number of insts issued each cycle
478 system.cpu.iq.issued_per_cycle::1 31360805 26.96% 73.97% # Number of insts issued each cycle
479 system.cpu.iq.issued_per_cycle::2 22009670 18.92% 92.89% # Number of insts issued each cycle
480 system.cpu.iq.issued_per_cycle::3 7071691 6.08% 98.97% # Number of insts issued each cycle
481 system.cpu.iq.issued_per_cycle::4 1198071 1.03% 100.00% # Number of insts issued each cycle
482 system.cpu.iq.issued_per_cycle::5 313 0.00% 100.00% # Number of insts issued each cycle
483 system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
484 system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
485 system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
486 system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
487 system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
488 system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
489 system.cpu.iq.issued_per_cycle::total 116305190 # Number of insts issued each cycle
490 system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
491 system.cpu.iq.fu_full::IntAlu 9787073 48.68% 48.68% # attempts to use FU when none available
492 system.cpu.iq.fu_full::IntMult 50 0.00% 48.68% # attempts to use FU when none available
493 system.cpu.iq.fu_full::IntDiv 0 0.00% 48.68% # attempts to use FU when none available
494 system.cpu.iq.fu_full::FloatAdd 0 0.00% 48.68% # attempts to use FU when none available
495 system.cpu.iq.fu_full::FloatCmp 0 0.00% 48.68% # attempts to use FU when none available
496 system.cpu.iq.fu_full::FloatCvt 0 0.00% 48.68% # attempts to use FU when none available
497 system.cpu.iq.fu_full::FloatMult 0 0.00% 48.68% # attempts to use FU when none available
498 system.cpu.iq.fu_full::FloatDiv 0 0.00% 48.68% # attempts to use FU when none available
499 system.cpu.iq.fu_full::FloatSqrt 0 0.00% 48.68% # attempts to use FU when none available
500 system.cpu.iq.fu_full::SimdAdd 0 0.00% 48.68% # attempts to use FU when none available
501 system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 48.68% # attempts to use FU when none available
502 system.cpu.iq.fu_full::SimdAlu 0 0.00% 48.68% # attempts to use FU when none available
503 system.cpu.iq.fu_full::SimdCmp 0 0.00% 48.68% # attempts to use FU when none available
504 system.cpu.iq.fu_full::SimdCvt 0 0.00% 48.68% # attempts to use FU when none available
505 system.cpu.iq.fu_full::SimdMisc 0 0.00% 48.68% # attempts to use FU when none available
506 system.cpu.iq.fu_full::SimdMult 0 0.00% 48.68% # attempts to use FU when none available
507 system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 48.68% # attempts to use FU when none available
508 system.cpu.iq.fu_full::SimdShift 0 0.00% 48.68% # attempts to use FU when none available
509 system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 48.68% # attempts to use FU when none available
510 system.cpu.iq.fu_full::SimdSqrt 0 0.00% 48.68% # attempts to use FU when none available
511 system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 48.68% # attempts to use FU when none available
512 system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 48.68% # attempts to use FU when none available
513 system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 48.68% # attempts to use FU when none available
514 system.cpu.iq.fu_full::SimdFloatCvt 13 0.00% 48.68% # attempts to use FU when none available
515 system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 48.68% # attempts to use FU when none available
516 system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 48.68% # attempts to use FU when none available
517 system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 48.68% # attempts to use FU when none available
518 system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 48.68% # attempts to use FU when none available
519 system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 48.68% # attempts to use FU when none available
520 system.cpu.iq.fu_full::MemRead 9614641 47.82% 96.50% # attempts to use FU when none available
521 system.cpu.iq.fu_full::MemWrite 704123 3.50% 100.00% # attempts to use FU when none available
522 system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
523 system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
524 system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
525 system.cpu.iq.FU_type_0::IntAlu 71985140 71.00% 71.00% # Type of FU issued
526 system.cpu.iq.FU_type_0::IntMult 10711 0.01% 71.01% # Type of FU issued
527 system.cpu.iq.FU_type_0::IntDiv 0 0.00% 71.01% # Type of FU issued
528 system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 71.01% # Type of FU issued
529 system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 71.01% # Type of FU issued
530 system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 71.01% # Type of FU issued
531 system.cpu.iq.FU_type_0::FloatMult 0 0.00% 71.01% # Type of FU issued
532 system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 71.01% # Type of FU issued
533 system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 71.01% # Type of FU issued
534 system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 71.01% # Type of FU issued
535 system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 71.01% # Type of FU issued
536 system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 71.01% # Type of FU issued
537 system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 71.01% # Type of FU issued
538 system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 71.01% # Type of FU issued
539 system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 71.01% # Type of FU issued
540 system.cpu.iq.FU_type_0::SimdMult 0 0.00% 71.01% # Type of FU issued
541 system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 71.01% # Type of FU issued
542 system.cpu.iq.FU_type_0::SimdShift 0 0.00% 71.01% # Type of FU issued
543 system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 71.01% # Type of FU issued
544 system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 71.01% # Type of FU issued
545 system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 71.01% # Type of FU issued
546 system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 71.01% # Type of FU issued
547 system.cpu.iq.FU_type_0::SimdFloatCmp 2 0.00% 71.01% # Type of FU issued
548 system.cpu.iq.FU_type_0::SimdFloatCvt 54 0.00% 71.01% # Type of FU issued
549 system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 71.01% # Type of FU issued
550 system.cpu.iq.FU_type_0::SimdFloatMisc 124 0.00% 71.01% # Type of FU issued
551 system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 71.01% # Type of FU issued
552 system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 71.01% # Type of FU issued
553 system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 71.01% # Type of FU issued
554 system.cpu.iq.FU_type_0::MemRead 24343416 24.01% 95.02% # Type of FU issued
555 system.cpu.iq.FU_type_0::MemWrite 5049618 4.98% 100.00% # Type of FU issued
556 system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
557 system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
558 system.cpu.iq.FU_type_0::total 101389067 # Type of FU issued
559 system.cpu.iq.rate 0.871355 # Inst issue rate
560 system.cpu.iq.fu_busy_cnt 20105900 # FU busy when requested
561 system.cpu.iq.fu_busy_rate 0.198304 # FU busy rate (busy events/executed inst)
562 system.cpu.iq.int_inst_queue_reads 340264641 # Number of integer instruction queue reads
563 system.cpu.iq.int_inst_queue_writes 128359131 # Number of integer instruction queue writes
564 system.cpu.iq.int_inst_queue_wakeup_accesses 99626279 # Number of integer instruction queue wakeup accesses
565 system.cpu.iq.fp_inst_queue_reads 460 # Number of floating instruction queue reads
566 system.cpu.iq.fp_inst_queue_writes 626 # Number of floating instruction queue writes
567 system.cpu.iq.fp_inst_queue_wakeup_accesses 113 # Number of floating instruction queue wakeup accesses
568 system.cpu.iq.int_alu_accesses 121494727 # Number of integer alu accesses
569 system.cpu.iq.fp_alu_accesses 240 # Number of floating point alu accesses
570 system.cpu.iew.lsq.thread0.forwLoads 289423 # Number of loads that had data forwarded from stores
571 system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
572 system.cpu.iew.lsq.thread0.squashedLoads 4336791 # Number of loads squashed
573 system.cpu.iew.lsq.thread0.ignoredResponses 1514 # Number of memory responses ignored because the instruction is squashed
574 system.cpu.iew.lsq.thread0.memOrderViolation 1348 # Number of memory ordering violations
575 system.cpu.iew.lsq.thread0.squashedStores 605232 # Number of stores squashed
576 system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
577 system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
578 system.cpu.iew.lsq.thread0.rescheduledLoads 7566 # Number of loads that were rescheduled
579 system.cpu.iew.lsq.thread0.cacheBlocked 130606 # Number of times an access to memory failed due to the cache being blocked
580 system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
581 system.cpu.iew.iewSquashCycles 827318 # Number of cycles IEW is squashing
582 system.cpu.iew.iewBlockCycles 8114310 # Number of cycles IEW is blocking
583 system.cpu.iew.iewUnblockCycles 683997 # Number of cycles IEW is unblocking
584 system.cpu.iew.iewDispatchedInsts 109712406 # Number of instructions dispatched to IQ
585 system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
586 system.cpu.iew.iewDispLoadInsts 26812702 # Number of dispatched load instructions
587 system.cpu.iew.iewDispStoreInsts 5350076 # Number of dispatched store instructions
588 system.cpu.iew.iewDispNonSpecInsts 4360 # Number of dispatched non-speculative instructions
589 system.cpu.iew.iewIQFullEvents 178818 # Number of times the IQ has become full, causing a stall
590 system.cpu.iew.iewLSQFullEvents 342272 # Number of times the LSQ has become full, causing a stall
591 system.cpu.iew.memOrderViolationEvents 1348 # Number of memory order violations
592 system.cpu.iew.predictedTakenIncorrect 436595 # Number of branches that were predicted taken incorrectly
593 system.cpu.iew.predictedNotTakenIncorrect 412881 # Number of branches that were predicted not taken incorrectly
594 system.cpu.iew.branchMispredicts 849476 # Number of branch mispredicts detected at execute
595 system.cpu.iew.iewExecutedInsts 100127969 # Number of executed instructions
596 system.cpu.iew.iewExecLoadInsts 23806710 # Number of load instructions executed
597 system.cpu.iew.iewExecSquashedInsts 1261098 # Number of squashed instructions skipped in execute
598 system.cpu.iew.exec_swp 0 # number of swp insts executed
599 system.cpu.iew.exec_nop 12669 # number of nop insts executed
600 system.cpu.iew.exec_refs 28724643 # number of memory reference insts executed
601 system.cpu.iew.exec_branches 20624882 # Number of branches executed
602 system.cpu.iew.exec_stores 4917933 # Number of stores executed
603 system.cpu.iew.exec_rate 0.860517 # Inst execution rate
604 system.cpu.iew.wb_sent 99711034 # cumulative count of insts sent to commit
605 system.cpu.iew.wb_count 99626392 # cumulative count of insts written-back
606 system.cpu.iew.wb_producers 59704097 # num instructions producing a value
607 system.cpu.iew.wb_consumers 95546076 # num instructions consuming a value
608 system.cpu.iew.wb_rate 0.856206 # insts written-back per cycle
609 system.cpu.iew.wb_fanout 0.624872 # average fanout of values written-back
610 system.cpu.commit.commitSquashedInsts 17384953 # The number of squashed insts skipped by commit
611 system.cpu.commit.commitNonSpecStalls 8218 # The number of times commit has been forced to stall to communicate backwards
612 system.cpu.commit.branchMispredicts 825610 # The number of times a branch was mispredicted
613 system.cpu.commit.committed_per_cycle::samples 113612998 # Number of insts commited each cycle
614 system.cpu.commit.committed_per_cycle::mean 0.801437 # Number of insts commited each cycle
615 system.cpu.commit.committed_per_cycle::stdev 1.737923 # Number of insts commited each cycle
616 system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
617 system.cpu.commit.committed_per_cycle::0 77188479 67.94% 67.94% # Number of insts commited each cycle
618 system.cpu.commit.committed_per_cycle::1 18612991 16.38% 84.32% # Number of insts commited each cycle
619 system.cpu.commit.committed_per_cycle::2 7152574 6.30% 90.62% # Number of insts commited each cycle
620 system.cpu.commit.committed_per_cycle::3 3468909 3.05% 93.67% # Number of insts commited each cycle
621 system.cpu.commit.committed_per_cycle::4 1644585 1.45% 95.12% # Number of insts commited each cycle
622 system.cpu.commit.committed_per_cycle::5 541952 0.48% 95.60% # Number of insts commited each cycle
623 system.cpu.commit.committed_per_cycle::6 704226 0.62% 96.22% # Number of insts commited each cycle
624 system.cpu.commit.committed_per_cycle::7 178939 0.16% 96.37% # Number of insts commited each cycle
625 system.cpu.commit.committed_per_cycle::8 4120343 3.63% 100.00% # Number of insts commited each cycle
626 system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
627 system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
628 system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
629 system.cpu.commit.committed_per_cycle::total 113612998 # Number of insts commited each cycle
630 system.cpu.commit.committedInsts 90602408 # Number of instructions committed
631 system.cpu.commit.committedOps 91053639 # Number of ops (including micro ops) committed
632 system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
633 system.cpu.commit.refs 27220755 # Number of memory references committed
634 system.cpu.commit.loads 22475911 # Number of loads committed
635 system.cpu.commit.membars 3888 # Number of memory barriers committed
636 system.cpu.commit.branches 18732305 # Number of branches committed
637 system.cpu.commit.fp_insts 48 # Number of committed floating point instructions.
638 system.cpu.commit.int_insts 72326352 # Number of committed integer instructions.
639 system.cpu.commit.function_calls 56148 # Number of function calls committed.
640 system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
641 system.cpu.commit.op_class_0::IntAlu 63822387 70.09% 70.09% # Class of committed instruction
642 system.cpu.commit.op_class_0::IntMult 10474 0.01% 70.10% # Class of committed instruction
643 system.cpu.commit.op_class_0::IntDiv 0 0.00% 70.10% # Class of committed instruction
644 system.cpu.commit.op_class_0::FloatAdd 0 0.00% 70.10% # Class of committed instruction
645 system.cpu.commit.op_class_0::FloatCmp 0 0.00% 70.10% # Class of committed instruction
646 system.cpu.commit.op_class_0::FloatCvt 0 0.00% 70.10% # Class of committed instruction
647 system.cpu.commit.op_class_0::FloatMult 0 0.00% 70.10% # Class of committed instruction
648 system.cpu.commit.op_class_0::FloatDiv 0 0.00% 70.10% # Class of committed instruction
649 system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 70.10% # Class of committed instruction
650 system.cpu.commit.op_class_0::SimdAdd 0 0.00% 70.10% # Class of committed instruction
651 system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 70.10% # Class of committed instruction
652 system.cpu.commit.op_class_0::SimdAlu 0 0.00% 70.10% # Class of committed instruction
653 system.cpu.commit.op_class_0::SimdCmp 0 0.00% 70.10% # Class of committed instruction
654 system.cpu.commit.op_class_0::SimdCvt 0 0.00% 70.10% # Class of committed instruction
655 system.cpu.commit.op_class_0::SimdMisc 0 0.00% 70.10% # Class of committed instruction
656 system.cpu.commit.op_class_0::SimdMult 0 0.00% 70.10% # Class of committed instruction
657 system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 70.10% # Class of committed instruction
658 system.cpu.commit.op_class_0::SimdShift 0 0.00% 70.10% # Class of committed instruction
659 system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 70.10% # Class of committed instruction
660 system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 70.10% # Class of committed instruction
661 system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 70.10% # Class of committed instruction
662 system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 70.10% # Class of committed instruction
663 system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 70.10% # Class of committed instruction
664 system.cpu.commit.op_class_0::SimdFloatCvt 6 0.00% 70.10% # Class of committed instruction
665 system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 70.10% # Class of committed instruction
666 system.cpu.commit.op_class_0::SimdFloatMisc 15 0.00% 70.10% # Class of committed instruction
667 system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 70.10% # Class of committed instruction
668 system.cpu.commit.op_class_0::SimdFloatMultAcc 2 0.00% 70.10% # Class of committed instruction
669 system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.10% # Class of committed instruction
670 system.cpu.commit.op_class_0::MemRead 22475911 24.68% 94.79% # Class of committed instruction
671 system.cpu.commit.op_class_0::MemWrite 4744844 5.21% 100.00% # Class of committed instruction
672 system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
673 system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
674 system.cpu.commit.op_class_0::total 91053639 # Class of committed instruction
675 system.cpu.commit.bw_lim_events 4120343 # number cycles where commit BW limit reached
676 system.cpu.rob.rob_reads 217925513 # The number of ROB reads
677 system.cpu.rob.rob_writes 219569964 # The number of ROB writes
678 system.cpu.timesIdled 581 # Number of times that the entire CPU went into an idle state and unscheduled itself
679 system.cpu.idleCycles 52792 # Total number of cycles that the CPU has spent unscheduled due to idling
680 system.cpu.committedInsts 90589799 # Number of Instructions Simulated
681 system.cpu.committedOps 91041030 # Number of Ops (including micro ops) Simulated
682 system.cpu.cpi 1.284449 # CPI: Cycles Per Instruction
683 system.cpu.cpi_total 1.284449 # CPI: Total CPI of All Threads
684 system.cpu.ipc 0.778544 # IPC: Instructions Per Cycle
685 system.cpu.ipc_total 0.778544 # IPC: Total IPC of All Threads
686 system.cpu.int_regfile_reads 108112154 # number of integer regfile reads
687 system.cpu.int_regfile_writes 58701199 # number of integer regfile writes
688 system.cpu.fp_regfile_reads 58 # number of floating regfile reads
689 system.cpu.fp_regfile_writes 93 # number of floating regfile writes
690 system.cpu.cc_regfile_reads 369067542 # number of cc regfile reads
691 system.cpu.cc_regfile_writes 58693892 # number of cc regfile writes
692 system.cpu.misc_regfile_reads 28415154 # number of misc regfile reads
693 system.cpu.misc_regfile_writes 7784 # number of misc regfile writes
694 system.cpu.dcache.tags.replacements 5470195 # number of replacements
695 system.cpu.dcache.tags.tagsinuse 511.784912 # Cycle average of tags in use
696 system.cpu.dcache.tags.total_refs 18253010 # Total number of references to valid blocks.
697 system.cpu.dcache.tags.sampled_refs 5470707 # Sample count of references to valid blocks.
698 system.cpu.dcache.tags.avg_refs 3.336499 # Average number of references to valid blocks.
699 system.cpu.dcache.tags.warmup_cycle 35707500 # Cycle when the warmup percentage was hit.
700 system.cpu.dcache.tags.occ_blocks::cpu.data 511.784912 # Average occupied blocks per requestor
701 system.cpu.dcache.tags.occ_percent::cpu.data 0.999580 # Average percentage of cache occupancy
702 system.cpu.dcache.tags.occ_percent::total 0.999580 # Average percentage of cache occupancy
703 system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
704 system.cpu.dcache.tags.age_task_id_blocks_1024::0 355 # Occupied blocks per task id
705 system.cpu.dcache.tags.age_task_id_blocks_1024::1 157 # Occupied blocks per task id
706 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
707 system.cpu.dcache.tags.tag_accesses 61911209 # Number of tag accesses
708 system.cpu.dcache.tags.data_accesses 61911209 # Number of data accesses
709 system.cpu.dcache.ReadReq_hits::cpu.data 13890997 # number of ReadReq hits
710 system.cpu.dcache.ReadReq_hits::total 13890997 # number of ReadReq hits
711 system.cpu.dcache.WriteReq_hits::cpu.data 4353726 # number of WriteReq hits
712 system.cpu.dcache.WriteReq_hits::total 4353726 # number of WriteReq hits
713 system.cpu.dcache.SoftPFReq_hits::cpu.data 522 # number of SoftPFReq hits
714 system.cpu.dcache.SoftPFReq_hits::total 522 # number of SoftPFReq hits
715 system.cpu.dcache.LoadLockedReq_hits::cpu.data 3872 # number of LoadLockedReq hits
716 system.cpu.dcache.LoadLockedReq_hits::total 3872 # number of LoadLockedReq hits
717 system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits
718 system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits
719 system.cpu.dcache.demand_hits::cpu.data 18244723 # number of demand (read+write) hits
720 system.cpu.dcache.demand_hits::total 18244723 # number of demand (read+write) hits
721 system.cpu.dcache.overall_hits::cpu.data 18245245 # number of overall hits
722 system.cpu.dcache.overall_hits::total 18245245 # number of overall hits
723 system.cpu.dcache.ReadReq_misses::cpu.data 9585970 # number of ReadReq misses
724 system.cpu.dcache.ReadReq_misses::total 9585970 # number of ReadReq misses
725 system.cpu.dcache.WriteReq_misses::cpu.data 381255 # number of WriteReq misses
726 system.cpu.dcache.WriteReq_misses::total 381255 # number of WriteReq misses
727 system.cpu.dcache.SoftPFReq_misses::cpu.data 7 # number of SoftPFReq misses
728 system.cpu.dcache.SoftPFReq_misses::total 7 # number of SoftPFReq misses
729 system.cpu.dcache.LoadLockedReq_misses::cpu.data 15 # number of LoadLockedReq misses
730 system.cpu.dcache.LoadLockedReq_misses::total 15 # number of LoadLockedReq misses
731 system.cpu.dcache.demand_misses::cpu.data 9967225 # number of demand (read+write) misses
732 system.cpu.dcache.demand_misses::total 9967225 # number of demand (read+write) misses
733 system.cpu.dcache.overall_misses::cpu.data 9967232 # number of overall misses
734 system.cpu.dcache.overall_misses::total 9967232 # number of overall misses
735 system.cpu.dcache.ReadReq_miss_latency::cpu.data 88736242500 # number of ReadReq miss cycles
736 system.cpu.dcache.ReadReq_miss_latency::total 88736242500 # number of ReadReq miss cycles
737 system.cpu.dcache.WriteReq_miss_latency::cpu.data 4002302858 # number of WriteReq miss cycles
738 system.cpu.dcache.WriteReq_miss_latency::total 4002302858 # number of WriteReq miss cycles
739 system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 296500 # number of LoadLockedReq miss cycles
740 system.cpu.dcache.LoadLockedReq_miss_latency::total 296500 # number of LoadLockedReq miss cycles
741 system.cpu.dcache.demand_miss_latency::cpu.data 92738545358 # number of demand (read+write) miss cycles
742 system.cpu.dcache.demand_miss_latency::total 92738545358 # number of demand (read+write) miss cycles
743 system.cpu.dcache.overall_miss_latency::cpu.data 92738545358 # number of overall miss cycles
744 system.cpu.dcache.overall_miss_latency::total 92738545358 # number of overall miss cycles
745 system.cpu.dcache.ReadReq_accesses::cpu.data 23476967 # number of ReadReq accesses(hits+misses)
746 system.cpu.dcache.ReadReq_accesses::total 23476967 # number of ReadReq accesses(hits+misses)
747 system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses)
748 system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses)
749 system.cpu.dcache.SoftPFReq_accesses::cpu.data 529 # number of SoftPFReq accesses(hits+misses)
750 system.cpu.dcache.SoftPFReq_accesses::total 529 # number of SoftPFReq accesses(hits+misses)
751 system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 # number of LoadLockedReq accesses(hits+misses)
752 system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses)
753 system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses)
754 system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses)
755 system.cpu.dcache.demand_accesses::cpu.data 28211948 # number of demand (read+write) accesses
756 system.cpu.dcache.demand_accesses::total 28211948 # number of demand (read+write) accesses
757 system.cpu.dcache.overall_accesses::cpu.data 28212477 # number of overall (read+write) accesses
758 system.cpu.dcache.overall_accesses::total 28212477 # number of overall (read+write) accesses
759 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.408314 # miss rate for ReadReq accesses
760 system.cpu.dcache.ReadReq_miss_rate::total 0.408314 # miss rate for ReadReq accesses
761 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.080519 # miss rate for WriteReq accesses
762 system.cpu.dcache.WriteReq_miss_rate::total 0.080519 # miss rate for WriteReq accesses
763 system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.013233 # miss rate for SoftPFReq accesses
764 system.cpu.dcache.SoftPFReq_miss_rate::total 0.013233 # miss rate for SoftPFReq accesses
765 system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.003859 # miss rate for LoadLockedReq accesses
766 system.cpu.dcache.LoadLockedReq_miss_rate::total 0.003859 # miss rate for LoadLockedReq accesses
767 system.cpu.dcache.demand_miss_rate::cpu.data 0.353298 # miss rate for demand accesses
768 system.cpu.dcache.demand_miss_rate::total 0.353298 # miss rate for demand accesses
769 system.cpu.dcache.overall_miss_rate::cpu.data 0.353292 # miss rate for overall accesses
770 system.cpu.dcache.overall_miss_rate::total 0.353292 # miss rate for overall accesses
771 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9256.887149 # average ReadReq miss latency
772 system.cpu.dcache.ReadReq_avg_miss_latency::total 9256.887149 # average ReadReq miss latency
773 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10497.705887 # average WriteReq miss latency
774 system.cpu.dcache.WriteReq_avg_miss_latency::total 10497.705887 # average WriteReq miss latency
775 system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 19766.666667 # average LoadLockedReq miss latency
776 system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 19766.666667 # average LoadLockedReq miss latency
777 system.cpu.dcache.demand_avg_miss_latency::cpu.data 9304.349541 # average overall miss latency
778 system.cpu.dcache.demand_avg_miss_latency::total 9304.349541 # average overall miss latency
779 system.cpu.dcache.overall_avg_miss_latency::cpu.data 9304.343007 # average overall miss latency
780 system.cpu.dcache.overall_avg_miss_latency::total 9304.343007 # average overall miss latency
781 system.cpu.dcache.blocked_cycles::no_mshrs 330007 # number of cycles access was blocked
782 system.cpu.dcache.blocked_cycles::no_targets 109189 # number of cycles access was blocked
783 system.cpu.dcache.blocked::no_mshrs 121421 # number of cycles access was blocked
784 system.cpu.dcache.blocked::no_targets 12842 # number of cycles access was blocked
785 system.cpu.dcache.avg_blocked_cycles::no_mshrs 2.717874 # average number of cycles each access was blocked
786 system.cpu.dcache.avg_blocked_cycles::no_targets 8.502492 # average number of cycles each access was blocked
787 system.cpu.dcache.fast_writes 0 # number of fast writes performed
788 system.cpu.dcache.cache_copies 0 # number of cache copies performed
789 system.cpu.dcache.writebacks::writebacks 5470195 # number of writebacks
790 system.cpu.dcache.writebacks::total 5470195 # number of writebacks
791 system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4337753 # number of ReadReq MSHR hits
792 system.cpu.dcache.ReadReq_mshr_hits::total 4337753 # number of ReadReq MSHR hits
793 system.cpu.dcache.WriteReq_mshr_hits::cpu.data 158766 # number of WriteReq MSHR hits
794 system.cpu.dcache.WriteReq_mshr_hits::total 158766 # number of WriteReq MSHR hits
795 system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 15 # number of LoadLockedReq MSHR hits
796 system.cpu.dcache.LoadLockedReq_mshr_hits::total 15 # number of LoadLockedReq MSHR hits
797 system.cpu.dcache.demand_mshr_hits::cpu.data 4496519 # number of demand (read+write) MSHR hits
798 system.cpu.dcache.demand_mshr_hits::total 4496519 # number of demand (read+write) MSHR hits
799 system.cpu.dcache.overall_mshr_hits::cpu.data 4496519 # number of overall MSHR hits
800 system.cpu.dcache.overall_mshr_hits::total 4496519 # number of overall MSHR hits
801 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5248217 # number of ReadReq MSHR misses
802 system.cpu.dcache.ReadReq_mshr_misses::total 5248217 # number of ReadReq MSHR misses
803 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 222489 # number of WriteReq MSHR misses
804 system.cpu.dcache.WriteReq_mshr_misses::total 222489 # number of WriteReq MSHR misses
805 system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 4 # number of SoftPFReq MSHR misses
806 system.cpu.dcache.SoftPFReq_mshr_misses::total 4 # number of SoftPFReq MSHR misses
807 system.cpu.dcache.demand_mshr_misses::cpu.data 5470706 # number of demand (read+write) MSHR misses
808 system.cpu.dcache.demand_mshr_misses::total 5470706 # number of demand (read+write) MSHR misses
809 system.cpu.dcache.overall_mshr_misses::cpu.data 5470710 # number of overall MSHR misses
810 system.cpu.dcache.overall_mshr_misses::total 5470710 # number of overall MSHR misses
811 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 43257355500 # number of ReadReq MSHR miss cycles
812 system.cpu.dcache.ReadReq_mshr_miss_latency::total 43257355500 # number of ReadReq MSHR miss cycles
813 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2285854739 # number of WriteReq MSHR miss cycles
814 system.cpu.dcache.WriteReq_mshr_miss_latency::total 2285854739 # number of WriteReq MSHR miss cycles
815 system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 214500 # number of SoftPFReq MSHR miss cycles
816 system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 214500 # number of SoftPFReq MSHR miss cycles
817 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 45543210239 # number of demand (read+write) MSHR miss cycles
818 system.cpu.dcache.demand_mshr_miss_latency::total 45543210239 # number of demand (read+write) MSHR miss cycles
819 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 45543424739 # number of overall MSHR miss cycles
820 system.cpu.dcache.overall_mshr_miss_latency::total 45543424739 # number of overall MSHR miss cycles
821 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.223547 # mshr miss rate for ReadReq accesses
822 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.223547 # mshr miss rate for ReadReq accesses
823 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046988 # mshr miss rate for WriteReq accesses
824 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046988 # mshr miss rate for WriteReq accesses
825 system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.007561 # mshr miss rate for SoftPFReq accesses
826 system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.007561 # mshr miss rate for SoftPFReq accesses
827 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.193915 # mshr miss rate for demand accesses
828 system.cpu.dcache.demand_mshr_miss_rate::total 0.193915 # mshr miss rate for demand accesses
829 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.193911 # mshr miss rate for overall accesses
830 system.cpu.dcache.overall_mshr_miss_rate::total 0.193911 # mshr miss rate for overall accesses
831 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8242.295526 # average ReadReq mshr miss latency
832 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 8242.295526 # average ReadReq mshr miss latency
833 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10274.012374 # average WriteReq mshr miss latency
834 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10274.012374 # average WriteReq mshr miss latency
835 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53625 # average SoftPFReq mshr miss latency
836 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53625 # average SoftPFReq mshr miss latency
837 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8324.923737 # average overall mshr miss latency
838 system.cpu.dcache.demand_avg_mshr_miss_latency::total 8324.923737 # average overall mshr miss latency
839 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8324.956859 # average overall mshr miss latency
840 system.cpu.dcache.overall_avg_mshr_miss_latency::total 8324.956859 # average overall mshr miss latency
841 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
842 system.cpu.icache.tags.replacements 452 # number of replacements
843 system.cpu.icache.tags.tagsinuse 428.759642 # Cycle average of tags in use
844 system.cpu.icache.tags.total_refs 32301343 # Total number of references to valid blocks.
845 system.cpu.icache.tags.sampled_refs 911 # Sample count of references to valid blocks.
846 system.cpu.icache.tags.avg_refs 35457.017563 # Average number of references to valid blocks.
847 system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
848 system.cpu.icache.tags.occ_blocks::cpu.inst 428.759642 # Average occupied blocks per requestor
849 system.cpu.icache.tags.occ_percent::cpu.inst 0.837421 # Average percentage of cache occupancy
850 system.cpu.icache.tags.occ_percent::total 0.837421 # Average percentage of cache occupancy
851 system.cpu.icache.tags.occ_task_id_blocks::1024 459 # Occupied blocks per task id
852 system.cpu.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id
853 system.cpu.icache.tags.age_task_id_blocks_1024::2 52 # Occupied blocks per task id
854 system.cpu.icache.tags.age_task_id_blocks_1024::3 22 # Occupied blocks per task id
855 system.cpu.icache.tags.age_task_id_blocks_1024::4 331 # Occupied blocks per task id
856 system.cpu.icache.tags.occ_task_id_percent::1024 0.896484 # Percentage of cache occupancy per task id
857 system.cpu.icache.tags.tag_accesses 64605911 # Number of tag accesses
858 system.cpu.icache.tags.data_accesses 64605911 # Number of data accesses
859 system.cpu.icache.ReadReq_hits::cpu.inst 32301343 # number of ReadReq hits
860 system.cpu.icache.ReadReq_hits::total 32301343 # number of ReadReq hits
861 system.cpu.icache.demand_hits::cpu.inst 32301343 # number of demand (read+write) hits
862 system.cpu.icache.demand_hits::total 32301343 # number of demand (read+write) hits
863 system.cpu.icache.overall_hits::cpu.inst 32301343 # number of overall hits
864 system.cpu.icache.overall_hits::total 32301343 # number of overall hits
865 system.cpu.icache.ReadReq_misses::cpu.inst 1157 # number of ReadReq misses
866 system.cpu.icache.ReadReq_misses::total 1157 # number of ReadReq misses
867 system.cpu.icache.demand_misses::cpu.inst 1157 # number of demand (read+write) misses
868 system.cpu.icache.demand_misses::total 1157 # number of demand (read+write) misses
869 system.cpu.icache.overall_misses::cpu.inst 1157 # number of overall misses
870 system.cpu.icache.overall_misses::total 1157 # number of overall misses
871 system.cpu.icache.ReadReq_miss_latency::cpu.inst 61697981 # number of ReadReq miss cycles
872 system.cpu.icache.ReadReq_miss_latency::total 61697981 # number of ReadReq miss cycles
873 system.cpu.icache.demand_miss_latency::cpu.inst 61697981 # number of demand (read+write) miss cycles
874 system.cpu.icache.demand_miss_latency::total 61697981 # number of demand (read+write) miss cycles
875 system.cpu.icache.overall_miss_latency::cpu.inst 61697981 # number of overall miss cycles
876 system.cpu.icache.overall_miss_latency::total 61697981 # number of overall miss cycles
877 system.cpu.icache.ReadReq_accesses::cpu.inst 32302500 # number of ReadReq accesses(hits+misses)
878 system.cpu.icache.ReadReq_accesses::total 32302500 # number of ReadReq accesses(hits+misses)
879 system.cpu.icache.demand_accesses::cpu.inst 32302500 # number of demand (read+write) accesses
880 system.cpu.icache.demand_accesses::total 32302500 # number of demand (read+write) accesses
881 system.cpu.icache.overall_accesses::cpu.inst 32302500 # number of overall (read+write) accesses
882 system.cpu.icache.overall_accesses::total 32302500 # number of overall (read+write) accesses
883 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000036 # miss rate for ReadReq accesses
884 system.cpu.icache.ReadReq_miss_rate::total 0.000036 # miss rate for ReadReq accesses
885 system.cpu.icache.demand_miss_rate::cpu.inst 0.000036 # miss rate for demand accesses
886 system.cpu.icache.demand_miss_rate::total 0.000036 # miss rate for demand accesses
887 system.cpu.icache.overall_miss_rate::cpu.inst 0.000036 # miss rate for overall accesses
888 system.cpu.icache.overall_miss_rate::total 0.000036 # miss rate for overall accesses
889 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53325.826275 # average ReadReq miss latency
890 system.cpu.icache.ReadReq_avg_miss_latency::total 53325.826275 # average ReadReq miss latency
891 system.cpu.icache.demand_avg_miss_latency::cpu.inst 53325.826275 # average overall miss latency
892 system.cpu.icache.demand_avg_miss_latency::total 53325.826275 # average overall miss latency
893 system.cpu.icache.overall_avg_miss_latency::cpu.inst 53325.826275 # average overall miss latency
894 system.cpu.icache.overall_avg_miss_latency::total 53325.826275 # average overall miss latency
895 system.cpu.icache.blocked_cycles::no_mshrs 18986 # number of cycles access was blocked
896 system.cpu.icache.blocked_cycles::no_targets 108 # number of cycles access was blocked
897 system.cpu.icache.blocked::no_mshrs 225 # number of cycles access was blocked
898 system.cpu.icache.blocked::no_targets 5 # number of cycles access was blocked
899 system.cpu.icache.avg_blocked_cycles::no_mshrs 84.382222 # average number of cycles each access was blocked
900 system.cpu.icache.avg_blocked_cycles::no_targets 21.600000 # average number of cycles each access was blocked
901 system.cpu.icache.fast_writes 0 # number of fast writes performed
902 system.cpu.icache.cache_copies 0 # number of cache copies performed
903 system.cpu.icache.writebacks::writebacks 452 # number of writebacks
904 system.cpu.icache.writebacks::total 452 # number of writebacks
905 system.cpu.icache.ReadReq_mshr_hits::cpu.inst 245 # number of ReadReq MSHR hits
906 system.cpu.icache.ReadReq_mshr_hits::total 245 # number of ReadReq MSHR hits
907 system.cpu.icache.demand_mshr_hits::cpu.inst 245 # number of demand (read+write) MSHR hits
908 system.cpu.icache.demand_mshr_hits::total 245 # number of demand (read+write) MSHR hits
909 system.cpu.icache.overall_mshr_hits::cpu.inst 245 # number of overall MSHR hits
910 system.cpu.icache.overall_mshr_hits::total 245 # number of overall MSHR hits
911 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 912 # number of ReadReq MSHR misses
912 system.cpu.icache.ReadReq_mshr_misses::total 912 # number of ReadReq MSHR misses
913 system.cpu.icache.demand_mshr_misses::cpu.inst 912 # number of demand (read+write) MSHR misses
914 system.cpu.icache.demand_mshr_misses::total 912 # number of demand (read+write) MSHR misses
915 system.cpu.icache.overall_mshr_misses::cpu.inst 912 # number of overall MSHR misses
916 system.cpu.icache.overall_mshr_misses::total 912 # number of overall MSHR misses
917 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 50324485 # number of ReadReq MSHR miss cycles
918 system.cpu.icache.ReadReq_mshr_miss_latency::total 50324485 # number of ReadReq MSHR miss cycles
919 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 50324485 # number of demand (read+write) MSHR miss cycles
920 system.cpu.icache.demand_mshr_miss_latency::total 50324485 # number of demand (read+write) MSHR miss cycles
921 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 50324485 # number of overall MSHR miss cycles
922 system.cpu.icache.overall_mshr_miss_latency::total 50324485 # number of overall MSHR miss cycles
923 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for ReadReq accesses
924 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000028 # mshr miss rate for ReadReq accesses
925 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for demand accesses
926 system.cpu.icache.demand_mshr_miss_rate::total 0.000028 # mshr miss rate for demand accesses
927 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for overall accesses
928 system.cpu.icache.overall_mshr_miss_rate::total 0.000028 # mshr miss rate for overall accesses
929 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 55180.356360 # average ReadReq mshr miss latency
930 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 55180.356360 # average ReadReq mshr miss latency
931 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 55180.356360 # average overall mshr miss latency
932 system.cpu.icache.demand_avg_mshr_miss_latency::total 55180.356360 # average overall mshr miss latency
933 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 55180.356360 # average overall mshr miss latency
934 system.cpu.icache.overall_avg_mshr_miss_latency::total 55180.356360 # average overall mshr miss latency
935 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
936 system.cpu.l2cache.prefetcher.num_hwpf_issued 4981576 # number of hwpf issued
937 system.cpu.l2cache.prefetcher.pfIdentified 5296807 # number of prefetch candidates identified
938 system.cpu.l2cache.prefetcher.pfBufferHit 274066 # number of redundant prefetches already in prefetch queue
939 system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
940 system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
941 system.cpu.l2cache.prefetcher.pfSpanPage 14075593 # number of prefetches not generated due to page crossing
942 system.cpu.l2cache.tags.replacements 236 # number of replacements
943 system.cpu.l2cache.tags.tagsinuse 11228.158132 # Cycle average of tags in use
944 system.cpu.l2cache.tags.total_refs 5318864 # Total number of references to valid blocks.
945 system.cpu.l2cache.tags.sampled_refs 14906 # Sample count of references to valid blocks.
946 system.cpu.l2cache.tags.avg_refs 356.827050 # Average number of references to valid blocks.
947 system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
948 system.cpu.l2cache.tags.occ_blocks::writebacks 11064.722538 # Average occupied blocks per requestor
949 system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 163.435594 # Average occupied blocks per requestor
950 system.cpu.l2cache.tags.occ_percent::writebacks 0.675337 # Average percentage of cache occupancy
951 system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.009975 # Average percentage of cache occupancy
952 system.cpu.l2cache.tags.occ_percent::total 0.685312 # Average percentage of cache occupancy
953 system.cpu.l2cache.tags.occ_task_id_blocks::1022 176 # Occupied blocks per task id
954 system.cpu.l2cache.tags.occ_task_id_blocks::1024 14494 # Occupied blocks per task id
955 system.cpu.l2cache.tags.age_task_id_blocks_1022::0 2 # Occupied blocks per task id
956 system.cpu.l2cache.tags.age_task_id_blocks_1022::1 10 # Occupied blocks per task id
957 system.cpu.l2cache.tags.age_task_id_blocks_1022::2 4 # Occupied blocks per task id
958 system.cpu.l2cache.tags.age_task_id_blocks_1022::4 160 # Occupied blocks per task id
959 system.cpu.l2cache.tags.age_task_id_blocks_1024::0 493 # Occupied blocks per task id
960 system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3697 # Occupied blocks per task id
961 system.cpu.l2cache.tags.age_task_id_blocks_1024::2 9309 # Occupied blocks per task id
962 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 105 # Occupied blocks per task id
963 system.cpu.l2cache.tags.age_task_id_blocks_1024::4 890 # Occupied blocks per task id
964 system.cpu.l2cache.tags.occ_task_id_percent::1022 0.010742 # Percentage of cache occupancy per task id
965 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.884644 # Percentage of cache occupancy per task id
966 system.cpu.l2cache.tags.tag_accesses 180495153 # Number of tag accesses
967 system.cpu.l2cache.tags.data_accesses 180495153 # Number of data accesses
968 system.cpu.l2cache.WritebackDirty_hits::writebacks 5450602 # number of WritebackDirty hits
969 system.cpu.l2cache.WritebackDirty_hits::total 5450602 # number of WritebackDirty hits
970 system.cpu.l2cache.WritebackClean_hits::writebacks 17129 # number of WritebackClean hits
971 system.cpu.l2cache.WritebackClean_hits::total 17129 # number of WritebackClean hits
972 system.cpu.l2cache.ReadExReq_hits::cpu.data 226024 # number of ReadExReq hits
973 system.cpu.l2cache.ReadExReq_hits::total 226024 # number of ReadExReq hits
974 system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 209 # number of ReadCleanReq hits
975 system.cpu.l2cache.ReadCleanReq_hits::total 209 # number of ReadCleanReq hits
976 system.cpu.l2cache.ReadSharedReq_hits::cpu.data 5243596 # number of ReadSharedReq hits
977 system.cpu.l2cache.ReadSharedReq_hits::total 5243596 # number of ReadSharedReq hits
978 system.cpu.l2cache.demand_hits::cpu.inst 209 # number of demand (read+write) hits
979 system.cpu.l2cache.demand_hits::cpu.data 5469620 # number of demand (read+write) hits
980 system.cpu.l2cache.demand_hits::total 5469829 # number of demand (read+write) hits
981 system.cpu.l2cache.overall_hits::cpu.inst 209 # number of overall hits
982 system.cpu.l2cache.overall_hits::cpu.data 5469620 # number of overall hits
983 system.cpu.l2cache.overall_hits::total 5469829 # number of overall hits
984 system.cpu.l2cache.UpgradeReq_misses::cpu.data 3 # number of UpgradeReq misses
985 system.cpu.l2cache.UpgradeReq_misses::total 3 # number of UpgradeReq misses
986 system.cpu.l2cache.ReadExReq_misses::cpu.data 499 # number of ReadExReq misses
987 system.cpu.l2cache.ReadExReq_misses::total 499 # number of ReadExReq misses
988 system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 703 # number of ReadCleanReq misses
989 system.cpu.l2cache.ReadCleanReq_misses::total 703 # number of ReadCleanReq misses
990 system.cpu.l2cache.ReadSharedReq_misses::cpu.data 588 # number of ReadSharedReq misses
991 system.cpu.l2cache.ReadSharedReq_misses::total 588 # number of ReadSharedReq misses
992 system.cpu.l2cache.demand_misses::cpu.inst 703 # number of demand (read+write) misses
993 system.cpu.l2cache.demand_misses::cpu.data 1087 # number of demand (read+write) misses
994 system.cpu.l2cache.demand_misses::total 1790 # number of demand (read+write) misses
995 system.cpu.l2cache.overall_misses::cpu.inst 703 # number of overall misses
996 system.cpu.l2cache.overall_misses::cpu.data 1087 # number of overall misses
997 system.cpu.l2cache.overall_misses::total 1790 # number of overall misses
998 system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 60500 # number of UpgradeReq miss cycles
999 system.cpu.l2cache.UpgradeReq_miss_latency::total 60500 # number of UpgradeReq miss cycles
1000 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 41219500 # number of ReadExReq miss cycles
1001 system.cpu.l2cache.ReadExReq_miss_latency::total 41219500 # number of ReadExReq miss cycles
1002 system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 48001500 # number of ReadCleanReq miss cycles
1003 system.cpu.l2cache.ReadCleanReq_miss_latency::total 48001500 # number of ReadCleanReq miss cycles
1004 system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 40148500 # number of ReadSharedReq miss cycles
1005 system.cpu.l2cache.ReadSharedReq_miss_latency::total 40148500 # number of ReadSharedReq miss cycles
1006 system.cpu.l2cache.demand_miss_latency::cpu.inst 48001500 # number of demand (read+write) miss cycles
1007 system.cpu.l2cache.demand_miss_latency::cpu.data 81368000 # number of demand (read+write) miss cycles
1008 system.cpu.l2cache.demand_miss_latency::total 129369500 # number of demand (read+write) miss cycles
1009 system.cpu.l2cache.overall_miss_latency::cpu.inst 48001500 # number of overall miss cycles
1010 system.cpu.l2cache.overall_miss_latency::cpu.data 81368000 # number of overall miss cycles
1011 system.cpu.l2cache.overall_miss_latency::total 129369500 # number of overall miss cycles
1012 system.cpu.l2cache.WritebackDirty_accesses::writebacks 5450602 # number of WritebackDirty accesses(hits+misses)
1013 system.cpu.l2cache.WritebackDirty_accesses::total 5450602 # number of WritebackDirty accesses(hits+misses)
1014 system.cpu.l2cache.WritebackClean_accesses::writebacks 17129 # number of WritebackClean accesses(hits+misses)
1015 system.cpu.l2cache.WritebackClean_accesses::total 17129 # number of WritebackClean accesses(hits+misses)
1016 system.cpu.l2cache.UpgradeReq_accesses::cpu.data 3 # number of UpgradeReq accesses(hits+misses)
1017 system.cpu.l2cache.UpgradeReq_accesses::total 3 # number of UpgradeReq accesses(hits+misses)
1018 system.cpu.l2cache.ReadExReq_accesses::cpu.data 226523 # number of ReadExReq accesses(hits+misses)
1019 system.cpu.l2cache.ReadExReq_accesses::total 226523 # number of ReadExReq accesses(hits+misses)
1020 system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 912 # number of ReadCleanReq accesses(hits+misses)
1021 system.cpu.l2cache.ReadCleanReq_accesses::total 912 # number of ReadCleanReq accesses(hits+misses)
1022 system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 5244184 # number of ReadSharedReq accesses(hits+misses)
1023 system.cpu.l2cache.ReadSharedReq_accesses::total 5244184 # number of ReadSharedReq accesses(hits+misses)
1024 system.cpu.l2cache.demand_accesses::cpu.inst 912 # number of demand (read+write) accesses
1025 system.cpu.l2cache.demand_accesses::cpu.data 5470707 # number of demand (read+write) accesses
1026 system.cpu.l2cache.demand_accesses::total 5471619 # number of demand (read+write) accesses
1027 system.cpu.l2cache.overall_accesses::cpu.inst 912 # number of overall (read+write) accesses
1028 system.cpu.l2cache.overall_accesses::cpu.data 5470707 # number of overall (read+write) accesses
1029 system.cpu.l2cache.overall_accesses::total 5471619 # number of overall (read+write) accesses
1030 system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses
1031 system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses
1032 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.002203 # miss rate for ReadExReq accesses
1033 system.cpu.l2cache.ReadExReq_miss_rate::total 0.002203 # miss rate for ReadExReq accesses
1034 system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.770833 # miss rate for ReadCleanReq accesses
1035 system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.770833 # miss rate for ReadCleanReq accesses
1036 system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000112 # miss rate for ReadSharedReq accesses
1037 system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000112 # miss rate for ReadSharedReq accesses
1038 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.770833 # miss rate for demand accesses
1039 system.cpu.l2cache.demand_miss_rate::cpu.data 0.000199 # miss rate for demand accesses
1040 system.cpu.l2cache.demand_miss_rate::total 0.000327 # miss rate for demand accesses
1041 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.770833 # miss rate for overall accesses
1042 system.cpu.l2cache.overall_miss_rate::cpu.data 0.000199 # miss rate for overall accesses
1043 system.cpu.l2cache.overall_miss_rate::total 0.000327 # miss rate for overall accesses
1044 system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 20166.666667 # average UpgradeReq miss latency
1045 system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 20166.666667 # average UpgradeReq miss latency
1046 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 82604.208417 # average ReadExReq miss latency
1047 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 82604.208417 # average ReadExReq miss latency
1048 system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 68280.938834 # average ReadCleanReq miss latency
1049 system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 68280.938834 # average ReadCleanReq miss latency
1050 system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 68279.761905 # average ReadSharedReq miss latency
1051 system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 68279.761905 # average ReadSharedReq miss latency
1052 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68280.938834 # average overall miss latency
1053 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74855.565777 # average overall miss latency
1054 system.cpu.l2cache.demand_avg_miss_latency::total 72273.463687 # average overall miss latency
1055 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68280.938834 # average overall miss latency
1056 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74855.565777 # average overall miss latency
1057 system.cpu.l2cache.overall_avg_miss_latency::total 72273.463687 # average overall miss latency
1058 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1059 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1060 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
1061 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1062 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1063 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1064 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
1065 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
1066 system.cpu.l2cache.writebacks::writebacks 170 # number of writebacks
1067 system.cpu.l2cache.writebacks::total 170 # number of writebacks
1068 system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 158 # number of ReadExReq MSHR hits
1069 system.cpu.l2cache.ReadExReq_mshr_hits::total 158 # number of ReadExReq MSHR hits
1070 system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits
1071 system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits
1072 system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 32 # number of ReadSharedReq MSHR hits
1073 system.cpu.l2cache.ReadSharedReq_mshr_hits::total 32 # number of ReadSharedReq MSHR hits
1074 system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
1075 system.cpu.l2cache.demand_mshr_hits::cpu.data 190 # number of demand (read+write) MSHR hits
1076 system.cpu.l2cache.demand_mshr_hits::total 191 # number of demand (read+write) MSHR hits
1077 system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
1078 system.cpu.l2cache.overall_mshr_hits::cpu.data 190 # number of overall MSHR hits
1079 system.cpu.l2cache.overall_mshr_hits::total 191 # number of overall MSHR hits
1080 system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 316176 # number of HardPFReq MSHR misses
1081 system.cpu.l2cache.HardPFReq_mshr_misses::total 316176 # number of HardPFReq MSHR misses
1082 system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 3 # number of UpgradeReq MSHR misses
1083 system.cpu.l2cache.UpgradeReq_mshr_misses::total 3 # number of UpgradeReq MSHR misses
1084 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 341 # number of ReadExReq MSHR misses
1085 system.cpu.l2cache.ReadExReq_mshr_misses::total 341 # number of ReadExReq MSHR misses
1086 system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 702 # number of ReadCleanReq MSHR misses
1087 system.cpu.l2cache.ReadCleanReq_mshr_misses::total 702 # number of ReadCleanReq MSHR misses
1088 system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 556 # number of ReadSharedReq MSHR misses
1089 system.cpu.l2cache.ReadSharedReq_mshr_misses::total 556 # number of ReadSharedReq MSHR misses
1090 system.cpu.l2cache.demand_mshr_misses::cpu.inst 702 # number of demand (read+write) MSHR misses
1091 system.cpu.l2cache.demand_mshr_misses::cpu.data 897 # number of demand (read+write) MSHR misses
1092 system.cpu.l2cache.demand_mshr_misses::total 1599 # number of demand (read+write) MSHR misses
1093 system.cpu.l2cache.overall_mshr_misses::cpu.inst 702 # number of overall MSHR misses
1094 system.cpu.l2cache.overall_mshr_misses::cpu.data 897 # number of overall MSHR misses
1095 system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 316176 # number of overall MSHR misses
1096 system.cpu.l2cache.overall_mshr_misses::total 317775 # number of overall MSHR misses
1097 system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 851895298 # number of HardPFReq MSHR miss cycles
1098 system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 851895298 # number of HardPFReq MSHR miss cycles
1099 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 42500 # number of UpgradeReq MSHR miss cycles
1100 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 42500 # number of UpgradeReq MSHR miss cycles
1101 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 32684500 # number of ReadExReq MSHR miss cycles
1102 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 32684500 # number of ReadExReq MSHR miss cycles
1103 system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 43736000 # number of ReadCleanReq MSHR miss cycles
1104 system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 43736000 # number of ReadCleanReq MSHR miss cycles
1105 system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 35150000 # number of ReadSharedReq MSHR miss cycles
1106 system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 35150000 # number of ReadSharedReq MSHR miss cycles
1107 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 43736000 # number of demand (read+write) MSHR miss cycles
1108 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 67834500 # number of demand (read+write) MSHR miss cycles
1109 system.cpu.l2cache.demand_mshr_miss_latency::total 111570500 # number of demand (read+write) MSHR miss cycles
1110 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 43736000 # number of overall MSHR miss cycles
1111 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 67834500 # number of overall MSHR miss cycles
1112 system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 851895298 # number of overall MSHR miss cycles
1113 system.cpu.l2cache.overall_mshr_miss_latency::total 963465798 # number of overall MSHR miss cycles
1114 system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
1115 system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
1116 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses
1117 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
1118 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001505 # mshr miss rate for ReadExReq accesses
1119 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001505 # mshr miss rate for ReadExReq accesses
1120 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.769737 # mshr miss rate for ReadCleanReq accesses
1121 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.769737 # mshr miss rate for ReadCleanReq accesses
1122 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000106 # mshr miss rate for ReadSharedReq accesses
1123 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000106 # mshr miss rate for ReadSharedReq accesses
1124 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.769737 # mshr miss rate for demand accesses
1125 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.000164 # mshr miss rate for demand accesses
1126 system.cpu.l2cache.demand_mshr_miss_rate::total 0.000292 # mshr miss rate for demand accesses
1127 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.769737 # mshr miss rate for overall accesses
1128 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.000164 # mshr miss rate for overall accesses
1129 system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses
1130 system.cpu.l2cache.overall_mshr_miss_rate::total 0.058077 # mshr miss rate for overall accesses
1131 system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 2694.370534 # average HardPFReq mshr miss latency
1132 system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 2694.370534 # average HardPFReq mshr miss latency
1133 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14166.666667 # average UpgradeReq mshr miss latency
1134 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14166.666667 # average UpgradeReq mshr miss latency
1135 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 95848.973607 # average ReadExReq mshr miss latency
1136 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 95848.973607 # average ReadExReq mshr miss latency
1137 system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 62301.994302 # average ReadCleanReq mshr miss latency
1138 system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 62301.994302 # average ReadCleanReq mshr miss latency
1139 system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 63219.424460 # average ReadSharedReq mshr miss latency
1140 system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 63219.424460 # average ReadSharedReq mshr miss latency
1141 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62301.994302 # average overall mshr miss latency
1142 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 75623.745819 # average overall mshr miss latency
1143 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69775.171982 # average overall mshr miss latency
1144 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62301.994302 # average overall mshr miss latency
1145 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 75623.745819 # average overall mshr miss latency
1146 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 2694.370534 # average overall mshr miss latency
1147 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 3031.911881 # average overall mshr miss latency
1148 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
1149 system.cpu.toL2Bus.snoop_filter.tot_requests 10942269 # Total number of requests made to the snoop filter.
1150 system.cpu.toL2Bus.snoop_filter.hit_single_requests 5470664 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1151 system.cpu.toL2Bus.snoop_filter.hit_multi_requests 2916 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1152 system.cpu.toL2Bus.snoop_filter.tot_snoops 303004 # Total number of snoops made to the snoop filter.
1153 system.cpu.toL2Bus.snoop_filter.hit_single_snoops 302696 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1154 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 308 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
1155 system.cpu.toL2Bus.trans_dist::ReadResp 5245095 # Transaction distribution
1156 system.cpu.toL2Bus.trans_dist::WritebackDirty 5450772 # Transaction distribution
1157 system.cpu.toL2Bus.trans_dist::WritebackClean 20045 # Transaction distribution
1158 system.cpu.toL2Bus.trans_dist::CleanEvict 1323 # Transaction distribution
1159 system.cpu.toL2Bus.trans_dist::HardPFReq 318050 # Transaction distribution
1160 system.cpu.toL2Bus.trans_dist::HardPFResp 4 # Transaction distribution
1161 system.cpu.toL2Bus.trans_dist::UpgradeReq 3 # Transaction distribution
1162 system.cpu.toL2Bus.trans_dist::UpgradeResp 3 # Transaction distribution
1163 system.cpu.toL2Bus.trans_dist::ReadExReq 226523 # Transaction distribution
1164 system.cpu.toL2Bus.trans_dist::ReadExResp 226523 # Transaction distribution
1165 system.cpu.toL2Bus.trans_dist::ReadCleanReq 912 # Transaction distribution
1166 system.cpu.toL2Bus.trans_dist::ReadSharedReq 5244184 # Transaction distribution
1167 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2275 # Packet count per connected master and slave (bytes)
1168 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 16411619 # Packet count per connected master and slave (bytes)
1169 system.cpu.toL2Bus.pkt_count::total 16413894 # Packet count per connected master and slave (bytes)
1170 system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 87232 # Cumulative packet size per connected master and slave (bytes)
1171 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 700217984 # Cumulative packet size per connected master and slave (bytes)
1172 system.cpu.toL2Bus.pkt_size::total 700305216 # Cumulative packet size per connected master and slave (bytes)
1173 system.cpu.toL2Bus.snoops 319547 # Total snoops (count)
1174 system.cpu.toL2Bus.snoop_fanout::samples 5791165 # Request fanout histogram
1175 system.cpu.toL2Bus.snoop_fanout::mean 0.052881 # Request fanout histogram
1176 system.cpu.toL2Bus.snoop_fanout::stdev 0.224033 # Request fanout histogram
1177 system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1178 system.cpu.toL2Bus.snoop_fanout::0 5485231 94.72% 94.72% # Request fanout histogram
1179 system.cpu.toL2Bus.snoop_fanout::1 305626 5.28% 99.99% # Request fanout histogram
1180 system.cpu.toL2Bus.snoop_fanout::2 308 0.01% 100.00% # Request fanout histogram
1181 system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1182 system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
1183 system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
1184 system.cpu.toL2Bus.snoop_fanout::total 5791165 # Request fanout histogram
1185 system.cpu.toL2Bus.reqLayer0.occupancy 10941781515 # Layer occupancy (ticks)
1186 system.cpu.toL2Bus.reqLayer0.utilization 18.8 # Layer utilization (%)
1187 system.cpu.toL2Bus.snoopLayer0.occupancy 6019 # Layer occupancy (ticks)
1188 system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
1189 system.cpu.toL2Bus.respLayer0.occupancy 1367498 # Layer occupancy (ticks)
1190 system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
1191 system.cpu.toL2Bus.respLayer1.occupancy 8206066491 # Layer occupancy (ticks)
1192 system.cpu.toL2Bus.respLayer1.utilization 14.1 # Layer utilization (%)
1193 system.membus.trans_dist::ReadResp 15694 # Transaction distribution
1194 system.membus.trans_dist::WritebackDirty 170 # Transaction distribution
1195 system.membus.trans_dist::CleanEvict 58 # Transaction distribution
1196 system.membus.trans_dist::UpgradeReq 4 # Transaction distribution
1197 system.membus.trans_dist::ReadExReq 340 # Transaction distribution
1198 system.membus.trans_dist::ReadExResp 340 # Transaction distribution
1199 system.membus.trans_dist::ReadSharedReq 15695 # Transaction distribution
1200 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 32301 # Packet count per connected master and slave (bytes)
1201 system.membus.pkt_count::total 32301 # Packet count per connected master and slave (bytes)
1202 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1037056 # Cumulative packet size per connected master and slave (bytes)
1203 system.membus.pkt_size::total 1037056 # Cumulative packet size per connected master and slave (bytes)
1204 system.membus.snoops 0 # Total snoops (count)
1205 system.membus.snoop_fanout::samples 16267 # Request fanout histogram
1206 system.membus.snoop_fanout::mean 0 # Request fanout histogram
1207 system.membus.snoop_fanout::stdev 0 # Request fanout histogram
1208 system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1209 system.membus.snoop_fanout::0 16267 100.00% 100.00% # Request fanout histogram
1210 system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
1211 system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1212 system.membus.snoop_fanout::min_value 0 # Request fanout histogram
1213 system.membus.snoop_fanout::max_value 0 # Request fanout histogram
1214 system.membus.snoop_fanout::total 16267 # Request fanout histogram
1215 system.membus.reqLayer0.occupancy 26872796 # Layer occupancy (ticks)
1216 system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
1217 system.membus.respLayer1.occupancy 83907066 # Layer occupancy (ticks)
1218 system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
1220 ---------- End Simulation Statistics ----------
projects / gem5.git / blob