2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.057713 # Number of seconds simulated
4 sim_ticks 57712782000 # Number of ticks simulated
5 final_tick 57712782000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 133015 # Simulator instruction rate (inst/s)
8 host_op_rate 133677 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 84740771 # Simulator tick rate (ticks/s)
10 host_mem_usage 440040 # Number of bytes of host memory used
11 host_seconds 681.05 # Real time elapsed on the host
12 sim_insts 90589798 # Number of instructions simulated
13 sim_ops 91041029 # Number of ops (including micro ops) simulated
14 system.voltage_domain.voltage 1 # Voltage in Volts
15 system.clk_domain.clock 1000 # Clock period in ticks
16 system.physmem.bytes_read::cpu.inst 8896 # Number of bytes read from this memory
17 system.physmem.bytes_read::cpu.data 68416 # Number of bytes read from this memory
18 system.physmem.bytes_read::cpu.l2cache.prefetcher 1042048 # Number of bytes read from this memory
19 system.physmem.bytes_read::total 1119360 # Number of bytes read from this memory
20 system.physmem.bytes_inst_read::cpu.inst 8896 # Number of instructions bytes read from this memory
21 system.physmem.bytes_inst_read::total 8896 # Number of instructions bytes read from this memory
22 system.physmem.bytes_written::writebacks 73600 # Number of bytes written to this memory
23 system.physmem.bytes_written::total 73600 # Number of bytes written to this memory
24 system.physmem.num_reads::cpu.inst 139 # Number of read requests responded to by this memory
25 system.physmem.num_reads::cpu.data 1069 # Number of read requests responded to by this memory
26 system.physmem.num_reads::cpu.l2cache.prefetcher 16282 # Number of read requests responded to by this memory
27 system.physmem.num_reads::total 17490 # Number of read requests responded to by this memory
28 system.physmem.num_writes::writebacks 1150 # Number of write requests responded to by this memory
29 system.physmem.num_writes::total 1150 # Number of write requests responded to by this memory
30 system.physmem.bw_read::cpu.inst 154143 # Total read bandwidth from this memory (bytes/s)
31 system.physmem.bw_read::cpu.data 1185457 # Total read bandwidth from this memory (bytes/s)
32 system.physmem.bw_read::cpu.l2cache.prefetcher 18055758 # Total read bandwidth from this memory (bytes/s)
33 system.physmem.bw_read::total 19395357 # Total read bandwidth from this memory (bytes/s)
34 system.physmem.bw_inst_read::cpu.inst 154143 # Instruction read bandwidth from this memory (bytes/s)
35 system.physmem.bw_inst_read::total 154143 # Instruction read bandwidth from this memory (bytes/s)
36 system.physmem.bw_write::writebacks 1275281 # Write bandwidth from this memory (bytes/s)
37 system.physmem.bw_write::total 1275281 # Write bandwidth from this memory (bytes/s)
38 system.physmem.bw_total::writebacks 1275281 # Total bandwidth to/from this memory (bytes/s)
39 system.physmem.bw_total::cpu.inst 154143 # Total bandwidth to/from this memory (bytes/s)
40 system.physmem.bw_total::cpu.data 1185457 # Total bandwidth to/from this memory (bytes/s)
41 system.physmem.bw_total::cpu.l2cache.prefetcher 18055758 # Total bandwidth to/from this memory (bytes/s)
42 system.physmem.bw_total::total 20670638 # Total bandwidth to/from this memory (bytes/s)
43 system.physmem.readReqs 17490 # Number of read requests accepted
44 system.physmem.writeReqs 1150 # Number of write requests accepted
45 system.physmem.readBursts 17490 # Number of DRAM read bursts, including those serviced by the write queue
46 system.physmem.writeBursts 1150 # Number of DRAM write bursts, including those merged in the write queue
47 system.physmem.bytesReadDRAM 1100032 # Total number of bytes read from DRAM
48 system.physmem.bytesReadWrQ 19328 # Total number of bytes read from write queue
49 system.physmem.bytesWritten 71488 # Total number of bytes written to DRAM
50 system.physmem.bytesReadSys 1119360 # Total read bytes from the system interface side
51 system.physmem.bytesWrittenSys 73600 # Total written bytes from the system interface side
52 system.physmem.servicedByWrQ 302 # Number of DRAM read bursts serviced by the write queue
53 system.physmem.mergedWrBursts 4 # Number of DRAM write bursts merged with an existing one
54 system.physmem.neitherReadNorWriteReqs 2 # Number of requests that are neither read nor write
55 system.physmem.perBankRdBursts::0 1094 # Per bank write bursts
56 system.physmem.perBankRdBursts::1 953 # Per bank write bursts
57 system.physmem.perBankRdBursts::2 1083 # Per bank write bursts
58 system.physmem.perBankRdBursts::3 1113 # Per bank write bursts
59 system.physmem.perBankRdBursts::4 1125 # Per bank write bursts
60 system.physmem.perBankRdBursts::5 1235 # Per bank write bursts
61 system.physmem.perBankRdBursts::6 1314 # Per bank write bursts
62 system.physmem.perBankRdBursts::7 1243 # Per bank write bursts
63 system.physmem.perBankRdBursts::8 1060 # Per bank write bursts
64 system.physmem.perBankRdBursts::9 962 # Per bank write bursts
65 system.physmem.perBankRdBursts::10 1021 # Per bank write bursts
66 system.physmem.perBankRdBursts::11 923 # Per bank write bursts
67 system.physmem.perBankRdBursts::12 921 # Per bank write bursts
68 system.physmem.perBankRdBursts::13 987 # Per bank write bursts
69 system.physmem.perBankRdBursts::14 1105 # Per bank write bursts
70 system.physmem.perBankRdBursts::15 1049 # Per bank write bursts
71 system.physmem.perBankWrBursts::0 72 # Per bank write bursts
72 system.physmem.perBankWrBursts::1 0 # Per bank write bursts
73 system.physmem.perBankWrBursts::2 62 # Per bank write bursts
74 system.physmem.perBankWrBursts::3 19 # Per bank write bursts
75 system.physmem.perBankWrBursts::4 14 # Per bank write bursts
76 system.physmem.perBankWrBursts::5 111 # Per bank write bursts
77 system.physmem.perBankWrBursts::6 193 # Per bank write bursts
78 system.physmem.perBankWrBursts::7 122 # Per bank write bursts
79 system.physmem.perBankWrBursts::8 49 # Per bank write bursts
80 system.physmem.perBankWrBursts::9 0 # Per bank write bursts
81 system.physmem.perBankWrBursts::10 68 # Per bank write bursts
82 system.physmem.perBankWrBursts::11 20 # Per bank write bursts
83 system.physmem.perBankWrBursts::12 15 # Per bank write bursts
84 system.physmem.perBankWrBursts::13 94 # Per bank write bursts
85 system.physmem.perBankWrBursts::14 168 # Per bank write bursts
86 system.physmem.perBankWrBursts::15 110 # Per bank write bursts
87 system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
88 system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
89 system.physmem.totGap 57712604500 # Total gap between requests
90 system.physmem.readPktSize::0 0 # Read request sizes (log2)
91 system.physmem.readPktSize::1 0 # Read request sizes (log2)
92 system.physmem.readPktSize::2 0 # Read request sizes (log2)
93 system.physmem.readPktSize::3 0 # Read request sizes (log2)
94 system.physmem.readPktSize::4 0 # Read request sizes (log2)
95 system.physmem.readPktSize::5 0 # Read request sizes (log2)
96 system.physmem.readPktSize::6 17490 # Read request sizes (log2)
97 system.physmem.writePktSize::0 0 # Write request sizes (log2)
98 system.physmem.writePktSize::1 0 # Write request sizes (log2)
99 system.physmem.writePktSize::2 0 # Write request sizes (log2)
100 system.physmem.writePktSize::3 0 # Write request sizes (log2)
101 system.physmem.writePktSize::4 0 # Write request sizes (log2)
102 system.physmem.writePktSize::5 0 # Write request sizes (log2)
103 system.physmem.writePktSize::6 1150 # Write request sizes (log2)
104 system.physmem.rdQLenPdf::0 11254 # What read queue length does an incoming req see
105 system.physmem.rdQLenPdf::1 2508 # What read queue length does an incoming req see
106 system.physmem.rdQLenPdf::2 618 # What read queue length does an incoming req see
107 system.physmem.rdQLenPdf::3 551 # What read queue length does an incoming req see
108 system.physmem.rdQLenPdf::4 453 # What read queue length does an incoming req see
109 system.physmem.rdQLenPdf::5 423 # What read queue length does an incoming req see
110 system.physmem.rdQLenPdf::6 408 # What read queue length does an incoming req see
111 system.physmem.rdQLenPdf::7 392 # What read queue length does an incoming req see
112 system.physmem.rdQLenPdf::8 391 # What read queue length does an incoming req see
113 system.physmem.rdQLenPdf::9 120 # What read queue length does an incoming req see
114 system.physmem.rdQLenPdf::10 33 # What read queue length does an incoming req see
115 system.physmem.rdQLenPdf::11 23 # What read queue length does an incoming req see
116 system.physmem.rdQLenPdf::12 7 # What read queue length does an incoming req see
117 system.physmem.rdQLenPdf::13 4 # What read queue length does an incoming req see
118 system.physmem.rdQLenPdf::14 3 # What read queue length does an incoming req see
119 system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
120 system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
121 system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
122 system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
123 system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
124 system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
125 system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
126 system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
127 system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
128 system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
129 system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
130 system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
131 system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
132 system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
133 system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
134 system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
135 system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
136 system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
137 system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
138 system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
139 system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
140 system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
141 system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
142 system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
143 system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
144 system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
145 system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
146 system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
147 system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
148 system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
149 system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
150 system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
151 system.physmem.wrQLenPdf::15 50 # What write queue length does an incoming req see
152 system.physmem.wrQLenPdf::16 51 # What write queue length does an incoming req see
153 system.physmem.wrQLenPdf::17 59 # What write queue length does an incoming req see
154 system.physmem.wrQLenPdf::18 61 # What write queue length does an incoming req see
155 system.physmem.wrQLenPdf::19 62 # What write queue length does an incoming req see
156 system.physmem.wrQLenPdf::20 63 # What write queue length does an incoming req see
157 system.physmem.wrQLenPdf::21 63 # What write queue length does an incoming req see
158 system.physmem.wrQLenPdf::22 66 # What write queue length does an incoming req see
159 system.physmem.wrQLenPdf::23 66 # What write queue length does an incoming req see
160 system.physmem.wrQLenPdf::24 66 # What write queue length does an incoming req see
161 system.physmem.wrQLenPdf::25 66 # What write queue length does an incoming req see
162 system.physmem.wrQLenPdf::26 68 # What write queue length does an incoming req see
163 system.physmem.wrQLenPdf::27 70 # What write queue length does an incoming req see
164 system.physmem.wrQLenPdf::28 68 # What write queue length does an incoming req see
165 system.physmem.wrQLenPdf::29 63 # What write queue length does an incoming req see
166 system.physmem.wrQLenPdf::30 63 # What write queue length does an incoming req see
167 system.physmem.wrQLenPdf::31 63 # What write queue length does an incoming req see
168 system.physmem.wrQLenPdf::32 63 # What write queue length does an incoming req see
169 system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
170 system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
171 system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
172 system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
173 system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
174 system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
175 system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
176 system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
177 system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
178 system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
179 system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
180 system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
181 system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
182 system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
183 system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
184 system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
185 system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
186 system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
187 system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
188 system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
189 system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
190 system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
191 system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
192 system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
193 system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
194 system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
195 system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
196 system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
197 system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
198 system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
199 system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
200 system.physmem.bytesPerActivate::samples 2975 # Bytes accessed per row activation
201 system.physmem.bytesPerActivate::mean 393.336471 # Bytes accessed per row activation
202 system.physmem.bytesPerActivate::gmean 197.951950 # Bytes accessed per row activation
203 system.physmem.bytesPerActivate::stdev 413.488148 # Bytes accessed per row activation
204 system.physmem.bytesPerActivate::0-127 1360 45.71% 45.71% # Bytes accessed per row activation
205 system.physmem.bytesPerActivate::128-255 404 13.58% 59.29% # Bytes accessed per row activation
206 system.physmem.bytesPerActivate::256-383 131 4.40% 63.70% # Bytes accessed per row activation
207 system.physmem.bytesPerActivate::384-511 68 2.29% 65.98% # Bytes accessed per row activation
208 system.physmem.bytesPerActivate::512-639 81 2.72% 68.71% # Bytes accessed per row activation
209 system.physmem.bytesPerActivate::640-767 67 2.25% 70.96% # Bytes accessed per row activation
210 system.physmem.bytesPerActivate::768-895 54 1.82% 72.77% # Bytes accessed per row activation
211 system.physmem.bytesPerActivate::896-1023 34 1.14% 73.92% # Bytes accessed per row activation
212 system.physmem.bytesPerActivate::1024-1151 776 26.08% 100.00% # Bytes accessed per row activation
213 system.physmem.bytesPerActivate::total 2975 # Bytes accessed per row activation
214 system.physmem.rdPerTurnAround::samples 63 # Reads before turning the bus around for writes
215 system.physmem.rdPerTurnAround::mean 272.444444 # Reads before turning the bus around for writes
216 system.physmem.rdPerTurnAround::gmean 27.585882 # Reads before turning the bus around for writes
217 system.physmem.rdPerTurnAround::stdev 1910.173610 # Reads before turning the bus around for writes
218 system.physmem.rdPerTurnAround::0-511 62 98.41% 98.41% # Reads before turning the bus around for writes
219 system.physmem.rdPerTurnAround::14848-15359 1 1.59% 100.00% # Reads before turning the bus around for writes
220 system.physmem.rdPerTurnAround::total 63 # Reads before turning the bus around for writes
221 system.physmem.wrPerTurnAround::samples 63 # Writes before turning the bus around for reads
222 system.physmem.wrPerTurnAround::mean 17.730159 # Writes before turning the bus around for reads
223 system.physmem.wrPerTurnAround::gmean 17.698769 # Writes before turning the bus around for reads
224 system.physmem.wrPerTurnAround::stdev 1.080716 # Writes before turning the bus around for reads
225 system.physmem.wrPerTurnAround::16 12 19.05% 19.05% # Writes before turning the bus around for reads
226 system.physmem.wrPerTurnAround::17 1 1.59% 20.63% # Writes before turning the bus around for reads
227 system.physmem.wrPerTurnAround::18 46 73.02% 93.65% # Writes before turning the bus around for reads
228 system.physmem.wrPerTurnAround::19 3 4.76% 98.41% # Writes before turning the bus around for reads
229 system.physmem.wrPerTurnAround::23 1 1.59% 100.00% # Writes before turning the bus around for reads
230 system.physmem.wrPerTurnAround::total 63 # Writes before turning the bus around for reads
231 system.physmem.totQLat 228948216 # Total ticks spent queuing
232 system.physmem.totMemAccLat 551223216 # Total ticks spent from burst creation until serviced by the DRAM
233 system.physmem.totBusLat 85940000 # Total ticks spent in databus transfers
234 system.physmem.avgQLat 13320.24 # Average queueing delay per DRAM burst
235 system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
236 system.physmem.avgMemAccLat 32070.24 # Average memory access latency per DRAM burst
237 system.physmem.avgRdBW 19.06 # Average DRAM read bandwidth in MiByte/s
238 system.physmem.avgWrBW 1.24 # Average achieved write bandwidth in MiByte/s
239 system.physmem.avgRdBWSys 19.40 # Average system read bandwidth in MiByte/s
240 system.physmem.avgWrBWSys 1.28 # Average system write bandwidth in MiByte/s
241 system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
242 system.physmem.busUtil 0.16 # Data bus utilization in percentage
243 system.physmem.busUtilRead 0.15 # Data bus utilization in percentage for reads
244 system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
245 system.physmem.avgRdQLen 1.10 # Average read queue length when enqueuing
246 system.physmem.avgWrQLen 14.66 # Average write queue length when enqueuing
247 system.physmem.readRowHits 14950 # Number of row buffer hits during reads
248 system.physmem.writeRowHits 375 # Number of row buffer hits during writes
249 system.physmem.readRowHitRate 86.98 # Row buffer hit rate for reads
250 system.physmem.writeRowHitRate 32.72 # Row buffer hit rate for writes
251 system.physmem.avgGap 3096169.77 # Average gap between requests
252 system.physmem.pageHitRate 83.59 # Row buffer hit rate, read and write combined
253 system.physmem.memoryStateTime::IDLE 51355249007 # Time in different power states
254 system.physmem.memoryStateTime::REF 1927120000 # Time in different power states
255 system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
256 system.physmem.memoryStateTime::ACT 4429633993 # Time in different power states
257 system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
258 system.membus.trans_dist::ReadReq 17158 # Transaction distribution
259 system.membus.trans_dist::ReadResp 17158 # Transaction distribution
260 system.membus.trans_dist::Writeback 1150 # Transaction distribution
261 system.membus.trans_dist::UpgradeReq 2 # Transaction distribution
262 system.membus.trans_dist::UpgradeResp 2 # Transaction distribution
263 system.membus.trans_dist::ReadExReq 332 # Transaction distribution
264 system.membus.trans_dist::ReadExResp 332 # Transaction distribution
265 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 36134 # Packet count per connected master and slave (bytes)
266 system.membus.pkt_count::total 36134 # Packet count per connected master and slave (bytes)
267 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1192960 # Cumulative packet size per connected master and slave (bytes)
268 system.membus.pkt_size::total 1192960 # Cumulative packet size per connected master and slave (bytes)
269 system.membus.snoops 0 # Total snoops (count)
270 system.membus.snoop_fanout::samples 18642 # Request fanout histogram
271 system.membus.snoop_fanout::mean 0 # Request fanout histogram
272 system.membus.snoop_fanout::stdev 0 # Request fanout histogram
273 system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
274 system.membus.snoop_fanout::0 18642 100.00% 100.00% # Request fanout histogram
275 system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
276 system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
277 system.membus.snoop_fanout::min_value 0 # Request fanout histogram
278 system.membus.snoop_fanout::max_value 0 # Request fanout histogram
279 system.membus.snoop_fanout::total 18642 # Request fanout histogram
280 system.membus.reqLayer0.occupancy 32019899 # Layer occupancy (ticks)
281 system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
282 system.membus.respLayer1.occupancy 163550691 # Layer occupancy (ticks)
283 system.membus.respLayer1.utilization 0.3 # Layer utilization (%)
284 system.cpu_clk_domain.clock 500 # Clock period in ticks
285 system.cpu.branchPred.lookups 28272297 # Number of BP lookups
286 system.cpu.branchPred.condPredicted 23289786 # Number of conditional branches predicted
287 system.cpu.branchPred.condIncorrect 837936 # Number of conditional branches incorrect
288 system.cpu.branchPred.BTBLookups 11858499 # Number of BTB lookups
289 system.cpu.branchPred.BTBHits 11790100 # Number of BTB hits
290 system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
291 system.cpu.branchPred.BTBHitPct 99.423207 # BTB Hit Percentage
292 system.cpu.branchPred.usedRAS 75765 # Number of times the RAS was used to get a target.
293 system.cpu.branchPred.RASInCorrect 88 # Number of incorrect RAS predictions.
294 system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
295 system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
296 system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
297 system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
298 system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
299 system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
300 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
301 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
302 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
303 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
304 system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
305 system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
306 system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
307 system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
308 system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
309 system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
310 system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
311 system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
312 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
313 system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
314 system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
315 system.cpu.dtb.inst_hits 0 # ITB inst hits
316 system.cpu.dtb.inst_misses 0 # ITB inst misses
317 system.cpu.dtb.read_hits 0 # DTB read hits
318 system.cpu.dtb.read_misses 0 # DTB read misses
319 system.cpu.dtb.write_hits 0 # DTB write hits
320 system.cpu.dtb.write_misses 0 # DTB write misses
321 system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
322 system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
323 system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
324 system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
325 system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
326 system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
327 system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
328 system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
329 system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
330 system.cpu.dtb.read_accesses 0 # DTB read accesses
331 system.cpu.dtb.write_accesses 0 # DTB write accesses
332 system.cpu.dtb.inst_accesses 0 # ITB inst accesses
333 system.cpu.dtb.hits 0 # DTB hits
334 system.cpu.dtb.misses 0 # DTB misses
335 system.cpu.dtb.accesses 0 # DTB accesses
336 system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
337 system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
338 system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
339 system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
340 system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
341 system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
342 system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
343 system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
344 system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
345 system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
346 system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
347 system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
348 system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
349 system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
350 system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
351 system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
352 system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
353 system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
354 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
355 system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
356 system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
357 system.cpu.itb.inst_hits 0 # ITB inst hits
358 system.cpu.itb.inst_misses 0 # ITB inst misses
359 system.cpu.itb.read_hits 0 # DTB read hits
360 system.cpu.itb.read_misses 0 # DTB read misses
361 system.cpu.itb.write_hits 0 # DTB write hits
362 system.cpu.itb.write_misses 0 # DTB write misses
363 system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
364 system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
365 system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
366 system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
367 system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
368 system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
369 system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
370 system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
371 system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
372 system.cpu.itb.read_accesses 0 # DTB read accesses
373 system.cpu.itb.write_accesses 0 # DTB write accesses
374 system.cpu.itb.inst_accesses 0 # ITB inst accesses
375 system.cpu.itb.hits 0 # DTB hits
376 system.cpu.itb.misses 0 # DTB misses
377 system.cpu.itb.accesses 0 # DTB accesses
378 system.cpu.workload.num_syscalls 442 # Number of system calls
379 system.cpu.numCycles 115425565 # number of cpu cycles simulated
380 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
381 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
382 system.cpu.fetch.icacheStallCycles 745807 # Number of cycles fetch is stalled on an Icache miss
383 system.cpu.fetch.Insts 135034231 # Number of instructions fetch has processed
384 system.cpu.fetch.Branches 28272297 # Number of branches that fetch encountered
385 system.cpu.fetch.predictedBranches 11865865 # Number of branches that fetch has predicted taken
386 system.cpu.fetch.Cycles 113822766 # Number of cycles fetch has run and was not squashing or blocked
387 system.cpu.fetch.SquashCycles 1679444 # Number of cycles fetch has spent squashing
388 system.cpu.fetch.MiscStallCycles 53 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
389 system.cpu.fetch.IcacheWaitRetryStallCycles 259 # Number of stall cycles due to full MSHR
390 system.cpu.fetch.CacheLines 32316581 # Number of cache lines fetched
391 system.cpu.fetch.IcacheSquashes 456 # Number of outstanding Icache misses that were squashed
392 system.cpu.fetch.rateDist::samples 115408607 # Number of instructions fetched each cycle (Total)
393 system.cpu.fetch.rateDist::mean 1.175345 # Number of instructions fetched each cycle (Total)
394 system.cpu.fetch.rateDist::stdev 1.320714 # Number of instructions fetched each cycle (Total)
395 system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
396 system.cpu.fetch.rateDist::0 57851940 50.13% 50.13% # Number of instructions fetched each cycle (Total)
397 system.cpu.fetch.rateDist::1 13925142 12.07% 62.19% # Number of instructions fetched each cycle (Total)
398 system.cpu.fetch.rateDist::2 9174755 7.95% 70.14% # Number of instructions fetched each cycle (Total)
399 system.cpu.fetch.rateDist::3 34456770 29.86% 100.00% # Number of instructions fetched each cycle (Total)
400 system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
401 system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
402 system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
403 system.cpu.fetch.rateDist::total 115408607 # Number of instructions fetched each cycle (Total)
404 system.cpu.fetch.branchRate 0.244940 # Number of branch fetches per cycle
405 system.cpu.fetch.rate 1.169881 # Number of inst fetches per cycle
406 system.cpu.decode.IdleCycles 8865132 # Number of cycles decode is idle
407 system.cpu.decode.BlockedCycles 63135589 # Number of cycles decode is blocked
408 system.cpu.decode.RunCycles 33034927 # Number of cycles decode is running
409 system.cpu.decode.UnblockCycles 9545475 # Number of cycles decode is unblocking
410 system.cpu.decode.SquashCycles 827484 # Number of cycles decode is squashing
411 system.cpu.decode.BranchResolved 4101291 # Number of times decode resolved a branch
412 system.cpu.decode.BranchMispred 12346 # Number of times decode detected a branch misprediction
413 system.cpu.decode.DecodedInsts 114392929 # Number of instructions handled by decode
414 system.cpu.decode.SquashedInsts 1987160 # Number of squashed instructions handled by decode
415 system.cpu.rename.SquashCycles 827484 # Number of cycles rename is squashing
416 system.cpu.rename.IdleCycles 15218972 # Number of cycles rename is idle
417 system.cpu.rename.BlockCycles 49233807 # Number of cycles rename is blocking
418 system.cpu.rename.serializeStallCycles 108012 # count of cycles rename stalled for serializing inst
419 system.cpu.rename.RunCycles 35472939 # Number of cycles rename is running
420 system.cpu.rename.UnblockCycles 14547393 # Number of cycles rename is unblocking
421 system.cpu.rename.RenamedInsts 110855235 # Number of instructions processed by rename
422 system.cpu.rename.SquashedInsts 1413432 # Number of squashed instructions processed by rename
423 system.cpu.rename.ROBFullEvents 11041669 # Number of times rename has blocked due to ROB full
424 system.cpu.rename.IQFullEvents 1056479 # Number of times rename has blocked due to IQ full
425 system.cpu.rename.LQFullEvents 1457795 # Number of times rename has blocked due to LQ full
426 system.cpu.rename.SQFullEvents 455993 # Number of times rename has blocked due to SQ full
427 system.cpu.rename.RenamedOperands 129914313 # Number of destination operands rename has renamed
428 system.cpu.rename.RenameLookups 483072528 # Number of register rename lookups that rename has made
429 system.cpu.rename.int_rename_lookups 119436601 # Number of integer rename lookups
430 system.cpu.rename.fp_rename_lookups 420 # Number of floating rename lookups
431 system.cpu.rename.CommittedMaps 107312919 # Number of HB maps that are committed
432 system.cpu.rename.UndoneMaps 22601394 # Number of HB maps that are undone due to squashing
433 system.cpu.rename.serializingInsts 4364 # count of serializing insts renamed
434 system.cpu.rename.tempSerializingInsts 4358 # count of temporary serializing insts renamed
435 system.cpu.rename.skidInsts 21215231 # count of insts added to the skid buffer
436 system.cpu.memDep0.insertedLoads 26814209 # Number of loads inserted to the mem dependence unit.
437 system.cpu.memDep0.insertedStores 5348913 # Number of stores inserted to the mem dependence unit.
438 system.cpu.memDep0.conflictingLoads 553765 # Number of conflicting loads.
439 system.cpu.memDep0.conflictingStores 291016 # Number of conflicting stores.
440 system.cpu.iq.iqInstsAdded 109685133 # Number of instructions added to the IQ (excludes non-spec)
441 system.cpu.iq.iqNonSpecInstsAdded 8247 # Number of non-speculative instructions added to the IQ
442 system.cpu.iq.iqInstsIssued 101428277 # Number of instructions issued
443 system.cpu.iq.iqSquashedInstsIssued 1059458 # Number of squashed instructions issued
444 system.cpu.iq.iqSquashedInstsExamined 18454529 # Number of squashed instructions iterated over during squash; mainly for profiling
445 system.cpu.iq.iqSquashedOperandsExamined 41507183 # Number of squashed operands that are examined and possibly removed from graph
446 system.cpu.iq.iqSquashedNonSpecRemoved 29 # Number of squashed non-spec instructions that were removed
447 system.cpu.iq.issued_per_cycle::samples 115408607 # Number of insts issued each cycle
448 system.cpu.iq.issued_per_cycle::mean 0.878862 # Number of insts issued each cycle
449 system.cpu.iq.issued_per_cycle::stdev 1.000028 # Number of insts issued each cycle
450 system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
451 system.cpu.iq.issued_per_cycle::0 54542432 47.26% 47.26% # Number of insts issued each cycle
452 system.cpu.iq.issued_per_cycle::1 30109521 26.09% 73.35% # Number of insts issued each cycle
453 system.cpu.iq.issued_per_cycle::2 22147517 19.19% 92.54% # Number of insts issued each cycle
454 system.cpu.iq.issued_per_cycle::3 7413143 6.42% 98.96% # Number of insts issued each cycle
455 system.cpu.iq.issued_per_cycle::4 1195677 1.04% 100.00% # Number of insts issued each cycle
456 system.cpu.iq.issued_per_cycle::5 317 0.00% 100.00% # Number of insts issued each cycle
457 system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
458 system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
459 system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
460 system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
461 system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
462 system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
463 system.cpu.iq.issued_per_cycle::total 115408607 # Number of insts issued each cycle
464 system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
465 system.cpu.iq.fu_full::IntAlu 9750275 48.86% 48.86% # attempts to use FU when none available
466 system.cpu.iq.fu_full::IntMult 50 0.00% 48.86% # attempts to use FU when none available
467 system.cpu.iq.fu_full::IntDiv 0 0.00% 48.86% # attempts to use FU when none available
468 system.cpu.iq.fu_full::FloatAdd 0 0.00% 48.86% # attempts to use FU when none available
469 system.cpu.iq.fu_full::FloatCmp 0 0.00% 48.86% # attempts to use FU when none available
470 system.cpu.iq.fu_full::FloatCvt 0 0.00% 48.86% # attempts to use FU when none available
471 system.cpu.iq.fu_full::FloatMult 0 0.00% 48.86% # attempts to use FU when none available
472 system.cpu.iq.fu_full::FloatDiv 0 0.00% 48.86% # attempts to use FU when none available
473 system.cpu.iq.fu_full::FloatSqrt 0 0.00% 48.86% # attempts to use FU when none available
474 system.cpu.iq.fu_full::SimdAdd 0 0.00% 48.86% # attempts to use FU when none available
475 system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 48.86% # attempts to use FU when none available
476 system.cpu.iq.fu_full::SimdAlu 0 0.00% 48.86% # attempts to use FU when none available
477 system.cpu.iq.fu_full::SimdCmp 0 0.00% 48.86% # attempts to use FU when none available
478 system.cpu.iq.fu_full::SimdCvt 0 0.00% 48.86% # attempts to use FU when none available
479 system.cpu.iq.fu_full::SimdMisc 0 0.00% 48.86% # attempts to use FU when none available
480 system.cpu.iq.fu_full::SimdMult 0 0.00% 48.86% # attempts to use FU when none available
481 system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 48.86% # attempts to use FU when none available
482 system.cpu.iq.fu_full::SimdShift 0 0.00% 48.86% # attempts to use FU when none available
483 system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 48.86% # attempts to use FU when none available
484 system.cpu.iq.fu_full::SimdSqrt 0 0.00% 48.86% # attempts to use FU when none available
485 system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 48.86% # attempts to use FU when none available
486 system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 48.86% # attempts to use FU when none available
487 system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 48.86% # attempts to use FU when none available
488 system.cpu.iq.fu_full::SimdFloatCvt 13 0.00% 48.86% # attempts to use FU when none available
489 system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 48.86% # attempts to use FU when none available
490 system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 48.86% # attempts to use FU when none available
491 system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 48.86% # attempts to use FU when none available
492 system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 48.86% # attempts to use FU when none available
493 system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 48.86% # attempts to use FU when none available
494 system.cpu.iq.fu_full::MemRead 9493870 47.57% 96.43% # attempts to use FU when none available
495 system.cpu.iq.fu_full::MemWrite 712253 3.57% 100.00% # attempts to use FU when none available
496 system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
497 system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
498 system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
499 system.cpu.iq.FU_type_0::IntAlu 71987588 70.97% 70.97% # Type of FU issued
500 system.cpu.iq.FU_type_0::IntMult 10708 0.01% 70.98% # Type of FU issued
501 system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.98% # Type of FU issued
502 system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.98% # Type of FU issued
503 system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.98% # Type of FU issued
504 system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.98% # Type of FU issued
505 system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.98% # Type of FU issued
506 system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.98% # Type of FU issued
507 system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.98% # Type of FU issued
508 system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.98% # Type of FU issued
509 system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.98% # Type of FU issued
510 system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.98% # Type of FU issued
511 system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.98% # Type of FU issued
512 system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.98% # Type of FU issued
513 system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.98% # Type of FU issued
514 system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.98% # Type of FU issued
515 system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.98% # Type of FU issued
516 system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.98% # Type of FU issued
517 system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.98% # Type of FU issued
518 system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.98% # Type of FU issued
519 system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.98% # Type of FU issued
520 system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.98% # Type of FU issued
521 system.cpu.iq.FU_type_0::SimdFloatCmp 2 0.00% 70.98% # Type of FU issued
522 system.cpu.iq.FU_type_0::SimdFloatCvt 56 0.00% 70.98% # Type of FU issued
523 system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.98% # Type of FU issued
524 system.cpu.iq.FU_type_0::SimdFloatMisc 125 0.00% 70.98% # Type of FU issued
525 system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.98% # Type of FU issued
526 system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 70.98% # Type of FU issued
527 system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.98% # Type of FU issued
528 system.cpu.iq.FU_type_0::MemRead 24380841 24.04% 95.02% # Type of FU issued
529 system.cpu.iq.FU_type_0::MemWrite 5048955 4.98% 100.00% # Type of FU issued
530 system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
531 system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
532 system.cpu.iq.FU_type_0::total 101428277 # Type of FU issued
533 system.cpu.iq.rate 0.878733 # Inst issue rate
534 system.cpu.iq.fu_busy_cnt 19956461 # FU busy when requested
535 system.cpu.iq.fu_busy_rate 0.196754 # FU busy rate (busy events/executed inst)
536 system.cpu.iq.int_inst_queue_reads 339280619 # Number of integer instruction queue reads
537 system.cpu.iq.int_inst_queue_writes 128148692 # Number of integer instruction queue writes
538 system.cpu.iq.int_inst_queue_wakeup_accesses 99657487 # Number of integer instruction queue wakeup accesses
539 system.cpu.iq.fp_inst_queue_reads 461 # Number of floating instruction queue reads
540 system.cpu.iq.fp_inst_queue_writes 607 # Number of floating instruction queue writes
541 system.cpu.iq.fp_inst_queue_wakeup_accesses 120 # Number of floating instruction queue wakeup accesses
542 system.cpu.iq.int_alu_accesses 121384498 # Number of integer alu accesses
543 system.cpu.iq.fp_alu_accesses 240 # Number of floating point alu accesses
544 system.cpu.iew.lsq.thread0.forwLoads 285190 # Number of loads that had data forwarded from stores
545 system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
546 system.cpu.iew.lsq.thread0.squashedLoads 4338298 # Number of loads squashed
547 system.cpu.iew.lsq.thread0.ignoredResponses 1479 # Number of memory responses ignored because the instruction is squashed
548 system.cpu.iew.lsq.thread0.memOrderViolation 1420 # Number of memory ordering violations
549 system.cpu.iew.lsq.thread0.squashedStores 604069 # Number of stores squashed
550 system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
551 system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
552 system.cpu.iew.lsq.thread0.rescheduledLoads 7565 # Number of loads that were rescheduled
553 system.cpu.iew.lsq.thread0.cacheBlocked 130354 # Number of times an access to memory failed due to the cache being blocked
554 system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
555 system.cpu.iew.iewSquashCycles 827484 # Number of cycles IEW is squashing
556 system.cpu.iew.iewBlockCycles 8008710 # Number of cycles IEW is blocking
557 system.cpu.iew.iewUnblockCycles 730406 # Number of cycles IEW is unblocking
558 system.cpu.iew.iewDispatchedInsts 109706046 # Number of instructions dispatched to IQ
559 system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
560 system.cpu.iew.iewDispLoadInsts 26814209 # Number of dispatched load instructions
561 system.cpu.iew.iewDispStoreInsts 5348913 # Number of dispatched store instructions
562 system.cpu.iew.iewDispNonSpecInsts 4359 # Number of dispatched non-speculative instructions
563 system.cpu.iew.iewIQFullEvents 187279 # Number of times the IQ has become full, causing a stall
564 system.cpu.iew.iewLSQFullEvents 360662 # Number of times the LSQ has become full, causing a stall
565 system.cpu.iew.memOrderViolationEvents 1420 # Number of memory order violations
566 system.cpu.iew.predictedTakenIncorrect 436360 # Number of branches that were predicted taken incorrectly
567 system.cpu.iew.predictedNotTakenIncorrect 412881 # Number of branches that were predicted not taken incorrectly
568 system.cpu.iew.branchMispredicts 849241 # Number of branch mispredicts detected at execute
569 system.cpu.iew.iewExecutedInsts 100145631 # Number of executed instructions
570 system.cpu.iew.iewExecLoadInsts 23824107 # Number of load instructions executed
571 system.cpu.iew.iewExecSquashedInsts 1282646 # Number of squashed instructions skipped in execute
572 system.cpu.iew.exec_swp 0 # number of swp insts executed
573 system.cpu.iew.exec_nop 12666 # number of nop insts executed
574 system.cpu.iew.exec_refs 28742996 # number of memory reference insts executed
575 system.cpu.iew.exec_branches 20629033 # Number of branches executed
576 system.cpu.iew.exec_stores 4918889 # Number of stores executed
577 system.cpu.iew.exec_rate 0.867621 # Inst execution rate
578 system.cpu.iew.wb_sent 99755826 # cumulative count of insts sent to commit
579 system.cpu.iew.wb_count 99657607 # cumulative count of insts written-back
580 system.cpu.iew.wb_producers 59710820 # num instructions producing a value
581 system.cpu.iew.wb_consumers 95563157 # num instructions consuming a value
582 system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
583 system.cpu.iew.wb_rate 0.863393 # insts written-back per cycle
584 system.cpu.iew.wb_fanout 0.624831 # average fanout of values written-back
585 system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
586 system.cpu.commit.commitSquashedInsts 17390640 # The number of squashed insts skipped by commit
587 system.cpu.commit.commitNonSpecStalls 8218 # The number of times commit has been forced to stall to communicate backwards
588 system.cpu.commit.branchMispredicts 825698 # The number of times a branch was mispredicted
589 system.cpu.commit.committed_per_cycle::samples 112714742 # Number of insts commited each cycle
590 system.cpu.commit.committed_per_cycle::mean 0.807824 # Number of insts commited each cycle
591 system.cpu.commit.committed_per_cycle::stdev 1.745908 # Number of insts commited each cycle
592 system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
593 system.cpu.commit.committed_per_cycle::0 76462569 67.84% 67.84% # Number of insts commited each cycle
594 system.cpu.commit.committed_per_cycle::1 18443635 16.36% 84.20% # Number of insts commited each cycle
595 system.cpu.commit.committed_per_cycle::2 7118441 6.32% 90.52% # Number of insts commited each cycle
596 system.cpu.commit.committed_per_cycle::3 3374531 2.99% 93.51% # Number of insts commited each cycle
597 system.cpu.commit.committed_per_cycle::4 1758227 1.56% 95.07% # Number of insts commited each cycle
598 system.cpu.commit.committed_per_cycle::5 536893 0.48% 95.55% # Number of insts commited each cycle
599 system.cpu.commit.committed_per_cycle::6 726177 0.64% 96.19% # Number of insts commited each cycle
600 system.cpu.commit.committed_per_cycle::7 179059 0.16% 96.35% # Number of insts commited each cycle
601 system.cpu.commit.committed_per_cycle::8 4115210 3.65% 100.00% # Number of insts commited each cycle
602 system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
603 system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
604 system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
605 system.cpu.commit.committed_per_cycle::total 112714742 # Number of insts commited each cycle
606 system.cpu.commit.committedInsts 90602407 # Number of instructions committed
607 system.cpu.commit.committedOps 91053638 # Number of ops (including micro ops) committed
608 system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
609 system.cpu.commit.refs 27220755 # Number of memory references committed
610 system.cpu.commit.loads 22475911 # Number of loads committed
611 system.cpu.commit.membars 3888 # Number of memory barriers committed
612 system.cpu.commit.branches 18732304 # Number of branches committed
613 system.cpu.commit.fp_insts 48 # Number of committed floating point instructions.
614 system.cpu.commit.int_insts 72326352 # Number of committed integer instructions.
615 system.cpu.commit.function_calls 56148 # Number of function calls committed.
616 system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
617 system.cpu.commit.op_class_0::IntAlu 63822386 70.09% 70.09% # Class of committed instruction
618 system.cpu.commit.op_class_0::IntMult 10474 0.01% 70.10% # Class of committed instruction
619 system.cpu.commit.op_class_0::IntDiv 0 0.00% 70.10% # Class of committed instruction
620 system.cpu.commit.op_class_0::FloatAdd 0 0.00% 70.10% # Class of committed instruction
621 system.cpu.commit.op_class_0::FloatCmp 0 0.00% 70.10% # Class of committed instruction
622 system.cpu.commit.op_class_0::FloatCvt 0 0.00% 70.10% # Class of committed instruction
623 system.cpu.commit.op_class_0::FloatMult 0 0.00% 70.10% # Class of committed instruction
624 system.cpu.commit.op_class_0::FloatDiv 0 0.00% 70.10% # Class of committed instruction
625 system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 70.10% # Class of committed instruction
626 system.cpu.commit.op_class_0::SimdAdd 0 0.00% 70.10% # Class of committed instruction
627 system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 70.10% # Class of committed instruction
628 system.cpu.commit.op_class_0::SimdAlu 0 0.00% 70.10% # Class of committed instruction
629 system.cpu.commit.op_class_0::SimdCmp 0 0.00% 70.10% # Class of committed instruction
630 system.cpu.commit.op_class_0::SimdCvt 0 0.00% 70.10% # Class of committed instruction
631 system.cpu.commit.op_class_0::SimdMisc 0 0.00% 70.10% # Class of committed instruction
632 system.cpu.commit.op_class_0::SimdMult 0 0.00% 70.10% # Class of committed instruction
633 system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 70.10% # Class of committed instruction
634 system.cpu.commit.op_class_0::SimdShift 0 0.00% 70.10% # Class of committed instruction
635 system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 70.10% # Class of committed instruction
636 system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 70.10% # Class of committed instruction
637 system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 70.10% # Class of committed instruction
638 system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 70.10% # Class of committed instruction
639 system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 70.10% # Class of committed instruction
640 system.cpu.commit.op_class_0::SimdFloatCvt 6 0.00% 70.10% # Class of committed instruction
641 system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 70.10% # Class of committed instruction
642 system.cpu.commit.op_class_0::SimdFloatMisc 15 0.00% 70.10% # Class of committed instruction
643 system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 70.10% # Class of committed instruction
644 system.cpu.commit.op_class_0::SimdFloatMultAcc 2 0.00% 70.10% # Class of committed instruction
645 system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.10% # Class of committed instruction
646 system.cpu.commit.op_class_0::MemRead 22475911 24.68% 94.79% # Class of committed instruction
647 system.cpu.commit.op_class_0::MemWrite 4744844 5.21% 100.00% # Class of committed instruction
648 system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
649 system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
650 system.cpu.commit.op_class_0::total 91053638 # Class of committed instruction
651 system.cpu.commit.bw_lim_events 4115210 # number cycles where commit BW limit reached
652 system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
653 system.cpu.rob.rob_reads 217038076 # The number of ROB reads
654 system.cpu.rob.rob_writes 219583064 # The number of ROB writes
655 system.cpu.timesIdled 319 # Number of times that the entire CPU went into an idle state and unscheduled itself
656 system.cpu.idleCycles 16958 # Total number of cycles that the CPU has spent unscheduled due to idling
657 system.cpu.committedInsts 90589798 # Number of Instructions Simulated
658 system.cpu.committedOps 91041029 # Number of Ops (including micro ops) Simulated
659 system.cpu.cpi 1.274156 # CPI: Cycles Per Instruction
660 system.cpu.cpi_total 1.274156 # CPI: Total CPI of All Threads
661 system.cpu.ipc 0.784833 # IPC: Instructions Per Cycle
662 system.cpu.ipc_total 0.784833 # IPC: Total IPC of All Threads
663 system.cpu.int_regfile_reads 108123919 # number of integer regfile reads
664 system.cpu.int_regfile_writes 58738896 # number of integer regfile writes
665 system.cpu.fp_regfile_reads 58 # number of floating regfile reads
666 system.cpu.fp_regfile_writes 100 # number of floating regfile writes
667 system.cpu.cc_regfile_reads 369252810 # number of cc regfile reads
668 system.cpu.cc_regfile_writes 58698459 # number of cc regfile writes
669 system.cpu.misc_regfile_reads 28460470 # number of misc regfile reads
670 system.cpu.misc_regfile_writes 7784 # number of misc regfile writes
671 system.cpu.toL2Bus.trans_dist::ReadReq 5262392 # Transaction distribution
672 system.cpu.toL2Bus.trans_dist::ReadResp 5262392 # Transaction distribution
673 system.cpu.toL2Bus.trans_dist::Writeback 5407164 # Transaction distribution
674 system.cpu.toL2Bus.trans_dist::HardPFReq 28368 # Transaction distribution
675 system.cpu.toL2Bus.trans_dist::HardPFResp 2 # Transaction distribution
676 system.cpu.toL2Bus.trans_dist::ReadExReq 225287 # Transaction distribution
677 system.cpu.toL2Bus.trans_dist::ReadExResp 225287 # Transaction distribution
678 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1832 # Packet count per connected master and slave (bytes)
679 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 16380692 # Packet count per connected master and slave (bytes)
680 system.cpu.toL2Bus.pkt_count::total 16382524 # Packet count per connected master and slave (bytes)
681 system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 58624 # Cumulative packet size per connected master and slave (bytes)
682 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 697211456 # Cumulative packet size per connected master and slave (bytes)
683 system.cpu.toL2Bus.pkt_size::total 697270080 # Cumulative packet size per connected master and slave (bytes)
684 system.cpu.toL2Bus.snoops 28370 # Total snoops (count)
685 system.cpu.toL2Bus.snoop_fanout::samples 10923218 # Request fanout histogram
686 system.cpu.toL2Bus.snoop_fanout::mean 5.002597 # Request fanout histogram
687 system.cpu.toL2Bus.snoop_fanout::stdev 0.050895 # Request fanout histogram
688 system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
689 system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
690 system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
691 system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
692 system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
693 system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
694 system.cpu.toL2Bus.snoop_fanout::5 10894850 99.74% 99.74% # Request fanout histogram
695 system.cpu.toL2Bus.snoop_fanout::6 28368 0.26% 100.00% # Request fanout histogram
696 system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
697 system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
698 system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
699 system.cpu.toL2Bus.snoop_fanout::total 10923218 # Request fanout histogram
700 system.cpu.toL2Bus.reqLayer0.occupancy 10854591744 # Layer occupancy (ticks)
701 system.cpu.toL2Bus.reqLayer0.utilization 18.8 # Layer utilization (%)
702 system.cpu.toL2Bus.snoopLayer0.occupancy 3000 # Layer occupancy (ticks)
703 system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
704 system.cpu.toL2Bus.respLayer0.occupancy 1387749 # Layer occupancy (ticks)
705 system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
706 system.cpu.toL2Bus.respLayer1.occupancy 8230203749 # Layer occupancy (ticks)
707 system.cpu.toL2Bus.respLayer1.utilization 14.3 # Layer utilization (%)
708 system.cpu.icache.tags.replacements 456 # number of replacements
709 system.cpu.icache.tags.tagsinuse 432.039034 # Cycle average of tags in use
710 system.cpu.icache.tags.total_refs 32315555 # Total number of references to valid blocks.
711 system.cpu.icache.tags.sampled_refs 916 # Sample count of references to valid blocks.
712 system.cpu.icache.tags.avg_refs 35278.990175 # Average number of references to valid blocks.
713 system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
714 system.cpu.icache.tags.occ_blocks::cpu.inst 432.039034 # Average occupied blocks per requestor
715 system.cpu.icache.tags.occ_percent::cpu.inst 0.843826 # Average percentage of cache occupancy
716 system.cpu.icache.tags.occ_percent::total 0.843826 # Average percentage of cache occupancy
717 system.cpu.icache.tags.occ_task_id_blocks::1024 460 # Occupied blocks per task id
718 system.cpu.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id
719 system.cpu.icache.tags.age_task_id_blocks_1024::2 52 # Occupied blocks per task id
720 system.cpu.icache.tags.age_task_id_blocks_1024::3 19 # Occupied blocks per task id
721 system.cpu.icache.tags.age_task_id_blocks_1024::4 335 # Occupied blocks per task id
722 system.cpu.icache.tags.occ_task_id_percent::1024 0.898438 # Percentage of cache occupancy per task id
723 system.cpu.icache.tags.tag_accesses 64634074 # Number of tag accesses
724 system.cpu.icache.tags.data_accesses 64634074 # Number of data accesses
725 system.cpu.icache.ReadReq_hits::cpu.inst 32315555 # number of ReadReq hits
726 system.cpu.icache.ReadReq_hits::total 32315555 # number of ReadReq hits
727 system.cpu.icache.demand_hits::cpu.inst 32315555 # number of demand (read+write) hits
728 system.cpu.icache.demand_hits::total 32315555 # number of demand (read+write) hits
729 system.cpu.icache.overall_hits::cpu.inst 32315555 # number of overall hits
730 system.cpu.icache.overall_hits::total 32315555 # number of overall hits
731 system.cpu.icache.ReadReq_misses::cpu.inst 1024 # number of ReadReq misses
732 system.cpu.icache.ReadReq_misses::total 1024 # number of ReadReq misses
733 system.cpu.icache.demand_misses::cpu.inst 1024 # number of demand (read+write) misses
734 system.cpu.icache.demand_misses::total 1024 # number of demand (read+write) misses
735 system.cpu.icache.overall_misses::cpu.inst 1024 # number of overall misses
736 system.cpu.icache.overall_misses::total 1024 # number of overall misses
737 system.cpu.icache.ReadReq_miss_latency::cpu.inst 21430236 # number of ReadReq miss cycles
738 system.cpu.icache.ReadReq_miss_latency::total 21430236 # number of ReadReq miss cycles
739 system.cpu.icache.demand_miss_latency::cpu.inst 21430236 # number of demand (read+write) miss cycles
740 system.cpu.icache.demand_miss_latency::total 21430236 # number of demand (read+write) miss cycles
741 system.cpu.icache.overall_miss_latency::cpu.inst 21430236 # number of overall miss cycles
742 system.cpu.icache.overall_miss_latency::total 21430236 # number of overall miss cycles
743 system.cpu.icache.ReadReq_accesses::cpu.inst 32316579 # number of ReadReq accesses(hits+misses)
744 system.cpu.icache.ReadReq_accesses::total 32316579 # number of ReadReq accesses(hits+misses)
745 system.cpu.icache.demand_accesses::cpu.inst 32316579 # number of demand (read+write) accesses
746 system.cpu.icache.demand_accesses::total 32316579 # number of demand (read+write) accesses
747 system.cpu.icache.overall_accesses::cpu.inst 32316579 # number of overall (read+write) accesses
748 system.cpu.icache.overall_accesses::total 32316579 # number of overall (read+write) accesses
749 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000032 # miss rate for ReadReq accesses
750 system.cpu.icache.ReadReq_miss_rate::total 0.000032 # miss rate for ReadReq accesses
751 system.cpu.icache.demand_miss_rate::cpu.inst 0.000032 # miss rate for demand accesses
752 system.cpu.icache.demand_miss_rate::total 0.000032 # miss rate for demand accesses
753 system.cpu.icache.overall_miss_rate::cpu.inst 0.000032 # miss rate for overall accesses
754 system.cpu.icache.overall_miss_rate::total 0.000032 # miss rate for overall accesses
755 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20927.964844 # average ReadReq miss latency
756 system.cpu.icache.ReadReq_avg_miss_latency::total 20927.964844 # average ReadReq miss latency
757 system.cpu.icache.demand_avg_miss_latency::cpu.inst 20927.964844 # average overall miss latency
758 system.cpu.icache.demand_avg_miss_latency::total 20927.964844 # average overall miss latency
759 system.cpu.icache.overall_avg_miss_latency::cpu.inst 20927.964844 # average overall miss latency
760 system.cpu.icache.overall_avg_miss_latency::total 20927.964844 # average overall miss latency
761 system.cpu.icache.blocked_cycles::no_mshrs 3188 # number of cycles access was blocked
762 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
763 system.cpu.icache.blocked::no_mshrs 170 # number of cycles access was blocked
764 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
765 system.cpu.icache.avg_blocked_cycles::no_mshrs 18.752941 # average number of cycles each access was blocked
766 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
767 system.cpu.icache.fast_writes 0 # number of fast writes performed
768 system.cpu.icache.cache_copies 0 # number of cache copies performed
769 system.cpu.icache.ReadReq_mshr_hits::cpu.inst 108 # number of ReadReq MSHR hits
770 system.cpu.icache.ReadReq_mshr_hits::total 108 # number of ReadReq MSHR hits
771 system.cpu.icache.demand_mshr_hits::cpu.inst 108 # number of demand (read+write) MSHR hits
772 system.cpu.icache.demand_mshr_hits::total 108 # number of demand (read+write) MSHR hits
773 system.cpu.icache.overall_mshr_hits::cpu.inst 108 # number of overall MSHR hits
774 system.cpu.icache.overall_mshr_hits::total 108 # number of overall MSHR hits
775 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 916 # number of ReadReq MSHR misses
776 system.cpu.icache.ReadReq_mshr_misses::total 916 # number of ReadReq MSHR misses
777 system.cpu.icache.demand_mshr_misses::cpu.inst 916 # number of demand (read+write) MSHR misses
778 system.cpu.icache.demand_mshr_misses::total 916 # number of demand (read+write) MSHR misses
779 system.cpu.icache.overall_mshr_misses::cpu.inst 916 # number of overall MSHR misses
780 system.cpu.icache.overall_mshr_misses::total 916 # number of overall MSHR misses
781 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17850739 # number of ReadReq MSHR miss cycles
782 system.cpu.icache.ReadReq_mshr_miss_latency::total 17850739 # number of ReadReq MSHR miss cycles
783 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17850739 # number of demand (read+write) MSHR miss cycles
784 system.cpu.icache.demand_mshr_miss_latency::total 17850739 # number of demand (read+write) MSHR miss cycles
785 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17850739 # number of overall MSHR miss cycles
786 system.cpu.icache.overall_mshr_miss_latency::total 17850739 # number of overall MSHR miss cycles
787 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for ReadReq accesses
788 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000028 # mshr miss rate for ReadReq accesses
789 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for demand accesses
790 system.cpu.icache.demand_mshr_miss_rate::total 0.000028 # mshr miss rate for demand accesses
791 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for overall accesses
792 system.cpu.icache.overall_mshr_miss_rate::total 0.000028 # mshr miss rate for overall accesses
793 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19487.706332 # average ReadReq mshr miss latency
794 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19487.706332 # average ReadReq mshr miss latency
795 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19487.706332 # average overall mshr miss latency
796 system.cpu.icache.demand_avg_mshr_miss_latency::total 19487.706332 # average overall mshr miss latency
797 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19487.706332 # average overall mshr miss latency
798 system.cpu.icache.overall_avg_mshr_miss_latency::total 19487.706332 # average overall mshr miss latency
799 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
800 system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_identified 8891809 # number of hwpf identified
801 system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 13933 # number of hwpf that were already in mshr
802 system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 7995771 # number of hwpf that were already in the cache
803 system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 738007 # number of hwpf that were already in the prefetch queue
804 system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
805 system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 118754 # number of hwpf removed because MSHR allocated
806 system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_issued 25344 # number of hwpf issued
807 system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_span_page 15103327 # number of hwpf spanning a virtual page
808 system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
809 system.cpu.l2cache.tags.replacements 1672 # number of replacements
810 system.cpu.l2cache.tags.tagsinuse 12558.688532 # Cycle average of tags in use
811 system.cpu.l2cache.tags.total_refs 10641390 # Total number of references to valid blocks.
812 system.cpu.l2cache.tags.sampled_refs 17530 # Sample count of references to valid blocks.
813 system.cpu.l2cache.tags.avg_refs 607.038791 # Average number of references to valid blocks.
814 system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
815 system.cpu.l2cache.tags.occ_blocks::writebacks 10807.797190 # Average occupied blocks per requestor
816 system.cpu.l2cache.tags.occ_blocks::cpu.inst 104.008842 # Average occupied blocks per requestor
817 system.cpu.l2cache.tags.occ_blocks::cpu.data 299.224972 # Average occupied blocks per requestor
818 system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 1347.657528 # Average occupied blocks per requestor
819 system.cpu.l2cache.tags.occ_percent::writebacks 0.659656 # Average percentage of cache occupancy
820 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.006348 # Average percentage of cache occupancy
821 system.cpu.l2cache.tags.occ_percent::cpu.data 0.018263 # Average percentage of cache occupancy
822 system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.082254 # Average percentage of cache occupancy
823 system.cpu.l2cache.tags.occ_percent::total 0.766522 # Average percentage of cache occupancy
824 system.cpu.l2cache.tags.occ_task_id_blocks::1022 1557 # Occupied blocks per task id
825 system.cpu.l2cache.tags.occ_task_id_blocks::1024 14301 # Occupied blocks per task id
826 system.cpu.l2cache.tags.age_task_id_blocks_1022::0 48 # Occupied blocks per task id
827 system.cpu.l2cache.tags.age_task_id_blocks_1022::1 11 # Occupied blocks per task id
828 system.cpu.l2cache.tags.age_task_id_blocks_1022::2 89 # Occupied blocks per task id
829 system.cpu.l2cache.tags.age_task_id_blocks_1022::3 39 # Occupied blocks per task id
830 system.cpu.l2cache.tags.age_task_id_blocks_1022::4 1370 # Occupied blocks per task id
831 system.cpu.l2cache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id
832 system.cpu.l2cache.tags.age_task_id_blocks_1024::1 57 # Occupied blocks per task id
833 system.cpu.l2cache.tags.age_task_id_blocks_1024::2 989 # Occupied blocks per task id
834 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1037 # Occupied blocks per task id
835 system.cpu.l2cache.tags.age_task_id_blocks_1024::4 12200 # Occupied blocks per task id
836 system.cpu.l2cache.tags.occ_task_id_percent::1022 0.095032 # Percentage of cache occupancy per task id
837 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.872864 # Percentage of cache occupancy per task id
838 system.cpu.l2cache.tags.tag_accesses 174560305 # Number of tag accesses
839 system.cpu.l2cache.tags.data_accesses 174560305 # Number of data accesses
840 system.cpu.l2cache.ReadReq_hits::cpu.inst 753 # number of ReadReq hits
841 system.cpu.l2cache.ReadReq_hits::cpu.data 5260483 # number of ReadReq hits
842 system.cpu.l2cache.ReadReq_hits::total 5261236 # number of ReadReq hits
843 system.cpu.l2cache.Writeback_hits::writebacks 5407164 # number of Writeback hits
844 system.cpu.l2cache.Writeback_hits::total 5407164 # number of Writeback hits
845 system.cpu.l2cache.ReadExReq_hits::cpu.data 224791 # number of ReadExReq hits
846 system.cpu.l2cache.ReadExReq_hits::total 224791 # number of ReadExReq hits
847 system.cpu.l2cache.demand_hits::cpu.inst 753 # number of demand (read+write) hits
848 system.cpu.l2cache.demand_hits::cpu.data 5485274 # number of demand (read+write) hits
849 system.cpu.l2cache.demand_hits::total 5486027 # number of demand (read+write) hits
850 system.cpu.l2cache.overall_hits::cpu.inst 753 # number of overall hits
851 system.cpu.l2cache.overall_hits::cpu.data 5485274 # number of overall hits
852 system.cpu.l2cache.overall_hits::total 5486027 # number of overall hits
853 system.cpu.l2cache.ReadReq_misses::cpu.inst 163 # number of ReadReq misses
854 system.cpu.l2cache.ReadReq_misses::cpu.data 993 # number of ReadReq misses
855 system.cpu.l2cache.ReadReq_misses::total 1156 # number of ReadReq misses
856 system.cpu.l2cache.ReadExReq_misses::cpu.data 496 # number of ReadExReq misses
857 system.cpu.l2cache.ReadExReq_misses::total 496 # number of ReadExReq misses
858 system.cpu.l2cache.demand_misses::cpu.inst 163 # number of demand (read+write) misses
859 system.cpu.l2cache.demand_misses::cpu.data 1489 # number of demand (read+write) misses
860 system.cpu.l2cache.demand_misses::total 1652 # number of demand (read+write) misses
861 system.cpu.l2cache.overall_misses::cpu.inst 163 # number of overall misses
862 system.cpu.l2cache.overall_misses::cpu.data 1489 # number of overall misses
863 system.cpu.l2cache.overall_misses::total 1652 # number of overall misses
864 system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 12439500 # number of ReadReq miss cycles
865 system.cpu.l2cache.ReadReq_miss_latency::cpu.data 59393247 # number of ReadReq miss cycles
866 system.cpu.l2cache.ReadReq_miss_latency::total 71832747 # number of ReadReq miss cycles
867 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 31513998 # number of ReadExReq miss cycles
868 system.cpu.l2cache.ReadExReq_miss_latency::total 31513998 # number of ReadExReq miss cycles
869 system.cpu.l2cache.demand_miss_latency::cpu.inst 12439500 # number of demand (read+write) miss cycles
870 system.cpu.l2cache.demand_miss_latency::cpu.data 90907245 # number of demand (read+write) miss cycles
871 system.cpu.l2cache.demand_miss_latency::total 103346745 # number of demand (read+write) miss cycles
872 system.cpu.l2cache.overall_miss_latency::cpu.inst 12439500 # number of overall miss cycles
873 system.cpu.l2cache.overall_miss_latency::cpu.data 90907245 # number of overall miss cycles
874 system.cpu.l2cache.overall_miss_latency::total 103346745 # number of overall miss cycles
875 system.cpu.l2cache.ReadReq_accesses::cpu.inst 916 # number of ReadReq accesses(hits+misses)
876 system.cpu.l2cache.ReadReq_accesses::cpu.data 5261476 # number of ReadReq accesses(hits+misses)
877 system.cpu.l2cache.ReadReq_accesses::total 5262392 # number of ReadReq accesses(hits+misses)
878 system.cpu.l2cache.Writeback_accesses::writebacks 5407164 # number of Writeback accesses(hits+misses)
879 system.cpu.l2cache.Writeback_accesses::total 5407164 # number of Writeback accesses(hits+misses)
880 system.cpu.l2cache.ReadExReq_accesses::cpu.data 225287 # number of ReadExReq accesses(hits+misses)
881 system.cpu.l2cache.ReadExReq_accesses::total 225287 # number of ReadExReq accesses(hits+misses)
882 system.cpu.l2cache.demand_accesses::cpu.inst 916 # number of demand (read+write) accesses
883 system.cpu.l2cache.demand_accesses::cpu.data 5486763 # number of demand (read+write) accesses
884 system.cpu.l2cache.demand_accesses::total 5487679 # number of demand (read+write) accesses
885 system.cpu.l2cache.overall_accesses::cpu.inst 916 # number of overall (read+write) accesses
886 system.cpu.l2cache.overall_accesses::cpu.data 5486763 # number of overall (read+write) accesses
887 system.cpu.l2cache.overall_accesses::total 5487679 # number of overall (read+write) accesses
888 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.177948 # miss rate for ReadReq accesses
889 system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000189 # miss rate for ReadReq accesses
890 system.cpu.l2cache.ReadReq_miss_rate::total 0.000220 # miss rate for ReadReq accesses
891 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.002202 # miss rate for ReadExReq accesses
892 system.cpu.l2cache.ReadExReq_miss_rate::total 0.002202 # miss rate for ReadExReq accesses
893 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.177948 # miss rate for demand accesses
894 system.cpu.l2cache.demand_miss_rate::cpu.data 0.000271 # miss rate for demand accesses
895 system.cpu.l2cache.demand_miss_rate::total 0.000301 # miss rate for demand accesses
896 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.177948 # miss rate for overall accesses
897 system.cpu.l2cache.overall_miss_rate::cpu.data 0.000271 # miss rate for overall accesses
898 system.cpu.l2cache.overall_miss_rate::total 0.000301 # miss rate for overall accesses
899 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76315.950920 # average ReadReq miss latency
900 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 59811.930514 # average ReadReq miss latency
901 system.cpu.l2cache.ReadReq_avg_miss_latency::total 62139.054498 # average ReadReq miss latency
902 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 63536.286290 # average ReadExReq miss latency
903 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 63536.286290 # average ReadExReq miss latency
904 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76315.950920 # average overall miss latency
905 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 61052.548690 # average overall miss latency
906 system.cpu.l2cache.demand_avg_miss_latency::total 62558.562349 # average overall miss latency
907 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76315.950920 # average overall miss latency
908 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 61052.548690 # average overall miss latency
909 system.cpu.l2cache.overall_avg_miss_latency::total 62558.562349 # average overall miss latency
910 system.cpu.l2cache.blocked_cycles::no_mshrs 820 # number of cycles access was blocked
911 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
912 system.cpu.l2cache.blocked::no_mshrs 50 # number of cycles access was blocked
913 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
914 system.cpu.l2cache.avg_blocked_cycles::no_mshrs 16.400000 # average number of cycles each access was blocked
915 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
916 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
917 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
918 system.cpu.l2cache.writebacks::writebacks 1150 # number of writebacks
919 system.cpu.l2cache.writebacks::total 1150 # number of writebacks
920 system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 24 # number of ReadReq MSHR hits
921 system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 256 # number of ReadReq MSHR hits
922 system.cpu.l2cache.ReadReq_mshr_hits::total 280 # number of ReadReq MSHR hits
923 system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 162 # number of ReadExReq MSHR hits
924 system.cpu.l2cache.ReadExReq_mshr_hits::total 162 # number of ReadExReq MSHR hits
925 system.cpu.l2cache.demand_mshr_hits::cpu.inst 24 # number of demand (read+write) MSHR hits
926 system.cpu.l2cache.demand_mshr_hits::cpu.data 418 # number of demand (read+write) MSHR hits
927 system.cpu.l2cache.demand_mshr_hits::total 442 # number of demand (read+write) MSHR hits
928 system.cpu.l2cache.overall_mshr_hits::cpu.inst 24 # number of overall MSHR hits
929 system.cpu.l2cache.overall_mshr_hits::cpu.data 418 # number of overall MSHR hits
930 system.cpu.l2cache.overall_mshr_hits::total 442 # number of overall MSHR hits
931 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 139 # number of ReadReq MSHR misses
932 system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 737 # number of ReadReq MSHR misses
933 system.cpu.l2cache.ReadReq_mshr_misses::total 876 # number of ReadReq MSHR misses
934 system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 25344 # number of HardPFReq MSHR misses
935 system.cpu.l2cache.HardPFReq_mshr_misses::total 25344 # number of HardPFReq MSHR misses
936 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 334 # number of ReadExReq MSHR misses
937 system.cpu.l2cache.ReadExReq_mshr_misses::total 334 # number of ReadExReq MSHR misses
938 system.cpu.l2cache.demand_mshr_misses::cpu.inst 139 # number of demand (read+write) MSHR misses
939 system.cpu.l2cache.demand_mshr_misses::cpu.data 1071 # number of demand (read+write) MSHR misses
940 system.cpu.l2cache.demand_mshr_misses::total 1210 # number of demand (read+write) MSHR misses
941 system.cpu.l2cache.overall_mshr_misses::cpu.inst 139 # number of overall MSHR misses
942 system.cpu.l2cache.overall_mshr_misses::cpu.data 1071 # number of overall MSHR misses
943 system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 25344 # number of overall MSHR misses
944 system.cpu.l2cache.overall_mshr_misses::total 26554 # number of overall MSHR misses
945 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10286000 # number of ReadReq MSHR miss cycles
946 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 41114499 # number of ReadReq MSHR miss cycles
947 system.cpu.l2cache.ReadReq_mshr_miss_latency::total 51400499 # number of ReadReq MSHR miss cycles
948 system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 910618800 # number of HardPFReq MSHR miss cycles
949 system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 910618800 # number of HardPFReq MSHR miss cycles
950 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 20873252 # number of ReadExReq MSHR miss cycles
951 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 20873252 # number of ReadExReq MSHR miss cycles
952 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10286000 # number of demand (read+write) MSHR miss cycles
953 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 61987751 # number of demand (read+write) MSHR miss cycles
954 system.cpu.l2cache.demand_mshr_miss_latency::total 72273751 # number of demand (read+write) MSHR miss cycles
955 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10286000 # number of overall MSHR miss cycles
956 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 61987751 # number of overall MSHR miss cycles
957 system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 910618800 # number of overall MSHR miss cycles
958 system.cpu.l2cache.overall_mshr_miss_latency::total 982892551 # number of overall MSHR miss cycles
959 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.151747 # mshr miss rate for ReadReq accesses
960 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000140 # mshr miss rate for ReadReq accesses
961 system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000166 # mshr miss rate for ReadReq accesses
962 system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
963 system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
964 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001483 # mshr miss rate for ReadExReq accesses
965 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001483 # mshr miss rate for ReadExReq accesses
966 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.151747 # mshr miss rate for demand accesses
967 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.000195 # mshr miss rate for demand accesses
968 system.cpu.l2cache.demand_mshr_miss_rate::total 0.000220 # mshr miss rate for demand accesses
969 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.151747 # mshr miss rate for overall accesses
970 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.000195 # mshr miss rate for overall accesses
971 system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses
972 system.cpu.l2cache.overall_mshr_miss_rate::total 0.004839 # mshr miss rate for overall accesses
973 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 74000 # average ReadReq mshr miss latency
974 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 55786.294437 # average ReadReq mshr miss latency
975 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58676.368721 # average ReadReq mshr miss latency
976 system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 35930.350379 # average HardPFReq mshr miss latency
977 system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 35930.350379 # average HardPFReq mshr miss latency
978 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62494.766467 # average ReadExReq mshr miss latency
979 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62494.766467 # average ReadExReq mshr miss latency
980 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 74000 # average overall mshr miss latency
981 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57878.385621 # average overall mshr miss latency
982 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59730.372727 # average overall mshr miss latency
983 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 74000 # average overall mshr miss latency
984 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57878.385621 # average overall mshr miss latency
985 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 35930.350379 # average overall mshr miss latency
986 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 37014.858439 # average overall mshr miss latency
987 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
988 system.cpu.dcache.tags.replacements 5486251 # number of replacements
989 system.cpu.dcache.tags.tagsinuse 511.841559 # Cycle average of tags in use
990 system.cpu.dcache.tags.total_refs 18271309 # Total number of references to valid blocks.
991 system.cpu.dcache.tags.sampled_refs 5486763 # Sample count of references to valid blocks.
992 system.cpu.dcache.tags.avg_refs 3.330071 # Average number of references to valid blocks.
993 system.cpu.dcache.tags.warmup_cycle 27123000 # Cycle when the warmup percentage was hit.
994 system.cpu.dcache.tags.occ_blocks::cpu.data 511.841559 # Average occupied blocks per requestor
995 system.cpu.dcache.tags.occ_percent::cpu.data 0.999691 # Average percentage of cache occupancy
996 system.cpu.dcache.tags.occ_percent::total 0.999691 # Average percentage of cache occupancy
997 system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
998 system.cpu.dcache.tags.age_task_id_blocks_1024::0 391 # Occupied blocks per task id
999 system.cpu.dcache.tags.age_task_id_blocks_1024::1 121 # Occupied blocks per task id
1000 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
1001 system.cpu.dcache.tags.tag_accesses 61969579 # Number of tag accesses
1002 system.cpu.dcache.tags.data_accesses 61969579 # Number of data accesses
1003 system.cpu.dcache.ReadReq_hits::cpu.data 13905693 # number of ReadReq hits
1004 system.cpu.dcache.ReadReq_hits::total 13905693 # number of ReadReq hits
1005 system.cpu.dcache.WriteReq_hits::cpu.data 4357334 # number of WriteReq hits
1006 system.cpu.dcache.WriteReq_hits::total 4357334 # number of WriteReq hits
1007 system.cpu.dcache.SoftPFReq_hits::cpu.data 522 # number of SoftPFReq hits
1008 system.cpu.dcache.SoftPFReq_hits::total 522 # number of SoftPFReq hits
1009 system.cpu.dcache.LoadLockedReq_hits::cpu.data 3873 # number of LoadLockedReq hits
1010 system.cpu.dcache.LoadLockedReq_hits::total 3873 # number of LoadLockedReq hits
1011 system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits
1012 system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits
1013 system.cpu.dcache.demand_hits::cpu.data 18263027 # number of demand (read+write) hits
1014 system.cpu.dcache.demand_hits::total 18263027 # number of demand (read+write) hits
1015 system.cpu.dcache.overall_hits::cpu.data 18263549 # number of overall hits
1016 system.cpu.dcache.overall_hits::total 18263549 # number of overall hits
1017 system.cpu.dcache.ReadReq_misses::cpu.data 9592430 # number of ReadReq misses
1018 system.cpu.dcache.ReadReq_misses::total 9592430 # number of ReadReq misses
1019 system.cpu.dcache.WriteReq_misses::cpu.data 377647 # number of WriteReq misses
1020 system.cpu.dcache.WriteReq_misses::total 377647 # number of WriteReq misses
1021 system.cpu.dcache.SoftPFReq_misses::cpu.data 8 # number of SoftPFReq misses
1022 system.cpu.dcache.SoftPFReq_misses::total 8 # number of SoftPFReq misses
1023 system.cpu.dcache.LoadLockedReq_misses::cpu.data 14 # number of LoadLockedReq misses
1024 system.cpu.dcache.LoadLockedReq_misses::total 14 # number of LoadLockedReq misses
1025 system.cpu.dcache.demand_misses::cpu.data 9970077 # number of demand (read+write) misses
1026 system.cpu.dcache.demand_misses::total 9970077 # number of demand (read+write) misses
1027 system.cpu.dcache.overall_misses::cpu.data 9970085 # number of overall misses
1028 system.cpu.dcache.overall_misses::total 9970085 # number of overall misses
1029 system.cpu.dcache.ReadReq_miss_latency::cpu.data 87035855746 # number of ReadReq miss cycles
1030 system.cpu.dcache.ReadReq_miss_latency::total 87035855746 # number of ReadReq miss cycles
1031 system.cpu.dcache.WriteReq_miss_latency::cpu.data 3957576177 # number of WriteReq miss cycles
1032 system.cpu.dcache.WriteReq_miss_latency::total 3957576177 # number of WriteReq miss cycles
1033 system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 283250 # number of LoadLockedReq miss cycles
1034 system.cpu.dcache.LoadLockedReq_miss_latency::total 283250 # number of LoadLockedReq miss cycles
1035 system.cpu.dcache.demand_miss_latency::cpu.data 90993431923 # number of demand (read+write) miss cycles
1036 system.cpu.dcache.demand_miss_latency::total 90993431923 # number of demand (read+write) miss cycles
1037 system.cpu.dcache.overall_miss_latency::cpu.data 90993431923 # number of overall miss cycles
1038 system.cpu.dcache.overall_miss_latency::total 90993431923 # number of overall miss cycles
1039 system.cpu.dcache.ReadReq_accesses::cpu.data 23498123 # number of ReadReq accesses(hits+misses)
1040 system.cpu.dcache.ReadReq_accesses::total 23498123 # number of ReadReq accesses(hits+misses)
1041 system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses)
1042 system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses)
1043 system.cpu.dcache.SoftPFReq_accesses::cpu.data 530 # number of SoftPFReq accesses(hits+misses)
1044 system.cpu.dcache.SoftPFReq_accesses::total 530 # number of SoftPFReq accesses(hits+misses)
1045 system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 # number of LoadLockedReq accesses(hits+misses)
1046 system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses)
1047 system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses)
1048 system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses)
1049 system.cpu.dcache.demand_accesses::cpu.data 28233104 # number of demand (read+write) accesses
1050 system.cpu.dcache.demand_accesses::total 28233104 # number of demand (read+write) accesses
1051 system.cpu.dcache.overall_accesses::cpu.data 28233634 # number of overall (read+write) accesses
1052 system.cpu.dcache.overall_accesses::total 28233634 # number of overall (read+write) accesses
1053 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.408221 # miss rate for ReadReq accesses
1054 system.cpu.dcache.ReadReq_miss_rate::total 0.408221 # miss rate for ReadReq accesses
1055 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.079757 # miss rate for WriteReq accesses
1056 system.cpu.dcache.WriteReq_miss_rate::total 0.079757 # miss rate for WriteReq accesses
1057 system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.015094 # miss rate for SoftPFReq accesses
1058 system.cpu.dcache.SoftPFReq_miss_rate::total 0.015094 # miss rate for SoftPFReq accesses
1059 system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.003602 # miss rate for LoadLockedReq accesses
1060 system.cpu.dcache.LoadLockedReq_miss_rate::total 0.003602 # miss rate for LoadLockedReq accesses
1061 system.cpu.dcache.demand_miss_rate::cpu.data 0.353134 # miss rate for demand accesses
1062 system.cpu.dcache.demand_miss_rate::total 0.353134 # miss rate for demand accesses
1063 system.cpu.dcache.overall_miss_rate::cpu.data 0.353128 # miss rate for overall accesses
1064 system.cpu.dcache.overall_miss_rate::total 0.353128 # miss rate for overall accesses
1065 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9073.389719 # average ReadReq miss latency
1066 system.cpu.dcache.ReadReq_avg_miss_latency::total 9073.389719 # average ReadReq miss latency
1067 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10479.564718 # average WriteReq miss latency
1068 system.cpu.dcache.WriteReq_avg_miss_latency::total 10479.564718 # average WriteReq miss latency
1069 system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 20232.142857 # average LoadLockedReq miss latency
1070 system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 20232.142857 # average LoadLockedReq miss latency
1071 system.cpu.dcache.demand_avg_miss_latency::cpu.data 9126.652876 # average overall miss latency
1072 system.cpu.dcache.demand_avg_miss_latency::total 9126.652876 # average overall miss latency
1073 system.cpu.dcache.overall_avg_miss_latency::cpu.data 9126.645552 # average overall miss latency
1074 system.cpu.dcache.overall_avg_miss_latency::total 9126.645552 # average overall miss latency
1075 system.cpu.dcache.blocked_cycles::no_mshrs 301384 # number of cycles access was blocked
1076 system.cpu.dcache.blocked_cycles::no_targets 67125 # number of cycles access was blocked
1077 system.cpu.dcache.blocked::no_mshrs 120500 # number of cycles access was blocked
1078 system.cpu.dcache.blocked::no_targets 12183 # number of cycles access was blocked
1079 system.cpu.dcache.avg_blocked_cycles::no_mshrs 2.501112 # average number of cycles each access was blocked
1080 system.cpu.dcache.avg_blocked_cycles::no_targets 5.509727 # average number of cycles each access was blocked
1081 system.cpu.dcache.fast_writes 0 # number of fast writes performed
1082 system.cpu.dcache.cache_copies 0 # number of cache copies performed
1083 system.cpu.dcache.writebacks::writebacks 5407164 # number of writebacks
1084 system.cpu.dcache.writebacks::total 5407164 # number of writebacks
1085 system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4328464 # number of ReadReq MSHR hits
1086 system.cpu.dcache.ReadReq_mshr_hits::total 4328464 # number of ReadReq MSHR hits
1087 system.cpu.dcache.WriteReq_mshr_hits::cpu.data 154855 # number of WriteReq MSHR hits
1088 system.cpu.dcache.WriteReq_mshr_hits::total 154855 # number of WriteReq MSHR hits
1089 system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14 # number of LoadLockedReq MSHR hits
1090 system.cpu.dcache.LoadLockedReq_mshr_hits::total 14 # number of LoadLockedReq MSHR hits
1091 system.cpu.dcache.demand_mshr_hits::cpu.data 4483319 # number of demand (read+write) MSHR hits
1092 system.cpu.dcache.demand_mshr_hits::total 4483319 # number of demand (read+write) MSHR hits
1093 system.cpu.dcache.overall_mshr_hits::cpu.data 4483319 # number of overall MSHR hits
1094 system.cpu.dcache.overall_mshr_hits::total 4483319 # number of overall MSHR hits
1095 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5263966 # number of ReadReq MSHR misses
1096 system.cpu.dcache.ReadReq_mshr_misses::total 5263966 # number of ReadReq MSHR misses
1097 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 222792 # number of WriteReq MSHR misses
1098 system.cpu.dcache.WriteReq_mshr_misses::total 222792 # number of WriteReq MSHR misses
1099 system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 5 # number of SoftPFReq MSHR misses
1100 system.cpu.dcache.SoftPFReq_mshr_misses::total 5 # number of SoftPFReq MSHR misses
1101 system.cpu.dcache.demand_mshr_misses::cpu.data 5486758 # number of demand (read+write) MSHR misses
1102 system.cpu.dcache.demand_mshr_misses::total 5486758 # number of demand (read+write) MSHR misses
1103 system.cpu.dcache.overall_mshr_misses::cpu.data 5486763 # number of overall MSHR misses
1104 system.cpu.dcache.overall_mshr_misses::total 5486763 # number of overall MSHR misses
1105 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 38232328002 # number of ReadReq MSHR miss cycles
1106 system.cpu.dcache.ReadReq_mshr_miss_latency::total 38232328002 # number of ReadReq MSHR miss cycles
1107 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2158774283 # number of WriteReq MSHR miss cycles
1108 system.cpu.dcache.WriteReq_mshr_miss_latency::total 2158774283 # number of WriteReq MSHR miss cycles
1109 system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 284500 # number of SoftPFReq MSHR miss cycles
1110 system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 284500 # number of SoftPFReq MSHR miss cycles
1111 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 40391102285 # number of demand (read+write) MSHR miss cycles
1112 system.cpu.dcache.demand_mshr_miss_latency::total 40391102285 # number of demand (read+write) MSHR miss cycles
1113 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 40391386785 # number of overall MSHR miss cycles
1114 system.cpu.dcache.overall_mshr_miss_latency::total 40391386785 # number of overall MSHR miss cycles
1115 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.224016 # mshr miss rate for ReadReq accesses
1116 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.224016 # mshr miss rate for ReadReq accesses
1117 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047052 # mshr miss rate for WriteReq accesses
1118 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047052 # mshr miss rate for WriteReq accesses
1119 system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.009434 # mshr miss rate for SoftPFReq accesses
1120 system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.009434 # mshr miss rate for SoftPFReq accesses
1121 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.194338 # mshr miss rate for demand accesses
1122 system.cpu.dcache.demand_mshr_miss_rate::total 0.194338 # mshr miss rate for demand accesses
1123 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.194334 # mshr miss rate for overall accesses
1124 system.cpu.dcache.overall_mshr_miss_rate::total 0.194334 # mshr miss rate for overall accesses
1125 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7263.027155 # average ReadReq mshr miss latency
1126 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 7263.027155 # average ReadReq mshr miss latency
1127 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 9689.640036 # average WriteReq mshr miss latency
1128 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 9689.640036 # average WriteReq mshr miss latency
1129 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 56900 # average SoftPFReq mshr miss latency
1130 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 56900 # average SoftPFReq mshr miss latency
1131 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 7361.560740 # average overall mshr miss latency
1132 system.cpu.dcache.demand_avg_mshr_miss_latency::total 7361.560740 # average overall mshr miss latency
1133 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 7361.605884 # average overall mshr miss latency
1134 system.cpu.dcache.overall_avg_mshr_miss_latency::total 7361.605884 # average overall mshr miss latency
1135 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1137 ---------- End Simulation Statistics ----------
projects / gem5.git / blob