2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.058675 # Number of seconds simulated
4 sim_ticks 58675371500 # Number of ticks simulated
5 final_tick 58675371500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 111966 # Simulator instruction rate (inst/s)
8 host_op_rate 112523 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 72520515 # Simulator tick rate (ticks/s)
10 host_mem_usage 490592 # Number of bytes of host memory used
11 host_seconds 809.09 # Real time elapsed on the host
12 sim_insts 90589799 # Number of instructions simulated
13 sim_ops 91041030 # Number of ops (including micro ops) simulated
14 system.voltage_domain.voltage 1 # Voltage in Volts
15 system.clk_domain.clock 1000 # Clock period in ticks
16 system.physmem.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states
17 system.physmem.bytes_read::cpu.inst 44736 # Number of bytes read from this memory
18 system.physmem.bytes_read::cpu.data 218240 # Number of bytes read from this memory
19 system.physmem.bytes_read::cpu.l2cache.prefetcher 923072 # Number of bytes read from this memory
20 system.physmem.bytes_read::total 1186048 # Number of bytes read from this memory
21 system.physmem.bytes_inst_read::cpu.inst 44736 # Number of instructions bytes read from this memory
22 system.physmem.bytes_inst_read::total 44736 # Number of instructions bytes read from this memory
23 system.physmem.bytes_written::writebacks 6656 # Number of bytes written to this memory
24 system.physmem.bytes_written::total 6656 # Number of bytes written to this memory
25 system.physmem.num_reads::cpu.inst 699 # Number of read requests responded to by this memory
26 system.physmem.num_reads::cpu.data 3410 # Number of read requests responded to by this memory
27 system.physmem.num_reads::cpu.l2cache.prefetcher 14423 # Number of read requests responded to by this memory
28 system.physmem.num_reads::total 18532 # Number of read requests responded to by this memory
29 system.physmem.num_writes::writebacks 104 # Number of write requests responded to by this memory
30 system.physmem.num_writes::total 104 # Number of write requests responded to by this memory
31 system.physmem.bw_read::cpu.inst 762432 # Total read bandwidth from this memory (bytes/s)
32 system.physmem.bw_read::cpu.data 3719448 # Total read bandwidth from this memory (bytes/s)
33 system.physmem.bw_read::cpu.l2cache.prefetcher 15731848 # Total read bandwidth from this memory (bytes/s)
34 system.physmem.bw_read::total 20213728 # Total read bandwidth from this memory (bytes/s)
35 system.physmem.bw_inst_read::cpu.inst 762432 # Instruction read bandwidth from this memory (bytes/s)
36 system.physmem.bw_inst_read::total 762432 # Instruction read bandwidth from this memory (bytes/s)
37 system.physmem.bw_write::writebacks 113438 # Write bandwidth from this memory (bytes/s)
38 system.physmem.bw_write::total 113438 # Write bandwidth from this memory (bytes/s)
39 system.physmem.bw_total::writebacks 113438 # Total bandwidth to/from this memory (bytes/s)
40 system.physmem.bw_total::cpu.inst 762432 # Total bandwidth to/from this memory (bytes/s)
41 system.physmem.bw_total::cpu.data 3719448 # Total bandwidth to/from this memory (bytes/s)
42 system.physmem.bw_total::cpu.l2cache.prefetcher 15731848 # Total bandwidth to/from this memory (bytes/s)
43 system.physmem.bw_total::total 20327166 # Total bandwidth to/from this memory (bytes/s)
44 system.physmem.readReqs 18533 # Number of read requests accepted
45 system.physmem.writeReqs 104 # Number of write requests accepted
46 system.physmem.readBursts 18533 # Number of DRAM read bursts, including those serviced by the write queue
47 system.physmem.writeBursts 104 # Number of DRAM write bursts, including those merged in the write queue
48 system.physmem.bytesReadDRAM 1180480 # Total number of bytes read from DRAM
49 system.physmem.bytesReadWrQ 5632 # Total number of bytes read from write queue
50 system.physmem.bytesWritten 4608 # Total number of bytes written to DRAM
51 system.physmem.bytesReadSys 1186112 # Total read bytes from the system interface side
52 system.physmem.bytesWrittenSys 6656 # Total written bytes from the system interface side
53 system.physmem.servicedByWrQ 88 # Number of DRAM read bursts serviced by the write queue
54 system.physmem.mergedWrBursts 3 # Number of DRAM write bursts merged with an existing one
55 system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
56 system.physmem.perBankRdBursts::0 3245 # Per bank write bursts
57 system.physmem.perBankRdBursts::1 921 # Per bank write bursts
58 system.physmem.perBankRdBursts::2 952 # Per bank write bursts
59 system.physmem.perBankRdBursts::3 1031 # Per bank write bursts
60 system.physmem.perBankRdBursts::4 1065 # Per bank write bursts
61 system.physmem.perBankRdBursts::5 1118 # Per bank write bursts
62 system.physmem.perBankRdBursts::6 1097 # Per bank write bursts
63 system.physmem.perBankRdBursts::7 1096 # Per bank write bursts
64 system.physmem.perBankRdBursts::8 1024 # Per bank write bursts
65 system.physmem.perBankRdBursts::9 962 # Per bank write bursts
66 system.physmem.perBankRdBursts::10 932 # Per bank write bursts
67 system.physmem.perBankRdBursts::11 899 # Per bank write bursts
68 system.physmem.perBankRdBursts::12 904 # Per bank write bursts
69 system.physmem.perBankRdBursts::13 895 # Per bank write bursts
70 system.physmem.perBankRdBursts::14 1401 # Per bank write bursts
71 system.physmem.perBankRdBursts::15 903 # Per bank write bursts
72 system.physmem.perBankWrBursts::0 0 # Per bank write bursts
73 system.physmem.perBankWrBursts::1 0 # Per bank write bursts
74 system.physmem.perBankWrBursts::2 3 # Per bank write bursts
75 system.physmem.perBankWrBursts::3 3 # Per bank write bursts
76 system.physmem.perBankWrBursts::4 12 # Per bank write bursts
77 system.physmem.perBankWrBursts::5 10 # Per bank write bursts
78 system.physmem.perBankWrBursts::6 15 # Per bank write bursts
79 system.physmem.perBankWrBursts::7 0 # Per bank write bursts
80 system.physmem.perBankWrBursts::8 1 # Per bank write bursts
81 system.physmem.perBankWrBursts::9 0 # Per bank write bursts
82 system.physmem.perBankWrBursts::10 1 # Per bank write bursts
83 system.physmem.perBankWrBursts::11 3 # Per bank write bursts
84 system.physmem.perBankWrBursts::12 5 # Per bank write bursts
85 system.physmem.perBankWrBursts::13 12 # Per bank write bursts
86 system.physmem.perBankWrBursts::14 7 # Per bank write bursts
87 system.physmem.perBankWrBursts::15 0 # Per bank write bursts
88 system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
89 system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
90 system.physmem.totGap 58675363000 # Total gap between requests
91 system.physmem.readPktSize::0 0 # Read request sizes (log2)
92 system.physmem.readPktSize::1 0 # Read request sizes (log2)
93 system.physmem.readPktSize::2 0 # Read request sizes (log2)
94 system.physmem.readPktSize::3 0 # Read request sizes (log2)
95 system.physmem.readPktSize::4 0 # Read request sizes (log2)
96 system.physmem.readPktSize::5 0 # Read request sizes (log2)
97 system.physmem.readPktSize::6 18533 # Read request sizes (log2)
98 system.physmem.writePktSize::0 0 # Write request sizes (log2)
99 system.physmem.writePktSize::1 0 # Write request sizes (log2)
100 system.physmem.writePktSize::2 0 # Write request sizes (log2)
101 system.physmem.writePktSize::3 0 # Write request sizes (log2)
102 system.physmem.writePktSize::4 0 # Write request sizes (log2)
103 system.physmem.writePktSize::5 0 # Write request sizes (log2)
104 system.physmem.writePktSize::6 104 # Write request sizes (log2)
105 system.physmem.rdQLenPdf::0 12556 # What read queue length does an incoming req see
106 system.physmem.rdQLenPdf::1 3396 # What read queue length does an incoming req see
107 system.physmem.rdQLenPdf::2 496 # What read queue length does an incoming req see
108 system.physmem.rdQLenPdf::3 410 # What read queue length does an incoming req see
109 system.physmem.rdQLenPdf::4 314 # What read queue length does an incoming req see
110 system.physmem.rdQLenPdf::5 300 # What read queue length does an incoming req see
111 system.physmem.rdQLenPdf::6 298 # What read queue length does an incoming req see
112 system.physmem.rdQLenPdf::7 296 # What read queue length does an incoming req see
113 system.physmem.rdQLenPdf::8 280 # What read queue length does an incoming req see
114 system.physmem.rdQLenPdf::9 99 # What read queue length does an incoming req see
115 system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
116 system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
117 system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
118 system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
119 system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
120 system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
121 system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
122 system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
123 system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
124 system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
125 system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
126 system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
127 system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
128 system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
129 system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
130 system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
131 system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
132 system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
133 system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
134 system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
135 system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
136 system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
137 system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
138 system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
139 system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
140 system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
141 system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
142 system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
143 system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
144 system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
145 system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
146 system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
147 system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
148 system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
149 system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
150 system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
151 system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
152 system.physmem.wrQLenPdf::15 5 # What write queue length does an incoming req see
153 system.physmem.wrQLenPdf::16 5 # What write queue length does an incoming req see
154 system.physmem.wrQLenPdf::17 5 # What write queue length does an incoming req see
155 system.physmem.wrQLenPdf::18 5 # What write queue length does an incoming req see
156 system.physmem.wrQLenPdf::19 5 # What write queue length does an incoming req see
157 system.physmem.wrQLenPdf::20 5 # What write queue length does an incoming req see
158 system.physmem.wrQLenPdf::21 5 # What write queue length does an incoming req see
159 system.physmem.wrQLenPdf::22 5 # What write queue length does an incoming req see
160 system.physmem.wrQLenPdf::23 5 # What write queue length does an incoming req see
161 system.physmem.wrQLenPdf::24 5 # What write queue length does an incoming req see
162 system.physmem.wrQLenPdf::25 5 # What write queue length does an incoming req see
163 system.physmem.wrQLenPdf::26 5 # What write queue length does an incoming req see
164 system.physmem.wrQLenPdf::27 5 # What write queue length does an incoming req see
165 system.physmem.wrQLenPdf::28 5 # What write queue length does an incoming req see
166 system.physmem.wrQLenPdf::29 4 # What write queue length does an incoming req see
167 system.physmem.wrQLenPdf::30 4 # What write queue length does an incoming req see
168 system.physmem.wrQLenPdf::31 4 # What write queue length does an incoming req see
169 system.physmem.wrQLenPdf::32 4 # What write queue length does an incoming req see
170 system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
171 system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
172 system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
173 system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
174 system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
175 system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
176 system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
177 system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
178 system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
179 system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
180 system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
181 system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
182 system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
183 system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
184 system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
185 system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
186 system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
187 system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
188 system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
189 system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
190 system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
191 system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
192 system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
193 system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
194 system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
195 system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
196 system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
197 system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
198 system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
199 system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
200 system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
201 system.physmem.bytesPerActivate::samples 2974 # Bytes accessed per row activation
202 system.physmem.bytesPerActivate::mean 397.815736 # Bytes accessed per row activation
203 system.physmem.bytesPerActivate::gmean 217.392167 # Bytes accessed per row activation
204 system.physmem.bytesPerActivate::stdev 406.651837 # Bytes accessed per row activation
205 system.physmem.bytesPerActivate::0-127 841 28.28% 28.28% # Bytes accessed per row activation
206 system.physmem.bytesPerActivate::128-255 992 33.36% 61.63% # Bytes accessed per row activation
207 system.physmem.bytesPerActivate::256-383 92 3.09% 64.73% # Bytes accessed per row activation
208 system.physmem.bytesPerActivate::384-511 59 1.98% 66.71% # Bytes accessed per row activation
209 system.physmem.bytesPerActivate::512-639 59 1.98% 68.70% # Bytes accessed per row activation
210 system.physmem.bytesPerActivate::640-767 62 2.08% 70.78% # Bytes accessed per row activation
211 system.physmem.bytesPerActivate::768-895 53 1.78% 72.56% # Bytes accessed per row activation
212 system.physmem.bytesPerActivate::896-1023 59 1.98% 74.55% # Bytes accessed per row activation
213 system.physmem.bytesPerActivate::1024-1151 757 25.45% 100.00% # Bytes accessed per row activation
214 system.physmem.bytesPerActivate::total 2974 # Bytes accessed per row activation
215 system.physmem.rdPerTurnAround::samples 4 # Reads before turning the bus around for writes
216 system.physmem.rdPerTurnAround::mean 4542 # Reads before turning the bus around for writes
217 system.physmem.rdPerTurnAround::gmean 1434.998534 # Reads before turning the bus around for writes
218 system.physmem.rdPerTurnAround::stdev 7438.956513 # Reads before turning the bus around for writes
219 system.physmem.rdPerTurnAround::0-511 2 50.00% 50.00% # Reads before turning the bus around for writes
220 system.physmem.rdPerTurnAround::1536-2047 1 25.00% 75.00% # Reads before turning the bus around for writes
221 system.physmem.rdPerTurnAround::15360-15871 1 25.00% 100.00% # Reads before turning the bus around for writes
222 system.physmem.rdPerTurnAround::total 4 # Reads before turning the bus around for writes
223 system.physmem.wrPerTurnAround::samples 4 # Writes before turning the bus around for reads
224 system.physmem.wrPerTurnAround::mean 18 # Writes before turning the bus around for reads
225 system.physmem.wrPerTurnAround::gmean 18.000000 # Writes before turning the bus around for reads
226 system.physmem.wrPerTurnAround::18 4 100.00% 100.00% # Writes before turning the bus around for reads
227 system.physmem.wrPerTurnAround::total 4 # Writes before turning the bus around for reads
228 system.physmem.totQLat 819558662 # Total ticks spent queuing
229 system.physmem.totMemAccLat 1165402412 # Total ticks spent from burst creation until serviced by the DRAM
230 system.physmem.totBusLat 92225000 # Total ticks spent in databus transfers
231 system.physmem.avgQLat 44432.57 # Average queueing delay per DRAM burst
232 system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
233 system.physmem.avgMemAccLat 63182.57 # Average memory access latency per DRAM burst
234 system.physmem.avgRdBW 20.12 # Average DRAM read bandwidth in MiByte/s
235 system.physmem.avgWrBW 0.08 # Average achieved write bandwidth in MiByte/s
236 system.physmem.avgRdBWSys 20.21 # Average system read bandwidth in MiByte/s
237 system.physmem.avgWrBWSys 0.11 # Average system write bandwidth in MiByte/s
238 system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
239 system.physmem.busUtil 0.16 # Data bus utilization in percentage
240 system.physmem.busUtilRead 0.16 # Data bus utilization in percentage for reads
241 system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
242 system.physmem.avgRdQLen 1.07 # Average read queue length when enqueuing
243 system.physmem.avgWrQLen 17.01 # Average write queue length when enqueuing
244 system.physmem.readRowHits 15523 # Number of row buffer hits during reads
245 system.physmem.writeRowHits 12 # Number of row buffer hits during writes
246 system.physmem.readRowHitRate 84.16 # Row buffer hit rate for reads
247 system.physmem.writeRowHitRate 11.88 # Row buffer hit rate for writes
248 system.physmem.avgGap 3148326.61 # Average gap between requests
249 system.physmem.pageHitRate 83.76 # Row buffer hit rate, read and write combined
250 system.physmem_0.actEnergy 15986460 # Energy for activate commands per rank (pJ)
251 system.physmem_0.preEnergy 8481825 # Energy for precharge commands per rank (pJ)
252 system.physmem_0.readEnergy 75141360 # Energy for read commands per rank (pJ)
253 system.physmem_0.writeEnergy 224460 # Energy for write commands per rank (pJ)
254 system.physmem_0.refreshEnergy 1848222480.000000 # Energy for refresh commands per rank (pJ)
255 system.physmem_0.actBackEnergy 457291620 # Energy for active background per rank (pJ)
256 system.physmem_0.preBackEnergy 99494880 # Energy for precharge background per rank (pJ)
257 system.physmem_0.actPowerDownEnergy 3995273070 # Energy for active power-down per rank (pJ)
258 system.physmem_0.prePowerDownEnergy 3179264640 # Energy for precharge power-down per rank (pJ)
259 system.physmem_0.selfRefreshEnergy 10079734425 # Energy for self refresh per rank (pJ)
260 system.physmem_0.totalEnergy 19762775190 # Total energy per rank (pJ)
261 system.physmem_0.averagePower 336.815504 # Core power per rank (mW)
262 system.physmem_0.totalIdleTime 57405272063 # Total Idle time Per DRAM Rank
263 system.physmem_0.memoryStateTime::IDLE 196297250 # Time in different power states
264 system.physmem_0.memoryStateTime::REF 786242000 # Time in different power states
265 system.physmem_0.memoryStateTime::SREF 40364411250 # Time in different power states
266 system.physmem_0.memoryStateTime::PRE_PDN 8279321820 # Time in different power states
267 system.physmem_0.memoryStateTime::ACT 287560187 # Time in different power states
268 system.physmem_0.memoryStateTime::ACT_PDN 8761538993 # Time in different power states
269 system.physmem_1.actEnergy 5305020 # Energy for activate commands per rank (pJ)
270 system.physmem_1.preEnergy 2804505 # Energy for precharge commands per rank (pJ)
271 system.physmem_1.readEnergy 56548800 # Energy for read commands per rank (pJ)
272 system.physmem_1.writeEnergy 151380 # Energy for write commands per rank (pJ)
273 system.physmem_1.refreshEnergy 250773120.000000 # Energy for refresh commands per rank (pJ)
274 system.physmem_1.actBackEnergy 129702360 # Energy for active background per rank (pJ)
275 system.physmem_1.preBackEnergy 13640160 # Energy for precharge background per rank (pJ)
276 system.physmem_1.actPowerDownEnergy 769421340 # Energy for active power-down per rank (pJ)
277 system.physmem_1.prePowerDownEnergy 250623360 # Energy for precharge power-down per rank (pJ)
278 system.physmem_1.selfRefreshEnergy 13483521390 # Energy for self refresh per rank (pJ)
279 system.physmem_1.totalEnergy 14962606875 # Total energy per rank (pJ)
280 system.physmem_1.averagePower 255.006594 # Core power per rank (mW)
281 system.physmem_1.totalIdleTime 58353889098 # Total Idle time Per DRAM Rank
282 system.physmem_1.memoryStateTime::IDLE 22210250 # Time in different power states
283 system.physmem_1.memoryStateTime::REF 106530000 # Time in different power states
284 system.physmem_1.memoryStateTime::SREF 56015166500 # Time in different power states
285 system.physmem_1.memoryStateTime::PRE_PDN 652672389 # Time in different power states
286 system.physmem_1.memoryStateTime::ACT 191421152 # Time in different power states
287 system.physmem_1.memoryStateTime::ACT_PDN 1687371209 # Time in different power states
288 system.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states
289 system.cpu.branchPred.lookups 28234010 # Number of BP lookups
290 system.cpu.branchPred.condPredicted 23266490 # Number of conditional branches predicted
291 system.cpu.branchPred.condIncorrect 835433 # Number of conditional branches incorrect
292 system.cpu.branchPred.BTBLookups 11829728 # Number of BTB lookups
293 system.cpu.branchPred.BTBHits 11748003 # Number of BTB hits
294 system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
295 system.cpu.branchPred.BTBHitPct 99.309156 # BTB Hit Percentage
296 system.cpu.branchPred.usedRAS 74546 # Number of times the RAS was used to get a target.
297 system.cpu.branchPred.RASInCorrect 96 # Number of incorrect RAS predictions.
298 system.cpu.branchPred.indirectLookups 27219 # Number of indirect predictor lookups.
299 system.cpu.branchPred.indirectHits 25475 # Number of indirect target hits.
300 system.cpu.branchPred.indirectMisses 1744 # Number of indirect misses.
301 system.cpu.branchPredindirectMispredicted 245 # Number of mispredicted indirect branches.
302 system.cpu_clk_domain.clock 500 # Clock period in ticks
303 system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states
304 system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
305 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
306 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
307 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
308 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
309 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
310 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
311 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
312 system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
313 system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
314 system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
315 system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
316 system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
317 system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
318 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
319 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
320 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
321 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
322 system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
323 system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
324 system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
325 system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
326 system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
327 system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
328 system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
329 system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
330 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
331 system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
332 system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
333 system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states
334 system.cpu.dtb.walker.walks 0 # Table walker walks requested
335 system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
336 system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
337 system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
338 system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
339 system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
340 system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
341 system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
342 system.cpu.dtb.inst_hits 0 # ITB inst hits
343 system.cpu.dtb.inst_misses 0 # ITB inst misses
344 system.cpu.dtb.read_hits 0 # DTB read hits
345 system.cpu.dtb.read_misses 0 # DTB read misses
346 system.cpu.dtb.write_hits 0 # DTB write hits
347 system.cpu.dtb.write_misses 0 # DTB write misses
348 system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
349 system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
350 system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
351 system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
352 system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
353 system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
354 system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
355 system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
356 system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
357 system.cpu.dtb.read_accesses 0 # DTB read accesses
358 system.cpu.dtb.write_accesses 0 # DTB write accesses
359 system.cpu.dtb.inst_accesses 0 # ITB inst accesses
360 system.cpu.dtb.hits 0 # DTB hits
361 system.cpu.dtb.misses 0 # DTB misses
362 system.cpu.dtb.accesses 0 # DTB accesses
363 system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states
364 system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
365 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
366 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
367 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
368 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
369 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
370 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
371 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
372 system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
373 system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
374 system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
375 system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
376 system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
377 system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
378 system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
379 system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
380 system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
381 system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
382 system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
383 system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
384 system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
385 system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
386 system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
387 system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
388 system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
389 system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
390 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
391 system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
392 system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
393 system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states
394 system.cpu.itb.walker.walks 0 # Table walker walks requested
395 system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
396 system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
397 system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
398 system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
399 system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
400 system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
401 system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
402 system.cpu.itb.inst_hits 0 # ITB inst hits
403 system.cpu.itb.inst_misses 0 # ITB inst misses
404 system.cpu.itb.read_hits 0 # DTB read hits
405 system.cpu.itb.read_misses 0 # DTB read misses
406 system.cpu.itb.write_hits 0 # DTB write hits
407 system.cpu.itb.write_misses 0 # DTB write misses
408 system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
409 system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
410 system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
411 system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
412 system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
413 system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
414 system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
415 system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
416 system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
417 system.cpu.itb.read_accesses 0 # DTB read accesses
418 system.cpu.itb.write_accesses 0 # DTB write accesses
419 system.cpu.itb.inst_accesses 0 # ITB inst accesses
420 system.cpu.itb.hits 0 # DTB hits
421 system.cpu.itb.misses 0 # DTB misses
422 system.cpu.itb.accesses 0 # DTB accesses
423 system.cpu.workload.num_syscalls 442 # Number of system calls
424 system.cpu.pwrStateResidencyTicks::ON 58675371500 # Cumulative time (in ticks) in various power states
425 system.cpu.numCycles 117350744 # number of cpu cycles simulated
426 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
427 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
428 system.cpu.fetch.icacheStallCycles 746331 # Number of cycles fetch is stalled on an Icache miss
429 system.cpu.fetch.Insts 134908246 # Number of instructions fetch has processed
430 system.cpu.fetch.Branches 28234010 # Number of branches that fetch encountered
431 system.cpu.fetch.predictedBranches 11848024 # Number of branches that fetch has predicted taken
432 system.cpu.fetch.Cycles 115699810 # Number of cycles fetch has run and was not squashing or blocked
433 system.cpu.fetch.SquashCycles 1674291 # Number of cycles fetch has spent squashing
434 system.cpu.fetch.MiscStallCycles 849 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
435 system.cpu.fetch.IcacheWaitRetryStallCycles 926 # Number of stall cycles due to full MSHR
436 system.cpu.fetch.CacheLines 32275670 # Number of cache lines fetched
437 system.cpu.fetch.IcacheSquashes 568 # Number of outstanding Icache misses that were squashed
438 system.cpu.fetch.rateDist::samples 117285061 # Number of instructions fetched each cycle (Total)
439 system.cpu.fetch.rateDist::mean 1.155401 # Number of instructions fetched each cycle (Total)
440 system.cpu.fetch.rateDist::stdev 1.317679 # Number of instructions fetched each cycle (Total)
441 system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
442 system.cpu.fetch.rateDist::0 59749210 50.94% 50.94% # Number of instructions fetched each cycle (Total)
443 system.cpu.fetch.rateDist::1 13933958 11.88% 62.82% # Number of instructions fetched each cycle (Total)
444 system.cpu.fetch.rateDist::2 9228354 7.87% 70.69% # Number of instructions fetched each cycle (Total)
445 system.cpu.fetch.rateDist::3 34373539 29.31% 100.00% # Number of instructions fetched each cycle (Total)
446 system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
447 system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
448 system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
449 system.cpu.fetch.rateDist::total 117285061 # Number of instructions fetched each cycle (Total)
450 system.cpu.fetch.branchRate 0.240595 # Number of branch fetches per cycle
451 system.cpu.fetch.rate 1.149616 # Number of inst fetches per cycle
452 system.cpu.decode.IdleCycles 8835265 # Number of cycles decode is idle
453 system.cpu.decode.BlockedCycles 65049836 # Number of cycles decode is blocked
454 system.cpu.decode.RunCycles 33012809 # Number of cycles decode is running
455 system.cpu.decode.UnblockCycles 9561722 # Number of cycles decode is unblocking
456 system.cpu.decode.SquashCycles 825429 # Number of cycles decode is squashing
457 system.cpu.decode.BranchResolved 4097911 # Number of times decode resolved a branch
458 system.cpu.decode.BranchMispred 11817 # Number of times decode detected a branch misprediction
459 system.cpu.decode.DecodedInsts 114395758 # Number of instructions handled by decode
460 system.cpu.decode.SquashedInsts 1985288 # Number of squashed instructions handled by decode
461 system.cpu.rename.SquashCycles 825429 # Number of cycles rename is squashing
462 system.cpu.rename.IdleCycles 15272092 # Number of cycles rename is idle
463 system.cpu.rename.BlockCycles 50298480 # Number of cycles rename is blocking
464 system.cpu.rename.serializeStallCycles 112986 # count of cycles rename stalled for serializing inst
465 system.cpu.rename.RunCycles 35409562 # Number of cycles rename is running
466 system.cpu.rename.UnblockCycles 15366512 # Number of cycles rename is unblocking
467 system.cpu.rename.RenamedInsts 110872789 # Number of instructions processed by rename
468 system.cpu.rename.SquashedInsts 1412207 # Number of squashed instructions processed by rename
469 system.cpu.rename.ROBFullEvents 11133815 # Number of times rename has blocked due to ROB full
470 system.cpu.rename.IQFullEvents 1555614 # Number of times rename has blocked due to IQ full
471 system.cpu.rename.LQFullEvents 2094363 # Number of times rename has blocked due to LQ full
472 system.cpu.rename.SQFullEvents 506230 # Number of times rename has blocked due to SQ full
473 system.cpu.rename.RenamedOperands 129945991 # Number of destination operands rename has renamed
474 system.cpu.rename.RenameLookups 483154289 # Number of register rename lookups that rename has made
475 system.cpu.rename.int_rename_lookups 119447702 # Number of integer rename lookups
476 system.cpu.rename.fp_rename_lookups 431 # Number of floating rename lookups
477 system.cpu.rename.CommittedMaps 107312919 # Number of HB maps that are committed
478 system.cpu.rename.UndoneMaps 22633072 # Number of HB maps that are undone due to squashing
479 system.cpu.rename.serializingInsts 4409 # count of serializing insts renamed
480 system.cpu.rename.tempSerializingInsts 4401 # count of temporary serializing insts renamed
481 system.cpu.rename.skidInsts 21514760 # count of insts added to the skid buffer
482 system.cpu.memDep0.insertedLoads 26805262 # Number of loads inserted to the mem dependence unit.
483 system.cpu.memDep0.insertedStores 5347320 # Number of stores inserted to the mem dependence unit.
484 system.cpu.memDep0.conflictingLoads 521988 # Number of conflicting loads.
485 system.cpu.memDep0.conflictingStores 256188 # Number of conflicting stores.
486 system.cpu.iq.iqInstsAdded 109667585 # Number of instructions added to the IQ (excludes non-spec)
487 system.cpu.iq.iqNonSpecInstsAdded 8283 # Number of non-speculative instructions added to the IQ
488 system.cpu.iq.iqInstsIssued 101366888 # Number of instructions issued
489 system.cpu.iq.iqSquashedInstsIssued 1074694 # Number of squashed instructions issued
490 system.cpu.iq.iqSquashedInstsExamined 18634838 # Number of squashed instructions iterated over during squash; mainly for profiling
491 system.cpu.iq.iqSquashedOperandsExamined 41670017 # Number of squashed operands that are examined and possibly removed from graph
492 system.cpu.iq.iqSquashedNonSpecRemoved 65 # Number of squashed non-spec instructions that were removed
493 system.cpu.iq.issued_per_cycle::samples 117285061 # Number of insts issued each cycle
494 system.cpu.iq.issued_per_cycle::mean 0.864278 # Number of insts issued each cycle
495 system.cpu.iq.issued_per_cycle::stdev 0.988233 # Number of insts issued each cycle
496 system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
497 system.cpu.iq.issued_per_cycle::0 55650042 47.45% 47.45% # Number of insts issued each cycle
498 system.cpu.iq.issued_per_cycle::1 31364266 26.74% 74.19% # Number of insts issued each cycle
499 system.cpu.iq.issued_per_cycle::2 22008003 18.76% 92.95% # Number of insts issued each cycle
500 system.cpu.iq.issued_per_cycle::3 7064697 6.02% 98.98% # Number of insts issued each cycle
501 system.cpu.iq.issued_per_cycle::4 1197740 1.02% 100.00% # Number of insts issued each cycle
502 system.cpu.iq.issued_per_cycle::5 313 0.00% 100.00% # Number of insts issued each cycle
503 system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
504 system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
505 system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
506 system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
507 system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
508 system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
509 system.cpu.iq.issued_per_cycle::total 117285061 # Number of insts issued each cycle
510 system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
511 system.cpu.iq.fu_full::IntAlu 9783493 48.67% 48.67% # attempts to use FU when none available
512 system.cpu.iq.fu_full::IntMult 50 0.00% 48.67% # attempts to use FU when none available
513 system.cpu.iq.fu_full::IntDiv 0 0.00% 48.67% # attempts to use FU when none available
514 system.cpu.iq.fu_full::FloatAdd 0 0.00% 48.67% # attempts to use FU when none available
515 system.cpu.iq.fu_full::FloatCmp 0 0.00% 48.67% # attempts to use FU when none available
516 system.cpu.iq.fu_full::FloatCvt 0 0.00% 48.67% # attempts to use FU when none available
517 system.cpu.iq.fu_full::FloatMult 0 0.00% 48.67% # attempts to use FU when none available
518 system.cpu.iq.fu_full::FloatDiv 0 0.00% 48.67% # attempts to use FU when none available
519 system.cpu.iq.fu_full::FloatSqrt 0 0.00% 48.67% # attempts to use FU when none available
520 system.cpu.iq.fu_full::SimdAdd 0 0.00% 48.67% # attempts to use FU when none available
521 system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 48.67% # attempts to use FU when none available
522 system.cpu.iq.fu_full::SimdAlu 0 0.00% 48.67% # attempts to use FU when none available
523 system.cpu.iq.fu_full::SimdCmp 0 0.00% 48.67% # attempts to use FU when none available
524 system.cpu.iq.fu_full::SimdCvt 0 0.00% 48.67% # attempts to use FU when none available
525 system.cpu.iq.fu_full::SimdMisc 0 0.00% 48.67% # attempts to use FU when none available
526 system.cpu.iq.fu_full::SimdMult 0 0.00% 48.67% # attempts to use FU when none available
527 system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 48.67% # attempts to use FU when none available
528 system.cpu.iq.fu_full::SimdShift 0 0.00% 48.67% # attempts to use FU when none available
529 system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 48.67% # attempts to use FU when none available
530 system.cpu.iq.fu_full::SimdSqrt 0 0.00% 48.67% # attempts to use FU when none available
531 system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 48.67% # attempts to use FU when none available
532 system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 48.67% # attempts to use FU when none available
533 system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 48.67% # attempts to use FU when none available
534 system.cpu.iq.fu_full::SimdFloatCvt 13 0.00% 48.67% # attempts to use FU when none available
535 system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 48.67% # attempts to use FU when none available
536 system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 48.67% # attempts to use FU when none available
537 system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 48.67% # attempts to use FU when none available
538 system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 48.67% # attempts to use FU when none available
539 system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 48.67% # attempts to use FU when none available
540 system.cpu.iq.fu_full::MemRead 9615894 47.83% 96.50% # attempts to use FU when none available
541 system.cpu.iq.fu_full::MemWrite 702925 3.50% 100.00% # attempts to use FU when none available
542 system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
543 system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
544 system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
545 system.cpu.iq.FU_type_0::IntAlu 71970995 71.00% 71.00% # Type of FU issued
546 system.cpu.iq.FU_type_0::IntMult 10697 0.01% 71.01% # Type of FU issued
547 system.cpu.iq.FU_type_0::IntDiv 0 0.00% 71.01% # Type of FU issued
548 system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 71.01% # Type of FU issued
549 system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 71.01% # Type of FU issued
550 system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 71.01% # Type of FU issued
551 system.cpu.iq.FU_type_0::FloatMult 0 0.00% 71.01% # Type of FU issued
552 system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 71.01% # Type of FU issued
553 system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 71.01% # Type of FU issued
554 system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 71.01% # Type of FU issued
555 system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 71.01% # Type of FU issued
556 system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 71.01% # Type of FU issued
557 system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 71.01% # Type of FU issued
558 system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 71.01% # Type of FU issued
559 system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 71.01% # Type of FU issued
560 system.cpu.iq.FU_type_0::SimdMult 0 0.00% 71.01% # Type of FU issued
561 system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 71.01% # Type of FU issued
562 system.cpu.iq.FU_type_0::SimdShift 0 0.00% 71.01% # Type of FU issued
563 system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 71.01% # Type of FU issued
564 system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 71.01% # Type of FU issued
565 system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 71.01% # Type of FU issued
566 system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 71.01% # Type of FU issued
567 system.cpu.iq.FU_type_0::SimdFloatCmp 2 0.00% 71.01% # Type of FU issued
568 system.cpu.iq.FU_type_0::SimdFloatCvt 54 0.00% 71.01% # Type of FU issued
569 system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 71.01% # Type of FU issued
570 system.cpu.iq.FU_type_0::SimdFloatMisc 124 0.00% 71.01% # Type of FU issued
571 system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 71.01% # Type of FU issued
572 system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 71.01% # Type of FU issued
573 system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 71.01% # Type of FU issued
574 system.cpu.iq.FU_type_0::MemRead 24337772 24.01% 95.02% # Type of FU issued
575 system.cpu.iq.FU_type_0::MemWrite 5047242 4.98% 100.00% # Type of FU issued
576 system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
577 system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
578 system.cpu.iq.FU_type_0::total 101366888 # Type of FU issued
579 system.cpu.iq.rate 0.863794 # Inst issue rate
580 system.cpu.iq.fu_busy_cnt 20102375 # FU busy when requested
581 system.cpu.iq.fu_busy_rate 0.198313 # FU busy rate (busy events/executed inst)
582 system.cpu.iq.int_inst_queue_reads 341195448 # Number of integer instruction queue reads
583 system.cpu.iq.int_inst_queue_writes 128311397 # Number of integer instruction queue writes
584 system.cpu.iq.int_inst_queue_wakeup_accesses 99608403 # Number of integer instruction queue wakeup accesses
585 system.cpu.iq.fp_inst_queue_reads 458 # Number of floating instruction queue reads
586 system.cpu.iq.fp_inst_queue_writes 626 # Number of floating instruction queue writes
587 system.cpu.iq.fp_inst_queue_wakeup_accesses 113 # Number of floating instruction queue wakeup accesses
588 system.cpu.iq.int_alu_accesses 121469025 # Number of integer alu accesses
589 system.cpu.iq.fp_alu_accesses 238 # Number of floating point alu accesses
590 system.cpu.iew.lsq.thread0.forwLoads 288057 # Number of loads that had data forwarded from stores
591 system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
592 system.cpu.iew.lsq.thread0.squashedLoads 4329351 # Number of loads squashed
593 system.cpu.iew.lsq.thread0.ignoredResponses 1498 # Number of memory responses ignored because the instruction is squashed
594 system.cpu.iew.lsq.thread0.memOrderViolation 1351 # Number of memory ordering violations
595 system.cpu.iew.lsq.thread0.squashedStores 602476 # Number of stores squashed
596 system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
597 system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
598 system.cpu.iew.lsq.thread0.rescheduledLoads 7583 # Number of loads that were rescheduled
599 system.cpu.iew.lsq.thread0.cacheBlocked 130798 # Number of times an access to memory failed due to the cache being blocked
600 system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
601 system.cpu.iew.iewSquashCycles 825429 # Number of cycles IEW is squashing
602 system.cpu.iew.iewBlockCycles 8290686 # Number of cycles IEW is blocking
603 system.cpu.iew.iewUnblockCycles 768265 # Number of cycles IEW is unblocking
604 system.cpu.iew.iewDispatchedInsts 109688691 # Number of instructions dispatched to IQ
605 system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
606 system.cpu.iew.iewDispLoadInsts 26805262 # Number of dispatched load instructions
607 system.cpu.iew.iewDispStoreInsts 5347320 # Number of dispatched store instructions
608 system.cpu.iew.iewDispNonSpecInsts 4395 # Number of dispatched non-speculative instructions
609 system.cpu.iew.iewIQFullEvents 180386 # Number of times the IQ has become full, causing a stall
610 system.cpu.iew.iewLSQFullEvents 424316 # Number of times the LSQ has become full, causing a stall
611 system.cpu.iew.memOrderViolationEvents 1351 # Number of memory order violations
612 system.cpu.iew.predictedTakenIncorrect 435090 # Number of branches that were predicted taken incorrectly
613 system.cpu.iew.predictedNotTakenIncorrect 412415 # Number of branches that were predicted not taken incorrectly
614 system.cpu.iew.branchMispredicts 847505 # Number of branch mispredicts detected at execute
615 system.cpu.iew.iewExecutedInsts 100109953 # Number of executed instructions
616 system.cpu.iew.iewExecLoadInsts 23803133 # Number of load instructions executed
617 system.cpu.iew.iewExecSquashedInsts 1256935 # Number of squashed instructions skipped in execute
618 system.cpu.iew.exec_swp 0 # number of swp insts executed
619 system.cpu.iew.exec_nop 12823 # number of nop insts executed
620 system.cpu.iew.exec_refs 28718801 # number of memory reference insts executed
621 system.cpu.iew.exec_branches 20621332 # Number of branches executed
622 system.cpu.iew.exec_stores 4915668 # Number of stores executed
623 system.cpu.iew.exec_rate 0.853083 # Inst execution rate
624 system.cpu.iew.wb_sent 99693665 # cumulative count of insts sent to commit
625 system.cpu.iew.wb_count 99608516 # cumulative count of insts written-back
626 system.cpu.iew.wb_producers 59691499 # num instructions producing a value
627 system.cpu.iew.wb_consumers 95528314 # num instructions consuming a value
628 system.cpu.iew.wb_rate 0.848810 # insts written-back per cycle
629 system.cpu.iew.wb_fanout 0.624857 # average fanout of values written-back
630 system.cpu.commit.commitSquashedInsts 17363350 # The number of squashed insts skipped by commit
631 system.cpu.commit.commitNonSpecStalls 8218 # The number of times commit has been forced to stall to communicate backwards
632 system.cpu.commit.branchMispredicts 823717 # The number of times a branch was mispredicted
633 system.cpu.commit.committed_per_cycle::samples 114597116 # Number of insts commited each cycle
634 system.cpu.commit.committed_per_cycle::mean 0.794554 # Number of insts commited each cycle
635 system.cpu.commit.committed_per_cycle::stdev 1.732042 # Number of insts commited each cycle
636 system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
637 system.cpu.commit.committed_per_cycle::0 78173194 68.22% 68.22% # Number of insts commited each cycle
638 system.cpu.commit.committed_per_cycle::1 18611100 16.24% 84.46% # Number of insts commited each cycle
639 system.cpu.commit.committed_per_cycle::2 7154015 6.24% 90.70% # Number of insts commited each cycle
640 system.cpu.commit.committed_per_cycle::3 3469592 3.03% 93.73% # Number of insts commited each cycle
641 system.cpu.commit.committed_per_cycle::4 1644807 1.44% 95.16% # Number of insts commited each cycle
642 system.cpu.commit.committed_per_cycle::5 541237 0.47% 95.63% # Number of insts commited each cycle
643 system.cpu.commit.committed_per_cycle::6 703127 0.61% 96.25% # Number of insts commited each cycle
644 system.cpu.commit.committed_per_cycle::7 178794 0.16% 96.40% # Number of insts commited each cycle
645 system.cpu.commit.committed_per_cycle::8 4121250 3.60% 100.00% # Number of insts commited each cycle
646 system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
647 system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
648 system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
649 system.cpu.commit.committed_per_cycle::total 114597116 # Number of insts commited each cycle
650 system.cpu.commit.committedInsts 90602408 # Number of instructions committed
651 system.cpu.commit.committedOps 91053639 # Number of ops (including micro ops) committed
652 system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
653 system.cpu.commit.refs 27220755 # Number of memory references committed
654 system.cpu.commit.loads 22475911 # Number of loads committed
655 system.cpu.commit.membars 3888 # Number of memory barriers committed
656 system.cpu.commit.branches 18732305 # Number of branches committed
657 system.cpu.commit.fp_insts 48 # Number of committed floating point instructions.
658 system.cpu.commit.int_insts 72326352 # Number of committed integer instructions.
659 system.cpu.commit.function_calls 56148 # Number of function calls committed.
660 system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
661 system.cpu.commit.op_class_0::IntAlu 63822387 70.09% 70.09% # Class of committed instruction
662 system.cpu.commit.op_class_0::IntMult 10474 0.01% 70.10% # Class of committed instruction
663 system.cpu.commit.op_class_0::IntDiv 0 0.00% 70.10% # Class of committed instruction
664 system.cpu.commit.op_class_0::FloatAdd 0 0.00% 70.10% # Class of committed instruction
665 system.cpu.commit.op_class_0::FloatCmp 0 0.00% 70.10% # Class of committed instruction
666 system.cpu.commit.op_class_0::FloatCvt 0 0.00% 70.10% # Class of committed instruction
667 system.cpu.commit.op_class_0::FloatMult 0 0.00% 70.10% # Class of committed instruction
668 system.cpu.commit.op_class_0::FloatDiv 0 0.00% 70.10% # Class of committed instruction
669 system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 70.10% # Class of committed instruction
670 system.cpu.commit.op_class_0::SimdAdd 0 0.00% 70.10% # Class of committed instruction
671 system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 70.10% # Class of committed instruction
672 system.cpu.commit.op_class_0::SimdAlu 0 0.00% 70.10% # Class of committed instruction
673 system.cpu.commit.op_class_0::SimdCmp 0 0.00% 70.10% # Class of committed instruction
674 system.cpu.commit.op_class_0::SimdCvt 0 0.00% 70.10% # Class of committed instruction
675 system.cpu.commit.op_class_0::SimdMisc 0 0.00% 70.10% # Class of committed instruction
676 system.cpu.commit.op_class_0::SimdMult 0 0.00% 70.10% # Class of committed instruction
677 system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 70.10% # Class of committed instruction
678 system.cpu.commit.op_class_0::SimdShift 0 0.00% 70.10% # Class of committed instruction
679 system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 70.10% # Class of committed instruction
680 system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 70.10% # Class of committed instruction
681 system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 70.10% # Class of committed instruction
682 system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 70.10% # Class of committed instruction
683 system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 70.10% # Class of committed instruction
684 system.cpu.commit.op_class_0::SimdFloatCvt 6 0.00% 70.10% # Class of committed instruction
685 system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 70.10% # Class of committed instruction
686 system.cpu.commit.op_class_0::SimdFloatMisc 15 0.00% 70.10% # Class of committed instruction
687 system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 70.10% # Class of committed instruction
688 system.cpu.commit.op_class_0::SimdFloatMultAcc 2 0.00% 70.10% # Class of committed instruction
689 system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.10% # Class of committed instruction
690 system.cpu.commit.op_class_0::MemRead 22475911 24.68% 94.79% # Class of committed instruction
691 system.cpu.commit.op_class_0::MemWrite 4744844 5.21% 100.00% # Class of committed instruction
692 system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
693 system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
694 system.cpu.commit.op_class_0::total 91053639 # Class of committed instruction
695 system.cpu.commit.bw_lim_events 4121250 # number cycles where commit BW limit reached
696 system.cpu.rob.rob_reads 218887121 # The number of ROB reads
697 system.cpu.rob.rob_writes 219522508 # The number of ROB writes
698 system.cpu.timesIdled 581 # Number of times that the entire CPU went into an idle state and unscheduled itself
699 system.cpu.idleCycles 65683 # Total number of cycles that the CPU has spent unscheduled due to idling
700 system.cpu.committedInsts 90589799 # Number of Instructions Simulated
701 system.cpu.committedOps 91041030 # Number of Ops (including micro ops) Simulated
702 system.cpu.cpi 1.295408 # CPI: Cycles Per Instruction
703 system.cpu.cpi_total 1.295408 # CPI: Total CPI of All Threads
704 system.cpu.ipc 0.771958 # IPC: Instructions Per Cycle
705 system.cpu.ipc_total 0.771958 # IPC: Total IPC of All Threads
706 system.cpu.int_regfile_reads 108097860 # number of integer regfile reads
707 system.cpu.int_regfile_writes 58692141 # number of integer regfile writes
708 system.cpu.fp_regfile_reads 58 # number of floating regfile reads
709 system.cpu.fp_regfile_writes 93 # number of floating regfile writes
710 system.cpu.cc_regfile_reads 369004584 # number of cc regfile reads
711 system.cpu.cc_regfile_writes 58686965 # number of cc regfile writes
712 system.cpu.misc_regfile_reads 28409767 # number of misc regfile reads
713 system.cpu.misc_regfile_writes 7784 # number of misc regfile writes
714 system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states
715 system.cpu.dcache.tags.replacements 5470621 # number of replacements
716 system.cpu.dcache.tags.tagsinuse 511.769293 # Cycle average of tags in use
717 system.cpu.dcache.tags.total_refs 18249382 # Total number of references to valid blocks.
718 system.cpu.dcache.tags.sampled_refs 5471133 # Sample count of references to valid blocks.
719 system.cpu.dcache.tags.avg_refs 3.335576 # Average number of references to valid blocks.
720 system.cpu.dcache.tags.warmup_cycle 38111500 # Cycle when the warmup percentage was hit.
721 system.cpu.dcache.tags.occ_blocks::cpu.data 511.769293 # Average occupied blocks per requestor
722 system.cpu.dcache.tags.occ_percent::cpu.data 0.999549 # Average percentage of cache occupancy
723 system.cpu.dcache.tags.occ_percent::total 0.999549 # Average percentage of cache occupancy
724 system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
725 system.cpu.dcache.tags.age_task_id_blocks_1024::0 338 # Occupied blocks per task id
726 system.cpu.dcache.tags.age_task_id_blocks_1024::1 174 # Occupied blocks per task id
727 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
728 system.cpu.dcache.tags.tag_accesses 61907171 # Number of tag accesses
729 system.cpu.dcache.tags.data_accesses 61907171 # Number of data accesses
730 system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states
731 system.cpu.dcache.ReadReq_hits::cpu.data 13887260 # number of ReadReq hits
732 system.cpu.dcache.ReadReq_hits::total 13887260 # number of ReadReq hits
733 system.cpu.dcache.WriteReq_hits::cpu.data 4353834 # number of WriteReq hits
734 system.cpu.dcache.WriteReq_hits::total 4353834 # number of WriteReq hits
735 system.cpu.dcache.SoftPFReq_hits::cpu.data 522 # number of SoftPFReq hits
736 system.cpu.dcache.SoftPFReq_hits::total 522 # number of SoftPFReq hits
737 system.cpu.dcache.LoadLockedReq_hits::cpu.data 3873 # number of LoadLockedReq hits
738 system.cpu.dcache.LoadLockedReq_hits::total 3873 # number of LoadLockedReq hits
739 system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits
740 system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits
741 system.cpu.dcache.demand_hits::cpu.data 18241094 # number of demand (read+write) hits
742 system.cpu.dcache.demand_hits::total 18241094 # number of demand (read+write) hits
743 system.cpu.dcache.overall_hits::cpu.data 18241616 # number of overall hits
744 system.cpu.dcache.overall_hits::total 18241616 # number of overall hits
745 system.cpu.dcache.ReadReq_misses::cpu.data 9587475 # number of ReadReq misses
746 system.cpu.dcache.ReadReq_misses::total 9587475 # number of ReadReq misses
747 system.cpu.dcache.WriteReq_misses::cpu.data 381147 # number of WriteReq misses
748 system.cpu.dcache.WriteReq_misses::total 381147 # number of WriteReq misses
749 system.cpu.dcache.SoftPFReq_misses::cpu.data 7 # number of SoftPFReq misses
750 system.cpu.dcache.SoftPFReq_misses::total 7 # number of SoftPFReq misses
751 system.cpu.dcache.LoadLockedReq_misses::cpu.data 14 # number of LoadLockedReq misses
752 system.cpu.dcache.LoadLockedReq_misses::total 14 # number of LoadLockedReq misses
753 system.cpu.dcache.demand_misses::cpu.data 9968622 # number of demand (read+write) misses
754 system.cpu.dcache.demand_misses::total 9968622 # number of demand (read+write) misses
755 system.cpu.dcache.overall_misses::cpu.data 9968629 # number of overall misses
756 system.cpu.dcache.overall_misses::total 9968629 # number of overall misses
757 system.cpu.dcache.ReadReq_miss_latency::cpu.data 89371349000 # number of ReadReq miss cycles
758 system.cpu.dcache.ReadReq_miss_latency::total 89371349000 # number of ReadReq miss cycles
759 system.cpu.dcache.WriteReq_miss_latency::cpu.data 4092576700 # number of WriteReq miss cycles
760 system.cpu.dcache.WriteReq_miss_latency::total 4092576700 # number of WriteReq miss cycles
761 system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 302000 # number of LoadLockedReq miss cycles
762 system.cpu.dcache.LoadLockedReq_miss_latency::total 302000 # number of LoadLockedReq miss cycles
763 system.cpu.dcache.demand_miss_latency::cpu.data 93463925700 # number of demand (read+write) miss cycles
764 system.cpu.dcache.demand_miss_latency::total 93463925700 # number of demand (read+write) miss cycles
765 system.cpu.dcache.overall_miss_latency::cpu.data 93463925700 # number of overall miss cycles
766 system.cpu.dcache.overall_miss_latency::total 93463925700 # number of overall miss cycles
767 system.cpu.dcache.ReadReq_accesses::cpu.data 23474735 # number of ReadReq accesses(hits+misses)
768 system.cpu.dcache.ReadReq_accesses::total 23474735 # number of ReadReq accesses(hits+misses)
769 system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses)
770 system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses)
771 system.cpu.dcache.SoftPFReq_accesses::cpu.data 529 # number of SoftPFReq accesses(hits+misses)
772 system.cpu.dcache.SoftPFReq_accesses::total 529 # number of SoftPFReq accesses(hits+misses)
773 system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 # number of LoadLockedReq accesses(hits+misses)
774 system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses)
775 system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses)
776 system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses)
777 system.cpu.dcache.demand_accesses::cpu.data 28209716 # number of demand (read+write) accesses
778 system.cpu.dcache.demand_accesses::total 28209716 # number of demand (read+write) accesses
779 system.cpu.dcache.overall_accesses::cpu.data 28210245 # number of overall (read+write) accesses
780 system.cpu.dcache.overall_accesses::total 28210245 # number of overall (read+write) accesses
781 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.408417 # miss rate for ReadReq accesses
782 system.cpu.dcache.ReadReq_miss_rate::total 0.408417 # miss rate for ReadReq accesses
783 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.080496 # miss rate for WriteReq accesses
784 system.cpu.dcache.WriteReq_miss_rate::total 0.080496 # miss rate for WriteReq accesses
785 system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.013233 # miss rate for SoftPFReq accesses
786 system.cpu.dcache.SoftPFReq_miss_rate::total 0.013233 # miss rate for SoftPFReq accesses
787 system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.003602 # miss rate for LoadLockedReq accesses
788 system.cpu.dcache.LoadLockedReq_miss_rate::total 0.003602 # miss rate for LoadLockedReq accesses
789 system.cpu.dcache.demand_miss_rate::cpu.data 0.353375 # miss rate for demand accesses
790 system.cpu.dcache.demand_miss_rate::total 0.353375 # miss rate for demand accesses
791 system.cpu.dcache.overall_miss_rate::cpu.data 0.353369 # miss rate for overall accesses
792 system.cpu.dcache.overall_miss_rate::total 0.353369 # miss rate for overall accesses
793 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9321.677397 # average ReadReq miss latency
794 system.cpu.dcache.ReadReq_avg_miss_latency::total 9321.677397 # average ReadReq miss latency
795 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10737.528303 # average WriteReq miss latency
796 system.cpu.dcache.WriteReq_avg_miss_latency::total 10737.528303 # average WriteReq miss latency
797 system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 21571.428571 # average LoadLockedReq miss latency
798 system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 21571.428571 # average LoadLockedReq miss latency
799 system.cpu.dcache.demand_avg_miss_latency::cpu.data 9375.811993 # average overall miss latency
800 system.cpu.dcache.demand_avg_miss_latency::total 9375.811993 # average overall miss latency
801 system.cpu.dcache.overall_avg_miss_latency::cpu.data 9375.805409 # average overall miss latency
802 system.cpu.dcache.overall_avg_miss_latency::total 9375.805409 # average overall miss latency
803 system.cpu.dcache.blocked_cycles::no_mshrs 331977 # number of cycles access was blocked
804 system.cpu.dcache.blocked_cycles::no_targets 129797 # number of cycles access was blocked
805 system.cpu.dcache.blocked::no_mshrs 121610 # number of cycles access was blocked
806 system.cpu.dcache.blocked::no_targets 12840 # number of cycles access was blocked
807 system.cpu.dcache.avg_blocked_cycles::no_mshrs 2.729850 # average number of cycles each access was blocked
808 system.cpu.dcache.avg_blocked_cycles::no_targets 10.108801 # average number of cycles each access was blocked
809 system.cpu.dcache.writebacks::writebacks 5470621 # number of writebacks
810 system.cpu.dcache.writebacks::total 5470621 # number of writebacks
811 system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4338830 # number of ReadReq MSHR hits
812 system.cpu.dcache.ReadReq_mshr_hits::total 4338830 # number of ReadReq MSHR hits
813 system.cpu.dcache.WriteReq_mshr_hits::cpu.data 158660 # number of WriteReq MSHR hits
814 system.cpu.dcache.WriteReq_mshr_hits::total 158660 # number of WriteReq MSHR hits
815 system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14 # number of LoadLockedReq MSHR hits
816 system.cpu.dcache.LoadLockedReq_mshr_hits::total 14 # number of LoadLockedReq MSHR hits
817 system.cpu.dcache.demand_mshr_hits::cpu.data 4497490 # number of demand (read+write) MSHR hits
818 system.cpu.dcache.demand_mshr_hits::total 4497490 # number of demand (read+write) MSHR hits
819 system.cpu.dcache.overall_mshr_hits::cpu.data 4497490 # number of overall MSHR hits
820 system.cpu.dcache.overall_mshr_hits::total 4497490 # number of overall MSHR hits
821 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5248645 # number of ReadReq MSHR misses
822 system.cpu.dcache.ReadReq_mshr_misses::total 5248645 # number of ReadReq MSHR misses
823 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 222487 # number of WriteReq MSHR misses
824 system.cpu.dcache.WriteReq_mshr_misses::total 222487 # number of WriteReq MSHR misses
825 system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 4 # number of SoftPFReq MSHR misses
826 system.cpu.dcache.SoftPFReq_mshr_misses::total 4 # number of SoftPFReq MSHR misses
827 system.cpu.dcache.demand_mshr_misses::cpu.data 5471132 # number of demand (read+write) MSHR misses
828 system.cpu.dcache.demand_mshr_misses::total 5471132 # number of demand (read+write) MSHR misses
829 system.cpu.dcache.overall_mshr_misses::cpu.data 5471136 # number of overall MSHR misses
830 system.cpu.dcache.overall_mshr_misses::total 5471136 # number of overall MSHR misses
831 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 43817219500 # number of ReadReq MSHR miss cycles
832 system.cpu.dcache.ReadReq_mshr_miss_latency::total 43817219500 # number of ReadReq MSHR miss cycles
833 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2296823105 # number of WriteReq MSHR miss cycles
834 system.cpu.dcache.WriteReq_mshr_miss_latency::total 2296823105 # number of WriteReq MSHR miss cycles
835 system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 235500 # number of SoftPFReq MSHR miss cycles
836 system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 235500 # number of SoftPFReq MSHR miss cycles
837 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 46114042605 # number of demand (read+write) MSHR miss cycles
838 system.cpu.dcache.demand_mshr_miss_latency::total 46114042605 # number of demand (read+write) MSHR miss cycles
839 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 46114278105 # number of overall MSHR miss cycles
840 system.cpu.dcache.overall_mshr_miss_latency::total 46114278105 # number of overall MSHR miss cycles
841 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.223587 # mshr miss rate for ReadReq accesses
842 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.223587 # mshr miss rate for ReadReq accesses
843 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046988 # mshr miss rate for WriteReq accesses
844 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046988 # mshr miss rate for WriteReq accesses
845 system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.007561 # mshr miss rate for SoftPFReq accesses
846 system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.007561 # mshr miss rate for SoftPFReq accesses
847 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.193945 # mshr miss rate for demand accesses
848 system.cpu.dcache.demand_mshr_miss_rate::total 0.193945 # mshr miss rate for demand accesses
849 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.193941 # mshr miss rate for overall accesses
850 system.cpu.dcache.overall_mshr_miss_rate::total 0.193941 # mshr miss rate for overall accesses
851 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8348.291702 # average ReadReq mshr miss latency
852 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 8348.291702 # average ReadReq mshr miss latency
853 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10323.403637 # average WriteReq mshr miss latency
854 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10323.403637 # average WriteReq mshr miss latency
855 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 58875 # average SoftPFReq mshr miss latency
856 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 58875 # average SoftPFReq mshr miss latency
857 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8428.610862 # average overall mshr miss latency
858 system.cpu.dcache.demand_avg_mshr_miss_latency::total 8428.610862 # average overall mshr miss latency
859 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8428.647744 # average overall mshr miss latency
860 system.cpu.dcache.overall_avg_mshr_miss_latency::total 8428.647744 # average overall mshr miss latency
861 system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states
862 system.cpu.icache.tags.replacements 448 # number of replacements
863 system.cpu.icache.tags.tagsinuse 427.600534 # Cycle average of tags in use
864 system.cpu.icache.tags.total_refs 32274508 # Total number of references to valid blocks.
865 system.cpu.icache.tags.sampled_refs 906 # Sample count of references to valid blocks.
866 system.cpu.icache.tags.avg_refs 35623.077263 # Average number of references to valid blocks.
867 system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
868 system.cpu.icache.tags.occ_blocks::cpu.inst 427.600534 # Average occupied blocks per requestor
869 system.cpu.icache.tags.occ_percent::cpu.inst 0.835157 # Average percentage of cache occupancy
870 system.cpu.icache.tags.occ_percent::total 0.835157 # Average percentage of cache occupancy
871 system.cpu.icache.tags.occ_task_id_blocks::1024 458 # Occupied blocks per task id
872 system.cpu.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id
873 system.cpu.icache.tags.age_task_id_blocks_1024::2 51 # Occupied blocks per task id
874 system.cpu.icache.tags.age_task_id_blocks_1024::3 19 # Occupied blocks per task id
875 system.cpu.icache.tags.age_task_id_blocks_1024::4 335 # Occupied blocks per task id
876 system.cpu.icache.tags.occ_task_id_percent::1024 0.894531 # Percentage of cache occupancy per task id
877 system.cpu.icache.tags.tag_accesses 64552224 # Number of tag accesses
878 system.cpu.icache.tags.data_accesses 64552224 # Number of data accesses
879 system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states
880 system.cpu.icache.ReadReq_hits::cpu.inst 32274508 # number of ReadReq hits
881 system.cpu.icache.ReadReq_hits::total 32274508 # number of ReadReq hits
882 system.cpu.icache.demand_hits::cpu.inst 32274508 # number of demand (read+write) hits
883 system.cpu.icache.demand_hits::total 32274508 # number of demand (read+write) hits
884 system.cpu.icache.overall_hits::cpu.inst 32274508 # number of overall hits
885 system.cpu.icache.overall_hits::total 32274508 # number of overall hits
886 system.cpu.icache.ReadReq_misses::cpu.inst 1151 # number of ReadReq misses
887 system.cpu.icache.ReadReq_misses::total 1151 # number of ReadReq misses
888 system.cpu.icache.demand_misses::cpu.inst 1151 # number of demand (read+write) misses
889 system.cpu.icache.demand_misses::total 1151 # number of demand (read+write) misses
890 system.cpu.icache.overall_misses::cpu.inst 1151 # number of overall misses
891 system.cpu.icache.overall_misses::total 1151 # number of overall misses
892 system.cpu.icache.ReadReq_miss_latency::cpu.inst 79113980 # number of ReadReq miss cycles
893 system.cpu.icache.ReadReq_miss_latency::total 79113980 # number of ReadReq miss cycles
894 system.cpu.icache.demand_miss_latency::cpu.inst 79113980 # number of demand (read+write) miss cycles
895 system.cpu.icache.demand_miss_latency::total 79113980 # number of demand (read+write) miss cycles
896 system.cpu.icache.overall_miss_latency::cpu.inst 79113980 # number of overall miss cycles
897 system.cpu.icache.overall_miss_latency::total 79113980 # number of overall miss cycles
898 system.cpu.icache.ReadReq_accesses::cpu.inst 32275659 # number of ReadReq accesses(hits+misses)
899 system.cpu.icache.ReadReq_accesses::total 32275659 # number of ReadReq accesses(hits+misses)
900 system.cpu.icache.demand_accesses::cpu.inst 32275659 # number of demand (read+write) accesses
901 system.cpu.icache.demand_accesses::total 32275659 # number of demand (read+write) accesses
902 system.cpu.icache.overall_accesses::cpu.inst 32275659 # number of overall (read+write) accesses
903 system.cpu.icache.overall_accesses::total 32275659 # number of overall (read+write) accesses
904 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000036 # miss rate for ReadReq accesses
905 system.cpu.icache.ReadReq_miss_rate::total 0.000036 # miss rate for ReadReq accesses
906 system.cpu.icache.demand_miss_rate::cpu.inst 0.000036 # miss rate for demand accesses
907 system.cpu.icache.demand_miss_rate::total 0.000036 # miss rate for demand accesses
908 system.cpu.icache.overall_miss_rate::cpu.inst 0.000036 # miss rate for overall accesses
909 system.cpu.icache.overall_miss_rate::total 0.000036 # miss rate for overall accesses
910 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68734.995656 # average ReadReq miss latency
911 system.cpu.icache.ReadReq_avg_miss_latency::total 68734.995656 # average ReadReq miss latency
912 system.cpu.icache.demand_avg_miss_latency::cpu.inst 68734.995656 # average overall miss latency
913 system.cpu.icache.demand_avg_miss_latency::total 68734.995656 # average overall miss latency
914 system.cpu.icache.overall_avg_miss_latency::cpu.inst 68734.995656 # average overall miss latency
915 system.cpu.icache.overall_avg_miss_latency::total 68734.995656 # average overall miss latency
916 system.cpu.icache.blocked_cycles::no_mshrs 21173 # number of cycles access was blocked
917 system.cpu.icache.blocked_cycles::no_targets 759 # number of cycles access was blocked
918 system.cpu.icache.blocked::no_mshrs 225 # number of cycles access was blocked
919 system.cpu.icache.blocked::no_targets 6 # number of cycles access was blocked
920 system.cpu.icache.avg_blocked_cycles::no_mshrs 94.102222 # average number of cycles each access was blocked
921 system.cpu.icache.avg_blocked_cycles::no_targets 126.500000 # average number of cycles each access was blocked
922 system.cpu.icache.writebacks::writebacks 448 # number of writebacks
923 system.cpu.icache.writebacks::total 448 # number of writebacks
924 system.cpu.icache.ReadReq_mshr_hits::cpu.inst 244 # number of ReadReq MSHR hits
925 system.cpu.icache.ReadReq_mshr_hits::total 244 # number of ReadReq MSHR hits
926 system.cpu.icache.demand_mshr_hits::cpu.inst 244 # number of demand (read+write) MSHR hits
927 system.cpu.icache.demand_mshr_hits::total 244 # number of demand (read+write) MSHR hits
928 system.cpu.icache.overall_mshr_hits::cpu.inst 244 # number of overall MSHR hits
929 system.cpu.icache.overall_mshr_hits::total 244 # number of overall MSHR hits
930 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 907 # number of ReadReq MSHR misses
931 system.cpu.icache.ReadReq_mshr_misses::total 907 # number of ReadReq MSHR misses
932 system.cpu.icache.demand_mshr_misses::cpu.inst 907 # number of demand (read+write) MSHR misses
933 system.cpu.icache.demand_mshr_misses::total 907 # number of demand (read+write) MSHR misses
934 system.cpu.icache.overall_mshr_misses::cpu.inst 907 # number of overall MSHR misses
935 system.cpu.icache.overall_mshr_misses::total 907 # number of overall MSHR misses
936 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 60405484 # number of ReadReq MSHR miss cycles
937 system.cpu.icache.ReadReq_mshr_miss_latency::total 60405484 # number of ReadReq MSHR miss cycles
938 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 60405484 # number of demand (read+write) MSHR miss cycles
939 system.cpu.icache.demand_mshr_miss_latency::total 60405484 # number of demand (read+write) MSHR miss cycles
940 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 60405484 # number of overall MSHR miss cycles
941 system.cpu.icache.overall_mshr_miss_latency::total 60405484 # number of overall MSHR miss cycles
942 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for ReadReq accesses
943 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000028 # mshr miss rate for ReadReq accesses
944 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for demand accesses
945 system.cpu.icache.demand_mshr_miss_rate::total 0.000028 # mshr miss rate for demand accesses
946 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for overall accesses
947 system.cpu.icache.overall_mshr_miss_rate::total 0.000028 # mshr miss rate for overall accesses
948 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66599.210584 # average ReadReq mshr miss latency
949 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66599.210584 # average ReadReq mshr miss latency
950 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66599.210584 # average overall mshr miss latency
951 system.cpu.icache.demand_avg_mshr_miss_latency::total 66599.210584 # average overall mshr miss latency
952 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66599.210584 # average overall mshr miss latency
953 system.cpu.icache.overall_avg_mshr_miss_latency::total 66599.210584 # average overall mshr miss latency
954 system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states
955 system.cpu.l2cache.prefetcher.num_hwpf_issued 4988856 # number of hwpf issued
956 system.cpu.l2cache.prefetcher.pfIdentified 5295771 # number of prefetch candidates identified
957 system.cpu.l2cache.prefetcher.pfBufferHit 266816 # number of redundant prefetches already in prefetch queue
958 system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
959 system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
960 system.cpu.l2cache.prefetcher.pfSpanPage 14074045 # number of prefetches not generated due to page crossing
961 system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states
962 system.cpu.l2cache.tags.replacements 140 # number of replacements
963 system.cpu.l2cache.tags.tagsinuse 11212.925557 # Cycle average of tags in use
964 system.cpu.l2cache.tags.total_refs 5291618 # Total number of references to valid blocks.
965 system.cpu.l2cache.tags.sampled_refs 14696 # Sample count of references to valid blocks.
966 system.cpu.l2cache.tags.avg_refs 360.071992 # Average number of references to valid blocks.
967 system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
968 system.cpu.l2cache.tags.occ_blocks::writebacks 11154.278216 # Average occupied blocks per requestor
969 system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 58.647341 # Average occupied blocks per requestor
970 system.cpu.l2cache.tags.occ_percent::writebacks 0.680803 # Average percentage of cache occupancy
971 system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.003580 # Average percentage of cache occupancy
972 system.cpu.l2cache.tags.occ_percent::total 0.684383 # Average percentage of cache occupancy
973 system.cpu.l2cache.tags.occ_task_id_blocks::1022 60 # Occupied blocks per task id
974 system.cpu.l2cache.tags.occ_task_id_blocks::1024 14496 # Occupied blocks per task id
975 system.cpu.l2cache.tags.age_task_id_blocks_1022::0 2 # Occupied blocks per task id
976 system.cpu.l2cache.tags.age_task_id_blocks_1022::1 9 # Occupied blocks per task id
977 system.cpu.l2cache.tags.age_task_id_blocks_1022::4 49 # Occupied blocks per task id
978 system.cpu.l2cache.tags.age_task_id_blocks_1024::0 477 # Occupied blocks per task id
979 system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3389 # Occupied blocks per task id
980 system.cpu.l2cache.tags.age_task_id_blocks_1024::2 9672 # Occupied blocks per task id
981 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 119 # Occupied blocks per task id
982 system.cpu.l2cache.tags.age_task_id_blocks_1024::4 839 # Occupied blocks per task id
983 system.cpu.l2cache.tags.occ_task_id_percent::1022 0.003662 # Percentage of cache occupancy per task id
984 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.884766 # Percentage of cache occupancy per task id
985 system.cpu.l2cache.tags.tag_accesses 180525801 # Number of tag accesses
986 system.cpu.l2cache.tags.data_accesses 180525801 # Number of data accesses
987 system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states
988 system.cpu.l2cache.WritebackDirty_hits::writebacks 5457281 # number of WritebackDirty hits
989 system.cpu.l2cache.WritebackDirty_hits::total 5457281 # number of WritebackDirty hits
990 system.cpu.l2cache.WritebackClean_hits::writebacks 10913 # number of WritebackClean hits
991 system.cpu.l2cache.WritebackClean_hits::total 10913 # number of WritebackClean hits
992 system.cpu.l2cache.ReadExReq_hits::cpu.data 226015 # number of ReadExReq hits
993 system.cpu.l2cache.ReadExReq_hits::total 226015 # number of ReadExReq hits
994 system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 206 # number of ReadCleanReq hits
995 system.cpu.l2cache.ReadCleanReq_hits::total 206 # number of ReadCleanReq hits
996 system.cpu.l2cache.ReadSharedReq_hits::cpu.data 5241513 # number of ReadSharedReq hits
997 system.cpu.l2cache.ReadSharedReq_hits::total 5241513 # number of ReadSharedReq hits
998 system.cpu.l2cache.demand_hits::cpu.inst 206 # number of demand (read+write) hits
999 system.cpu.l2cache.demand_hits::cpu.data 5467528 # number of demand (read+write) hits
1000 system.cpu.l2cache.demand_hits::total 5467734 # number of demand (read+write) hits
1001 system.cpu.l2cache.overall_hits::cpu.inst 206 # number of overall hits
1002 system.cpu.l2cache.overall_hits::cpu.data 5467528 # number of overall hits
1003 system.cpu.l2cache.overall_hits::total 5467734 # number of overall hits
1004 system.cpu.l2cache.UpgradeReq_misses::cpu.data 3 # number of UpgradeReq misses
1005 system.cpu.l2cache.UpgradeReq_misses::total 3 # number of UpgradeReq misses
1006 system.cpu.l2cache.ReadExReq_misses::cpu.data 505 # number of ReadExReq misses
1007 system.cpu.l2cache.ReadExReq_misses::total 505 # number of ReadExReq misses
1008 system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 701 # number of ReadCleanReq misses
1009 system.cpu.l2cache.ReadCleanReq_misses::total 701 # number of ReadCleanReq misses
1010 system.cpu.l2cache.ReadSharedReq_misses::cpu.data 3100 # number of ReadSharedReq misses
1011 system.cpu.l2cache.ReadSharedReq_misses::total 3100 # number of ReadSharedReq misses
1012 system.cpu.l2cache.demand_misses::cpu.inst 701 # number of demand (read+write) misses
1013 system.cpu.l2cache.demand_misses::cpu.data 3605 # number of demand (read+write) misses
1014 system.cpu.l2cache.demand_misses::total 4306 # number of demand (read+write) misses
1015 system.cpu.l2cache.overall_misses::cpu.inst 701 # number of overall misses
1016 system.cpu.l2cache.overall_misses::cpu.data 3605 # number of overall misses
1017 system.cpu.l2cache.overall_misses::total 4306 # number of overall misses
1018 system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 63500 # number of UpgradeReq miss cycles
1019 system.cpu.l2cache.UpgradeReq_miss_latency::total 63500 # number of UpgradeReq miss cycles
1020 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 64129500 # number of ReadExReq miss cycles
1021 system.cpu.l2cache.ReadExReq_miss_latency::total 64129500 # number of ReadExReq miss cycles
1022 system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 58109500 # number of ReadCleanReq miss cycles
1023 system.cpu.l2cache.ReadCleanReq_miss_latency::total 58109500 # number of ReadCleanReq miss cycles
1024 system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 616309000 # number of ReadSharedReq miss cycles
1025 system.cpu.l2cache.ReadSharedReq_miss_latency::total 616309000 # number of ReadSharedReq miss cycles
1026 system.cpu.l2cache.demand_miss_latency::cpu.inst 58109500 # number of demand (read+write) miss cycles
1027 system.cpu.l2cache.demand_miss_latency::cpu.data 680438500 # number of demand (read+write) miss cycles
1028 system.cpu.l2cache.demand_miss_latency::total 738548000 # number of demand (read+write) miss cycles
1029 system.cpu.l2cache.overall_miss_latency::cpu.inst 58109500 # number of overall miss cycles
1030 system.cpu.l2cache.overall_miss_latency::cpu.data 680438500 # number of overall miss cycles
1031 system.cpu.l2cache.overall_miss_latency::total 738548000 # number of overall miss cycles
1032 system.cpu.l2cache.WritebackDirty_accesses::writebacks 5457281 # number of WritebackDirty accesses(hits+misses)
1033 system.cpu.l2cache.WritebackDirty_accesses::total 5457281 # number of WritebackDirty accesses(hits+misses)
1034 system.cpu.l2cache.WritebackClean_accesses::writebacks 10913 # number of WritebackClean accesses(hits+misses)
1035 system.cpu.l2cache.WritebackClean_accesses::total 10913 # number of WritebackClean accesses(hits+misses)
1036 system.cpu.l2cache.UpgradeReq_accesses::cpu.data 3 # number of UpgradeReq accesses(hits+misses)
1037 system.cpu.l2cache.UpgradeReq_accesses::total 3 # number of UpgradeReq accesses(hits+misses)
1038 system.cpu.l2cache.ReadExReq_accesses::cpu.data 226520 # number of ReadExReq accesses(hits+misses)
1039 system.cpu.l2cache.ReadExReq_accesses::total 226520 # number of ReadExReq accesses(hits+misses)
1040 system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 907 # number of ReadCleanReq accesses(hits+misses)
1041 system.cpu.l2cache.ReadCleanReq_accesses::total 907 # number of ReadCleanReq accesses(hits+misses)
1042 system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 5244613 # number of ReadSharedReq accesses(hits+misses)
1043 system.cpu.l2cache.ReadSharedReq_accesses::total 5244613 # number of ReadSharedReq accesses(hits+misses)
1044 system.cpu.l2cache.demand_accesses::cpu.inst 907 # number of demand (read+write) accesses
1045 system.cpu.l2cache.demand_accesses::cpu.data 5471133 # number of demand (read+write) accesses
1046 system.cpu.l2cache.demand_accesses::total 5472040 # number of demand (read+write) accesses
1047 system.cpu.l2cache.overall_accesses::cpu.inst 907 # number of overall (read+write) accesses
1048 system.cpu.l2cache.overall_accesses::cpu.data 5471133 # number of overall (read+write) accesses
1049 system.cpu.l2cache.overall_accesses::total 5472040 # number of overall (read+write) accesses
1050 system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses
1051 system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses
1052 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.002229 # miss rate for ReadExReq accesses
1053 system.cpu.l2cache.ReadExReq_miss_rate::total 0.002229 # miss rate for ReadExReq accesses
1054 system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.772878 # miss rate for ReadCleanReq accesses
1055 system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.772878 # miss rate for ReadCleanReq accesses
1056 system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000591 # miss rate for ReadSharedReq accesses
1057 system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000591 # miss rate for ReadSharedReq accesses
1058 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.772878 # miss rate for demand accesses
1059 system.cpu.l2cache.demand_miss_rate::cpu.data 0.000659 # miss rate for demand accesses
1060 system.cpu.l2cache.demand_miss_rate::total 0.000787 # miss rate for demand accesses
1061 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.772878 # miss rate for overall accesses
1062 system.cpu.l2cache.overall_miss_rate::cpu.data 0.000659 # miss rate for overall accesses
1063 system.cpu.l2cache.overall_miss_rate::total 0.000787 # miss rate for overall accesses
1064 system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 21166.666667 # average UpgradeReq miss latency
1065 system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 21166.666667 # average UpgradeReq miss latency
1066 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 126989.108911 # average ReadExReq miss latency
1067 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 126989.108911 # average ReadExReq miss latency
1068 system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82895.149786 # average ReadCleanReq miss latency
1069 system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82895.149786 # average ReadCleanReq miss latency
1070 system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 198809.354839 # average ReadSharedReq miss latency
1071 system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 198809.354839 # average ReadSharedReq miss latency
1072 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82895.149786 # average overall miss latency
1073 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 188748.543689 # average overall miss latency
1074 system.cpu.l2cache.demand_avg_miss_latency::total 171516.024152 # average overall miss latency
1075 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82895.149786 # average overall miss latency
1076 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 188748.543689 # average overall miss latency
1077 system.cpu.l2cache.overall_avg_miss_latency::total 171516.024152 # average overall miss latency
1078 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1079 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1080 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
1081 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1082 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1083 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1084 system.cpu.l2cache.unused_prefetches 3 # number of HardPF blocks evicted w/o reference
1085 system.cpu.l2cache.writebacks::writebacks 104 # number of writebacks
1086 system.cpu.l2cache.writebacks::total 104 # number of writebacks
1087 system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 162 # number of ReadExReq MSHR hits
1088 system.cpu.l2cache.ReadExReq_mshr_hits::total 162 # number of ReadExReq MSHR hits
1089 system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits
1090 system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits
1091 system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 32 # number of ReadSharedReq MSHR hits
1092 system.cpu.l2cache.ReadSharedReq_mshr_hits::total 32 # number of ReadSharedReq MSHR hits
1093 system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
1094 system.cpu.l2cache.demand_mshr_hits::cpu.data 194 # number of demand (read+write) MSHR hits
1095 system.cpu.l2cache.demand_mshr_hits::total 195 # number of demand (read+write) MSHR hits
1096 system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
1097 system.cpu.l2cache.overall_mshr_hits::cpu.data 194 # number of overall MSHR hits
1098 system.cpu.l2cache.overall_mshr_hits::total 195 # number of overall MSHR hits
1099 system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 316848 # number of HardPFReq MSHR misses
1100 system.cpu.l2cache.HardPFReq_mshr_misses::total 316848 # number of HardPFReq MSHR misses
1101 system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 3 # number of UpgradeReq MSHR misses
1102 system.cpu.l2cache.UpgradeReq_mshr_misses::total 3 # number of UpgradeReq MSHR misses
1103 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 343 # number of ReadExReq MSHR misses
1104 system.cpu.l2cache.ReadExReq_mshr_misses::total 343 # number of ReadExReq MSHR misses
1105 system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 700 # number of ReadCleanReq MSHR misses
1106 system.cpu.l2cache.ReadCleanReq_mshr_misses::total 700 # number of ReadCleanReq MSHR misses
1107 system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 3068 # number of ReadSharedReq MSHR misses
1108 system.cpu.l2cache.ReadSharedReq_mshr_misses::total 3068 # number of ReadSharedReq MSHR misses
1109 system.cpu.l2cache.demand_mshr_misses::cpu.inst 700 # number of demand (read+write) MSHR misses
1110 system.cpu.l2cache.demand_mshr_misses::cpu.data 3411 # number of demand (read+write) MSHR misses
1111 system.cpu.l2cache.demand_mshr_misses::total 4111 # number of demand (read+write) MSHR misses
1112 system.cpu.l2cache.overall_mshr_misses::cpu.inst 700 # number of overall MSHR misses
1113 system.cpu.l2cache.overall_mshr_misses::cpu.data 3411 # number of overall MSHR misses
1114 system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 316848 # number of overall MSHR misses
1115 system.cpu.l2cache.overall_mshr_misses::total 320959 # number of overall MSHR misses
1116 system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 1079223443 # number of HardPFReq MSHR miss cycles
1117 system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 1079223443 # number of HardPFReq MSHR miss cycles
1118 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 45500 # number of UpgradeReq MSHR miss cycles
1119 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 45500 # number of UpgradeReq MSHR miss cycles
1120 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 45646000 # number of ReadExReq MSHR miss cycles
1121 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 45646000 # number of ReadExReq MSHR miss cycles
1122 system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 53848500 # number of ReadCleanReq MSHR miss cycles
1123 system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 53848500 # number of ReadCleanReq MSHR miss cycles
1124 system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 589212500 # number of ReadSharedReq MSHR miss cycles
1125 system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 589212500 # number of ReadSharedReq MSHR miss cycles
1126 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 53848500 # number of demand (read+write) MSHR miss cycles
1127 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 634858500 # number of demand (read+write) MSHR miss cycles
1128 system.cpu.l2cache.demand_mshr_miss_latency::total 688707000 # number of demand (read+write) MSHR miss cycles
1129 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 53848500 # number of overall MSHR miss cycles
1130 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 634858500 # number of overall MSHR miss cycles
1131 system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 1079223443 # number of overall MSHR miss cycles
1132 system.cpu.l2cache.overall_mshr_miss_latency::total 1767930443 # number of overall MSHR miss cycles
1133 system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
1134 system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
1135 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses
1136 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
1137 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001514 # mshr miss rate for ReadExReq accesses
1138 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001514 # mshr miss rate for ReadExReq accesses
1139 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.771775 # mshr miss rate for ReadCleanReq accesses
1140 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.771775 # mshr miss rate for ReadCleanReq accesses
1141 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000585 # mshr miss rate for ReadSharedReq accesses
1142 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000585 # mshr miss rate for ReadSharedReq accesses
1143 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.771775 # mshr miss rate for demand accesses
1144 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.000623 # mshr miss rate for demand accesses
1145 system.cpu.l2cache.demand_mshr_miss_rate::total 0.000751 # mshr miss rate for demand accesses
1146 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.771775 # mshr miss rate for overall accesses
1147 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.000623 # mshr miss rate for overall accesses
1148 system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses
1149 system.cpu.l2cache.overall_mshr_miss_rate::total 0.058654 # mshr miss rate for overall accesses
1150 system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3406.123577 # average HardPFReq mshr miss latency
1151 system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 3406.123577 # average HardPFReq mshr miss latency
1152 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15166.666667 # average UpgradeReq mshr miss latency
1153 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15166.666667 # average UpgradeReq mshr miss latency
1154 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 133078.717201 # average ReadExReq mshr miss latency
1155 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 133078.717201 # average ReadExReq mshr miss latency
1156 system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 76926.428571 # average ReadCleanReq mshr miss latency
1157 system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 76926.428571 # average ReadCleanReq mshr miss latency
1158 system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 192051.010430 # average ReadSharedReq mshr miss latency
1159 system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 192051.010430 # average ReadSharedReq mshr miss latency
1160 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 76926.428571 # average overall mshr miss latency
1161 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 186120.932278 # average overall mshr miss latency
1162 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 167527.852104 # average overall mshr miss latency
1163 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 76926.428571 # average overall mshr miss latency
1164 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 186120.932278 # average overall mshr miss latency
1165 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3406.123577 # average overall mshr miss latency
1166 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 5508.275023 # average overall mshr miss latency
1167 system.cpu.toL2Bus.snoop_filter.tot_requests 10943112 # Total number of requests made to the snoop filter.
1168 system.cpu.toL2Bus.snoop_filter.hit_single_requests 5471085 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1169 system.cpu.toL2Bus.snoop_filter.hit_multi_requests 2875 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1170 system.cpu.toL2Bus.snoop_filter.tot_snoops 302425 # Total number of snoops made to the snoop filter.
1171 system.cpu.toL2Bus.snoop_filter.hit_single_snoops 302424 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1172 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
1173 system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states
1174 system.cpu.toL2Bus.trans_dist::ReadResp 5245519 # Transaction distribution
1175 system.cpu.toL2Bus.trans_dist::WritebackDirty 5457385 # Transaction distribution
1176 system.cpu.toL2Bus.trans_dist::WritebackClean 13788 # Transaction distribution
1177 system.cpu.toL2Bus.trans_dist::CleanEvict 36 # Transaction distribution
1178 system.cpu.toL2Bus.trans_dist::HardPFReq 318720 # Transaction distribution
1179 system.cpu.toL2Bus.trans_dist::HardPFResp 4 # Transaction distribution
1180 system.cpu.toL2Bus.trans_dist::UpgradeReq 3 # Transaction distribution
1181 system.cpu.toL2Bus.trans_dist::UpgradeResp 3 # Transaction distribution
1182 system.cpu.toL2Bus.trans_dist::ReadExReq 226520 # Transaction distribution
1183 system.cpu.toL2Bus.trans_dist::ReadExResp 226520 # Transaction distribution
1184 system.cpu.toL2Bus.trans_dist::ReadCleanReq 907 # Transaction distribution
1185 system.cpu.toL2Bus.trans_dist::ReadSharedReq 5244613 # Transaction distribution
1186 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2261 # Packet count per connected master and slave (bytes)
1187 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 16412897 # Packet count per connected master and slave (bytes)
1188 system.cpu.toL2Bus.pkt_count::total 16415158 # Packet count per connected master and slave (bytes)
1189 system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 86656 # Cumulative packet size per connected master and slave (bytes)
1190 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 700272512 # Cumulative packet size per connected master and slave (bytes)
1191 system.cpu.toL2Bus.pkt_size::total 700359168 # Cumulative packet size per connected master and slave (bytes)
1192 system.cpu.toL2Bus.snoops 318864 # Total snoops (count)
1193 system.cpu.toL2Bus.snoopTraffic 6912 # Total snoop traffic (bytes)
1194 system.cpu.toL2Bus.snoop_fanout::samples 5790903 # Request fanout histogram
1195 system.cpu.toL2Bus.snoop_fanout::mean 0.052723 # Request fanout histogram
1196 system.cpu.toL2Bus.snoop_fanout::stdev 0.223481 # Request fanout histogram
1197 system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1198 system.cpu.toL2Bus.snoop_fanout::0 5485590 94.73% 94.73% # Request fanout histogram
1199 system.cpu.toL2Bus.snoop_fanout::1 305312 5.27% 100.00% # Request fanout histogram
1200 system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram
1201 system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1202 system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
1203 system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
1204 system.cpu.toL2Bus.snoop_fanout::total 5790903 # Request fanout histogram
1205 system.cpu.toL2Bus.reqLayer0.occupancy 10942625015 # Layer occupancy (ticks)
1206 system.cpu.toL2Bus.reqLayer0.utilization 18.6 # Layer utilization (%)
1207 system.cpu.toL2Bus.snoopLayer0.occupancy 6019 # Layer occupancy (ticks)
1208 system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
1209 system.cpu.toL2Bus.respLayer0.occupancy 1360996 # Layer occupancy (ticks)
1210 system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
1211 system.cpu.toL2Bus.respLayer1.occupancy 8206704493 # Layer occupancy (ticks)
1212 system.cpu.toL2Bus.respLayer1.utilization 14.0 # Layer utilization (%)
1213 system.membus.snoop_filter.tot_requests 18677 # Total number of requests made to the snoop filter.
1214 system.membus.snoop_filter.hit_single_requests 3023 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1215 system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1216 system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
1217 system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1218 system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
1219 system.membus.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states
1220 system.membus.trans_dist::ReadResp 18190 # Transaction distribution
1221 system.membus.trans_dist::WritebackDirty 104 # Transaction distribution
1222 system.membus.trans_dist::CleanEvict 36 # Transaction distribution
1223 system.membus.trans_dist::UpgradeReq 4 # Transaction distribution
1224 system.membus.trans_dist::ReadExReq 342 # Transaction distribution
1225 system.membus.trans_dist::ReadExResp 342 # Transaction distribution
1226 system.membus.trans_dist::ReadSharedReq 18191 # Transaction distribution
1227 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 37209 # Packet count per connected master and slave (bytes)
1228 system.membus.pkt_count::total 37209 # Packet count per connected master and slave (bytes)
1229 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1192704 # Cumulative packet size per connected master and slave (bytes)
1230 system.membus.pkt_size::total 1192704 # Cumulative packet size per connected master and slave (bytes)
1231 system.membus.snoops 0 # Total snoops (count)
1232 system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
1233 system.membus.snoop_fanout::samples 18537 # Request fanout histogram
1234 system.membus.snoop_fanout::mean 0 # Request fanout histogram
1235 system.membus.snoop_fanout::stdev 0 # Request fanout histogram
1236 system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1237 system.membus.snoop_fanout::0 18537 100.00% 100.00% # Request fanout histogram
1238 system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
1239 system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1240 system.membus.snoop_fanout::min_value 0 # Request fanout histogram
1241 system.membus.snoop_fanout::max_value 0 # Request fanout histogram
1242 system.membus.snoop_fanout::total 18537 # Request fanout histogram
1243 system.membus.reqLayer0.occupancy 29625930 # Layer occupancy (ticks)
1244 system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
1245 system.membus.respLayer1.occupancy 97326818 # Layer occupancy (ticks)
1246 system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
1248 ---------- End Simulation Statistics ----------
projects / gem5.git / blob