2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.054141 # Number of seconds simulated
4 sim_ticks 54141000000 # Number of ticks simulated
5 final_tick 54141000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 2068738 # Simulator instruction rate (inst/s)
8 host_op_rate 2079040 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 1236208278 # Simulator tick rate (ticks/s)
10 host_mem_usage 428768 # Number of bytes of host memory used
11 host_seconds 43.80 # Real time elapsed on the host
12 sim_insts 90602407 # Number of instructions simulated
13 sim_ops 91053638 # Number of ops (including micro ops) simulated
14 system.voltage_domain.voltage 1 # Voltage in Volts
15 system.clk_domain.clock 1000 # Clock period in ticks
16 system.physmem.bytes_read::cpu.inst 431323080 # Number of bytes read from this memory
17 system.physmem.bytes_read::cpu.data 90016598 # Number of bytes read from this memory
18 system.physmem.bytes_read::total 521339678 # Number of bytes read from this memory
19 system.physmem.bytes_inst_read::cpu.inst 431323080 # Number of instructions bytes read from this memory
20 system.physmem.bytes_inst_read::total 431323080 # Number of instructions bytes read from this memory
21 system.physmem.bytes_written::cpu.data 18908138 # Number of bytes written to this memory
22 system.physmem.bytes_written::total 18908138 # Number of bytes written to this memory
23 system.physmem.num_reads::cpu.inst 107830770 # Number of read requests responded to by this memory
24 system.physmem.num_reads::cpu.data 22461532 # Number of read requests responded to by this memory
25 system.physmem.num_reads::total 130292302 # Number of read requests responded to by this memory
26 system.physmem.num_writes::cpu.data 4738868 # Number of write requests responded to by this memory
27 system.physmem.num_writes::total 4738868 # Number of write requests responded to by this memory
28 system.physmem.bw_read::cpu.inst 7966662603 # Total read bandwidth from this memory (bytes/s)
29 system.physmem.bw_read::cpu.data 1662632718 # Total read bandwidth from this memory (bytes/s)
30 system.physmem.bw_read::total 9629295321 # Total read bandwidth from this memory (bytes/s)
31 system.physmem.bw_inst_read::cpu.inst 7966662603 # Instruction read bandwidth from this memory (bytes/s)
32 system.physmem.bw_inst_read::total 7966662603 # Instruction read bandwidth from this memory (bytes/s)
33 system.physmem.bw_write::cpu.data 349238802 # Write bandwidth from this memory (bytes/s)
34 system.physmem.bw_write::total 349238802 # Write bandwidth from this memory (bytes/s)
35 system.physmem.bw_total::cpu.inst 7966662603 # Total bandwidth to/from this memory (bytes/s)
36 system.physmem.bw_total::cpu.data 2011871521 # Total bandwidth to/from this memory (bytes/s)
37 system.physmem.bw_total::total 9978534124 # Total bandwidth to/from this memory (bytes/s)
38 system.membus.trans_dist::ReadReq 130287905 # Transaction distribution
39 system.membus.trans_dist::ReadResp 130291792 # Transaction distribution
40 system.membus.trans_dist::WriteReq 4734981 # Transaction distribution
41 system.membus.trans_dist::WriteResp 4734981 # Transaction distribution
42 system.membus.trans_dist::SoftPFReq 510 # Transaction distribution
43 system.membus.trans_dist::SoftPFResp 510 # Transaction distribution
44 system.membus.trans_dist::LoadLockedReq 3887 # Transaction distribution
45 system.membus.trans_dist::StoreCondReq 3887 # Transaction distribution
46 system.membus.trans_dist::StoreCondResp 3887 # Transaction distribution
47 system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 215661540 # Packet count per connected master and slave (bytes)
48 system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 54400800 # Packet count per connected master and slave (bytes)
49 system.membus.pkt_count::total 270062340 # Packet count per connected master and slave (bytes)
50 system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 431323080 # Cumulative packet size per connected master and slave (bytes)
51 system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 108924736 # Cumulative packet size per connected master and slave (bytes)
52 system.membus.pkt_size::total 540247816 # Cumulative packet size per connected master and slave (bytes)
53 system.membus.snoops 0 # Total snoops (count)
54 system.membus.snoop_fanout::samples 135031170 # Request fanout histogram
55 system.membus.snoop_fanout::mean 4.798562 # Request fanout histogram
56 system.membus.snoop_fanout::stdev 0.401074 # Request fanout histogram
57 system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
58 system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
59 system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
60 system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
61 system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
62 system.membus.snoop_fanout::4 27200400 20.14% 20.14% # Request fanout histogram
63 system.membus.snoop_fanout::5 107830770 79.86% 100.00% # Request fanout histogram
64 system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
65 system.membus.snoop_fanout::min_value 4 # Request fanout histogram
66 system.membus.snoop_fanout::max_value 5 # Request fanout histogram
67 system.membus.snoop_fanout::total 135031170 # Request fanout histogram
68 system.cpu_clk_domain.clock 500 # Clock period in ticks
69 system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
70 system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
71 system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
72 system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
73 system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
74 system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
75 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
76 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
77 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
78 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
79 system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
80 system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
81 system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
82 system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
83 system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
84 system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
85 system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
86 system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
87 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
88 system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
89 system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
90 system.cpu.dtb.inst_hits 0 # ITB inst hits
91 system.cpu.dtb.inst_misses 0 # ITB inst misses
92 system.cpu.dtb.read_hits 0 # DTB read hits
93 system.cpu.dtb.read_misses 0 # DTB read misses
94 system.cpu.dtb.write_hits 0 # DTB write hits
95 system.cpu.dtb.write_misses 0 # DTB write misses
96 system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
97 system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
98 system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
99 system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
100 system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
101 system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
102 system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
103 system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
104 system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
105 system.cpu.dtb.read_accesses 0 # DTB read accesses
106 system.cpu.dtb.write_accesses 0 # DTB write accesses
107 system.cpu.dtb.inst_accesses 0 # ITB inst accesses
108 system.cpu.dtb.hits 0 # DTB hits
109 system.cpu.dtb.misses 0 # DTB misses
110 system.cpu.dtb.accesses 0 # DTB accesses
111 system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
112 system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
113 system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
114 system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
115 system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
116 system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
117 system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
118 system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
119 system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
120 system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
121 system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
122 system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
123 system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
124 system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
125 system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
126 system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
127 system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
128 system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
129 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
130 system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
131 system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
132 system.cpu.itb.inst_hits 0 # ITB inst hits
133 system.cpu.itb.inst_misses 0 # ITB inst misses
134 system.cpu.itb.read_hits 0 # DTB read hits
135 system.cpu.itb.read_misses 0 # DTB read misses
136 system.cpu.itb.write_hits 0 # DTB write hits
137 system.cpu.itb.write_misses 0 # DTB write misses
138 system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
139 system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
140 system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
141 system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
142 system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
143 system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
144 system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
145 system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
146 system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
147 system.cpu.itb.read_accesses 0 # DTB read accesses
148 system.cpu.itb.write_accesses 0 # DTB write accesses
149 system.cpu.itb.inst_accesses 0 # ITB inst accesses
150 system.cpu.itb.hits 0 # DTB hits
151 system.cpu.itb.misses 0 # DTB misses
152 system.cpu.itb.accesses 0 # DTB accesses
153 system.cpu.workload.num_syscalls 442 # Number of system calls
154 system.cpu.numCycles 108282001 # number of cpu cycles simulated
155 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
156 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
157 system.cpu.committedInsts 90602407 # Number of instructions committed
158 system.cpu.committedOps 91053638 # Number of ops (including micro ops) committed
159 system.cpu.num_int_alu_accesses 72326352 # Number of integer alu accesses
160 system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses
161 system.cpu.num_func_calls 112245 # number of times a function call or return occured
162 system.cpu.num_conditional_control_insts 15520157 # number of instructions that are conditional controls
163 system.cpu.num_int_insts 72326352 # number of integer instructions
164 system.cpu.num_fp_insts 48 # number of float instructions
165 system.cpu.num_int_register_reads 124257699 # number of times the integer registers were read
166 system.cpu.num_int_register_writes 52782988 # number of times the integer registers were written
167 system.cpu.num_fp_register_reads 54 # number of times the floating registers were read
168 system.cpu.num_fp_register_writes 30 # number of times the floating registers were written
169 system.cpu.num_cc_register_reads 271814240 # number of times the CC registers were read
170 system.cpu.num_cc_register_writes 53956115 # number of times the CC registers were written
171 system.cpu.num_mem_refs 27220755 # number of memory refs
172 system.cpu.num_load_insts 22475911 # Number of load instructions
173 system.cpu.num_store_insts 4744844 # Number of store instructions
174 system.cpu.num_idle_cycles 0 # Number of idle cycles
175 system.cpu.num_busy_cycles 108282001 # Number of busy cycles
176 system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
177 system.cpu.idle_fraction 0 # Percentage of idle cycles
178 system.cpu.Branches 18732304 # Number of branches fetched
179 system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
180 system.cpu.op_class::IntAlu 63822828 70.09% 70.09% # Class of executed instruction
181 system.cpu.op_class::IntMult 10474 0.01% 70.10% # Class of executed instruction
182 system.cpu.op_class::IntDiv 0 0.00% 70.10% # Class of executed instruction
183 system.cpu.op_class::FloatAdd 0 0.00% 70.10% # Class of executed instruction
184 system.cpu.op_class::FloatCmp 0 0.00% 70.10% # Class of executed instruction
185 system.cpu.op_class::FloatCvt 0 0.00% 70.10% # Class of executed instruction
186 system.cpu.op_class::FloatMult 0 0.00% 70.10% # Class of executed instruction
187 system.cpu.op_class::FloatDiv 0 0.00% 70.10% # Class of executed instruction
188 system.cpu.op_class::FloatSqrt 0 0.00% 70.10% # Class of executed instruction
189 system.cpu.op_class::SimdAdd 0 0.00% 70.10% # Class of executed instruction
190 system.cpu.op_class::SimdAddAcc 0 0.00% 70.10% # Class of executed instruction
191 system.cpu.op_class::SimdAlu 0 0.00% 70.10% # Class of executed instruction
192 system.cpu.op_class::SimdCmp 0 0.00% 70.10% # Class of executed instruction
193 system.cpu.op_class::SimdCvt 0 0.00% 70.10% # Class of executed instruction
194 system.cpu.op_class::SimdMisc 0 0.00% 70.10% # Class of executed instruction
195 system.cpu.op_class::SimdMult 0 0.00% 70.10% # Class of executed instruction
196 system.cpu.op_class::SimdMultAcc 0 0.00% 70.10% # Class of executed instruction
197 system.cpu.op_class::SimdShift 0 0.00% 70.10% # Class of executed instruction
198 system.cpu.op_class::SimdShiftAcc 0 0.00% 70.10% # Class of executed instruction
199 system.cpu.op_class::SimdSqrt 0 0.00% 70.10% # Class of executed instruction
200 system.cpu.op_class::SimdFloatAdd 0 0.00% 70.10% # Class of executed instruction
201 system.cpu.op_class::SimdFloatAlu 0 0.00% 70.10% # Class of executed instruction
202 system.cpu.op_class::SimdFloatCmp 0 0.00% 70.10% # Class of executed instruction
203 system.cpu.op_class::SimdFloatCvt 6 0.00% 70.10% # Class of executed instruction
204 system.cpu.op_class::SimdFloatDiv 0 0.00% 70.10% # Class of executed instruction
205 system.cpu.op_class::SimdFloatMisc 15 0.00% 70.10% # Class of executed instruction
206 system.cpu.op_class::SimdFloatMult 0 0.00% 70.10% # Class of executed instruction
207 system.cpu.op_class::SimdFloatMultAcc 2 0.00% 70.10% # Class of executed instruction
208 system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.10% # Class of executed instruction
209 system.cpu.op_class::MemRead 22475911 24.68% 94.79% # Class of executed instruction
210 system.cpu.op_class::MemWrite 4744844 5.21% 100.00% # Class of executed instruction
211 system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
212 system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
213 system.cpu.op_class::total 91054080 # Class of executed instruction
215 ---------- End Simulation Statistics ----------
projects / gem5.git / blob