tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini

   1 [root]
   2 type=Root
   3 children=system
   4 eventq_index=0
   5 full_system=false
   6 sim_quantum=0
   7 time_sync_enable=false
   8 time_sync_period=100000000000
   9 time_sync_spin_threshold=100000000
  10
  11 [system]
  12 type=System
  13 children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
  14 boot_osflags=a
  15 cache_line_size=64
  16 clk_domain=system.clk_domain
  17 eventq_index=0
  18 init_param=0
  19 kernel=
  20 kernel_addr_check=true
  21 load_addr_mask=1099511627775
  22 load_offset=0
  23 mem_mode=timing
  24 mem_ranges=
  25 memories=system.physmem
  26 num_work_ids=16
  27 readfile=
  28 symbolfile=
  29 work_begin_ckpt_count=0
  30 work_begin_cpu_id_exit=-1
  31 work_begin_exit_count=0
  32 work_cpus_ckpt_count=0
  33 work_end_ckpt_count=0
  34 work_end_exit_count=0
  35 work_item_id=-1
  36 system_port=system.membus.slave[0]
  37
  38 [system.clk_domain]
  39 type=SrcClockDomain
  40 clock=1000
  41 domain_id=-1
  42 eventq_index=0
  43 init_perf_level=0
  44 voltage_domain=system.voltage_domain
  45
  46 [system.cpu]
  47 type=TimingSimpleCPU
  48 children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
  49 branchPred=Null
  50 checker=Null
  51 clk_domain=system.cpu_clk_domain
  52 cpu_id=0
  53 do_checkpoint_insts=true
  54 do_quiesce=true
  55 do_statistics_insts=true
  56 dtb=system.cpu.dtb
  57 eventq_index=0
  58 function_trace=false
  59 function_trace_start=0
  60 interrupts=system.cpu.interrupts
  61 isa=system.cpu.isa
  62 itb=system.cpu.itb
  63 max_insts_all_threads=0
  64 max_insts_any_thread=0
  65 max_loads_all_threads=0
  66 max_loads_any_thread=0
  67 numThreads=1
  68 profile=0
  69 progress_interval=0
  70 simpoint_start_insts=
  71 socket_id=0
  72 switched_out=false
  73 system=system
  74 tracer=system.cpu.tracer
  75 workload=system.cpu.workload
  76 dcache_port=system.cpu.dcache.cpu_side
  77 icache_port=system.cpu.icache.cpu_side
  78
  79 [system.cpu.dcache]
  80 type=BaseCache
  81 children=tags
  82 addr_ranges=0:18446744073709551615
  83 assoc=2
  84 clk_domain=system.cpu_clk_domain
  85 eventq_index=0
  86 forward_snoops=true
  87 hit_latency=2
  88 is_top_level=true
  89 max_miss_count=0
  90 mshrs=4
  91 prefetch_on_access=false
  92 prefetcher=Null
  93 response_latency=2
  94 sequential_access=false
  95 size=262144
  96 system=system
  97 tags=system.cpu.dcache.tags
  98 tgts_per_mshr=20
  99 two_queue=false
 100 write_buffers=8
 101 cpu_side=system.cpu.dcache_port
 102 mem_side=system.cpu.toL2Bus.slave[1]
 103
 104 [system.cpu.dcache.tags]
 105 type=LRU
 106 assoc=2
 107 block_size=64
 108 clk_domain=system.cpu_clk_domain
 109 eventq_index=0
 110 hit_latency=2
 111 sequential_access=false
 112 size=262144
 113
 114 [system.cpu.dtb]
 115 type=SparcTLB
 116 eventq_index=0
 117 size=64
 118
 119 [system.cpu.icache]
 120 type=BaseCache
 121 children=tags
 122 addr_ranges=0:18446744073709551615
 123 assoc=2
 124 clk_domain=system.cpu_clk_domain
 125 eventq_index=0
 126 forward_snoops=true
 127 hit_latency=2
 128 is_top_level=true
 129 max_miss_count=0
 130 mshrs=4
 131 prefetch_on_access=false
 132 prefetcher=Null
 133 response_latency=2
 134 sequential_access=false
 135 size=131072
 136 system=system
 137 tags=system.cpu.icache.tags
 138 tgts_per_mshr=20
 139 two_queue=false
 140 write_buffers=8
 141 cpu_side=system.cpu.icache_port
 142 mem_side=system.cpu.toL2Bus.slave[0]
 143
 144 [system.cpu.icache.tags]
 145 type=LRU
 146 assoc=2
 147 block_size=64
 148 clk_domain=system.cpu_clk_domain
 149 eventq_index=0
 150 hit_latency=2
 151 sequential_access=false
 152 size=131072
 153
 154 [system.cpu.interrupts]
 155 type=SparcInterrupts
 156 eventq_index=0
 157
 158 [system.cpu.isa]
 159 type=SparcISA
 160 eventq_index=0
 161
 162 [system.cpu.itb]
 163 type=SparcTLB
 164 eventq_index=0
 165 size=64
 166
 167 [system.cpu.l2cache]
 168 type=BaseCache
 169 children=tags
 170 addr_ranges=0:18446744073709551615
 171 assoc=8
 172 clk_domain=system.cpu_clk_domain
 173 eventq_index=0
 174 forward_snoops=true
 175 hit_latency=20
 176 is_top_level=false
 177 max_miss_count=0
 178 mshrs=20
 179 prefetch_on_access=false
 180 prefetcher=Null
 181 response_latency=20
 182 sequential_access=false
 183 size=2097152
 184 system=system
 185 tags=system.cpu.l2cache.tags
 186 tgts_per_mshr=12
 187 two_queue=false
 188 write_buffers=8
 189 cpu_side=system.cpu.toL2Bus.master[0]
 190 mem_side=system.membus.slave[1]
 191
 192 [system.cpu.l2cache.tags]
 193 type=LRU
 194 assoc=8
 195 block_size=64
 196 clk_domain=system.cpu_clk_domain
 197 eventq_index=0
 198 hit_latency=20
 199 sequential_access=false
 200 size=2097152
 201
 202 [system.cpu.toL2Bus]
 203 type=CoherentBus
 204 clk_domain=system.cpu_clk_domain
 205 eventq_index=0
 206 header_cycles=1
 207 system=system
 208 use_default_range=false
 209 width=32
 210 master=system.cpu.l2cache.cpu_side
 211 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
 212
 213 [system.cpu.tracer]
 214 type=ExeTracer
 215 eventq_index=0
 216
 217 [system.cpu.workload]
 218 type=LiveProcess
 219 cmd=mcf mcf.in
 220 cwd=build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-timing
 221 egid=100
 222 env=
 223 errout=cerr
 224 euid=100
 225 eventq_index=0
 226 executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/sparc/linux/mcf
 227 gid=100
 228 input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
 229 max_stack_size=67108864
 230 output=cout
 231 pid=100
 232 ppid=99
 233 simpoint=55300000000
 234 system=system
 235 uid=100
 236
 237 [system.cpu_clk_domain]
 238 type=SrcClockDomain
 239 clock=500
 240 domain_id=-1
 241 eventq_index=0
 242 init_perf_level=0
 243 voltage_domain=system.voltage_domain
 244
 245 [system.dvfs_handler]
 246 type=DVFSHandler
 247 domains=
 248 enable=false
 249 eventq_index=0
 250 sys_clk_domain=system.clk_domain
 251 transition_latency=100000000
 252
 253 [system.membus]
 254 type=CoherentBus
 255 clk_domain=system.clk_domain
 256 eventq_index=0
 257 header_cycles=1
 258 system=system
 259 use_default_range=false
 260 width=8
 261 master=system.physmem.port
 262 slave=system.system_port system.cpu.l2cache.mem_side
 263
 264 [system.physmem]
 265 type=SimpleMemory
 266 bandwidth=73.000000
 267 clk_domain=system.clk_domain
 268 conf_table_reported=true
 269 eventq_index=0
 270 in_addr_map=true
 271 latency=30000
 272 latency_var=0
 273 null=false
 274 range=0:268435455
 275 port=system.membus.master[0]
 276
 277 [system.voltage_domain]
 278 type=VoltageDomain
 279 eventq_index=0
 280 voltage=1.000000
 281