8 time_sync_period=100000000000
9 time_sync_spin_threshold=100000000
13 children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
16 clk_domain=system.clk_domain
20 kernel_addr_check=true
21 load_addr_mask=1099511627775
25 memories=system.physmem
29 work_begin_ckpt_count=0
30 work_begin_cpu_id_exit=-1
31 work_begin_exit_count=0
32 work_cpus_ckpt_count=0
36 system_port=system.membus.slave[0]
44 voltage_domain=system.voltage_domain
48 children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
51 clk_domain=system.cpu_clk_domain
53 do_checkpoint_insts=true
55 do_statistics_insts=true
59 function_trace_start=0
60 interrupts=system.cpu.interrupts
63 max_insts_all_threads=0
64 max_insts_any_thread=0
65 max_loads_all_threads=0
66 max_loads_any_thread=0
74 tracer=system.cpu.tracer
75 workload=system.cpu.workload
76 dcache_port=system.cpu.dcache.cpu_side
77 icache_port=system.cpu.icache.cpu_side
82 addr_ranges=0:18446744073709551615
84 clk_domain=system.cpu_clk_domain
91 prefetch_on_access=false
94 sequential_access=false
97 tags=system.cpu.dcache.tags
101 cpu_side=system.cpu.dcache_port
102 mem_side=system.cpu.toL2Bus.slave[1]
104 [system.cpu.dcache.tags]
108 clk_domain=system.cpu_clk_domain
111 sequential_access=false
122 addr_ranges=0:18446744073709551615
124 clk_domain=system.cpu_clk_domain
131 prefetch_on_access=false
134 sequential_access=false
137 tags=system.cpu.icache.tags
141 cpu_side=system.cpu.icache_port
142 mem_side=system.cpu.toL2Bus.slave[0]
144 [system.cpu.icache.tags]
148 clk_domain=system.cpu_clk_domain
151 sequential_access=false
154 [system.cpu.interrupts]
170 addr_ranges=0:18446744073709551615
172 clk_domain=system.cpu_clk_domain
179 prefetch_on_access=false
182 sequential_access=false
185 tags=system.cpu.l2cache.tags
189 cpu_side=system.cpu.toL2Bus.master[0]
190 mem_side=system.membus.slave[1]
192 [system.cpu.l2cache.tags]
196 clk_domain=system.cpu_clk_domain
199 sequential_access=false
204 clk_domain=system.cpu_clk_domain
209 use_default_range=false
211 master=system.cpu.l2cache.cpu_side
212 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
218 [system.cpu.workload]
221 cwd=build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-timing
227 executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/sparc/linux/mcf
229 input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
230 max_stack_size=67108864
239 [system.cpu_clk_domain]
245 voltage_domain=system.voltage_domain
247 [system.dvfs_handler]
252 sys_clk_domain=system.clk_domain
253 transition_latency=100000000
257 clk_domain=system.clk_domain
262 use_default_range=false
264 master=system.physmem.port
265 slave=system.system_port system.cpu.l2cache.mem_side
270 clk_domain=system.clk_domain
271 conf_table_reported=true
278 port=system.membus.master[0]
280 [system.voltage_domain]