2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.362431 # Number of seconds simulated
4 sim_ticks 362430887000 # Number of ticks simulated
5 final_tick 362430887000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 1267775 # Simulator instruction rate (inst/s)
8 host_op_rate 1267827 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 1884467398 # Simulator tick rate (ticks/s)
10 host_mem_usage 355400 # Number of bytes of host memory used
11 host_seconds 192.33 # Real time elapsed on the host
12 sim_insts 243825163 # Number of instructions simulated
13 sim_ops 243835278 # Number of ops (including micro ops) simulated
14 system.physmem.bytes_read::cpu.inst 56256 # Number of bytes read from this memory
15 system.physmem.bytes_read::cpu.data 945216 # Number of bytes read from this memory
16 system.physmem.bytes_read::total 1001472 # Number of bytes read from this memory
17 system.physmem.bytes_inst_read::cpu.inst 56256 # Number of instructions bytes read from this memory
18 system.physmem.bytes_inst_read::total 56256 # Number of instructions bytes read from this memory
19 system.physmem.bytes_written::writebacks 2560 # Number of bytes written to this memory
20 system.physmem.bytes_written::total 2560 # Number of bytes written to this memory
21 system.physmem.num_reads::cpu.inst 879 # Number of read requests responded to by this memory
22 system.physmem.num_reads::cpu.data 14769 # Number of read requests responded to by this memory
23 system.physmem.num_reads::total 15648 # Number of read requests responded to by this memory
24 system.physmem.num_writes::writebacks 40 # Number of write requests responded to by this memory
25 system.physmem.num_writes::total 40 # Number of write requests responded to by this memory
26 system.physmem.bw_read::cpu.inst 155219 # Total read bandwidth from this memory (bytes/s)
27 system.physmem.bw_read::cpu.data 2607990 # Total read bandwidth from this memory (bytes/s)
28 system.physmem.bw_read::total 2763208 # Total read bandwidth from this memory (bytes/s)
29 system.physmem.bw_inst_read::cpu.inst 155219 # Instruction read bandwidth from this memory (bytes/s)
30 system.physmem.bw_inst_read::total 155219 # Instruction read bandwidth from this memory (bytes/s)
31 system.physmem.bw_write::writebacks 7063 # Write bandwidth from this memory (bytes/s)
32 system.physmem.bw_write::total 7063 # Write bandwidth from this memory (bytes/s)
33 system.physmem.bw_total::writebacks 7063 # Total bandwidth to/from this memory (bytes/s)
34 system.physmem.bw_total::cpu.inst 155219 # Total bandwidth to/from this memory (bytes/s)
35 system.physmem.bw_total::cpu.data 2607990 # Total bandwidth to/from this memory (bytes/s)
36 system.physmem.bw_total::total 2770272 # Total bandwidth to/from this memory (bytes/s)
37 system.cpu.workload.num_syscalls 443 # Number of system calls
38 system.cpu.numCycles 724861774 # number of cpu cycles simulated
39 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
40 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
41 system.cpu.committedInsts 243825163 # Number of instructions committed
42 system.cpu.committedOps 243835278 # Number of ops (including micro ops) committed
43 system.cpu.num_int_alu_accesses 194726506 # Number of integer alu accesses
44 system.cpu.num_fp_alu_accesses 11630 # Number of float alu accesses
45 system.cpu.num_func_calls 4252956 # number of times a function call or return occured
46 system.cpu.num_conditional_control_insts 18619960 # number of instructions that are conditional controls
47 system.cpu.num_int_insts 194726506 # number of integer instructions
48 system.cpu.num_fp_insts 11630 # number of float instructions
49 system.cpu.num_int_register_reads 456819010 # number of times the integer registers were read
50 system.cpu.num_int_register_writes 215451566 # number of times the integer registers were written
51 system.cpu.num_fp_register_reads 23256 # number of times the floating registers were read
52 system.cpu.num_fp_register_writes 90 # number of times the floating registers were written
53 system.cpu.num_mem_refs 105711442 # number of memory refs
54 system.cpu.num_load_insts 82803522 # Number of load instructions
55 system.cpu.num_store_insts 22907920 # Number of store instructions
56 system.cpu.num_idle_cycles 0 # Number of idle cycles
57 system.cpu.num_busy_cycles 724861774 # Number of busy cycles
58 system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
59 system.cpu.idle_fraction 0 # Percentage of idle cycles
60 system.cpu.icache.replacements 25 # number of replacements
61 system.cpu.icache.tagsinuse 725.567632 # Cycle average of tags in use
62 system.cpu.icache.total_refs 244420630 # Total number of references to valid blocks.
63 system.cpu.icache.sampled_refs 882 # Sample count of references to valid blocks.
64 system.cpu.icache.avg_refs 277120.895692 # Average number of references to valid blocks.
65 system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
66 system.cpu.icache.occ_blocks::cpu.inst 725.567632 # Average occupied blocks per requestor
67 system.cpu.icache.occ_percent::cpu.inst 0.354281 # Average percentage of cache occupancy
68 system.cpu.icache.occ_percent::total 0.354281 # Average percentage of cache occupancy
69 system.cpu.icache.ReadReq_hits::cpu.inst 244420630 # number of ReadReq hits
70 system.cpu.icache.ReadReq_hits::total 244420630 # number of ReadReq hits
71 system.cpu.icache.demand_hits::cpu.inst 244420630 # number of demand (read+write) hits
72 system.cpu.icache.demand_hits::total 244420630 # number of demand (read+write) hits
73 system.cpu.icache.overall_hits::cpu.inst 244420630 # number of overall hits
74 system.cpu.icache.overall_hits::total 244420630 # number of overall hits
75 system.cpu.icache.ReadReq_misses::cpu.inst 882 # number of ReadReq misses
76 system.cpu.icache.ReadReq_misses::total 882 # number of ReadReq misses
77 system.cpu.icache.demand_misses::cpu.inst 882 # number of demand (read+write) misses
78 system.cpu.icache.demand_misses::total 882 # number of demand (read+write) misses
79 system.cpu.icache.overall_misses::cpu.inst 882 # number of overall misses
80 system.cpu.icache.overall_misses::total 882 # number of overall misses
81 system.cpu.icache.ReadReq_miss_latency::cpu.inst 49266000 # number of ReadReq miss cycles
82 system.cpu.icache.ReadReq_miss_latency::total 49266000 # number of ReadReq miss cycles
83 system.cpu.icache.demand_miss_latency::cpu.inst 49266000 # number of demand (read+write) miss cycles
84 system.cpu.icache.demand_miss_latency::total 49266000 # number of demand (read+write) miss cycles
85 system.cpu.icache.overall_miss_latency::cpu.inst 49266000 # number of overall miss cycles
86 system.cpu.icache.overall_miss_latency::total 49266000 # number of overall miss cycles
87 system.cpu.icache.ReadReq_accesses::cpu.inst 244421512 # number of ReadReq accesses(hits+misses)
88 system.cpu.icache.ReadReq_accesses::total 244421512 # number of ReadReq accesses(hits+misses)
89 system.cpu.icache.demand_accesses::cpu.inst 244421512 # number of demand (read+write) accesses
90 system.cpu.icache.demand_accesses::total 244421512 # number of demand (read+write) accesses
91 system.cpu.icache.overall_accesses::cpu.inst 244421512 # number of overall (read+write) accesses
92 system.cpu.icache.overall_accesses::total 244421512 # number of overall (read+write) accesses
93 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses
94 system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses
95 system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses
96 system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses
97 system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses
98 system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses
99 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55857.142857 # average ReadReq miss latency
100 system.cpu.icache.ReadReq_avg_miss_latency::total 55857.142857 # average ReadReq miss latency
101 system.cpu.icache.demand_avg_miss_latency::cpu.inst 55857.142857 # average overall miss latency
102 system.cpu.icache.demand_avg_miss_latency::total 55857.142857 # average overall miss latency
103 system.cpu.icache.overall_avg_miss_latency::cpu.inst 55857.142857 # average overall miss latency
104 system.cpu.icache.overall_avg_miss_latency::total 55857.142857 # average overall miss latency
105 system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
106 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
107 system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
108 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
109 system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
110 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
111 system.cpu.icache.fast_writes 0 # number of fast writes performed
112 system.cpu.icache.cache_copies 0 # number of cache copies performed
113 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 882 # number of ReadReq MSHR misses
114 system.cpu.icache.ReadReq_mshr_misses::total 882 # number of ReadReq MSHR misses
115 system.cpu.icache.demand_mshr_misses::cpu.inst 882 # number of demand (read+write) MSHR misses
116 system.cpu.icache.demand_mshr_misses::total 882 # number of demand (read+write) MSHR misses
117 system.cpu.icache.overall_mshr_misses::cpu.inst 882 # number of overall MSHR misses
118 system.cpu.icache.overall_mshr_misses::total 882 # number of overall MSHR misses
119 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 46620000 # number of ReadReq MSHR miss cycles
120 system.cpu.icache.ReadReq_mshr_miss_latency::total 46620000 # number of ReadReq MSHR miss cycles
121 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 46620000 # number of demand (read+write) MSHR miss cycles
122 system.cpu.icache.demand_mshr_miss_latency::total 46620000 # number of demand (read+write) MSHR miss cycles
123 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 46620000 # number of overall MSHR miss cycles
124 system.cpu.icache.overall_mshr_miss_latency::total 46620000 # number of overall MSHR miss cycles
125 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses
126 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses
127 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses
128 system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses
129 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses
130 system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses
131 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52857.142857 # average ReadReq mshr miss latency
132 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52857.142857 # average ReadReq mshr miss latency
133 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52857.142857 # average overall mshr miss latency
134 system.cpu.icache.demand_avg_mshr_miss_latency::total 52857.142857 # average overall mshr miss latency
135 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52857.142857 # average overall mshr miss latency
136 system.cpu.icache.overall_avg_mshr_miss_latency::total 52857.142857 # average overall mshr miss latency
137 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
138 system.cpu.dcache.replacements 935475 # number of replacements
139 system.cpu.dcache.tagsinuse 3563.824259 # Cycle average of tags in use
140 system.cpu.dcache.total_refs 104186700 # Total number of references to valid blocks.
141 system.cpu.dcache.sampled_refs 939571 # Sample count of references to valid blocks.
142 system.cpu.dcache.avg_refs 110.887522 # Average number of references to valid blocks.
143 system.cpu.dcache.warmup_cycle 134373316000 # Cycle when the warmup percentage was hit.
144 system.cpu.dcache.occ_blocks::cpu.data 3563.824259 # Average occupied blocks per requestor
145 system.cpu.dcache.occ_percent::cpu.data 0.870074 # Average percentage of cache occupancy
146 system.cpu.dcache.occ_percent::total 0.870074 # Average percentage of cache occupancy
147 system.cpu.dcache.ReadReq_hits::cpu.data 81327577 # number of ReadReq hits
148 system.cpu.dcache.ReadReq_hits::total 81327577 # number of ReadReq hits
149 system.cpu.dcache.WriteReq_hits::cpu.data 22855241 # number of WriteReq hits
150 system.cpu.dcache.WriteReq_hits::total 22855241 # number of WriteReq hits
151 system.cpu.dcache.SwapReq_hits::cpu.data 3882 # number of SwapReq hits
152 system.cpu.dcache.SwapReq_hits::total 3882 # number of SwapReq hits
153 system.cpu.dcache.demand_hits::cpu.data 104182818 # number of demand (read+write) hits
154 system.cpu.dcache.demand_hits::total 104182818 # number of demand (read+write) hits
155 system.cpu.dcache.overall_hits::cpu.data 104182818 # number of overall hits
156 system.cpu.dcache.overall_hits::total 104182818 # number of overall hits
157 system.cpu.dcache.ReadReq_misses::cpu.data 892857 # number of ReadReq misses
158 system.cpu.dcache.ReadReq_misses::total 892857 # number of ReadReq misses
159 system.cpu.dcache.WriteReq_misses::cpu.data 46710 # number of WriteReq misses
160 system.cpu.dcache.WriteReq_misses::total 46710 # number of WriteReq misses
161 system.cpu.dcache.SwapReq_misses::cpu.data 4 # number of SwapReq misses
162 system.cpu.dcache.SwapReq_misses::total 4 # number of SwapReq misses
163 system.cpu.dcache.demand_misses::cpu.data 939567 # number of demand (read+write) misses
164 system.cpu.dcache.demand_misses::total 939567 # number of demand (read+write) misses
165 system.cpu.dcache.overall_misses::cpu.data 939567 # number of overall misses
166 system.cpu.dcache.overall_misses::total 939567 # number of overall misses
167 system.cpu.dcache.ReadReq_miss_latency::cpu.data 12508482000 # number of ReadReq miss cycles
168 system.cpu.dcache.ReadReq_miss_latency::total 12508482000 # number of ReadReq miss cycles
169 system.cpu.dcache.WriteReq_miss_latency::cpu.data 1265712000 # number of WriteReq miss cycles
170 system.cpu.dcache.WriteReq_miss_latency::total 1265712000 # number of WriteReq miss cycles
171 system.cpu.dcache.SwapReq_miss_latency::cpu.data 98000 # number of SwapReq miss cycles
172 system.cpu.dcache.SwapReq_miss_latency::total 98000 # number of SwapReq miss cycles
173 system.cpu.dcache.demand_miss_latency::cpu.data 13774194000 # number of demand (read+write) miss cycles
174 system.cpu.dcache.demand_miss_latency::total 13774194000 # number of demand (read+write) miss cycles
175 system.cpu.dcache.overall_miss_latency::cpu.data 13774194000 # number of overall miss cycles
176 system.cpu.dcache.overall_miss_latency::total 13774194000 # number of overall miss cycles
177 system.cpu.dcache.ReadReq_accesses::cpu.data 82220434 # number of ReadReq accesses(hits+misses)
178 system.cpu.dcache.ReadReq_accesses::total 82220434 # number of ReadReq accesses(hits+misses)
179 system.cpu.dcache.WriteReq_accesses::cpu.data 22901951 # number of WriteReq accesses(hits+misses)
180 system.cpu.dcache.WriteReq_accesses::total 22901951 # number of WriteReq accesses(hits+misses)
181 system.cpu.dcache.SwapReq_accesses::cpu.data 3886 # number of SwapReq accesses(hits+misses)
182 system.cpu.dcache.SwapReq_accesses::total 3886 # number of SwapReq accesses(hits+misses)
183 system.cpu.dcache.demand_accesses::cpu.data 105122385 # number of demand (read+write) accesses
184 system.cpu.dcache.demand_accesses::total 105122385 # number of demand (read+write) accesses
185 system.cpu.dcache.overall_accesses::cpu.data 105122385 # number of overall (read+write) accesses
186 system.cpu.dcache.overall_accesses::total 105122385 # number of overall (read+write) accesses
187 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.010859 # miss rate for ReadReq accesses
188 system.cpu.dcache.ReadReq_miss_rate::total 0.010859 # miss rate for ReadReq accesses
189 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002040 # miss rate for WriteReq accesses
190 system.cpu.dcache.WriteReq_miss_rate::total 0.002040 # miss rate for WriteReq accesses
191 system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.001029 # miss rate for SwapReq accesses
192 system.cpu.dcache.SwapReq_miss_rate::total 0.001029 # miss rate for SwapReq accesses
193 system.cpu.dcache.demand_miss_rate::cpu.data 0.008938 # miss rate for demand accesses
194 system.cpu.dcache.demand_miss_rate::total 0.008938 # miss rate for demand accesses
195 system.cpu.dcache.overall_miss_rate::cpu.data 0.008938 # miss rate for overall accesses
196 system.cpu.dcache.overall_miss_rate::total 0.008938 # miss rate for overall accesses
197 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14009.502082 # average ReadReq miss latency
198 system.cpu.dcache.ReadReq_avg_miss_latency::total 14009.502082 # average ReadReq miss latency
199 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27097.238279 # average WriteReq miss latency
200 system.cpu.dcache.WriteReq_avg_miss_latency::total 27097.238279 # average WriteReq miss latency
201 system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 24500 # average SwapReq miss latency
202 system.cpu.dcache.SwapReq_avg_miss_latency::total 24500 # average SwapReq miss latency
203 system.cpu.dcache.demand_avg_miss_latency::cpu.data 14660.150899 # average overall miss latency
204 system.cpu.dcache.demand_avg_miss_latency::total 14660.150899 # average overall miss latency
205 system.cpu.dcache.overall_avg_miss_latency::cpu.data 14660.150899 # average overall miss latency
206 system.cpu.dcache.overall_avg_miss_latency::total 14660.150899 # average overall miss latency
207 system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
208 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
209 system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
210 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
211 system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
212 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
213 system.cpu.dcache.fast_writes 0 # number of fast writes performed
214 system.cpu.dcache.cache_copies 0 # number of cache copies performed
215 system.cpu.dcache.writebacks::writebacks 935237 # number of writebacks
216 system.cpu.dcache.writebacks::total 935237 # number of writebacks
217 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 892857 # number of ReadReq MSHR misses
218 system.cpu.dcache.ReadReq_mshr_misses::total 892857 # number of ReadReq MSHR misses
219 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46710 # number of WriteReq MSHR misses
220 system.cpu.dcache.WriteReq_mshr_misses::total 46710 # number of WriteReq MSHR misses
221 system.cpu.dcache.SwapReq_mshr_misses::cpu.data 4 # number of SwapReq MSHR misses
222 system.cpu.dcache.SwapReq_mshr_misses::total 4 # number of SwapReq MSHR misses
223 system.cpu.dcache.demand_mshr_misses::cpu.data 939567 # number of demand (read+write) MSHR misses
224 system.cpu.dcache.demand_mshr_misses::total 939567 # number of demand (read+write) MSHR misses
225 system.cpu.dcache.overall_mshr_misses::cpu.data 939567 # number of overall MSHR misses
226 system.cpu.dcache.overall_mshr_misses::total 939567 # number of overall MSHR misses
227 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9829911000 # number of ReadReq MSHR miss cycles
228 system.cpu.dcache.ReadReq_mshr_miss_latency::total 9829911000 # number of ReadReq MSHR miss cycles
229 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1125582000 # number of WriteReq MSHR miss cycles
230 system.cpu.dcache.WriteReq_mshr_miss_latency::total 1125582000 # number of WriteReq MSHR miss cycles
231 system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 86000 # number of SwapReq MSHR miss cycles
232 system.cpu.dcache.SwapReq_mshr_miss_latency::total 86000 # number of SwapReq MSHR miss cycles
233 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10955493000 # number of demand (read+write) MSHR miss cycles
234 system.cpu.dcache.demand_mshr_miss_latency::total 10955493000 # number of demand (read+write) MSHR miss cycles
235 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10955493000 # number of overall MSHR miss cycles
236 system.cpu.dcache.overall_mshr_miss_latency::total 10955493000 # number of overall MSHR miss cycles
237 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.010859 # mshr miss rate for ReadReq accesses
238 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.010859 # mshr miss rate for ReadReq accesses
239 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002040 # mshr miss rate for WriteReq accesses
240 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002040 # mshr miss rate for WriteReq accesses
241 system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.001029 # mshr miss rate for SwapReq accesses
242 system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.001029 # mshr miss rate for SwapReq accesses
243 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for demand accesses
244 system.cpu.dcache.demand_mshr_miss_rate::total 0.008938 # mshr miss rate for demand accesses
245 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for overall accesses
246 system.cpu.dcache.overall_mshr_miss_rate::total 0.008938 # mshr miss rate for overall accesses
247 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11009.502082 # average ReadReq mshr miss latency
248 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11009.502082 # average ReadReq mshr miss latency
249 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24097.238279 # average WriteReq mshr miss latency
250 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24097.238279 # average WriteReq mshr miss latency
251 system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 21500 # average SwapReq mshr miss latency
252 system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 21500 # average SwapReq mshr miss latency
253 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11660.150899 # average overall mshr miss latency
254 system.cpu.dcache.demand_avg_mshr_miss_latency::total 11660.150899 # average overall mshr miss latency
255 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11660.150899 # average overall mshr miss latency
256 system.cpu.dcache.overall_avg_mshr_miss_latency::total 11660.150899 # average overall mshr miss latency
257 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
258 system.cpu.l2cache.replacements 865 # number of replacements
259 system.cpu.l2cache.tagsinuse 9236.752232 # Cycle average of tags in use
260 system.cpu.l2cache.total_refs 1585884 # Total number of references to valid blocks.
261 system.cpu.l2cache.sampled_refs 15631 # Sample count of references to valid blocks.
262 system.cpu.l2cache.avg_refs 101.457616 # Average number of references to valid blocks.
263 system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
264 system.cpu.l2cache.occ_blocks::writebacks 8861.245791 # Average occupied blocks per requestor
265 system.cpu.l2cache.occ_blocks::cpu.inst 244.574580 # Average occupied blocks per requestor
266 system.cpu.l2cache.occ_blocks::cpu.data 130.931861 # Average occupied blocks per requestor
267 system.cpu.l2cache.occ_percent::writebacks 0.270424 # Average percentage of cache occupancy
268 system.cpu.l2cache.occ_percent::cpu.inst 0.007464 # Average percentage of cache occupancy
269 system.cpu.l2cache.occ_percent::cpu.data 0.003996 # Average percentage of cache occupancy
270 system.cpu.l2cache.occ_percent::total 0.281883 # Average percentage of cache occupancy
271 system.cpu.l2cache.ReadReq_hits::cpu.inst 3 # number of ReadReq hits
272 system.cpu.l2cache.ReadReq_hits::cpu.data 892655 # number of ReadReq hits
273 system.cpu.l2cache.ReadReq_hits::total 892658 # number of ReadReq hits
274 system.cpu.l2cache.Writeback_hits::writebacks 935237 # number of Writeback hits
275 system.cpu.l2cache.Writeback_hits::total 935237 # number of Writeback hits
276 system.cpu.l2cache.ReadExReq_hits::cpu.data 32147 # number of ReadExReq hits
277 system.cpu.l2cache.ReadExReq_hits::total 32147 # number of ReadExReq hits
278 system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits
279 system.cpu.l2cache.demand_hits::cpu.data 924802 # number of demand (read+write) hits
280 system.cpu.l2cache.demand_hits::total 924805 # number of demand (read+write) hits
281 system.cpu.l2cache.overall_hits::cpu.inst 3 # number of overall hits
282 system.cpu.l2cache.overall_hits::cpu.data 924802 # number of overall hits
283 system.cpu.l2cache.overall_hits::total 924805 # number of overall hits
284 system.cpu.l2cache.ReadReq_misses::cpu.inst 879 # number of ReadReq misses
285 system.cpu.l2cache.ReadReq_misses::cpu.data 202 # number of ReadReq misses
286 system.cpu.l2cache.ReadReq_misses::total 1081 # number of ReadReq misses
287 system.cpu.l2cache.ReadExReq_misses::cpu.data 14567 # number of ReadExReq misses
288 system.cpu.l2cache.ReadExReq_misses::total 14567 # number of ReadExReq misses
289 system.cpu.l2cache.demand_misses::cpu.inst 879 # number of demand (read+write) misses
290 system.cpu.l2cache.demand_misses::cpu.data 14769 # number of demand (read+write) misses
291 system.cpu.l2cache.demand_misses::total 15648 # number of demand (read+write) misses
292 system.cpu.l2cache.overall_misses::cpu.inst 879 # number of overall misses
293 system.cpu.l2cache.overall_misses::cpu.data 14769 # number of overall misses
294 system.cpu.l2cache.overall_misses::total 15648 # number of overall misses
295 system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 45708000 # number of ReadReq miss cycles
296 system.cpu.l2cache.ReadReq_miss_latency::cpu.data 10504000 # number of ReadReq miss cycles
297 system.cpu.l2cache.ReadReq_miss_latency::total 56212000 # number of ReadReq miss cycles
298 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 757484000 # number of ReadExReq miss cycles
299 system.cpu.l2cache.ReadExReq_miss_latency::total 757484000 # number of ReadExReq miss cycles
300 system.cpu.l2cache.demand_miss_latency::cpu.inst 45708000 # number of demand (read+write) miss cycles
301 system.cpu.l2cache.demand_miss_latency::cpu.data 767988000 # number of demand (read+write) miss cycles
302 system.cpu.l2cache.demand_miss_latency::total 813696000 # number of demand (read+write) miss cycles
303 system.cpu.l2cache.overall_miss_latency::cpu.inst 45708000 # number of overall miss cycles
304 system.cpu.l2cache.overall_miss_latency::cpu.data 767988000 # number of overall miss cycles
305 system.cpu.l2cache.overall_miss_latency::total 813696000 # number of overall miss cycles
306 system.cpu.l2cache.ReadReq_accesses::cpu.inst 882 # number of ReadReq accesses(hits+misses)
307 system.cpu.l2cache.ReadReq_accesses::cpu.data 892857 # number of ReadReq accesses(hits+misses)
308 system.cpu.l2cache.ReadReq_accesses::total 893739 # number of ReadReq accesses(hits+misses)
309 system.cpu.l2cache.Writeback_accesses::writebacks 935237 # number of Writeback accesses(hits+misses)
310 system.cpu.l2cache.Writeback_accesses::total 935237 # number of Writeback accesses(hits+misses)
311 system.cpu.l2cache.ReadExReq_accesses::cpu.data 46714 # number of ReadExReq accesses(hits+misses)
312 system.cpu.l2cache.ReadExReq_accesses::total 46714 # number of ReadExReq accesses(hits+misses)
313 system.cpu.l2cache.demand_accesses::cpu.inst 882 # number of demand (read+write) accesses
314 system.cpu.l2cache.demand_accesses::cpu.data 939571 # number of demand (read+write) accesses
315 system.cpu.l2cache.demand_accesses::total 940453 # number of demand (read+write) accesses
316 system.cpu.l2cache.overall_accesses::cpu.inst 882 # number of overall (read+write) accesses
317 system.cpu.l2cache.overall_accesses::cpu.data 939571 # number of overall (read+write) accesses
318 system.cpu.l2cache.overall_accesses::total 940453 # number of overall (read+write) accesses
319 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996599 # miss rate for ReadReq accesses
320 system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000226 # miss rate for ReadReq accesses
321 system.cpu.l2cache.ReadReq_miss_rate::total 0.001210 # miss rate for ReadReq accesses
322 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.311834 # miss rate for ReadExReq accesses
323 system.cpu.l2cache.ReadExReq_miss_rate::total 0.311834 # miss rate for ReadExReq accesses
324 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996599 # miss rate for demand accesses
325 system.cpu.l2cache.demand_miss_rate::cpu.data 0.015719 # miss rate for demand accesses
326 system.cpu.l2cache.demand_miss_rate::total 0.016639 # miss rate for demand accesses
327 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996599 # miss rate for overall accesses
328 system.cpu.l2cache.overall_miss_rate::cpu.data 0.015719 # miss rate for overall accesses
329 system.cpu.l2cache.overall_miss_rate::total 0.016639 # miss rate for overall accesses
330 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
331 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
332 system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
333 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
334 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
335 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
336 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
337 system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency
338 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
339 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
340 system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency
341 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
342 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
343 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
344 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
345 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
346 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
347 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
348 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
349 system.cpu.l2cache.writebacks::writebacks 40 # number of writebacks
350 system.cpu.l2cache.writebacks::total 40 # number of writebacks
351 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 879 # number of ReadReq MSHR misses
352 system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 202 # number of ReadReq MSHR misses
353 system.cpu.l2cache.ReadReq_mshr_misses::total 1081 # number of ReadReq MSHR misses
354 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14567 # number of ReadExReq MSHR misses
355 system.cpu.l2cache.ReadExReq_mshr_misses::total 14567 # number of ReadExReq MSHR misses
356 system.cpu.l2cache.demand_mshr_misses::cpu.inst 879 # number of demand (read+write) MSHR misses
357 system.cpu.l2cache.demand_mshr_misses::cpu.data 14769 # number of demand (read+write) MSHR misses
358 system.cpu.l2cache.demand_mshr_misses::total 15648 # number of demand (read+write) MSHR misses
359 system.cpu.l2cache.overall_mshr_misses::cpu.inst 879 # number of overall MSHR misses
360 system.cpu.l2cache.overall_mshr_misses::cpu.data 14769 # number of overall MSHR misses
361 system.cpu.l2cache.overall_mshr_misses::total 15648 # number of overall MSHR misses
362 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 35160000 # number of ReadReq MSHR miss cycles
363 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8080000 # number of ReadReq MSHR miss cycles
364 system.cpu.l2cache.ReadReq_mshr_miss_latency::total 43240000 # number of ReadReq MSHR miss cycles
365 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 582680000 # number of ReadExReq MSHR miss cycles
366 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 582680000 # number of ReadExReq MSHR miss cycles
367 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 35160000 # number of demand (read+write) MSHR miss cycles
368 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 590760000 # number of demand (read+write) MSHR miss cycles
369 system.cpu.l2cache.demand_mshr_miss_latency::total 625920000 # number of demand (read+write) MSHR miss cycles
370 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 35160000 # number of overall MSHR miss cycles
371 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 590760000 # number of overall MSHR miss cycles
372 system.cpu.l2cache.overall_mshr_miss_latency::total 625920000 # number of overall MSHR miss cycles
373 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for ReadReq accesses
374 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000226 # mshr miss rate for ReadReq accesses
375 system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001210 # mshr miss rate for ReadReq accesses
376 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.311834 # mshr miss rate for ReadExReq accesses
377 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.311834 # mshr miss rate for ReadExReq accesses
378 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for demand accesses
379 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015719 # mshr miss rate for demand accesses
380 system.cpu.l2cache.demand_mshr_miss_rate::total 0.016639 # mshr miss rate for demand accesses
381 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for overall accesses
382 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015719 # mshr miss rate for overall accesses
383 system.cpu.l2cache.overall_mshr_miss_rate::total 0.016639 # mshr miss rate for overall accesses
384 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
385 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
386 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
387 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
388 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
389 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
390 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
391 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
392 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
393 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
394 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
395 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
397 ---------- End Simulation Statistics ----------
projects / gem5.git / blob