tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini

   1 [root]
   2 type=Root
   3 children=system
   4 eventq_index=0
   5 full_system=false
   6 sim_quantum=0
   7 time_sync_enable=false
   8 time_sync_period=100000000000
   9 time_sync_spin_threshold=100000000
  10
  11 [system]
  12 type=System
  13 children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
  14 boot_osflags=a
  15 cache_line_size=64
  16 clk_domain=system.clk_domain
  17 eventq_index=0
  18 init_param=0
  19 kernel=
  20 load_addr_mask=1099511627775
  21 mem_mode=timing
  22 mem_ranges=
  23 memories=system.physmem
  24 num_work_ids=16
  25 readfile=
  26 symbolfile=
  27 work_begin_ckpt_count=0
  28 work_begin_cpu_id_exit=-1
  29 work_begin_exit_count=0
  30 work_cpus_ckpt_count=0
  31 work_end_ckpt_count=0
  32 work_end_exit_count=0
  33 work_item_id=-1
  34 system_port=system.membus.slave[0]
  35
  36 [system.clk_domain]
  37 type=SrcClockDomain
  38 clock=1000
  39 eventq_index=0
  40 voltage_domain=system.voltage_domain
  41
  42 [system.cpu]
  43 type=DerivO3CPU
  44 children=apic_clk_domain branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
  45 LFSTSize=1024
  46 LQEntries=32
  47 LSQCheckLoads=true
  48 LSQDepCheckShift=4
  49 SQEntries=32
  50 SSITSize=1024
  51 activity=0
  52 backComSize=5
  53 branchPred=system.cpu.branchPred
  54 cachePorts=200
  55 checker=Null
  56 clk_domain=system.cpu_clk_domain
  57 commitToDecodeDelay=1
  58 commitToFetchDelay=1
  59 commitToIEWDelay=1
  60 commitToRenameDelay=1
  61 commitWidth=8
  62 cpu_id=0
  63 decodeToFetchDelay=1
  64 decodeToRenameDelay=1
  65 decodeWidth=8
  66 dispatchWidth=8
  67 do_checkpoint_insts=true
  68 do_quiesce=true
  69 do_statistics_insts=true
  70 dtb=system.cpu.dtb
  71 eventq_index=0
  72 fetchBufferSize=64
  73 fetchToDecodeDelay=1
  74 fetchTrapLatency=1
  75 fetchWidth=8
  76 forwardComSize=5
  77 fuPool=system.cpu.fuPool
  78 function_trace=false
  79 function_trace_start=0
  80 iewToCommitDelay=1
  81 iewToDecodeDelay=1
  82 iewToFetchDelay=1
  83 iewToRenameDelay=1
  84 interrupts=system.cpu.interrupts
  85 isa=system.cpu.isa
  86 issueToExecuteDelay=1
  87 issueWidth=8
  88 itb=system.cpu.itb
  89 max_insts_all_threads=0
  90 max_insts_any_thread=0
  91 max_loads_all_threads=0
  92 max_loads_any_thread=0
  93 needsTSO=true
  94 numIQEntries=64
  95 numPhysCCRegs=1280
  96 numPhysFloatRegs=256
  97 numPhysIntRegs=256
  98 numROBEntries=192
  99 numRobs=1
 100 numThreads=1
 101 profile=0
 102 progress_interval=0
 103 renameToDecodeDelay=1
 104 renameToFetchDelay=1
 105 renameToIEWDelay=2
 106 renameToROBDelay=1
 107 renameWidth=8
 108 simpoint_start_insts=
 109 smtCommitPolicy=RoundRobin
 110 smtFetchPolicy=SingleThread
 111 smtIQPolicy=Partitioned
 112 smtIQThreshold=100
 113 smtLSQPolicy=Partitioned
 114 smtLSQThreshold=100
 115 smtNumFetchingThreads=1
 116 smtROBPolicy=Partitioned
 117 smtROBThreshold=100
 118 squashWidth=8
 119 store_set_clear_period=250000
 120 switched_out=false
 121 system=system
 122 tracer=system.cpu.tracer
 123 trapLatency=13
 124 wbDepth=1
 125 wbWidth=8
 126 workload=system.cpu.workload
 127 dcache_port=system.cpu.dcache.cpu_side
 128 icache_port=system.cpu.icache.cpu_side
 129
 130 [system.cpu.apic_clk_domain]
 131 type=DerivedClockDomain
 132 clk_divider=16
 133 clk_domain=system.cpu_clk_domain
 134 eventq_index=0
 135
 136 [system.cpu.branchPred]
 137 type=BranchPredictor
 138 BTBEntries=4096
 139 BTBTagSize=16
 140 RASSize=16
 141 choiceCtrBits=2
 142 choicePredictorSize=8192
 143 eventq_index=0
 144 globalCtrBits=2
 145 globalPredictorSize=8192
 146 instShiftAmt=2
 147 localCtrBits=2
 148 localHistoryTableSize=2048
 149 localPredictorSize=2048
 150 numThreads=1
 151 predType=tournament
 152
 153 [system.cpu.dcache]
 154 type=BaseCache
 155 children=tags
 156 addr_ranges=0:18446744073709551615
 157 assoc=2
 158 clk_domain=system.cpu_clk_domain
 159 eventq_index=0
 160 forward_snoops=true
 161 hit_latency=2
 162 is_top_level=true
 163 max_miss_count=0
 164 mshrs=4
 165 prefetch_on_access=false
 166 prefetcher=Null
 167 response_latency=2
 168 size=262144
 169 system=system
 170 tags=system.cpu.dcache.tags
 171 tgts_per_mshr=20
 172 two_queue=false
 173 write_buffers=8
 174 cpu_side=system.cpu.dcache_port
 175 mem_side=system.cpu.toL2Bus.slave[1]
 176
 177 [system.cpu.dcache.tags]
 178 type=LRU
 179 assoc=2
 180 block_size=64
 181 clk_domain=system.cpu_clk_domain
 182 eventq_index=0
 183 hit_latency=2
 184 size=262144
 185
 186 [system.cpu.dtb]
 187 type=X86TLB
 188 children=walker
 189 eventq_index=0
 190 size=64
 191 walker=system.cpu.dtb.walker
 192
 193 [system.cpu.dtb.walker]
 194 type=X86PagetableWalker
 195 clk_domain=system.cpu_clk_domain
 196 eventq_index=0
 197 num_squash_per_cycle=4
 198 system=system
 199 port=system.cpu.toL2Bus.slave[3]
 200
 201 [system.cpu.fuPool]
 202 type=FUPool
 203 children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
 204 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
 205 eventq_index=0
 206
 207 [system.cpu.fuPool.FUList0]
 208 type=FUDesc
 209 children=opList
 210 count=6
 211 eventq_index=0
 212 opList=system.cpu.fuPool.FUList0.opList
 213
 214 [system.cpu.fuPool.FUList0.opList]
 215 type=OpDesc
 216 eventq_index=0
 217 issueLat=1
 218 opClass=IntAlu
 219 opLat=1
 220
 221 [system.cpu.fuPool.FUList1]
 222 type=FUDesc
 223 children=opList0 opList1
 224 count=2
 225 eventq_index=0
 226 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
 227
 228 [system.cpu.fuPool.FUList1.opList0]
 229 type=OpDesc
 230 eventq_index=0
 231 issueLat=1
 232 opClass=IntMult
 233 opLat=3
 234
 235 [system.cpu.fuPool.FUList1.opList1]
 236 type=OpDesc
 237 eventq_index=0
 238 issueLat=19
 239 opClass=IntDiv
 240 opLat=20
 241
 242 [system.cpu.fuPool.FUList2]
 243 type=FUDesc
 244 children=opList0 opList1 opList2
 245 count=4
 246 eventq_index=0
 247 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
 248
 249 [system.cpu.fuPool.FUList2.opList0]
 250 type=OpDesc
 251 eventq_index=0
 252 issueLat=1
 253 opClass=FloatAdd
 254 opLat=2
 255
 256 [system.cpu.fuPool.FUList2.opList1]
 257 type=OpDesc
 258 eventq_index=0
 259 issueLat=1
 260 opClass=FloatCmp
 261 opLat=2
 262
 263 [system.cpu.fuPool.FUList2.opList2]
 264 type=OpDesc
 265 eventq_index=0
 266 issueLat=1
 267 opClass=FloatCvt
 268 opLat=2
 269
 270 [system.cpu.fuPool.FUList3]
 271 type=FUDesc
 272 children=opList0 opList1 opList2
 273 count=2
 274 eventq_index=0
 275 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
 276
 277 [system.cpu.fuPool.FUList3.opList0]
 278 type=OpDesc
 279 eventq_index=0
 280 issueLat=1
 281 opClass=FloatMult
 282 opLat=4
 283
 284 [system.cpu.fuPool.FUList3.opList1]
 285 type=OpDesc
 286 eventq_index=0
 287 issueLat=12
 288 opClass=FloatDiv
 289 opLat=12
 290
 291 [system.cpu.fuPool.FUList3.opList2]
 292 type=OpDesc
 293 eventq_index=0
 294 issueLat=24
 295 opClass=FloatSqrt
 296 opLat=24
 297
 298 [system.cpu.fuPool.FUList4]
 299 type=FUDesc
 300 children=opList
 301 count=0
 302 eventq_index=0
 303 opList=system.cpu.fuPool.FUList4.opList
 304
 305 [system.cpu.fuPool.FUList4.opList]
 306 type=OpDesc
 307 eventq_index=0
 308 issueLat=1
 309 opClass=MemRead
 310 opLat=1
 311
 312 [system.cpu.fuPool.FUList5]
 313 type=FUDesc
 314 children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
 315 count=4
 316 eventq_index=0
 317 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
 318
 319 [system.cpu.fuPool.FUList5.opList00]
 320 type=OpDesc
 321 eventq_index=0
 322 issueLat=1
 323 opClass=SimdAdd
 324 opLat=1
 325
 326 [system.cpu.fuPool.FUList5.opList01]
 327 type=OpDesc
 328 eventq_index=0
 329 issueLat=1
 330 opClass=SimdAddAcc
 331 opLat=1
 332
 333 [system.cpu.fuPool.FUList5.opList02]
 334 type=OpDesc
 335 eventq_index=0
 336 issueLat=1
 337 opClass=SimdAlu
 338 opLat=1
 339
 340 [system.cpu.fuPool.FUList5.opList03]
 341 type=OpDesc
 342 eventq_index=0
 343 issueLat=1
 344 opClass=SimdCmp
 345 opLat=1
 346
 347 [system.cpu.fuPool.FUList5.opList04]
 348 type=OpDesc
 349 eventq_index=0
 350 issueLat=1
 351 opClass=SimdCvt
 352 opLat=1
 353
 354 [system.cpu.fuPool.FUList5.opList05]
 355 type=OpDesc
 356 eventq_index=0
 357 issueLat=1
 358 opClass=SimdMisc
 359 opLat=1
 360
 361 [system.cpu.fuPool.FUList5.opList06]
 362 type=OpDesc
 363 eventq_index=0
 364 issueLat=1
 365 opClass=SimdMult
 366 opLat=1
 367
 368 [system.cpu.fuPool.FUList5.opList07]
 369 type=OpDesc
 370 eventq_index=0
 371 issueLat=1
 372 opClass=SimdMultAcc
 373 opLat=1
 374
 375 [system.cpu.fuPool.FUList5.opList08]
 376 type=OpDesc
 377 eventq_index=0
 378 issueLat=1
 379 opClass=SimdShift
 380 opLat=1
 381
 382 [system.cpu.fuPool.FUList5.opList09]
 383 type=OpDesc
 384 eventq_index=0
 385 issueLat=1
 386 opClass=SimdShiftAcc
 387 opLat=1
 388
 389 [system.cpu.fuPool.FUList5.opList10]
 390 type=OpDesc
 391 eventq_index=0
 392 issueLat=1
 393 opClass=SimdSqrt
 394 opLat=1
 395
 396 [system.cpu.fuPool.FUList5.opList11]
 397 type=OpDesc
 398 eventq_index=0
 399 issueLat=1
 400 opClass=SimdFloatAdd
 401 opLat=1
 402
 403 [system.cpu.fuPool.FUList5.opList12]
 404 type=OpDesc
 405 eventq_index=0
 406 issueLat=1
 407 opClass=SimdFloatAlu
 408 opLat=1
 409
 410 [system.cpu.fuPool.FUList5.opList13]
 411 type=OpDesc
 412 eventq_index=0
 413 issueLat=1
 414 opClass=SimdFloatCmp
 415 opLat=1
 416
 417 [system.cpu.fuPool.FUList5.opList14]
 418 type=OpDesc
 419 eventq_index=0
 420 issueLat=1
 421 opClass=SimdFloatCvt
 422 opLat=1
 423
 424 [system.cpu.fuPool.FUList5.opList15]
 425 type=OpDesc
 426 eventq_index=0
 427 issueLat=1
 428 opClass=SimdFloatDiv
 429 opLat=1
 430
 431 [system.cpu.fuPool.FUList5.opList16]
 432 type=OpDesc
 433 eventq_index=0
 434 issueLat=1
 435 opClass=SimdFloatMisc
 436 opLat=1
 437
 438 [system.cpu.fuPool.FUList5.opList17]
 439 type=OpDesc
 440 eventq_index=0
 441 issueLat=1
 442 opClass=SimdFloatMult
 443 opLat=1
 444
 445 [system.cpu.fuPool.FUList5.opList18]
 446 type=OpDesc
 447 eventq_index=0
 448 issueLat=1
 449 opClass=SimdFloatMultAcc
 450 opLat=1
 451
 452 [system.cpu.fuPool.FUList5.opList19]
 453 type=OpDesc
 454 eventq_index=0
 455 issueLat=1
 456 opClass=SimdFloatSqrt
 457 opLat=1
 458
 459 [system.cpu.fuPool.FUList6]
 460 type=FUDesc
 461 children=opList
 462 count=0
 463 eventq_index=0
 464 opList=system.cpu.fuPool.FUList6.opList
 465
 466 [system.cpu.fuPool.FUList6.opList]
 467 type=OpDesc
 468 eventq_index=0
 469 issueLat=1
 470 opClass=MemWrite
 471 opLat=1
 472
 473 [system.cpu.fuPool.FUList7]
 474 type=FUDesc
 475 children=opList0 opList1
 476 count=4
 477 eventq_index=0
 478 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
 479
 480 [system.cpu.fuPool.FUList7.opList0]
 481 type=OpDesc
 482 eventq_index=0
 483 issueLat=1
 484 opClass=MemRead
 485 opLat=1
 486
 487 [system.cpu.fuPool.FUList7.opList1]
 488 type=OpDesc
 489 eventq_index=0
 490 issueLat=1
 491 opClass=MemWrite
 492 opLat=1
 493
 494 [system.cpu.fuPool.FUList8]
 495 type=FUDesc
 496 children=opList
 497 count=1
 498 eventq_index=0
 499 opList=system.cpu.fuPool.FUList8.opList
 500
 501 [system.cpu.fuPool.FUList8.opList]
 502 type=OpDesc
 503 eventq_index=0
 504 issueLat=3
 505 opClass=IprAccess
 506 opLat=3
 507
 508 [system.cpu.icache]
 509 type=BaseCache
 510 children=tags
 511 addr_ranges=0:18446744073709551615
 512 assoc=2
 513 clk_domain=system.cpu_clk_domain
 514 eventq_index=0
 515 forward_snoops=true
 516 hit_latency=2
 517 is_top_level=true
 518 max_miss_count=0
 519 mshrs=4
 520 prefetch_on_access=false
 521 prefetcher=Null
 522 response_latency=2
 523 size=131072
 524 system=system
 525 tags=system.cpu.icache.tags
 526 tgts_per_mshr=20
 527 two_queue=false
 528 write_buffers=8
 529 cpu_side=system.cpu.icache_port
 530 mem_side=system.cpu.toL2Bus.slave[0]
 531
 532 [system.cpu.icache.tags]
 533 type=LRU
 534 assoc=2
 535 block_size=64
 536 clk_domain=system.cpu_clk_domain
 537 eventq_index=0
 538 hit_latency=2
 539 size=131072
 540
 541 [system.cpu.interrupts]
 542 type=X86LocalApic
 543 clk_domain=system.cpu.apic_clk_domain
 544 eventq_index=0
 545 int_latency=1000
 546 pio_addr=2305843009213693952
 547 pio_latency=100000
 548 system=system
 549 int_master=system.membus.slave[2]
 550 int_slave=system.membus.master[2]
 551 pio=system.membus.master[1]
 552
 553 [system.cpu.isa]
 554 type=X86ISA
 555 eventq_index=0
 556
 557 [system.cpu.itb]
 558 type=X86TLB
 559 children=walker
 560 eventq_index=0
 561 size=64
 562 walker=system.cpu.itb.walker
 563
 564 [system.cpu.itb.walker]
 565 type=X86PagetableWalker
 566 clk_domain=system.cpu_clk_domain
 567 eventq_index=0
 568 num_squash_per_cycle=4
 569 system=system
 570 port=system.cpu.toL2Bus.slave[2]
 571
 572 [system.cpu.l2cache]
 573 type=BaseCache
 574 children=tags
 575 addr_ranges=0:18446744073709551615
 576 assoc=8
 577 clk_domain=system.cpu_clk_domain
 578 eventq_index=0
 579 forward_snoops=true
 580 hit_latency=20
 581 is_top_level=false
 582 max_miss_count=0
 583 mshrs=20
 584 prefetch_on_access=false
 585 prefetcher=Null
 586 response_latency=20
 587 size=2097152
 588 system=system
 589 tags=system.cpu.l2cache.tags
 590 tgts_per_mshr=12
 591 two_queue=false
 592 write_buffers=8
 593 cpu_side=system.cpu.toL2Bus.master[0]
 594 mem_side=system.membus.slave[1]
 595
 596 [system.cpu.l2cache.tags]
 597 type=LRU
 598 assoc=8
 599 block_size=64
 600 clk_domain=system.cpu_clk_domain
 601 eventq_index=0
 602 hit_latency=20
 603 size=2097152
 604
 605 [system.cpu.toL2Bus]
 606 type=CoherentBus
 607 clk_domain=system.cpu_clk_domain
 608 eventq_index=0
 609 header_cycles=1
 610 system=system
 611 use_default_range=false
 612 width=32
 613 master=system.cpu.l2cache.cpu_side
 614 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
 615
 616 [system.cpu.tracer]
 617 type=ExeTracer
 618 eventq_index=0
 619
 620 [system.cpu.workload]
 621 type=LiveProcess
 622 cmd=mcf mcf.in
 623 cwd=build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing
 624 egid=100
 625 env=
 626 errout=cerr
 627 euid=100
 628 eventq_index=0
 629 executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/mcf
 630 gid=100
 631 input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
 632 max_stack_size=67108864
 633 output=cout
 634 pid=100
 635 ppid=99
 636 simpoint=55300000000
 637 system=system
 638 uid=100
 639
 640 [system.cpu_clk_domain]
 641 type=SrcClockDomain
 642 clock=500
 643 eventq_index=0
 644 voltage_domain=system.voltage_domain
 645
 646 [system.membus]
 647 type=CoherentBus
 648 clk_domain=system.clk_domain
 649 eventq_index=0
 650 header_cycles=1
 651 system=system
 652 use_default_range=false
 653 width=8
 654 master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave
 655 slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
 656
 657 [system.physmem]
 658 type=SimpleDRAM
 659 activation_limit=4
 660 addr_mapping=RaBaChCo
 661 banks_per_rank=8
 662 burst_length=8
 663 channels=1
 664 clk_domain=system.clk_domain
 665 conf_table_reported=true
 666 device_bus_width=8
 667 device_rowbuffer_size=1024
 668 devices_per_rank=8
 669 eventq_index=0
 670 in_addr_map=true
 671 mem_sched_policy=frfcfs
 672 null=false
 673 page_policy=open
 674 range=0:268435455
 675 ranks_per_channel=2
 676 read_buffer_size=32
 677 static_backend_latency=10000
 678 static_frontend_latency=10000
 679 tBURST=5000
 680 tCL=13750
 681 tRAS=35000
 682 tRCD=13750
 683 tREFI=7800000
 684 tRFC=300000
 685 tRP=13750
 686 tRRD=6250
 687 tWTR=7500
 688 tXAW=40000
 689 write_buffer_size=32
 690 write_high_thresh_perc=70
 691 write_low_thresh_perc=0
 692 port=system.membus.master[0]
 693
 694 [system.voltage_domain]
 695 type=VoltageDomain
 696 eventq_index=0
 697 voltage=1.000000
 698