tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini

   1 [root]
   2 type=Root
   3 children=system
   4 eventq_index=0
   5 full_system=false
   6 sim_quantum=0
   7 time_sync_enable=false
   8 time_sync_period=100000000000
   9 time_sync_spin_threshold=100000000
  10
  11 [system]
  12 type=System
  13 children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
  14 boot_osflags=a
  15 cache_line_size=64
  16 clk_domain=system.clk_domain
  17 eventq_index=0
  18 init_param=0
  19 kernel=
  20 kernel_addr_check=true
  21 load_addr_mask=1099511627775
  22 load_offset=0
  23 mem_mode=timing
  24 mem_ranges=
  25 memories=system.physmem
  26 num_work_ids=16
  27 readfile=
  28 symbolfile=
  29 work_begin_ckpt_count=0
  30 work_begin_cpu_id_exit=-1
  31 work_begin_exit_count=0
  32 work_cpus_ckpt_count=0
  33 work_end_ckpt_count=0
  34 work_end_exit_count=0
  35 work_item_id=-1
  36 system_port=system.membus.slave[0]
  37
  38 [system.clk_domain]
  39 type=SrcClockDomain
  40 clock=1000
  41 domain_id=-1
  42 eventq_index=0
  43 init_perf_level=0
  44 voltage_domain=system.voltage_domain
  45
  46 [system.cpu]
  47 type=DerivO3CPU
  48 children=apic_clk_domain branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
  49 LFSTSize=1024
  50 LQEntries=32
  51 LSQCheckLoads=true
  52 LSQDepCheckShift=4
  53 SQEntries=32
  54 SSITSize=1024
  55 activity=0
  56 backComSize=5
  57 branchPred=system.cpu.branchPred
  58 cachePorts=200
  59 checker=Null
  60 clk_domain=system.cpu_clk_domain
  61 commitToDecodeDelay=1
  62 commitToFetchDelay=1
  63 commitToIEWDelay=1
  64 commitToRenameDelay=1
  65 commitWidth=8
  66 cpu_id=0
  67 decodeToFetchDelay=1
  68 decodeToRenameDelay=1
  69 decodeWidth=8
  70 dispatchWidth=8
  71 do_checkpoint_insts=true
  72 do_quiesce=true
  73 do_statistics_insts=true
  74 dtb=system.cpu.dtb
  75 eventq_index=0
  76 fetchBufferSize=64
  77 fetchQueueSize=32
  78 fetchToDecodeDelay=1
  79 fetchTrapLatency=1
  80 fetchWidth=8
  81 forwardComSize=5
  82 fuPool=system.cpu.fuPool
  83 function_trace=false
  84 function_trace_start=0
  85 iewToCommitDelay=1
  86 iewToDecodeDelay=1
  87 iewToFetchDelay=1
  88 iewToRenameDelay=1
  89 interrupts=system.cpu.interrupts
  90 isa=system.cpu.isa
  91 issueToExecuteDelay=1
  92 issueWidth=8
  93 itb=system.cpu.itb
  94 max_insts_all_threads=0
  95 max_insts_any_thread=0
  96 max_loads_all_threads=0
  97 max_loads_any_thread=0
  98 needsTSO=true
  99 numIQEntries=64
 100 numPhysCCRegs=1280
 101 numPhysFloatRegs=256
 102 numPhysIntRegs=256
 103 numROBEntries=192
 104 numRobs=1
 105 numThreads=1
 106 profile=0
 107 progress_interval=0
 108 renameToDecodeDelay=1
 109 renameToFetchDelay=1
 110 renameToIEWDelay=2
 111 renameToROBDelay=1
 112 renameWidth=8
 113 simpoint_start_insts=
 114 smtCommitPolicy=RoundRobin
 115 smtFetchPolicy=SingleThread
 116 smtIQPolicy=Partitioned
 117 smtIQThreshold=100
 118 smtLSQPolicy=Partitioned
 119 smtLSQThreshold=100
 120 smtNumFetchingThreads=1
 121 smtROBPolicy=Partitioned
 122 smtROBThreshold=100
 123 socket_id=0
 124 squashWidth=8
 125 store_set_clear_period=250000
 126 switched_out=false
 127 system=system
 128 tracer=system.cpu.tracer
 129 trapLatency=13
 130 wbWidth=8
 131 workload=system.cpu.workload
 132 dcache_port=system.cpu.dcache.cpu_side
 133 icache_port=system.cpu.icache.cpu_side
 134
 135 [system.cpu.apic_clk_domain]
 136 type=DerivedClockDomain
 137 clk_divider=16
 138 clk_domain=system.cpu_clk_domain
 139 eventq_index=0
 140
 141 [system.cpu.branchPred]
 142 type=BranchPredictor
 143 BTBEntries=4096
 144 BTBTagSize=16
 145 RASSize=16
 146 choiceCtrBits=2
 147 choicePredictorSize=8192
 148 eventq_index=0
 149 globalCtrBits=2
 150 globalPredictorSize=8192
 151 instShiftAmt=2
 152 localCtrBits=2
 153 localHistoryTableSize=2048
 154 localPredictorSize=2048
 155 numThreads=1
 156 predType=tournament
 157
 158 [system.cpu.dcache]
 159 type=BaseCache
 160 children=tags
 161 addr_ranges=0:18446744073709551615
 162 assoc=2
 163 clk_domain=system.cpu_clk_domain
 164 demand_mshr_reserve=1
 165 eventq_index=0
 166 forward_snoops=true
 167 hit_latency=2
 168 is_top_level=true
 169 max_miss_count=0
 170 mshrs=4
 171 prefetch_on_access=false
 172 prefetcher=Null
 173 response_latency=2
 174 sequential_access=false
 175 size=262144
 176 system=system
 177 tags=system.cpu.dcache.tags
 178 tgts_per_mshr=20
 179 two_queue=false
 180 write_buffers=8
 181 cpu_side=system.cpu.dcache_port
 182 mem_side=system.cpu.toL2Bus.slave[1]
 183
 184 [system.cpu.dcache.tags]
 185 type=LRU
 186 assoc=2
 187 block_size=64
 188 clk_domain=system.cpu_clk_domain
 189 eventq_index=0
 190 hit_latency=2
 191 sequential_access=false
 192 size=262144
 193
 194 [system.cpu.dtb]
 195 type=X86TLB
 196 children=walker
 197 eventq_index=0
 198 size=64
 199 walker=system.cpu.dtb.walker
 200
 201 [system.cpu.dtb.walker]
 202 type=X86PagetableWalker
 203 clk_domain=system.cpu_clk_domain
 204 eventq_index=0
 205 num_squash_per_cycle=4
 206 system=system
 207 port=system.cpu.toL2Bus.slave[3]
 208
 209 [system.cpu.fuPool]
 210 type=FUPool
 211 children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
 212 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
 213 eventq_index=0
 214
 215 [system.cpu.fuPool.FUList0]
 216 type=FUDesc
 217 children=opList
 218 count=6
 219 eventq_index=0
 220 opList=system.cpu.fuPool.FUList0.opList
 221
 222 [system.cpu.fuPool.FUList0.opList]
 223 type=OpDesc
 224 eventq_index=0
 225 issueLat=1
 226 opClass=IntAlu
 227 opLat=1
 228
 229 [system.cpu.fuPool.FUList1]
 230 type=FUDesc
 231 children=opList0 opList1
 232 count=2
 233 eventq_index=0
 234 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
 235
 236 [system.cpu.fuPool.FUList1.opList0]
 237 type=OpDesc
 238 eventq_index=0
 239 issueLat=1
 240 opClass=IntMult
 241 opLat=3
 242
 243 [system.cpu.fuPool.FUList1.opList1]
 244 type=OpDesc
 245 eventq_index=0
 246 issueLat=19
 247 opClass=IntDiv
 248 opLat=20
 249
 250 [system.cpu.fuPool.FUList2]
 251 type=FUDesc
 252 children=opList0 opList1 opList2
 253 count=4
 254 eventq_index=0
 255 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
 256
 257 [system.cpu.fuPool.FUList2.opList0]
 258 type=OpDesc
 259 eventq_index=0
 260 issueLat=1
 261 opClass=FloatAdd
 262 opLat=2
 263
 264 [system.cpu.fuPool.FUList2.opList1]
 265 type=OpDesc
 266 eventq_index=0
 267 issueLat=1
 268 opClass=FloatCmp
 269 opLat=2
 270
 271 [system.cpu.fuPool.FUList2.opList2]
 272 type=OpDesc
 273 eventq_index=0
 274 issueLat=1
 275 opClass=FloatCvt
 276 opLat=2
 277
 278 [system.cpu.fuPool.FUList3]
 279 type=FUDesc
 280 children=opList0 opList1 opList2
 281 count=2
 282 eventq_index=0
 283 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
 284
 285 [system.cpu.fuPool.FUList3.opList0]
 286 type=OpDesc
 287 eventq_index=0
 288 issueLat=1
 289 opClass=FloatMult
 290 opLat=4
 291
 292 [system.cpu.fuPool.FUList3.opList1]
 293 type=OpDesc
 294 eventq_index=0
 295 issueLat=12
 296 opClass=FloatDiv
 297 opLat=12
 298
 299 [system.cpu.fuPool.FUList3.opList2]
 300 type=OpDesc
 301 eventq_index=0
 302 issueLat=24
 303 opClass=FloatSqrt
 304 opLat=24
 305
 306 [system.cpu.fuPool.FUList4]
 307 type=FUDesc
 308 children=opList
 309 count=0
 310 eventq_index=0
 311 opList=system.cpu.fuPool.FUList4.opList
 312
 313 [system.cpu.fuPool.FUList4.opList]
 314 type=OpDesc
 315 eventq_index=0
 316 issueLat=1
 317 opClass=MemRead
 318 opLat=1
 319
 320 [system.cpu.fuPool.FUList5]
 321 type=FUDesc
 322 children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
 323 count=4
 324 eventq_index=0
 325 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
 326
 327 [system.cpu.fuPool.FUList5.opList00]
 328 type=OpDesc
 329 eventq_index=0
 330 issueLat=1
 331 opClass=SimdAdd
 332 opLat=1
 333
 334 [system.cpu.fuPool.FUList5.opList01]
 335 type=OpDesc
 336 eventq_index=0
 337 issueLat=1
 338 opClass=SimdAddAcc
 339 opLat=1
 340
 341 [system.cpu.fuPool.FUList5.opList02]
 342 type=OpDesc
 343 eventq_index=0
 344 issueLat=1
 345 opClass=SimdAlu
 346 opLat=1
 347
 348 [system.cpu.fuPool.FUList5.opList03]
 349 type=OpDesc
 350 eventq_index=0
 351 issueLat=1
 352 opClass=SimdCmp
 353 opLat=1
 354
 355 [system.cpu.fuPool.FUList5.opList04]
 356 type=OpDesc
 357 eventq_index=0
 358 issueLat=1
 359 opClass=SimdCvt
 360 opLat=1
 361
 362 [system.cpu.fuPool.FUList5.opList05]
 363 type=OpDesc
 364 eventq_index=0
 365 issueLat=1
 366 opClass=SimdMisc
 367 opLat=1
 368
 369 [system.cpu.fuPool.FUList5.opList06]
 370 type=OpDesc
 371 eventq_index=0
 372 issueLat=1
 373 opClass=SimdMult
 374 opLat=1
 375
 376 [system.cpu.fuPool.FUList5.opList07]
 377 type=OpDesc
 378 eventq_index=0
 379 issueLat=1
 380 opClass=SimdMultAcc
 381 opLat=1
 382
 383 [system.cpu.fuPool.FUList5.opList08]
 384 type=OpDesc
 385 eventq_index=0
 386 issueLat=1
 387 opClass=SimdShift
 388 opLat=1
 389
 390 [system.cpu.fuPool.FUList5.opList09]
 391 type=OpDesc
 392 eventq_index=0
 393 issueLat=1
 394 opClass=SimdShiftAcc
 395 opLat=1
 396
 397 [system.cpu.fuPool.FUList5.opList10]
 398 type=OpDesc
 399 eventq_index=0
 400 issueLat=1
 401 opClass=SimdSqrt
 402 opLat=1
 403
 404 [system.cpu.fuPool.FUList5.opList11]
 405 type=OpDesc
 406 eventq_index=0
 407 issueLat=1
 408 opClass=SimdFloatAdd
 409 opLat=1
 410
 411 [system.cpu.fuPool.FUList5.opList12]
 412 type=OpDesc
 413 eventq_index=0
 414 issueLat=1
 415 opClass=SimdFloatAlu
 416 opLat=1
 417
 418 [system.cpu.fuPool.FUList5.opList13]
 419 type=OpDesc
 420 eventq_index=0
 421 issueLat=1
 422 opClass=SimdFloatCmp
 423 opLat=1
 424
 425 [system.cpu.fuPool.FUList5.opList14]
 426 type=OpDesc
 427 eventq_index=0
 428 issueLat=1
 429 opClass=SimdFloatCvt
 430 opLat=1
 431
 432 [system.cpu.fuPool.FUList5.opList15]
 433 type=OpDesc
 434 eventq_index=0
 435 issueLat=1
 436 opClass=SimdFloatDiv
 437 opLat=1
 438
 439 [system.cpu.fuPool.FUList5.opList16]
 440 type=OpDesc
 441 eventq_index=0
 442 issueLat=1
 443 opClass=SimdFloatMisc
 444 opLat=1
 445
 446 [system.cpu.fuPool.FUList5.opList17]
 447 type=OpDesc
 448 eventq_index=0
 449 issueLat=1
 450 opClass=SimdFloatMult
 451 opLat=1
 452
 453 [system.cpu.fuPool.FUList5.opList18]
 454 type=OpDesc
 455 eventq_index=0
 456 issueLat=1
 457 opClass=SimdFloatMultAcc
 458 opLat=1
 459
 460 [system.cpu.fuPool.FUList5.opList19]
 461 type=OpDesc
 462 eventq_index=0
 463 issueLat=1
 464 opClass=SimdFloatSqrt
 465 opLat=1
 466
 467 [system.cpu.fuPool.FUList6]
 468 type=FUDesc
 469 children=opList
 470 count=0
 471 eventq_index=0
 472 opList=system.cpu.fuPool.FUList6.opList
 473
 474 [system.cpu.fuPool.FUList6.opList]
 475 type=OpDesc
 476 eventq_index=0
 477 issueLat=1
 478 opClass=MemWrite
 479 opLat=1
 480
 481 [system.cpu.fuPool.FUList7]
 482 type=FUDesc
 483 children=opList0 opList1
 484 count=4
 485 eventq_index=0
 486 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
 487
 488 [system.cpu.fuPool.FUList7.opList0]
 489 type=OpDesc
 490 eventq_index=0
 491 issueLat=1
 492 opClass=MemRead
 493 opLat=1
 494
 495 [system.cpu.fuPool.FUList7.opList1]
 496 type=OpDesc
 497 eventq_index=0
 498 issueLat=1
 499 opClass=MemWrite
 500 opLat=1
 501
 502 [system.cpu.fuPool.FUList8]
 503 type=FUDesc
 504 children=opList
 505 count=1
 506 eventq_index=0
 507 opList=system.cpu.fuPool.FUList8.opList
 508
 509 [system.cpu.fuPool.FUList8.opList]
 510 type=OpDesc
 511 eventq_index=0
 512 issueLat=3
 513 opClass=IprAccess
 514 opLat=3
 515
 516 [system.cpu.icache]
 517 type=BaseCache
 518 children=tags
 519 addr_ranges=0:18446744073709551615
 520 assoc=2
 521 clk_domain=system.cpu_clk_domain
 522 demand_mshr_reserve=1
 523 eventq_index=0
 524 forward_snoops=true
 525 hit_latency=2
 526 is_top_level=true
 527 max_miss_count=0
 528 mshrs=4
 529 prefetch_on_access=false
 530 prefetcher=Null
 531 response_latency=2
 532 sequential_access=false
 533 size=131072
 534 system=system
 535 tags=system.cpu.icache.tags
 536 tgts_per_mshr=20
 537 two_queue=false
 538 write_buffers=8
 539 cpu_side=system.cpu.icache_port
 540 mem_side=system.cpu.toL2Bus.slave[0]
 541
 542 [system.cpu.icache.tags]
 543 type=LRU
 544 assoc=2
 545 block_size=64
 546 clk_domain=system.cpu_clk_domain
 547 eventq_index=0
 548 hit_latency=2
 549 sequential_access=false
 550 size=131072
 551
 552 [system.cpu.interrupts]
 553 type=X86LocalApic
 554 clk_domain=system.cpu.apic_clk_domain
 555 eventq_index=0
 556 int_latency=1000
 557 pio_addr=2305843009213693952
 558 pio_latency=100000
 559 system=system
 560 int_master=system.membus.slave[2]
 561 int_slave=system.membus.master[2]
 562 pio=system.membus.master[1]
 563
 564 [system.cpu.isa]
 565 type=X86ISA
 566 eventq_index=0
 567
 568 [system.cpu.itb]
 569 type=X86TLB
 570 children=walker
 571 eventq_index=0
 572 size=64
 573 walker=system.cpu.itb.walker
 574
 575 [system.cpu.itb.walker]
 576 type=X86PagetableWalker
 577 clk_domain=system.cpu_clk_domain
 578 eventq_index=0
 579 num_squash_per_cycle=4
 580 system=system
 581 port=system.cpu.toL2Bus.slave[2]
 582
 583 [system.cpu.l2cache]
 584 type=BaseCache
 585 children=tags
 586 addr_ranges=0:18446744073709551615
 587 assoc=8
 588 clk_domain=system.cpu_clk_domain
 589 demand_mshr_reserve=1
 590 eventq_index=0
 591 forward_snoops=true
 592 hit_latency=20
 593 is_top_level=false
 594 max_miss_count=0
 595 mshrs=20
 596 prefetch_on_access=false
 597 prefetcher=Null
 598 response_latency=20
 599 sequential_access=false
 600 size=2097152
 601 system=system
 602 tags=system.cpu.l2cache.tags
 603 tgts_per_mshr=12
 604 two_queue=false
 605 write_buffers=8
 606 cpu_side=system.cpu.toL2Bus.master[0]
 607 mem_side=system.membus.slave[1]
 608
 609 [system.cpu.l2cache.tags]
 610 type=LRU
 611 assoc=8
 612 block_size=64
 613 clk_domain=system.cpu_clk_domain
 614 eventq_index=0
 615 hit_latency=20
 616 sequential_access=false
 617 size=2097152
 618
 619 [system.cpu.toL2Bus]
 620 type=CoherentXBar
 621 clk_domain=system.cpu_clk_domain
 622 eventq_index=0
 623 header_cycles=1
 624 snoop_filter=Null
 625 system=system
 626 use_default_range=false
 627 width=32
 628 master=system.cpu.l2cache.cpu_side
 629 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
 630
 631 [system.cpu.tracer]
 632 type=ExeTracer
 633 eventq_index=0
 634
 635 [system.cpu.workload]
 636 type=LiveProcess
 637 cmd=mcf mcf.in
 638 cwd=build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing
 639 drivers=
 640 egid=100
 641 env=
 642 errout=cerr
 643 euid=100
 644 eventq_index=0
 645 executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/mcf
 646 gid=100
 647 input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
 648 kvmInSE=false
 649 max_stack_size=67108864
 650 output=cout
 651 pid=100
 652 ppid=99
 653 simpoint=55300000000
 654 system=system
 655 uid=100
 656 useArchPT=false
 657
 658 [system.cpu_clk_domain]
 659 type=SrcClockDomain
 660 clock=500
 661 domain_id=-1
 662 eventq_index=0
 663 init_perf_level=0
 664 voltage_domain=system.voltage_domain
 665
 666 [system.dvfs_handler]
 667 type=DVFSHandler
 668 domains=
 669 enable=false
 670 eventq_index=0
 671 sys_clk_domain=system.clk_domain
 672 transition_latency=100000000
 673
 674 [system.membus]
 675 type=CoherentXBar
 676 clk_domain=system.clk_domain
 677 eventq_index=0
 678 header_cycles=1
 679 snoop_filter=Null
 680 system=system
 681 use_default_range=false
 682 width=8
 683 master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave
 684 slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
 685
 686 [system.physmem]
 687 type=DRAMCtrl
 688 IDD0=0.075000
 689 IDD02=0.000000
 690 IDD2N=0.050000
 691 IDD2N2=0.000000
 692 IDD2P0=0.000000
 693 IDD2P02=0.000000
 694 IDD2P1=0.000000
 695 IDD2P12=0.000000
 696 IDD3N=0.057000
 697 IDD3N2=0.000000
 698 IDD3P0=0.000000
 699 IDD3P02=0.000000
 700 IDD3P1=0.000000
 701 IDD3P12=0.000000
 702 IDD4R=0.187000
 703 IDD4R2=0.000000
 704 IDD4W=0.165000
 705 IDD4W2=0.000000
 706 IDD5=0.220000
 707 IDD52=0.000000
 708 IDD6=0.000000
 709 IDD62=0.000000
 710 VDD=1.500000
 711 VDD2=0.000000
 712 activation_limit=4
 713 addr_mapping=RoRaBaChCo
 714 bank_groups_per_rank=0
 715 banks_per_rank=8
 716 burst_length=8
 717 channels=1
 718 clk_domain=system.clk_domain
 719 conf_table_reported=true
 720 device_bus_width=8
 721 device_rowbuffer_size=1024
 722 device_size=536870912
 723 devices_per_rank=8
 724 dll=true
 725 eventq_index=0
 726 in_addr_map=true
 727 max_accesses_per_row=16
 728 mem_sched_policy=frfcfs
 729 min_writes_per_switch=16
 730 null=false
 731 page_policy=open_adaptive
 732 range=0:268435455
 733 ranks_per_channel=2
 734 read_buffer_size=32
 735 static_backend_latency=10000
 736 static_frontend_latency=10000
 737 tBURST=5000
 738 tCCD_L=0
 739 tCK=1250
 740 tCL=13750
 741 tCS=2500
 742 tRAS=35000
 743 tRCD=13750
 744 tREFI=7800000
 745 tRFC=260000
 746 tRP=13750
 747 tRRD=6000
 748 tRRD_L=0
 749 tRTP=7500
 750 tRTW=2500
 751 tWR=15000
 752 tWTR=7500
 753 tXAW=30000
 754 tXP=0
 755 tXPDLL=0
 756 tXS=0
 757 tXSDLL=0
 758 write_buffer_size=64
 759 write_high_thresh_perc=85
 760 write_low_thresh_perc=50
 761 port=system.membus.master[0]
 762
 763 [system.voltage_domain]
 764 type=VoltageDomain
 765 eventq_index=0
 766 voltage=1.000000
 767