2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.061602 # Number of seconds simulated
4 sim_ticks 61602281500 # Number of ticks simulated
5 final_tick 61602281500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 60207 # Simulator instruction rate (inst/s)
8 host_op_rate 106015 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 23475786 # Simulator tick rate (ticks/s)
10 host_mem_usage 445092 # Number of bytes of host memory used
11 host_seconds 2624.08 # Real time elapsed on the host
12 sim_insts 157988547 # Number of instructions simulated
13 sim_ops 278192464 # Number of ops (including micro ops) simulated
14 system.voltage_domain.voltage 1 # Voltage in Volts
15 system.clk_domain.clock 1000 # Clock period in ticks
16 system.physmem.bytes_read::cpu.inst 63872 # Number of bytes read from this memory
17 system.physmem.bytes_read::cpu.data 1883072 # Number of bytes read from this memory
18 system.physmem.bytes_read::total 1946944 # Number of bytes read from this memory
19 system.physmem.bytes_inst_read::cpu.inst 63872 # Number of instructions bytes read from this memory
20 system.physmem.bytes_inst_read::total 63872 # Number of instructions bytes read from this memory
21 system.physmem.bytes_written::writebacks 12160 # Number of bytes written to this memory
22 system.physmem.bytes_written::total 12160 # Number of bytes written to this memory
23 system.physmem.num_reads::cpu.inst 998 # Number of read requests responded to by this memory
24 system.physmem.num_reads::cpu.data 29423 # Number of read requests responded to by this memory
25 system.physmem.num_reads::total 30421 # Number of read requests responded to by this memory
26 system.physmem.num_writes::writebacks 190 # Number of write requests responded to by this memory
27 system.physmem.num_writes::total 190 # Number of write requests responded to by this memory
28 system.physmem.bw_read::cpu.inst 1036845 # Total read bandwidth from this memory (bytes/s)
29 system.physmem.bw_read::cpu.data 30568218 # Total read bandwidth from this memory (bytes/s)
30 system.physmem.bw_read::total 31605063 # Total read bandwidth from this memory (bytes/s)
31 system.physmem.bw_inst_read::cpu.inst 1036845 # Instruction read bandwidth from this memory (bytes/s)
32 system.physmem.bw_inst_read::total 1036845 # Instruction read bandwidth from this memory (bytes/s)
33 system.physmem.bw_write::writebacks 197395 # Write bandwidth from this memory (bytes/s)
34 system.physmem.bw_write::total 197395 # Write bandwidth from this memory (bytes/s)
35 system.physmem.bw_total::writebacks 197395 # Total bandwidth to/from this memory (bytes/s)
36 system.physmem.bw_total::cpu.inst 1036845 # Total bandwidth to/from this memory (bytes/s)
37 system.physmem.bw_total::cpu.data 30568218 # Total bandwidth to/from this memory (bytes/s)
38 system.physmem.bw_total::total 31802458 # Total bandwidth to/from this memory (bytes/s)
39 system.physmem.readReqs 30421 # Number of read requests accepted
40 system.physmem.writeReqs 190 # Number of write requests accepted
41 system.physmem.readBursts 30421 # Number of DRAM read bursts, including those serviced by the write queue
42 system.physmem.writeBursts 190 # Number of DRAM write bursts, including those merged in the write queue
43 system.physmem.bytesReadDRAM 1941440 # Total number of bytes read from DRAM
44 system.physmem.bytesReadWrQ 5504 # Total number of bytes read from write queue
45 system.physmem.bytesWritten 10240 # Total number of bytes written to DRAM
46 system.physmem.bytesReadSys 1946944 # Total read bytes from the system interface side
47 system.physmem.bytesWrittenSys 12160 # Total written bytes from the system interface side
48 system.physmem.servicedByWrQ 86 # Number of DRAM read bursts serviced by the write queue
49 system.physmem.mergedWrBursts 1 # Number of DRAM write bursts merged with an existing one
50 system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
51 system.physmem.perBankRdBursts::0 1928 # Per bank write bursts
52 system.physmem.perBankRdBursts::1 2059 # Per bank write bursts
53 system.physmem.perBankRdBursts::2 2023 # Per bank write bursts
54 system.physmem.perBankRdBursts::3 1928 # Per bank write bursts
55 system.physmem.perBankRdBursts::4 2025 # Per bank write bursts
56 system.physmem.perBankRdBursts::5 1901 # Per bank write bursts
57 system.physmem.perBankRdBursts::6 1952 # Per bank write bursts
58 system.physmem.perBankRdBursts::7 1864 # Per bank write bursts
59 system.physmem.perBankRdBursts::8 1938 # Per bank write bursts
60 system.physmem.perBankRdBursts::9 1931 # Per bank write bursts
61 system.physmem.perBankRdBursts::10 1804 # Per bank write bursts
62 system.physmem.perBankRdBursts::11 1794 # Per bank write bursts
63 system.physmem.perBankRdBursts::12 1792 # Per bank write bursts
64 system.physmem.perBankRdBursts::13 1800 # Per bank write bursts
65 system.physmem.perBankRdBursts::14 1818 # Per bank write bursts
66 system.physmem.perBankRdBursts::15 1778 # Per bank write bursts
67 system.physmem.perBankWrBursts::0 10 # Per bank write bursts
68 system.physmem.perBankWrBursts::1 78 # Per bank write bursts
69 system.physmem.perBankWrBursts::2 7 # Per bank write bursts
70 system.physmem.perBankWrBursts::3 28 # Per bank write bursts
71 system.physmem.perBankWrBursts::4 6 # Per bank write bursts
72 system.physmem.perBankWrBursts::5 7 # Per bank write bursts
73 system.physmem.perBankWrBursts::6 16 # Per bank write bursts
74 system.physmem.perBankWrBursts::7 0 # Per bank write bursts
75 system.physmem.perBankWrBursts::8 0 # Per bank write bursts
76 system.physmem.perBankWrBursts::9 5 # Per bank write bursts
77 system.physmem.perBankWrBursts::10 3 # Per bank write bursts
78 system.physmem.perBankWrBursts::11 0 # Per bank write bursts
79 system.physmem.perBankWrBursts::12 0 # Per bank write bursts
80 system.physmem.perBankWrBursts::13 0 # Per bank write bursts
81 system.physmem.perBankWrBursts::14 0 # Per bank write bursts
82 system.physmem.perBankWrBursts::15 0 # Per bank write bursts
83 system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
84 system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
85 system.physmem.totGap 61602096500 # Total gap between requests
86 system.physmem.readPktSize::0 0 # Read request sizes (log2)
87 system.physmem.readPktSize::1 0 # Read request sizes (log2)
88 system.physmem.readPktSize::2 0 # Read request sizes (log2)
89 system.physmem.readPktSize::3 0 # Read request sizes (log2)
90 system.physmem.readPktSize::4 0 # Read request sizes (log2)
91 system.physmem.readPktSize::5 0 # Read request sizes (log2)
92 system.physmem.readPktSize::6 30421 # Read request sizes (log2)
93 system.physmem.writePktSize::0 0 # Write request sizes (log2)
94 system.physmem.writePktSize::1 0 # Write request sizes (log2)
95 system.physmem.writePktSize::2 0 # Write request sizes (log2)
96 system.physmem.writePktSize::3 0 # Write request sizes (log2)
97 system.physmem.writePktSize::4 0 # Write request sizes (log2)
98 system.physmem.writePktSize::5 0 # Write request sizes (log2)
99 system.physmem.writePktSize::6 190 # Write request sizes (log2)
100 system.physmem.rdQLenPdf::0 29853 # What read queue length does an incoming req see
101 system.physmem.rdQLenPdf::1 380 # What read queue length does an incoming req see
102 system.physmem.rdQLenPdf::2 85 # What read queue length does an incoming req see
103 system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see
104 system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see
105 system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
106 system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
107 system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
108 system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
109 system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
110 system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
111 system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
112 system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
113 system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
114 system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
115 system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
116 system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
117 system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
118 system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
119 system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
120 system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
121 system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
122 system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
123 system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
124 system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
125 system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
126 system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
127 system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
128 system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
129 system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
130 system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
131 system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
132 system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
133 system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
134 system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
135 system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
136 system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
137 system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
138 system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
139 system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
140 system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
141 system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
142 system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
143 system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
144 system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
145 system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
146 system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
147 system.physmem.wrQLenPdf::15 9 # What write queue length does an incoming req see
148 system.physmem.wrQLenPdf::16 9 # What write queue length does an incoming req see
149 system.physmem.wrQLenPdf::17 10 # What write queue length does an incoming req see
150 system.physmem.wrQLenPdf::18 10 # What write queue length does an incoming req see
151 system.physmem.wrQLenPdf::19 10 # What write queue length does an incoming req see
152 system.physmem.wrQLenPdf::20 10 # What write queue length does an incoming req see
153 system.physmem.wrQLenPdf::21 10 # What write queue length does an incoming req see
154 system.physmem.wrQLenPdf::22 10 # What write queue length does an incoming req see
155 system.physmem.wrQLenPdf::23 10 # What write queue length does an incoming req see
156 system.physmem.wrQLenPdf::24 10 # What write queue length does an incoming req see
157 system.physmem.wrQLenPdf::25 10 # What write queue length does an incoming req see
158 system.physmem.wrQLenPdf::26 10 # What write queue length does an incoming req see
159 system.physmem.wrQLenPdf::27 10 # What write queue length does an incoming req see
160 system.physmem.wrQLenPdf::28 10 # What write queue length does an incoming req see
161 system.physmem.wrQLenPdf::29 9 # What write queue length does an incoming req see
162 system.physmem.wrQLenPdf::30 9 # What write queue length does an incoming req see
163 system.physmem.wrQLenPdf::31 9 # What write queue length does an incoming req see
164 system.physmem.wrQLenPdf::32 9 # What write queue length does an incoming req see
165 system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
166 system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
167 system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
168 system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
169 system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
170 system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
171 system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
172 system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
173 system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
174 system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
175 system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
176 system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
177 system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
178 system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
179 system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
180 system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
181 system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
182 system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
183 system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
184 system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
185 system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
186 system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
187 system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
188 system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
189 system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
190 system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
191 system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
192 system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
193 system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
194 system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
195 system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
196 system.physmem.bytesPerActivate::samples 2721 # Bytes accessed per row activation
197 system.physmem.bytesPerActivate::mean 716.466005 # Bytes accessed per row activation
198 system.physmem.bytesPerActivate::gmean 515.355667 # Bytes accessed per row activation
199 system.physmem.bytesPerActivate::stdev 387.992511 # Bytes accessed per row activation
200 system.physmem.bytesPerActivate::0-127 365 13.41% 13.41% # Bytes accessed per row activation
201 system.physmem.bytesPerActivate::128-255 230 8.45% 21.87% # Bytes accessed per row activation
202 system.physmem.bytesPerActivate::256-383 123 4.52% 26.39% # Bytes accessed per row activation
203 system.physmem.bytesPerActivate::384-511 120 4.41% 30.80% # Bytes accessed per row activation
204 system.physmem.bytesPerActivate::512-639 92 3.38% 34.18% # Bytes accessed per row activation
205 system.physmem.bytesPerActivate::640-767 132 4.85% 39.03% # Bytes accessed per row activation
206 system.physmem.bytesPerActivate::768-895 112 4.12% 43.15% # Bytes accessed per row activation
207 system.physmem.bytesPerActivate::896-1023 67 2.46% 45.61% # Bytes accessed per row activation
208 system.physmem.bytesPerActivate::1024-1151 1480 54.39% 100.00% # Bytes accessed per row activation
209 system.physmem.bytesPerActivate::total 2721 # Bytes accessed per row activation
210 system.physmem.rdPerTurnAround::samples 9 # Reads before turning the bus around for writes
211 system.physmem.rdPerTurnAround::mean 3363.666667 # Reads before turning the bus around for writes
212 system.physmem.rdPerTurnAround::stdev 10055.376646 # Reads before turning the bus around for writes
213 system.physmem.rdPerTurnAround::0-1023 8 88.89% 88.89% # Reads before turning the bus around for writes
214 system.physmem.rdPerTurnAround::29696-30719 1 11.11% 100.00% # Reads before turning the bus around for writes
215 system.physmem.rdPerTurnAround::total 9 # Reads before turning the bus around for writes
216 system.physmem.wrPerTurnAround::samples 9 # Writes before turning the bus around for reads
217 system.physmem.wrPerTurnAround::mean 17.777778 # Writes before turning the bus around for reads
218 system.physmem.wrPerTurnAround::gmean 17.765969 # Writes before turning the bus around for reads
219 system.physmem.wrPerTurnAround::stdev 0.666667 # Writes before turning the bus around for reads
220 system.physmem.wrPerTurnAround::16 1 11.11% 11.11% # Writes before turning the bus around for reads
221 system.physmem.wrPerTurnAround::18 8 88.89% 100.00% # Writes before turning the bus around for reads
222 system.physmem.wrPerTurnAround::total 9 # Writes before turning the bus around for reads
223 system.physmem.totQLat 133021500 # Total ticks spent queuing
224 system.physmem.totMemAccLat 701802750 # Total ticks spent from burst creation until serviced by the DRAM
225 system.physmem.totBusLat 151675000 # Total ticks spent in databus transfers
226 system.physmem.avgQLat 4385.08 # Average queueing delay per DRAM burst
227 system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
228 system.physmem.avgMemAccLat 23135.08 # Average memory access latency per DRAM burst
229 system.physmem.avgRdBW 31.52 # Average DRAM read bandwidth in MiByte/s
230 system.physmem.avgWrBW 0.17 # Average achieved write bandwidth in MiByte/s
231 system.physmem.avgRdBWSys 31.61 # Average system read bandwidth in MiByte/s
232 system.physmem.avgWrBWSys 0.20 # Average system write bandwidth in MiByte/s
233 system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
234 system.physmem.busUtil 0.25 # Data bus utilization in percentage
235 system.physmem.busUtilRead 0.25 # Data bus utilization in percentage for reads
236 system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
237 system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing
238 system.physmem.avgWrQLen 15.67 # Average write queue length when enqueuing
239 system.physmem.readRowHits 27658 # Number of row buffer hits during reads
240 system.physmem.writeRowHits 106 # Number of row buffer hits during writes
241 system.physmem.readRowHitRate 91.18 # Row buffer hit rate for reads
242 system.physmem.writeRowHitRate 56.08 # Row buffer hit rate for writes
243 system.physmem.avgGap 2012416.99 # Average gap between requests
244 system.physmem.pageHitRate 90.96 # Row buffer hit rate, read and write combined
245 system.physmem_0.actEnergy 10924200 # Energy for activate commands per rank (pJ)
246 system.physmem_0.preEnergy 5960625 # Energy for precharge commands per rank (pJ)
247 system.physmem_0.readEnergy 121984200 # Energy for read commands per rank (pJ)
248 system.physmem_0.writeEnergy 984960 # Energy for write commands per rank (pJ)
249 system.physmem_0.refreshEnergy 4023218160 # Energy for refresh commands per rank (pJ)
250 system.physmem_0.actBackEnergy 2835924705 # Energy for active background per rank (pJ)
251 system.physmem_0.preBackEnergy 34470717000 # Energy for precharge background per rank (pJ)
252 system.physmem_0.totalEnergy 41469713850 # Total energy per rank (pJ)
253 system.physmem_0.averagePower 673.239327 # Core power per rank (mW)
254 system.physmem_0.memoryStateTime::IDLE 57330547250 # Time in different power states
255 system.physmem_0.memoryStateTime::REF 2056860000 # Time in different power states
256 system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
257 system.physmem_0.memoryStateTime::ACT 2211196750 # Time in different power states
258 system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
259 system.physmem_1.actEnergy 9608760 # Energy for activate commands per rank (pJ)
260 system.physmem_1.preEnergy 5242875 # Energy for precharge commands per rank (pJ)
261 system.physmem_1.readEnergy 114199800 # Energy for read commands per rank (pJ)
262 system.physmem_1.writeEnergy 51840 # Energy for write commands per rank (pJ)
263 system.physmem_1.refreshEnergy 4023218160 # Energy for refresh commands per rank (pJ)
264 system.physmem_1.actBackEnergy 3020047245 # Energy for active background per rank (pJ)
265 system.physmem_1.preBackEnergy 34309197750 # Energy for precharge background per rank (pJ)
266 system.physmem_1.totalEnergy 41481566430 # Total energy per rank (pJ)
267 system.physmem_1.averagePower 673.431898 # Core power per rank (mW)
268 system.physmem_1.memoryStateTime::IDLE 57061053250 # Time in different power states
269 system.physmem_1.memoryStateTime::REF 2056860000 # Time in different power states
270 system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
271 system.physmem_1.memoryStateTime::ACT 2480893250 # Time in different power states
272 system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
273 system.cpu.branchPred.lookups 36908905 # Number of BP lookups
274 system.cpu.branchPred.condPredicted 36908905 # Number of conditional branches predicted
275 system.cpu.branchPred.condIncorrect 741640 # Number of conditional branches incorrect
276 system.cpu.branchPred.BTBLookups 21094596 # Number of BTB lookups
277 system.cpu.branchPred.BTBHits 21013333 # Number of BTB hits
278 system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
279 system.cpu.branchPred.BTBHitPct 99.614769 # BTB Hit Percentage
280 system.cpu.branchPred.usedRAS 5443330 # Number of times the RAS was used to get a target.
281 system.cpu.branchPred.RASInCorrect 4414 # Number of incorrect RAS predictions.
282 system.cpu_clk_domain.clock 500 # Clock period in ticks
283 system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
284 system.cpu.workload.num_syscalls 444 # Number of system calls
285 system.cpu.numCycles 123204564 # number of cpu cycles simulated
286 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
287 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
288 system.cpu.fetch.icacheStallCycles 27815555 # Number of cycles fetch is stalled on an Icache miss
289 system.cpu.fetch.Insts 199030250 # Number of instructions fetch has processed
290 system.cpu.fetch.Branches 36908905 # Number of branches that fetch encountered
291 system.cpu.fetch.predictedBranches 26456663 # Number of branches that fetch has predicted taken
292 system.cpu.fetch.Cycles 94541896 # Number of cycles fetch has run and was not squashing or blocked
293 system.cpu.fetch.SquashCycles 1553195 # Number of cycles fetch has spent squashing
294 system.cpu.fetch.MiscStallCycles 366 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
295 system.cpu.fetch.PendingTrapStallCycles 5275 # Number of stall cycles due to pending traps
296 system.cpu.fetch.PendingQuiesceStallCycles 14 # Number of stall cycles due to pending quiesce instructions
297 system.cpu.fetch.CacheLines 27443897 # Number of cache lines fetched
298 system.cpu.fetch.IcacheSquashes 182895 # Number of outstanding Icache misses that were squashed
299 system.cpu.fetch.rateDist::samples 123139703 # Number of instructions fetched each cycle (Total)
300 system.cpu.fetch.rateDist::mean 2.847279 # Number of instructions fetched each cycle (Total)
301 system.cpu.fetch.rateDist::stdev 3.366421 # Number of instructions fetched each cycle (Total)
302 system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
303 system.cpu.fetch.rateDist::0 62945303 51.12% 51.12% # Number of instructions fetched each cycle (Total)
304 system.cpu.fetch.rateDist::1 3649645 2.96% 54.08% # Number of instructions fetched each cycle (Total)
305 system.cpu.fetch.rateDist::2 3480674 2.83% 56.91% # Number of instructions fetched each cycle (Total)
306 system.cpu.fetch.rateDist::3 5913881 4.80% 61.71% # Number of instructions fetched each cycle (Total)
307 system.cpu.fetch.rateDist::4 7544216 6.13% 67.84% # Number of instructions fetched each cycle (Total)
308 system.cpu.fetch.rateDist::5 5413971 4.40% 72.23% # Number of instructions fetched each cycle (Total)
309 system.cpu.fetch.rateDist::6 3251108 2.64% 74.87% # Number of instructions fetched each cycle (Total)
310 system.cpu.fetch.rateDist::7 2020095 1.64% 76.51% # Number of instructions fetched each cycle (Total)
311 system.cpu.fetch.rateDist::8 28920810 23.49% 100.00% # Number of instructions fetched each cycle (Total)
312 system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
313 system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
314 system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
315 system.cpu.fetch.rateDist::total 123139703 # Number of instructions fetched each cycle (Total)
316 system.cpu.fetch.branchRate 0.299574 # Number of branch fetches per cycle
317 system.cpu.fetch.rate 1.615445 # Number of inst fetches per cycle
318 system.cpu.decode.IdleCycles 12941515 # Number of cycles decode is idle
319 system.cpu.decode.BlockedCycles 63708297 # Number of cycles decode is blocked
320 system.cpu.decode.RunCycles 35887575 # Number of cycles decode is running
321 system.cpu.decode.UnblockCycles 9825719 # Number of cycles decode is unblocking
322 system.cpu.decode.SquashCycles 776597 # Number of cycles decode is squashing
323 system.cpu.decode.DecodedInsts 331225446 # Number of instructions handled by decode
324 system.cpu.rename.SquashCycles 776597 # Number of cycles rename is squashing
325 system.cpu.rename.IdleCycles 18253426 # Number of cycles rename is idle
326 system.cpu.rename.BlockCycles 8529207 # Number of cycles rename is blocking
327 system.cpu.rename.serializeStallCycles 16791 # count of cycles rename stalled for serializing inst
328 system.cpu.rename.RunCycles 40202725 # Number of cycles rename is running
329 system.cpu.rename.UnblockCycles 55360957 # Number of cycles rename is unblocking
330 system.cpu.rename.RenamedInsts 325142954 # Number of instructions processed by rename
331 system.cpu.rename.ROBFullEvents 1786 # Number of times rename has blocked due to ROB full
332 system.cpu.rename.IQFullEvents 778303 # Number of times rename has blocked due to IQ full
333 system.cpu.rename.LQFullEvents 48626694 # Number of times rename has blocked due to LQ full
334 system.cpu.rename.SQFullEvents 4947433 # Number of times rename has blocked due to SQ full
335 system.cpu.rename.RenamedOperands 327068188 # Number of destination operands rename has renamed
336 system.cpu.rename.RenameLookups 863737810 # Number of register rename lookups that rename has made
337 system.cpu.rename.int_rename_lookups 532004029 # Number of integer rename lookups
338 system.cpu.rename.fp_rename_lookups 425 # Number of floating rename lookups
339 system.cpu.rename.CommittedMaps 279212747 # Number of HB maps that are committed
340 system.cpu.rename.UndoneMaps 47855441 # Number of HB maps that are undone due to squashing
341 system.cpu.rename.serializingInsts 492 # count of serializing insts renamed
342 system.cpu.rename.tempSerializingInsts 490 # count of temporary serializing insts renamed
343 system.cpu.rename.skidInsts 66412323 # count of insts added to the skid buffer
344 system.cpu.memDep0.insertedLoads 105336194 # Number of loads inserted to the mem dependence unit.
345 system.cpu.memDep0.insertedStores 36169392 # Number of stores inserted to the mem dependence unit.
346 system.cpu.memDep0.conflictingLoads 49401722 # Number of conflicting loads.
347 system.cpu.memDep0.conflictingStores 8500449 # Number of conflicting stores.
348 system.cpu.iq.iqInstsAdded 322301392 # Number of instructions added to the IQ (excludes non-spec)
349 system.cpu.iq.iqNonSpecInstsAdded 2340 # Number of non-speculative instructions added to the IQ
350 system.cpu.iq.iqInstsIssued 306103027 # Number of instructions issued
351 system.cpu.iq.iqSquashedInstsIssued 45906 # Number of squashed instructions issued
352 system.cpu.iq.iqSquashedInstsExamined 44111268 # Number of squashed instructions iterated over during squash; mainly for profiling
353 system.cpu.iq.iqSquashedOperandsExamined 63882734 # Number of squashed operands that are examined and possibly removed from graph
354 system.cpu.iq.iqSquashedNonSpecRemoved 1895 # Number of squashed non-spec instructions that were removed
355 system.cpu.iq.issued_per_cycle::samples 123139703 # Number of insts issued each cycle
356 system.cpu.iq.issued_per_cycle::mean 2.485819 # Number of insts issued each cycle
357 system.cpu.iq.issued_per_cycle::stdev 2.139102 # Number of insts issued each cycle
358 system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
359 system.cpu.iq.issued_per_cycle::0 30259811 24.57% 24.57% # Number of insts issued each cycle
360 system.cpu.iq.issued_per_cycle::1 19566759 15.89% 40.46% # Number of insts issued each cycle
361 system.cpu.iq.issued_per_cycle::2 16687041 13.55% 54.01% # Number of insts issued each cycle
362 system.cpu.iq.issued_per_cycle::3 17331203 14.07% 68.09% # Number of insts issued each cycle
363 system.cpu.iq.issued_per_cycle::4 14759381 11.99% 80.08% # Number of insts issued each cycle
364 system.cpu.iq.issued_per_cycle::5 12567446 10.21% 90.28% # Number of insts issued each cycle
365 system.cpu.iq.issued_per_cycle::6 6273248 5.09% 95.38% # Number of insts issued each cycle
366 system.cpu.iq.issued_per_cycle::7 3904177 3.17% 98.55% # Number of insts issued each cycle
367 system.cpu.iq.issued_per_cycle::8 1790637 1.45% 100.00% # Number of insts issued each cycle
368 system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
369 system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
370 system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
371 system.cpu.iq.issued_per_cycle::total 123139703 # Number of insts issued each cycle
372 system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
373 system.cpu.iq.fu_full::IntAlu 338800 8.53% 8.53% # attempts to use FU when none available
374 system.cpu.iq.fu_full::IntMult 0 0.00% 8.53% # attempts to use FU when none available
375 system.cpu.iq.fu_full::IntDiv 0 0.00% 8.53% # attempts to use FU when none available
376 system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.53% # attempts to use FU when none available
377 system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.53% # attempts to use FU when none available
378 system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.53% # attempts to use FU when none available
379 system.cpu.iq.fu_full::FloatMult 0 0.00% 8.53% # attempts to use FU when none available
380 system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.53% # attempts to use FU when none available
381 system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.53% # attempts to use FU when none available
382 system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.53% # attempts to use FU when none available
383 system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.53% # attempts to use FU when none available
384 system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.53% # attempts to use FU when none available
385 system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.53% # attempts to use FU when none available
386 system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.53% # attempts to use FU when none available
387 system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.53% # attempts to use FU when none available
388 system.cpu.iq.fu_full::SimdMult 0 0.00% 8.53% # attempts to use FU when none available
389 system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.53% # attempts to use FU when none available
390 system.cpu.iq.fu_full::SimdShift 0 0.00% 8.53% # attempts to use FU when none available
391 system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.53% # attempts to use FU when none available
392 system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.53% # attempts to use FU when none available
393 system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.53% # attempts to use FU when none available
394 system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.53% # attempts to use FU when none available
395 system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.53% # attempts to use FU when none available
396 system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.53% # attempts to use FU when none available
397 system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.53% # attempts to use FU when none available
398 system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.53% # attempts to use FU when none available
399 system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.53% # attempts to use FU when none available
400 system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.53% # attempts to use FU when none available
401 system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.53% # attempts to use FU when none available
402 system.cpu.iq.fu_full::MemRead 3433517 86.49% 95.02% # attempts to use FU when none available
403 system.cpu.iq.fu_full::MemWrite 197610 4.98% 100.00% # attempts to use FU when none available
404 system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
405 system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
406 system.cpu.iq.FU_type_0::No_OpClass 33341 0.01% 0.01% # Type of FU issued
407 system.cpu.iq.FU_type_0::IntAlu 174121950 56.88% 56.89% # Type of FU issued
408 system.cpu.iq.FU_type_0::IntMult 11182 0.00% 56.90% # Type of FU issued
409 system.cpu.iq.FU_type_0::IntDiv 343 0.00% 56.90% # Type of FU issued
410 system.cpu.iq.FU_type_0::FloatAdd 31 0.00% 56.90% # Type of FU issued
411 system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.90% # Type of FU issued
412 system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.90% # Type of FU issued
413 system.cpu.iq.FU_type_0::FloatMult 0 0.00% 56.90% # Type of FU issued
414 system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 56.90% # Type of FU issued
415 system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.90% # Type of FU issued
416 system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.90% # Type of FU issued
417 system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.90% # Type of FU issued
418 system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.90% # Type of FU issued
419 system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.90% # Type of FU issued
420 system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.90% # Type of FU issued
421 system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.90% # Type of FU issued
422 system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.90% # Type of FU issued
423 system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.90% # Type of FU issued
424 system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.90% # Type of FU issued
425 system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.90% # Type of FU issued
426 system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.90% # Type of FU issued
427 system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.90% # Type of FU issued
428 system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.90% # Type of FU issued
429 system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.90% # Type of FU issued
430 system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.90% # Type of FU issued
431 system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.90% # Type of FU issued
432 system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.90% # Type of FU issued
433 system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.90% # Type of FU issued
434 system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.90% # Type of FU issued
435 system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.90% # Type of FU issued
436 system.cpu.iq.FU_type_0::MemRead 98066351 32.04% 88.94% # Type of FU issued
437 system.cpu.iq.FU_type_0::MemWrite 33869829 11.06% 100.00% # Type of FU issued
438 system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
439 system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
440 system.cpu.iq.FU_type_0::total 306103027 # Type of FU issued
441 system.cpu.iq.rate 2.484510 # Inst issue rate
442 system.cpu.iq.fu_busy_cnt 3969927 # FU busy when requested
443 system.cpu.iq.fu_busy_rate 0.012969 # FU busy rate (busy events/executed inst)
444 system.cpu.iq.int_inst_queue_reads 739361233 # Number of integer instruction queue reads
445 system.cpu.iq.int_inst_queue_writes 366454635 # Number of integer instruction queue writes
446 system.cpu.iq.int_inst_queue_wakeup_accesses 304282658 # Number of integer instruction queue wakeup accesses
447 system.cpu.iq.fp_inst_queue_reads 357 # Number of floating instruction queue reads
448 system.cpu.iq.fp_inst_queue_writes 618 # Number of floating instruction queue writes
449 system.cpu.iq.fp_inst_queue_wakeup_accesses 133 # Number of floating instruction queue wakeup accesses
450 system.cpu.iq.int_alu_accesses 310039433 # Number of integer alu accesses
451 system.cpu.iq.fp_alu_accesses 180 # Number of floating point alu accesses
452 system.cpu.iew.lsq.thread0.forwLoads 58196288 # Number of loads that had data forwarded from stores
453 system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
454 system.cpu.iew.lsq.thread0.squashedLoads 14556809 # Number of loads squashed
455 system.cpu.iew.lsq.thread0.ignoredResponses 63678 # Number of memory responses ignored because the instruction is squashed
456 system.cpu.iew.lsq.thread0.memOrderViolation 41328 # Number of memory ordering violations
457 system.cpu.iew.lsq.thread0.squashedStores 4729640 # Number of stores squashed
458 system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
459 system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
460 system.cpu.iew.lsq.thread0.rescheduledLoads 3641 # Number of loads that were rescheduled
461 system.cpu.iew.lsq.thread0.cacheBlocked 141544 # Number of times an access to memory failed due to the cache being blocked
462 system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
463 system.cpu.iew.iewSquashCycles 776597 # Number of cycles IEW is squashing
464 system.cpu.iew.iewBlockCycles 5329160 # Number of cycles IEW is blocking
465 system.cpu.iew.iewUnblockCycles 3100599 # Number of cycles IEW is unblocking
466 system.cpu.iew.iewDispatchedInsts 322303732 # Number of instructions dispatched to IQ
467 system.cpu.iew.iewDispSquashedInsts 76830 # Number of squashed instructions skipped by dispatch
468 system.cpu.iew.iewDispLoadInsts 105336194 # Number of dispatched load instructions
469 system.cpu.iew.iewDispStoreInsts 36169392 # Number of dispatched store instructions
470 system.cpu.iew.iewDispNonSpecInsts 1101 # Number of dispatched non-speculative instructions
471 system.cpu.iew.iewIQFullEvents 2588 # Number of times the IQ has become full, causing a stall
472 system.cpu.iew.iewLSQFullEvents 3102623 # Number of times the LSQ has become full, causing a stall
473 system.cpu.iew.memOrderViolationEvents 41328 # Number of memory order violations
474 system.cpu.iew.predictedTakenIncorrect 371679 # Number of branches that were predicted taken incorrectly
475 system.cpu.iew.predictedNotTakenIncorrect 414776 # Number of branches that were predicted not taken incorrectly
476 system.cpu.iew.branchMispredicts 786455 # Number of branch mispredicts detected at execute
477 system.cpu.iew.iewExecutedInsts 305156727 # Number of executed instructions
478 system.cpu.iew.iewExecLoadInsts 97750586 # Number of load instructions executed
479 system.cpu.iew.iewExecSquashedInsts 946300 # Number of squashed instructions skipped in execute
480 system.cpu.iew.exec_swp 0 # number of swp insts executed
481 system.cpu.iew.exec_nop 0 # number of nop insts executed
482 system.cpu.iew.exec_refs 131430384 # number of memory reference insts executed
483 system.cpu.iew.exec_branches 31401849 # Number of branches executed
484 system.cpu.iew.exec_stores 33679798 # Number of stores executed
485 system.cpu.iew.exec_rate 2.476830 # Inst execution rate
486 system.cpu.iew.wb_sent 304565843 # cumulative count of insts sent to commit
487 system.cpu.iew.wb_count 304282791 # cumulative count of insts written-back
488 system.cpu.iew.wb_producers 230213909 # num instructions producing a value
489 system.cpu.iew.wb_consumers 333860423 # num instructions consuming a value
490 system.cpu.iew.wb_rate 2.469736 # insts written-back per cycle
491 system.cpu.iew.wb_fanout 0.689551 # average fanout of values written-back
492 system.cpu.commit.commitSquashedInsts 44209690 # The number of squashed insts skipped by commit
493 system.cpu.commit.commitNonSpecStalls 445 # The number of times commit has been forced to stall to communicate backwards
494 system.cpu.commit.branchMispredicts 742008 # The number of times a branch was mispredicted
495 system.cpu.commit.committed_per_cycle::samples 117118936 # Number of insts commited each cycle
496 system.cpu.commit.committed_per_cycle::mean 2.375299 # Number of insts commited each cycle
497 system.cpu.commit.committed_per_cycle::stdev 3.092759 # Number of insts commited each cycle
498 system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
499 system.cpu.commit.committed_per_cycle::0 52925822 45.19% 45.19% # Number of insts commited each cycle
500 system.cpu.commit.committed_per_cycle::1 15815600 13.50% 58.69% # Number of insts commited each cycle
501 system.cpu.commit.committed_per_cycle::2 10978628 9.37% 68.07% # Number of insts commited each cycle
502 system.cpu.commit.committed_per_cycle::3 8749337 7.47% 75.54% # Number of insts commited each cycle
503 system.cpu.commit.committed_per_cycle::4 1860126 1.59% 77.13% # Number of insts commited each cycle
504 system.cpu.commit.committed_per_cycle::5 1720772 1.47% 78.60% # Number of insts commited each cycle
505 system.cpu.commit.committed_per_cycle::6 865935 0.74% 79.33% # Number of insts commited each cycle
506 system.cpu.commit.committed_per_cycle::7 690105 0.59% 79.92% # Number of insts commited each cycle
507 system.cpu.commit.committed_per_cycle::8 23512611 20.08% 100.00% # Number of insts commited each cycle
508 system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
509 system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
510 system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
511 system.cpu.commit.committed_per_cycle::total 117118936 # Number of insts commited each cycle
512 system.cpu.commit.committedInsts 157988547 # Number of instructions committed
513 system.cpu.commit.committedOps 278192464 # Number of ops (including micro ops) committed
514 system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
515 system.cpu.commit.refs 122219137 # Number of memory references committed
516 system.cpu.commit.loads 90779385 # Number of loads committed
517 system.cpu.commit.membars 0 # Number of memory barriers committed
518 system.cpu.commit.branches 29309705 # Number of branches committed
519 system.cpu.commit.fp_insts 40 # Number of committed floating point instructions.
520 system.cpu.commit.int_insts 278169481 # Number of committed integer instructions.
521 system.cpu.commit.function_calls 4237596 # Number of function calls committed.
522 system.cpu.commit.op_class_0::No_OpClass 16695 0.01% 0.01% # Class of committed instruction
523 system.cpu.commit.op_class_0::IntAlu 155945353 56.06% 56.06% # Class of committed instruction
524 system.cpu.commit.op_class_0::IntMult 10938 0.00% 56.07% # Class of committed instruction
525 system.cpu.commit.op_class_0::IntDiv 329 0.00% 56.07% # Class of committed instruction
526 system.cpu.commit.op_class_0::FloatAdd 12 0.00% 56.07% # Class of committed instruction
527 system.cpu.commit.op_class_0::FloatCmp 0 0.00% 56.07% # Class of committed instruction
528 system.cpu.commit.op_class_0::FloatCvt 0 0.00% 56.07% # Class of committed instruction
529 system.cpu.commit.op_class_0::FloatMult 0 0.00% 56.07% # Class of committed instruction
530 system.cpu.commit.op_class_0::FloatDiv 0 0.00% 56.07% # Class of committed instruction
531 system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 56.07% # Class of committed instruction
532 system.cpu.commit.op_class_0::SimdAdd 0 0.00% 56.07% # Class of committed instruction
533 system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 56.07% # Class of committed instruction
534 system.cpu.commit.op_class_0::SimdAlu 0 0.00% 56.07% # Class of committed instruction
535 system.cpu.commit.op_class_0::SimdCmp 0 0.00% 56.07% # Class of committed instruction
536 system.cpu.commit.op_class_0::SimdCvt 0 0.00% 56.07% # Class of committed instruction
537 system.cpu.commit.op_class_0::SimdMisc 0 0.00% 56.07% # Class of committed instruction
538 system.cpu.commit.op_class_0::SimdMult 0 0.00% 56.07% # Class of committed instruction
539 system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 56.07% # Class of committed instruction
540 system.cpu.commit.op_class_0::SimdShift 0 0.00% 56.07% # Class of committed instruction
541 system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 56.07% # Class of committed instruction
542 system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 56.07% # Class of committed instruction
543 system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 56.07% # Class of committed instruction
544 system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 56.07% # Class of committed instruction
545 system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 56.07% # Class of committed instruction
546 system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 56.07% # Class of committed instruction
547 system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 56.07% # Class of committed instruction
548 system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 56.07% # Class of committed instruction
549 system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 56.07% # Class of committed instruction
550 system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 56.07% # Class of committed instruction
551 system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 56.07% # Class of committed instruction
552 system.cpu.commit.op_class_0::MemRead 90779385 32.63% 88.70% # Class of committed instruction
553 system.cpu.commit.op_class_0::MemWrite 31439752 11.30% 100.00% # Class of committed instruction
554 system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
555 system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
556 system.cpu.commit.op_class_0::total 278192464 # Class of committed instruction
557 system.cpu.commit.bw_lim_events 23512611 # number cycles where commit BW limit reached
558 system.cpu.rob.rob_reads 416008479 # The number of ROB reads
559 system.cpu.rob.rob_writes 650833820 # The number of ROB writes
560 system.cpu.timesIdled 568 # Number of times that the entire CPU went into an idle state and unscheduled itself
561 system.cpu.idleCycles 64861 # Total number of cycles that the CPU has spent unscheduled due to idling
562 system.cpu.committedInsts 157988547 # Number of Instructions Simulated
563 system.cpu.committedOps 278192464 # Number of Ops (including micro ops) Simulated
564 system.cpu.cpi 0.779832 # CPI: Cycles Per Instruction
565 system.cpu.cpi_total 0.779832 # CPI: Total CPI of All Threads
566 system.cpu.ipc 1.282327 # IPC: Instructions Per Cycle
567 system.cpu.ipc_total 1.282327 # IPC: Total IPC of All Threads
568 system.cpu.int_regfile_reads 491477136 # number of integer regfile reads
569 system.cpu.int_regfile_writes 239432261 # number of integer regfile writes
570 system.cpu.fp_regfile_reads 110 # number of floating regfile reads
571 system.cpu.fp_regfile_writes 84 # number of floating regfile writes
572 system.cpu.cc_regfile_reads 107533030 # number of cc regfile reads
573 system.cpu.cc_regfile_writes 64416979 # number of cc regfile writes
574 system.cpu.misc_regfile_reads 195275946 # number of misc regfile reads
575 system.cpu.misc_regfile_writes 1 # number of misc regfile writes
576 system.cpu.dcache.tags.replacements 2072312 # number of replacements
577 system.cpu.dcache.tags.tagsinuse 4068.008256 # Cycle average of tags in use
578 system.cpu.dcache.tags.total_refs 68071038 # Total number of references to valid blocks.
579 system.cpu.dcache.tags.sampled_refs 2076408 # Sample count of references to valid blocks.
580 system.cpu.dcache.tags.avg_refs 32.783074 # Average number of references to valid blocks.
581 system.cpu.dcache.tags.warmup_cycle 19455459500 # Cycle when the warmup percentage was hit.
582 system.cpu.dcache.tags.occ_blocks::cpu.data 4068.008256 # Average occupied blocks per requestor
583 system.cpu.dcache.tags.occ_percent::cpu.data 0.993166 # Average percentage of cache occupancy
584 system.cpu.dcache.tags.occ_percent::total 0.993166 # Average percentage of cache occupancy
585 system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
586 system.cpu.dcache.tags.age_task_id_blocks_1024::0 633 # Occupied blocks per task id
587 system.cpu.dcache.tags.age_task_id_blocks_1024::1 3336 # Occupied blocks per task id
588 system.cpu.dcache.tags.age_task_id_blocks_1024::2 127 # Occupied blocks per task id
589 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
590 system.cpu.dcache.tags.tag_accesses 143788642 # Number of tag accesses
591 system.cpu.dcache.tags.data_accesses 143788642 # Number of data accesses
592 system.cpu.dcache.ReadReq_hits::cpu.data 36725212 # number of ReadReq hits
593 system.cpu.dcache.ReadReq_hits::total 36725212 # number of ReadReq hits
594 system.cpu.dcache.WriteReq_hits::cpu.data 31345825 # number of WriteReq hits
595 system.cpu.dcache.WriteReq_hits::total 31345825 # number of WriteReq hits
596 system.cpu.dcache.demand_hits::cpu.data 68071037 # number of demand (read+write) hits
597 system.cpu.dcache.demand_hits::total 68071037 # number of demand (read+write) hits
598 system.cpu.dcache.overall_hits::cpu.data 68071037 # number of overall hits
599 system.cpu.dcache.overall_hits::total 68071037 # number of overall hits
600 system.cpu.dcache.ReadReq_misses::cpu.data 2691153 # number of ReadReq misses
601 system.cpu.dcache.ReadReq_misses::total 2691153 # number of ReadReq misses
602 system.cpu.dcache.WriteReq_misses::cpu.data 93927 # number of WriteReq misses
603 system.cpu.dcache.WriteReq_misses::total 93927 # number of WriteReq misses
604 system.cpu.dcache.demand_misses::cpu.data 2785080 # number of demand (read+write) misses
605 system.cpu.dcache.demand_misses::total 2785080 # number of demand (read+write) misses
606 system.cpu.dcache.overall_misses::cpu.data 2785080 # number of overall misses
607 system.cpu.dcache.overall_misses::total 2785080 # number of overall misses
608 system.cpu.dcache.ReadReq_miss_latency::cpu.data 32304195500 # number of ReadReq miss cycles
609 system.cpu.dcache.ReadReq_miss_latency::total 32304195500 # number of ReadReq miss cycles
610 system.cpu.dcache.WriteReq_miss_latency::cpu.data 2956614994 # number of WriteReq miss cycles
611 system.cpu.dcache.WriteReq_miss_latency::total 2956614994 # number of WriteReq miss cycles
612 system.cpu.dcache.demand_miss_latency::cpu.data 35260810494 # number of demand (read+write) miss cycles
613 system.cpu.dcache.demand_miss_latency::total 35260810494 # number of demand (read+write) miss cycles
614 system.cpu.dcache.overall_miss_latency::cpu.data 35260810494 # number of overall miss cycles
615 system.cpu.dcache.overall_miss_latency::total 35260810494 # number of overall miss cycles
616 system.cpu.dcache.ReadReq_accesses::cpu.data 39416365 # number of ReadReq accesses(hits+misses)
617 system.cpu.dcache.ReadReq_accesses::total 39416365 # number of ReadReq accesses(hits+misses)
618 system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses)
619 system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses)
620 system.cpu.dcache.demand_accesses::cpu.data 70856117 # number of demand (read+write) accesses
621 system.cpu.dcache.demand_accesses::total 70856117 # number of demand (read+write) accesses
622 system.cpu.dcache.overall_accesses::cpu.data 70856117 # number of overall (read+write) accesses
623 system.cpu.dcache.overall_accesses::total 70856117 # number of overall (read+write) accesses
624 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.068275 # miss rate for ReadReq accesses
625 system.cpu.dcache.ReadReq_miss_rate::total 0.068275 # miss rate for ReadReq accesses
626 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002988 # miss rate for WriteReq accesses
627 system.cpu.dcache.WriteReq_miss_rate::total 0.002988 # miss rate for WriteReq accesses
628 system.cpu.dcache.demand_miss_rate::cpu.data 0.039306 # miss rate for demand accesses
629 system.cpu.dcache.demand_miss_rate::total 0.039306 # miss rate for demand accesses
630 system.cpu.dcache.overall_miss_rate::cpu.data 0.039306 # miss rate for overall accesses
631 system.cpu.dcache.overall_miss_rate::total 0.039306 # miss rate for overall accesses
632 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12003.849465 # average ReadReq miss latency
633 system.cpu.dcache.ReadReq_avg_miss_latency::total 12003.849465 # average ReadReq miss latency
634 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31477.796523 # average WriteReq miss latency
635 system.cpu.dcache.WriteReq_avg_miss_latency::total 31477.796523 # average WriteReq miss latency
636 system.cpu.dcache.demand_avg_miss_latency::cpu.data 12660.609567 # average overall miss latency
637 system.cpu.dcache.demand_avg_miss_latency::total 12660.609567 # average overall miss latency
638 system.cpu.dcache.overall_avg_miss_latency::cpu.data 12660.609567 # average overall miss latency
639 system.cpu.dcache.overall_avg_miss_latency::total 12660.609567 # average overall miss latency
640 system.cpu.dcache.blocked_cycles::no_mshrs 221476 # number of cycles access was blocked
641 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
642 system.cpu.dcache.blocked::no_mshrs 43220 # number of cycles access was blocked
643 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
644 system.cpu.dcache.avg_blocked_cycles::no_mshrs 5.124387 # average number of cycles each access was blocked
645 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
646 system.cpu.dcache.fast_writes 0 # number of fast writes performed
647 system.cpu.dcache.cache_copies 0 # number of cache copies performed
648 system.cpu.dcache.writebacks::writebacks 2066601 # number of writebacks
649 system.cpu.dcache.writebacks::total 2066601 # number of writebacks
650 system.cpu.dcache.ReadReq_mshr_hits::cpu.data 696788 # number of ReadReq MSHR hits
651 system.cpu.dcache.ReadReq_mshr_hits::total 696788 # number of ReadReq MSHR hits
652 system.cpu.dcache.WriteReq_mshr_hits::cpu.data 11883 # number of WriteReq MSHR hits
653 system.cpu.dcache.WriteReq_mshr_hits::total 11883 # number of WriteReq MSHR hits
654 system.cpu.dcache.demand_mshr_hits::cpu.data 708671 # number of demand (read+write) MSHR hits
655 system.cpu.dcache.demand_mshr_hits::total 708671 # number of demand (read+write) MSHR hits
656 system.cpu.dcache.overall_mshr_hits::cpu.data 708671 # number of overall MSHR hits
657 system.cpu.dcache.overall_mshr_hits::total 708671 # number of overall MSHR hits
658 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994365 # number of ReadReq MSHR misses
659 system.cpu.dcache.ReadReq_mshr_misses::total 1994365 # number of ReadReq MSHR misses
660 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82044 # number of WriteReq MSHR misses
661 system.cpu.dcache.WriteReq_mshr_misses::total 82044 # number of WriteReq MSHR misses
662 system.cpu.dcache.demand_mshr_misses::cpu.data 2076409 # number of demand (read+write) MSHR misses
663 system.cpu.dcache.demand_mshr_misses::total 2076409 # number of demand (read+write) MSHR misses
664 system.cpu.dcache.overall_mshr_misses::cpu.data 2076409 # number of overall MSHR misses
665 system.cpu.dcache.overall_mshr_misses::total 2076409 # number of overall MSHR misses
666 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24195923000 # number of ReadReq MSHR miss cycles
667 system.cpu.dcache.ReadReq_mshr_miss_latency::total 24195923000 # number of ReadReq MSHR miss cycles
668 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2799396995 # number of WriteReq MSHR miss cycles
669 system.cpu.dcache.WriteReq_mshr_miss_latency::total 2799396995 # number of WriteReq MSHR miss cycles
670 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26995319995 # number of demand (read+write) MSHR miss cycles
671 system.cpu.dcache.demand_mshr_miss_latency::total 26995319995 # number of demand (read+write) MSHR miss cycles
672 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26995319995 # number of overall MSHR miss cycles
673 system.cpu.dcache.overall_mshr_miss_latency::total 26995319995 # number of overall MSHR miss cycles
674 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.050597 # mshr miss rate for ReadReq accesses
675 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.050597 # mshr miss rate for ReadReq accesses
676 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002610 # mshr miss rate for WriteReq accesses
677 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002610 # mshr miss rate for WriteReq accesses
678 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.029305 # mshr miss rate for demand accesses
679 system.cpu.dcache.demand_mshr_miss_rate::total 0.029305 # mshr miss rate for demand accesses
680 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.029305 # mshr miss rate for overall accesses
681 system.cpu.dcache.overall_mshr_miss_rate::total 0.029305 # mshr miss rate for overall accesses
682 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12132.143815 # average ReadReq mshr miss latency
683 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12132.143815 # average ReadReq mshr miss latency
684 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34120.679087 # average WriteReq mshr miss latency
685 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34120.679087 # average WriteReq mshr miss latency
686 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13000.964644 # average overall mshr miss latency
687 system.cpu.dcache.demand_avg_mshr_miss_latency::total 13000.964644 # average overall mshr miss latency
688 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13000.964644 # average overall mshr miss latency
689 system.cpu.dcache.overall_avg_mshr_miss_latency::total 13000.964644 # average overall mshr miss latency
690 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
691 system.cpu.icache.tags.replacements 53 # number of replacements
692 system.cpu.icache.tags.tagsinuse 825.039758 # Cycle average of tags in use
693 system.cpu.icache.tags.total_refs 27442574 # Total number of references to valid blocks.
694 system.cpu.icache.tags.sampled_refs 1013 # Sample count of references to valid blocks.
695 system.cpu.icache.tags.avg_refs 27090.398815 # Average number of references to valid blocks.
696 system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
697 system.cpu.icache.tags.occ_blocks::cpu.inst 825.039758 # Average occupied blocks per requestor
698 system.cpu.icache.tags.occ_percent::cpu.inst 0.402851 # Average percentage of cache occupancy
699 system.cpu.icache.tags.occ_percent::total 0.402851 # Average percentage of cache occupancy
700 system.cpu.icache.tags.occ_task_id_blocks::1024 960 # Occupied blocks per task id
701 system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id
702 system.cpu.icache.tags.age_task_id_blocks_1024::2 25 # Occupied blocks per task id
703 system.cpu.icache.tags.age_task_id_blocks_1024::3 14 # Occupied blocks per task id
704 system.cpu.icache.tags.age_task_id_blocks_1024::4 870 # Occupied blocks per task id
705 system.cpu.icache.tags.occ_task_id_percent::1024 0.468750 # Percentage of cache occupancy per task id
706 system.cpu.icache.tags.tag_accesses 54888808 # Number of tag accesses
707 system.cpu.icache.tags.data_accesses 54888808 # Number of data accesses
708 system.cpu.icache.ReadReq_hits::cpu.inst 27442574 # number of ReadReq hits
709 system.cpu.icache.ReadReq_hits::total 27442574 # number of ReadReq hits
710 system.cpu.icache.demand_hits::cpu.inst 27442574 # number of demand (read+write) hits
711 system.cpu.icache.demand_hits::total 27442574 # number of demand (read+write) hits
712 system.cpu.icache.overall_hits::cpu.inst 27442574 # number of overall hits
713 system.cpu.icache.overall_hits::total 27442574 # number of overall hits
714 system.cpu.icache.ReadReq_misses::cpu.inst 1323 # number of ReadReq misses
715 system.cpu.icache.ReadReq_misses::total 1323 # number of ReadReq misses
716 system.cpu.icache.demand_misses::cpu.inst 1323 # number of demand (read+write) misses
717 system.cpu.icache.demand_misses::total 1323 # number of demand (read+write) misses
718 system.cpu.icache.overall_misses::cpu.inst 1323 # number of overall misses
719 system.cpu.icache.overall_misses::total 1323 # number of overall misses
720 system.cpu.icache.ReadReq_miss_latency::cpu.inst 97204000 # number of ReadReq miss cycles
721 system.cpu.icache.ReadReq_miss_latency::total 97204000 # number of ReadReq miss cycles
722 system.cpu.icache.demand_miss_latency::cpu.inst 97204000 # number of demand (read+write) miss cycles
723 system.cpu.icache.demand_miss_latency::total 97204000 # number of demand (read+write) miss cycles
724 system.cpu.icache.overall_miss_latency::cpu.inst 97204000 # number of overall miss cycles
725 system.cpu.icache.overall_miss_latency::total 97204000 # number of overall miss cycles
726 system.cpu.icache.ReadReq_accesses::cpu.inst 27443897 # number of ReadReq accesses(hits+misses)
727 system.cpu.icache.ReadReq_accesses::total 27443897 # number of ReadReq accesses(hits+misses)
728 system.cpu.icache.demand_accesses::cpu.inst 27443897 # number of demand (read+write) accesses
729 system.cpu.icache.demand_accesses::total 27443897 # number of demand (read+write) accesses
730 system.cpu.icache.overall_accesses::cpu.inst 27443897 # number of overall (read+write) accesses
731 system.cpu.icache.overall_accesses::total 27443897 # number of overall (read+write) accesses
732 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000048 # miss rate for ReadReq accesses
733 system.cpu.icache.ReadReq_miss_rate::total 0.000048 # miss rate for ReadReq accesses
734 system.cpu.icache.demand_miss_rate::cpu.inst 0.000048 # miss rate for demand accesses
735 system.cpu.icache.demand_miss_rate::total 0.000048 # miss rate for demand accesses
736 system.cpu.icache.overall_miss_rate::cpu.inst 0.000048 # miss rate for overall accesses
737 system.cpu.icache.overall_miss_rate::total 0.000048 # miss rate for overall accesses
738 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 73472.411187 # average ReadReq miss latency
739 system.cpu.icache.ReadReq_avg_miss_latency::total 73472.411187 # average ReadReq miss latency
740 system.cpu.icache.demand_avg_miss_latency::cpu.inst 73472.411187 # average overall miss latency
741 system.cpu.icache.demand_avg_miss_latency::total 73472.411187 # average overall miss latency
742 system.cpu.icache.overall_avg_miss_latency::cpu.inst 73472.411187 # average overall miss latency
743 system.cpu.icache.overall_avg_miss_latency::total 73472.411187 # average overall miss latency
744 system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
745 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
746 system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
747 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
748 system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
749 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
750 system.cpu.icache.fast_writes 0 # number of fast writes performed
751 system.cpu.icache.cache_copies 0 # number of cache copies performed
752 system.cpu.icache.writebacks::writebacks 53 # number of writebacks
753 system.cpu.icache.writebacks::total 53 # number of writebacks
754 system.cpu.icache.ReadReq_mshr_hits::cpu.inst 309 # number of ReadReq MSHR hits
755 system.cpu.icache.ReadReq_mshr_hits::total 309 # number of ReadReq MSHR hits
756 system.cpu.icache.demand_mshr_hits::cpu.inst 309 # number of demand (read+write) MSHR hits
757 system.cpu.icache.demand_mshr_hits::total 309 # number of demand (read+write) MSHR hits
758 system.cpu.icache.overall_mshr_hits::cpu.inst 309 # number of overall MSHR hits
759 system.cpu.icache.overall_mshr_hits::total 309 # number of overall MSHR hits
760 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1014 # number of ReadReq MSHR misses
761 system.cpu.icache.ReadReq_mshr_misses::total 1014 # number of ReadReq MSHR misses
762 system.cpu.icache.demand_mshr_misses::cpu.inst 1014 # number of demand (read+write) MSHR misses
763 system.cpu.icache.demand_mshr_misses::total 1014 # number of demand (read+write) MSHR misses
764 system.cpu.icache.overall_mshr_misses::cpu.inst 1014 # number of overall MSHR misses
765 system.cpu.icache.overall_mshr_misses::total 1014 # number of overall MSHR misses
766 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 77418000 # number of ReadReq MSHR miss cycles
767 system.cpu.icache.ReadReq_mshr_miss_latency::total 77418000 # number of ReadReq MSHR miss cycles
768 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 77418000 # number of demand (read+write) MSHR miss cycles
769 system.cpu.icache.demand_mshr_miss_latency::total 77418000 # number of demand (read+write) MSHR miss cycles
770 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 77418000 # number of overall MSHR miss cycles
771 system.cpu.icache.overall_mshr_miss_latency::total 77418000 # number of overall MSHR miss cycles
772 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000037 # mshr miss rate for ReadReq accesses
773 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000037 # mshr miss rate for ReadReq accesses
774 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000037 # mshr miss rate for demand accesses
775 system.cpu.icache.demand_mshr_miss_rate::total 0.000037 # mshr miss rate for demand accesses
776 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000037 # mshr miss rate for overall accesses
777 system.cpu.icache.overall_mshr_miss_rate::total 0.000037 # mshr miss rate for overall accesses
778 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76349.112426 # average ReadReq mshr miss latency
779 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76349.112426 # average ReadReq mshr miss latency
780 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76349.112426 # average overall mshr miss latency
781 system.cpu.icache.demand_avg_mshr_miss_latency::total 76349.112426 # average overall mshr miss latency
782 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76349.112426 # average overall mshr miss latency
783 system.cpu.icache.overall_avg_mshr_miss_latency::total 76349.112426 # average overall mshr miss latency
784 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
785 system.cpu.l2cache.tags.replacements 493 # number of replacements
786 system.cpu.l2cache.tags.tagsinuse 20711.322176 # Cycle average of tags in use
787 system.cpu.l2cache.tags.total_refs 4035102 # Total number of references to valid blocks.
788 system.cpu.l2cache.tags.sampled_refs 30410 # Sample count of references to valid blocks.
789 system.cpu.l2cache.tags.avg_refs 132.689970 # Average number of references to valid blocks.
790 system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
791 system.cpu.l2cache.tags.occ_blocks::writebacks 19791.559632 # Average occupied blocks per requestor
792 system.cpu.l2cache.tags.occ_blocks::cpu.inst 674.841856 # Average occupied blocks per requestor
793 system.cpu.l2cache.tags.occ_blocks::cpu.data 244.920687 # Average occupied blocks per requestor
794 system.cpu.l2cache.tags.occ_percent::writebacks 0.603990 # Average percentage of cache occupancy
795 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020595 # Average percentage of cache occupancy
796 system.cpu.l2cache.tags.occ_percent::cpu.data 0.007474 # Average percentage of cache occupancy
797 system.cpu.l2cache.tags.occ_percent::total 0.632059 # Average percentage of cache occupancy
798 system.cpu.l2cache.tags.occ_task_id_blocks::1024 29917 # Occupied blocks per task id
799 system.cpu.l2cache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id
800 system.cpu.l2cache.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id
801 system.cpu.l2cache.tags.age_task_id_blocks_1024::2 782 # Occupied blocks per task id
802 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1386 # Occupied blocks per task id
803 system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27622 # Occupied blocks per task id
804 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.912994 # Percentage of cache occupancy per task id
805 system.cpu.l2cache.tags.tag_accesses 33310456 # Number of tag accesses
806 system.cpu.l2cache.tags.data_accesses 33310456 # Number of data accesses
807 system.cpu.l2cache.WritebackDirty_hits::writebacks 2066601 # number of WritebackDirty hits
808 system.cpu.l2cache.WritebackDirty_hits::total 2066601 # number of WritebackDirty hits
809 system.cpu.l2cache.WritebackClean_hits::writebacks 53 # number of WritebackClean hits
810 system.cpu.l2cache.WritebackClean_hits::total 53 # number of WritebackClean hits
811 system.cpu.l2cache.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits
812 system.cpu.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits
813 system.cpu.l2cache.ReadExReq_hits::cpu.data 53071 # number of ReadExReq hits
814 system.cpu.l2cache.ReadExReq_hits::total 53071 # number of ReadExReq hits
815 system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 16 # number of ReadCleanReq hits
816 system.cpu.l2cache.ReadCleanReq_hits::total 16 # number of ReadCleanReq hits
817 system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1993914 # number of ReadSharedReq hits
818 system.cpu.l2cache.ReadSharedReq_hits::total 1993914 # number of ReadSharedReq hits
819 system.cpu.l2cache.demand_hits::cpu.inst 16 # number of demand (read+write) hits
820 system.cpu.l2cache.demand_hits::cpu.data 2046985 # number of demand (read+write) hits
821 system.cpu.l2cache.demand_hits::total 2047001 # number of demand (read+write) hits
822 system.cpu.l2cache.overall_hits::cpu.inst 16 # number of overall hits
823 system.cpu.l2cache.overall_hits::cpu.data 2046985 # number of overall hits
824 system.cpu.l2cache.overall_hits::total 2047001 # number of overall hits
825 system.cpu.l2cache.ReadExReq_misses::cpu.data 28998 # number of ReadExReq misses
826 system.cpu.l2cache.ReadExReq_misses::total 28998 # number of ReadExReq misses
827 system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 998 # number of ReadCleanReq misses
828 system.cpu.l2cache.ReadCleanReq_misses::total 998 # number of ReadCleanReq misses
829 system.cpu.l2cache.ReadSharedReq_misses::cpu.data 425 # number of ReadSharedReq misses
830 system.cpu.l2cache.ReadSharedReq_misses::total 425 # number of ReadSharedReq misses
831 system.cpu.l2cache.demand_misses::cpu.inst 998 # number of demand (read+write) misses
832 system.cpu.l2cache.demand_misses::cpu.data 29423 # number of demand (read+write) misses
833 system.cpu.l2cache.demand_misses::total 30421 # number of demand (read+write) misses
834 system.cpu.l2cache.overall_misses::cpu.inst 998 # number of overall misses
835 system.cpu.l2cache.overall_misses::cpu.data 29423 # number of overall misses
836 system.cpu.l2cache.overall_misses::total 30421 # number of overall misses
837 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2118138000 # number of ReadExReq miss cycles
838 system.cpu.l2cache.ReadExReq_miss_latency::total 2118138000 # number of ReadExReq miss cycles
839 system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 75717000 # number of ReadCleanReq miss cycles
840 system.cpu.l2cache.ReadCleanReq_miss_latency::total 75717000 # number of ReadCleanReq miss cycles
841 system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 32635000 # number of ReadSharedReq miss cycles
842 system.cpu.l2cache.ReadSharedReq_miss_latency::total 32635000 # number of ReadSharedReq miss cycles
843 system.cpu.l2cache.demand_miss_latency::cpu.inst 75717000 # number of demand (read+write) miss cycles
844 system.cpu.l2cache.demand_miss_latency::cpu.data 2150773000 # number of demand (read+write) miss cycles
845 system.cpu.l2cache.demand_miss_latency::total 2226490000 # number of demand (read+write) miss cycles
846 system.cpu.l2cache.overall_miss_latency::cpu.inst 75717000 # number of overall miss cycles
847 system.cpu.l2cache.overall_miss_latency::cpu.data 2150773000 # number of overall miss cycles
848 system.cpu.l2cache.overall_miss_latency::total 2226490000 # number of overall miss cycles
849 system.cpu.l2cache.WritebackDirty_accesses::writebacks 2066601 # number of WritebackDirty accesses(hits+misses)
850 system.cpu.l2cache.WritebackDirty_accesses::total 2066601 # number of WritebackDirty accesses(hits+misses)
851 system.cpu.l2cache.WritebackClean_accesses::writebacks 53 # number of WritebackClean accesses(hits+misses)
852 system.cpu.l2cache.WritebackClean_accesses::total 53 # number of WritebackClean accesses(hits+misses)
853 system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1 # number of UpgradeReq accesses(hits+misses)
854 system.cpu.l2cache.UpgradeReq_accesses::total 1 # number of UpgradeReq accesses(hits+misses)
855 system.cpu.l2cache.ReadExReq_accesses::cpu.data 82069 # number of ReadExReq accesses(hits+misses)
856 system.cpu.l2cache.ReadExReq_accesses::total 82069 # number of ReadExReq accesses(hits+misses)
857 system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1014 # number of ReadCleanReq accesses(hits+misses)
858 system.cpu.l2cache.ReadCleanReq_accesses::total 1014 # number of ReadCleanReq accesses(hits+misses)
859 system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1994339 # number of ReadSharedReq accesses(hits+misses)
860 system.cpu.l2cache.ReadSharedReq_accesses::total 1994339 # number of ReadSharedReq accesses(hits+misses)
861 system.cpu.l2cache.demand_accesses::cpu.inst 1014 # number of demand (read+write) accesses
862 system.cpu.l2cache.demand_accesses::cpu.data 2076408 # number of demand (read+write) accesses
863 system.cpu.l2cache.demand_accesses::total 2077422 # number of demand (read+write) accesses
864 system.cpu.l2cache.overall_accesses::cpu.inst 1014 # number of overall (read+write) accesses
865 system.cpu.l2cache.overall_accesses::cpu.data 2076408 # number of overall (read+write) accesses
866 system.cpu.l2cache.overall_accesses::total 2077422 # number of overall (read+write) accesses
867 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.353337 # miss rate for ReadExReq accesses
868 system.cpu.l2cache.ReadExReq_miss_rate::total 0.353337 # miss rate for ReadExReq accesses
869 system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.984221 # miss rate for ReadCleanReq accesses
870 system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.984221 # miss rate for ReadCleanReq accesses
871 system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000213 # miss rate for ReadSharedReq accesses
872 system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000213 # miss rate for ReadSharedReq accesses
873 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.984221 # miss rate for demand accesses
874 system.cpu.l2cache.demand_miss_rate::cpu.data 0.014170 # miss rate for demand accesses
875 system.cpu.l2cache.demand_miss_rate::total 0.014644 # miss rate for demand accesses
876 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.984221 # miss rate for overall accesses
877 system.cpu.l2cache.overall_miss_rate::cpu.data 0.014170 # miss rate for overall accesses
878 system.cpu.l2cache.overall_miss_rate::total 0.014644 # miss rate for overall accesses
879 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73044.278916 # average ReadExReq miss latency
880 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73044.278916 # average ReadExReq miss latency
881 system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75868.737475 # average ReadCleanReq miss latency
882 system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75868.737475 # average ReadCleanReq miss latency
883 system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 76788.235294 # average ReadSharedReq miss latency
884 system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 76788.235294 # average ReadSharedReq miss latency
885 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75868.737475 # average overall miss latency
886 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73098.358427 # average overall miss latency
887 system.cpu.l2cache.demand_avg_miss_latency::total 73189.244272 # average overall miss latency
888 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75868.737475 # average overall miss latency
889 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73098.358427 # average overall miss latency
890 system.cpu.l2cache.overall_avg_miss_latency::total 73189.244272 # average overall miss latency
891 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
892 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
893 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
894 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
895 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
896 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
897 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
898 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
899 system.cpu.l2cache.writebacks::writebacks 190 # number of writebacks
900 system.cpu.l2cache.writebacks::total 190 # number of writebacks
901 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 28998 # number of ReadExReq MSHR misses
902 system.cpu.l2cache.ReadExReq_mshr_misses::total 28998 # number of ReadExReq MSHR misses
903 system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 998 # number of ReadCleanReq MSHR misses
904 system.cpu.l2cache.ReadCleanReq_mshr_misses::total 998 # number of ReadCleanReq MSHR misses
905 system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 425 # number of ReadSharedReq MSHR misses
906 system.cpu.l2cache.ReadSharedReq_mshr_misses::total 425 # number of ReadSharedReq MSHR misses
907 system.cpu.l2cache.demand_mshr_misses::cpu.inst 998 # number of demand (read+write) MSHR misses
908 system.cpu.l2cache.demand_mshr_misses::cpu.data 29423 # number of demand (read+write) MSHR misses
909 system.cpu.l2cache.demand_mshr_misses::total 30421 # number of demand (read+write) MSHR misses
910 system.cpu.l2cache.overall_mshr_misses::cpu.inst 998 # number of overall MSHR misses
911 system.cpu.l2cache.overall_mshr_misses::cpu.data 29423 # number of overall MSHR misses
912 system.cpu.l2cache.overall_mshr_misses::total 30421 # number of overall MSHR misses
913 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1828158000 # number of ReadExReq MSHR miss cycles
914 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1828158000 # number of ReadExReq MSHR miss cycles
915 system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 65737000 # number of ReadCleanReq MSHR miss cycles
916 system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 65737000 # number of ReadCleanReq MSHR miss cycles
917 system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 28385000 # number of ReadSharedReq MSHR miss cycles
918 system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 28385000 # number of ReadSharedReq MSHR miss cycles
919 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 65737000 # number of demand (read+write) MSHR miss cycles
920 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1856543000 # number of demand (read+write) MSHR miss cycles
921 system.cpu.l2cache.demand_mshr_miss_latency::total 1922280000 # number of demand (read+write) MSHR miss cycles
922 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 65737000 # number of overall MSHR miss cycles
923 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1856543000 # number of overall MSHR miss cycles
924 system.cpu.l2cache.overall_mshr_miss_latency::total 1922280000 # number of overall MSHR miss cycles
925 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.353337 # mshr miss rate for ReadExReq accesses
926 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.353337 # mshr miss rate for ReadExReq accesses
927 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.984221 # mshr miss rate for ReadCleanReq accesses
928 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.984221 # mshr miss rate for ReadCleanReq accesses
929 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000213 # mshr miss rate for ReadSharedReq accesses
930 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000213 # mshr miss rate for ReadSharedReq accesses
931 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.984221 # mshr miss rate for demand accesses
932 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014170 # mshr miss rate for demand accesses
933 system.cpu.l2cache.demand_mshr_miss_rate::total 0.014644 # mshr miss rate for demand accesses
934 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.984221 # mshr miss rate for overall accesses
935 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014170 # mshr miss rate for overall accesses
936 system.cpu.l2cache.overall_mshr_miss_rate::total 0.014644 # mshr miss rate for overall accesses
937 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63044.278916 # average ReadExReq mshr miss latency
938 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63044.278916 # average ReadExReq mshr miss latency
939 system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65868.737475 # average ReadCleanReq mshr miss latency
940 system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65868.737475 # average ReadCleanReq mshr miss latency
941 system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 66788.235294 # average ReadSharedReq mshr miss latency
942 system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 66788.235294 # average ReadSharedReq mshr miss latency
943 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65868.737475 # average overall mshr miss latency
944 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63098.358427 # average overall mshr miss latency
945 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63189.244272 # average overall mshr miss latency
946 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65868.737475 # average overall mshr miss latency
947 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63098.358427 # average overall mshr miss latency
948 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63189.244272 # average overall mshr miss latency
949 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
950 system.cpu.toL2Bus.snoop_filter.tot_requests 4149788 # Total number of requests made to the snoop filter.
951 system.cpu.toL2Bus.snoop_filter.hit_single_requests 2072369 # Number of requests hitting in the snoop filter with a single holder of the requested data.
952 system.cpu.toL2Bus.snoop_filter.hit_multi_requests 42 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
953 system.cpu.toL2Bus.snoop_filter.tot_snoops 279 # Total number of snoops made to the snoop filter.
954 system.cpu.toL2Bus.snoop_filter.hit_single_snoops 279 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
955 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
956 system.cpu.toL2Bus.trans_dist::ReadResp 1995353 # Transaction distribution
957 system.cpu.toL2Bus.trans_dist::WritebackDirty 2066791 # Transaction distribution
958 system.cpu.toL2Bus.trans_dist::WritebackClean 53 # Transaction distribution
959 system.cpu.toL2Bus.trans_dist::CleanEvict 6014 # Transaction distribution
960 system.cpu.toL2Bus.trans_dist::UpgradeReq 1 # Transaction distribution
961 system.cpu.toL2Bus.trans_dist::UpgradeResp 1 # Transaction distribution
962 system.cpu.toL2Bus.trans_dist::ReadExReq 82069 # Transaction distribution
963 system.cpu.toL2Bus.trans_dist::ReadExResp 82069 # Transaction distribution
964 system.cpu.toL2Bus.trans_dist::ReadCleanReq 1014 # Transaction distribution
965 system.cpu.toL2Bus.trans_dist::ReadSharedReq 1994339 # Transaction distribution
966 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2081 # Packet count per connected master and slave (bytes)
967 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6225130 # Packet count per connected master and slave (bytes)
968 system.cpu.toL2Bus.pkt_count::total 6227211 # Packet count per connected master and slave (bytes)
969 system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 68288 # Cumulative packet size per connected master and slave (bytes)
970 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 265152576 # Cumulative packet size per connected master and slave (bytes)
971 system.cpu.toL2Bus.pkt_size::total 265220864 # Cumulative packet size per connected master and slave (bytes)
972 system.cpu.toL2Bus.snoops 493 # Total snoops (count)
973 system.cpu.toL2Bus.snoop_fanout::samples 2077916 # Request fanout histogram
974 system.cpu.toL2Bus.snoop_fanout::mean 0.000156 # Request fanout histogram
975 system.cpu.toL2Bus.snoop_fanout::stdev 0.012505 # Request fanout histogram
976 system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
977 system.cpu.toL2Bus.snoop_fanout::0 2077591 99.98% 99.98% # Request fanout histogram
978 system.cpu.toL2Bus.snoop_fanout::1 325 0.02% 100.00% # Request fanout histogram
979 system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
980 system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
981 system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
982 system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
983 system.cpu.toL2Bus.snoop_fanout::total 2077916 # Request fanout histogram
984 system.cpu.toL2Bus.reqLayer0.occupancy 4141548000 # Layer occupancy (ticks)
985 system.cpu.toL2Bus.reqLayer0.utilization 6.7 # Layer utilization (%)
986 system.cpu.toL2Bus.respLayer0.occupancy 1521000 # Layer occupancy (ticks)
987 system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
988 system.cpu.toL2Bus.respLayer1.occupancy 3114612500 # Layer occupancy (ticks)
989 system.cpu.toL2Bus.respLayer1.utilization 5.1 # Layer utilization (%)
990 system.membus.trans_dist::ReadResp 1423 # Transaction distribution
991 system.membus.trans_dist::WritebackDirty 190 # Transaction distribution
992 system.membus.trans_dist::CleanEvict 24 # Transaction distribution
993 system.membus.trans_dist::ReadExReq 28998 # Transaction distribution
994 system.membus.trans_dist::ReadExResp 28998 # Transaction distribution
995 system.membus.trans_dist::ReadSharedReq 1423 # Transaction distribution
996 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 61056 # Packet count per connected master and slave (bytes)
997 system.membus.pkt_count_system.cpu.l2cache.mem_side::total 61056 # Packet count per connected master and slave (bytes)
998 system.membus.pkt_count::total 61056 # Packet count per connected master and slave (bytes)
999 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1959104 # Cumulative packet size per connected master and slave (bytes)
1000 system.membus.pkt_size_system.cpu.l2cache.mem_side::total 1959104 # Cumulative packet size per connected master and slave (bytes)
1001 system.membus.pkt_size::total 1959104 # Cumulative packet size per connected master and slave (bytes)
1002 system.membus.snoops 0 # Total snoops (count)
1003 system.membus.snoop_fanout::samples 30635 # Request fanout histogram
1004 system.membus.snoop_fanout::mean 0 # Request fanout histogram
1005 system.membus.snoop_fanout::stdev 0 # Request fanout histogram
1006 system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1007 system.membus.snoop_fanout::0 30635 100.00% 100.00% # Request fanout histogram
1008 system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
1009 system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1010 system.membus.snoop_fanout::min_value 0 # Request fanout histogram
1011 system.membus.snoop_fanout::max_value 0 # Request fanout histogram
1012 system.membus.snoop_fanout::total 30635 # Request fanout histogram
1013 system.membus.reqLayer0.occupancy 42769000 # Layer occupancy (ticks)
1014 system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
1015 system.membus.respLayer1.occupancy 160316500 # Layer occupancy (ticks)
1016 system.membus.respLayer1.utilization 0.3 # Layer utilization (%)
1018 ---------- End Simulation Statistics ----------
projects / gem5.git / blob