2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.370011 # Number of seconds simulated
4 sim_ticks 370010840000 # Number of ticks simulated
5 final_tick 370010840000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 1163147 # Simulator instruction rate (inst/s)
8 host_tick_rate 1547047043 # Simulator tick rate (ticks/s)
9 host_mem_usage 348152 # Number of bytes of host memory used
10 host_seconds 239.17 # Real time elapsed on the host
11 sim_insts 278192520 # Number of instructions simulated
12 system.physmem.bytes_read 4900800 # Number of bytes read from this memory
13 system.physmem.bytes_inst_read 51712 # Number of instructions bytes read from this memory
14 system.physmem.bytes_written 1885440 # Number of bytes written to this memory
15 system.physmem.num_reads 76575 # Number of read requests responded to by this memory
16 system.physmem.num_writes 29460 # Number of write requests responded to by this memory
17 system.physmem.num_other 0 # Number of other requests responded to by this memory
18 system.physmem.bw_read 13245017 # Total read bandwidth from this memory (bytes/s)
19 system.physmem.bw_inst_read 139758 # Instruction read bandwidth from this memory (bytes/s)
20 system.physmem.bw_write 5095634 # Write bandwidth from this memory (bytes/s)
21 system.physmem.bw_total 18340652 # Total bandwidth to/from this memory (bytes/s)
22 system.cpu.workload.num_syscalls 444 # Number of system calls
23 system.cpu.numCycles 740021680 # number of cpu cycles simulated
24 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
25 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
26 system.cpu.num_insts 278192520 # Number of instructions executed
27 system.cpu.num_int_alu_accesses 278186228 # Number of integer alu accesses
28 system.cpu.num_fp_alu_accesses 40 # Number of float alu accesses
29 system.cpu.num_func_calls 0 # number of times a function call or return occured
30 system.cpu.num_conditional_control_insts 18628012 # number of instructions that are conditional controls
31 system.cpu.num_int_insts 278186228 # number of integer instructions
32 system.cpu.num_fp_insts 40 # number of float instructions
33 system.cpu.num_int_register_reads 685043114 # number of times the integer registers were read
34 system.cpu.num_int_register_writes 248344166 # number of times the integer registers were written
35 system.cpu.num_fp_register_reads 40 # number of times the floating registers were read
36 system.cpu.num_fp_register_writes 26 # number of times the floating registers were written
37 system.cpu.num_mem_refs 122219139 # number of memory refs
38 system.cpu.num_load_insts 90779388 # Number of load instructions
39 system.cpu.num_store_insts 31439751 # Number of store instructions
40 system.cpu.num_idle_cycles 0 # Number of idle cycles
41 system.cpu.num_busy_cycles 740021680 # Number of busy cycles
42 system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
43 system.cpu.idle_fraction 0 # Percentage of idle cycles
44 system.cpu.icache.replacements 24 # number of replacements
45 system.cpu.icache.tagsinuse 666.191948 # Cycle average of tags in use
46 system.cpu.icache.total_refs 217695401 # Total number of references to valid blocks.
47 system.cpu.icache.sampled_refs 808 # Sample count of references to valid blocks.
48 system.cpu.icache.avg_refs 269425.001238 # Average number of references to valid blocks.
49 system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
50 system.cpu.icache.occ_blocks::0 666.191948 # Average occupied blocks per context
51 system.cpu.icache.occ_percent::0 0.325289 # Average percentage of cache occupancy
52 system.cpu.icache.ReadReq_hits 217695401 # number of ReadReq hits
53 system.cpu.icache.demand_hits 217695401 # number of demand (read+write) hits
54 system.cpu.icache.overall_hits 217695401 # number of overall hits
55 system.cpu.icache.ReadReq_misses 808 # number of ReadReq misses
56 system.cpu.icache.demand_misses 808 # number of demand (read+write) misses
57 system.cpu.icache.overall_misses 808 # number of overall misses
58 system.cpu.icache.ReadReq_miss_latency 45248000 # number of ReadReq miss cycles
59 system.cpu.icache.demand_miss_latency 45248000 # number of demand (read+write) miss cycles
60 system.cpu.icache.overall_miss_latency 45248000 # number of overall miss cycles
61 system.cpu.icache.ReadReq_accesses 217696209 # number of ReadReq accesses(hits+misses)
62 system.cpu.icache.demand_accesses 217696209 # number of demand (read+write) accesses
63 system.cpu.icache.overall_accesses 217696209 # number of overall (read+write) accesses
64 system.cpu.icache.ReadReq_miss_rate 0.000004 # miss rate for ReadReq accesses
65 system.cpu.icache.demand_miss_rate 0.000004 # miss rate for demand accesses
66 system.cpu.icache.overall_miss_rate 0.000004 # miss rate for overall accesses
67 system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
68 system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency
69 system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency
70 system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
71 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
72 system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
73 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
74 system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
75 system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
76 system.cpu.icache.fast_writes 0 # number of fast writes performed
77 system.cpu.icache.cache_copies 0 # number of cache copies performed
78 system.cpu.icache.writebacks 0 # number of writebacks
79 system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
80 system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
81 system.cpu.icache.ReadReq_mshr_misses 808 # number of ReadReq MSHR misses
82 system.cpu.icache.demand_mshr_misses 808 # number of demand (read+write) MSHR misses
83 system.cpu.icache.overall_mshr_misses 808 # number of overall MSHR misses
84 system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
85 system.cpu.icache.ReadReq_mshr_miss_latency 42824000 # number of ReadReq MSHR miss cycles
86 system.cpu.icache.demand_mshr_miss_latency 42824000 # number of demand (read+write) MSHR miss cycles
87 system.cpu.icache.overall_mshr_miss_latency 42824000 # number of overall MSHR miss cycles
88 system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
89 system.cpu.icache.ReadReq_mshr_miss_rate 0.000004 # mshr miss rate for ReadReq accesses
90 system.cpu.icache.demand_mshr_miss_rate 0.000004 # mshr miss rate for demand accesses
91 system.cpu.icache.overall_mshr_miss_rate 0.000004 # mshr miss rate for overall accesses
92 system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
93 system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
94 system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
95 system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
96 system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
97 system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
98 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
99 system.cpu.dcache.replacements 2062733 # number of replacements
100 system.cpu.dcache.tagsinuse 4076.661903 # Cycle average of tags in use
101 system.cpu.dcache.total_refs 120152372 # Total number of references to valid blocks.
102 system.cpu.dcache.sampled_refs 2066829 # Sample count of references to valid blocks.
103 system.cpu.dcache.avg_refs 58.133678 # Average number of references to valid blocks.
104 system.cpu.dcache.warmup_cycle 126200130000 # Cycle when the warmup percentage was hit.
105 system.cpu.dcache.occ_blocks::0 4076.661903 # Average occupied blocks per context
106 system.cpu.dcache.occ_percent::0 0.995279 # Average percentage of cache occupancy
107 system.cpu.dcache.ReadReq_hits 88818730 # number of ReadReq hits
108 system.cpu.dcache.WriteReq_hits 31333642 # number of WriteReq hits
109 system.cpu.dcache.demand_hits 120152372 # number of demand (read+write) hits
110 system.cpu.dcache.overall_hits 120152372 # number of overall hits
111 system.cpu.dcache.ReadReq_misses 1960720 # number of ReadReq misses
112 system.cpu.dcache.WriteReq_misses 106109 # number of WriteReq misses
113 system.cpu.dcache.demand_misses 2066829 # number of demand (read+write) misses
114 system.cpu.dcache.overall_misses 2066829 # number of overall misses
115 system.cpu.dcache.ReadReq_miss_latency 28849058000 # number of ReadReq miss cycles
116 system.cpu.dcache.WriteReq_miss_latency 3268793000 # number of WriteReq miss cycles
117 system.cpu.dcache.demand_miss_latency 32117851000 # number of demand (read+write) miss cycles
118 system.cpu.dcache.overall_miss_latency 32117851000 # number of overall miss cycles
119 system.cpu.dcache.ReadReq_accesses 90779450 # number of ReadReq accesses(hits+misses)
120 system.cpu.dcache.WriteReq_accesses 31439751 # number of WriteReq accesses(hits+misses)
121 system.cpu.dcache.demand_accesses 122219201 # number of demand (read+write) accesses
122 system.cpu.dcache.overall_accesses 122219201 # number of overall (read+write) accesses
123 system.cpu.dcache.ReadReq_miss_rate 0.021599 # miss rate for ReadReq accesses
124 system.cpu.dcache.WriteReq_miss_rate 0.003375 # miss rate for WriteReq accesses
125 system.cpu.dcache.demand_miss_rate 0.016911 # miss rate for demand accesses
126 system.cpu.dcache.overall_miss_rate 0.016911 # miss rate for overall accesses
127 system.cpu.dcache.ReadReq_avg_miss_latency 14713.502183 # average ReadReq miss latency
128 system.cpu.dcache.WriteReq_avg_miss_latency 30805.991952 # average WriteReq miss latency
129 system.cpu.dcache.demand_avg_miss_latency 15539.675029 # average overall miss latency
130 system.cpu.dcache.overall_avg_miss_latency 15539.675029 # average overall miss latency
131 system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
132 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
133 system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
134 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
135 system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
136 system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
137 system.cpu.dcache.fast_writes 0 # number of fast writes performed
138 system.cpu.dcache.cache_copies 0 # number of cache copies performed
139 system.cpu.dcache.writebacks 1437080 # number of writebacks
140 system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
141 system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
142 system.cpu.dcache.ReadReq_mshr_misses 1960720 # number of ReadReq MSHR misses
143 system.cpu.dcache.WriteReq_mshr_misses 106109 # number of WriteReq MSHR misses
144 system.cpu.dcache.demand_mshr_misses 2066829 # number of demand (read+write) MSHR misses
145 system.cpu.dcache.overall_mshr_misses 2066829 # number of overall MSHR misses
146 system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
147 system.cpu.dcache.ReadReq_mshr_miss_latency 22966898000 # number of ReadReq MSHR miss cycles
148 system.cpu.dcache.WriteReq_mshr_miss_latency 2950464500 # number of WriteReq MSHR miss cycles
149 system.cpu.dcache.demand_mshr_miss_latency 25917362500 # number of demand (read+write) MSHR miss cycles
150 system.cpu.dcache.overall_mshr_miss_latency 25917362500 # number of overall MSHR miss cycles
151 system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
152 system.cpu.dcache.ReadReq_mshr_miss_rate 0.021599 # mshr miss rate for ReadReq accesses
153 system.cpu.dcache.WriteReq_mshr_miss_rate 0.003375 # mshr miss rate for WriteReq accesses
154 system.cpu.dcache.demand_mshr_miss_rate 0.016911 # mshr miss rate for demand accesses
155 system.cpu.dcache.overall_mshr_miss_rate 0.016911 # mshr miss rate for overall accesses
156 system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11713.502183 # average ReadReq mshr miss latency
157 system.cpu.dcache.WriteReq_avg_mshr_miss_latency 27805.977815 # average WriteReq mshr miss latency
158 system.cpu.dcache.demand_avg_mshr_miss_latency 12539.674303 # average overall mshr miss latency
159 system.cpu.dcache.overall_avg_mshr_miss_latency 12539.674303 # average overall mshr miss latency
160 system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
161 system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
162 system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
163 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
164 system.cpu.l2cache.replacements 49212 # number of replacements
165 system.cpu.l2cache.tagsinuse 18614.603260 # Cycle average of tags in use
166 system.cpu.l2cache.total_refs 3296079 # Total number of references to valid blocks.
167 system.cpu.l2cache.sampled_refs 77127 # Sample count of references to valid blocks.
168 system.cpu.l2cache.avg_refs 42.735735 # Average number of references to valid blocks.
169 system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
170 system.cpu.l2cache.occ_blocks::0 6551.798271 # Average occupied blocks per context
171 system.cpu.l2cache.occ_blocks::1 12062.804989 # Average occupied blocks per context
172 system.cpu.l2cache.occ_percent::0 0.199945 # Average percentage of cache occupancy
173 system.cpu.l2cache.occ_percent::1 0.368128 # Average percentage of cache occupancy
174 system.cpu.l2cache.ReadReq_hits 1927411 # number of ReadReq hits
175 system.cpu.l2cache.Writeback_hits 1437080 # number of Writeback hits
176 system.cpu.l2cache.ReadExReq_hits 63651 # number of ReadExReq hits
177 system.cpu.l2cache.demand_hits 1991062 # number of demand (read+write) hits
178 system.cpu.l2cache.overall_hits 1991062 # number of overall hits
179 system.cpu.l2cache.ReadReq_misses 34117 # number of ReadReq misses
180 system.cpu.l2cache.ReadExReq_misses 42458 # number of ReadExReq misses
181 system.cpu.l2cache.demand_misses 76575 # number of demand (read+write) misses
182 system.cpu.l2cache.overall_misses 76575 # number of overall misses
183 system.cpu.l2cache.ReadReq_miss_latency 1774084000 # number of ReadReq miss cycles
184 system.cpu.l2cache.ReadExReq_miss_latency 2207845500 # number of ReadExReq miss cycles
185 system.cpu.l2cache.demand_miss_latency 3981929500 # number of demand (read+write) miss cycles
186 system.cpu.l2cache.overall_miss_latency 3981929500 # number of overall miss cycles
187 system.cpu.l2cache.ReadReq_accesses 1961528 # number of ReadReq accesses(hits+misses)
188 system.cpu.l2cache.Writeback_accesses 1437080 # number of Writeback accesses(hits+misses)
189 system.cpu.l2cache.ReadExReq_accesses 106109 # number of ReadExReq accesses(hits+misses)
190 system.cpu.l2cache.demand_accesses 2067637 # number of demand (read+write) accesses
191 system.cpu.l2cache.overall_accesses 2067637 # number of overall (read+write) accesses
192 system.cpu.l2cache.ReadReq_miss_rate 0.017393 # miss rate for ReadReq accesses
193 system.cpu.l2cache.ReadExReq_miss_rate 0.400136 # miss rate for ReadExReq accesses
194 system.cpu.l2cache.demand_miss_rate 0.037035 # miss rate for demand accesses
195 system.cpu.l2cache.overall_miss_rate 0.037035 # miss rate for overall accesses
196 system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
197 system.cpu.l2cache.ReadExReq_avg_miss_latency 52000.694804 # average ReadExReq miss latency
198 system.cpu.l2cache.demand_avg_miss_latency 52000.385243 # average overall miss latency
199 system.cpu.l2cache.overall_avg_miss_latency 52000.385243 # average overall miss latency
200 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
201 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
202 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
203 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
204 system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
205 system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
206 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
207 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
208 system.cpu.l2cache.writebacks 29460 # number of writebacks
209 system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
210 system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
211 system.cpu.l2cache.ReadReq_mshr_misses 34117 # number of ReadReq MSHR misses
212 system.cpu.l2cache.ReadExReq_mshr_misses 42458 # number of ReadExReq MSHR misses
213 system.cpu.l2cache.demand_mshr_misses 76575 # number of demand (read+write) MSHR misses
214 system.cpu.l2cache.overall_mshr_misses 76575 # number of overall MSHR misses
215 system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
216 system.cpu.l2cache.ReadReq_mshr_miss_latency 1364680000 # number of ReadReq MSHR miss cycles
217 system.cpu.l2cache.ReadExReq_mshr_miss_latency 1698320000 # number of ReadExReq MSHR miss cycles
218 system.cpu.l2cache.demand_mshr_miss_latency 3063000000 # number of demand (read+write) MSHR miss cycles
219 system.cpu.l2cache.overall_mshr_miss_latency 3063000000 # number of overall MSHR miss cycles
220 system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
221 system.cpu.l2cache.ReadReq_mshr_miss_rate 0.017393 # mshr miss rate for ReadReq accesses
222 system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.400136 # mshr miss rate for ReadExReq accesses
223 system.cpu.l2cache.demand_mshr_miss_rate 0.037035 # mshr miss rate for demand accesses
224 system.cpu.l2cache.overall_mshr_miss_rate 0.037035 # mshr miss rate for overall accesses
225 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
226 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
227 system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
228 system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
229 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
230 system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
231 system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
232 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
234 ---------- End Simulation Statistics ----------
projects / gem5.git / blob