2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.365989 # Number of seconds simulated
4 sim_ticks 365989065000 # Number of ticks simulated
5 final_tick 365989065000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 466388 # Simulator instruction rate (inst/s)
8 host_op_rate 821234 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 1080412484 # Simulator tick rate (ticks/s)
10 host_mem_usage 431468 # Number of bytes of host memory used
11 host_seconds 338.75 # Real time elapsed on the host
12 sim_insts 157988548 # Number of instructions simulated
13 sim_ops 278192465 # Number of ops (including micro ops) simulated
14 system.physmem.bytes_read::cpu.inst 51392 # Number of bytes read from this memory
15 system.physmem.bytes_read::cpu.data 1871744 # Number of bytes read from this memory
16 system.physmem.bytes_read::total 1923136 # Number of bytes read from this memory
17 system.physmem.bytes_inst_read::cpu.inst 51392 # Number of instructions bytes read from this memory
18 system.physmem.bytes_inst_read::total 51392 # Number of instructions bytes read from this memory
19 system.physmem.bytes_written::writebacks 6400 # Number of bytes written to this memory
20 system.physmem.bytes_written::total 6400 # Number of bytes written to this memory
21 system.physmem.num_reads::cpu.inst 803 # Number of read requests responded to by this memory
22 system.physmem.num_reads::cpu.data 29246 # Number of read requests responded to by this memory
23 system.physmem.num_reads::total 30049 # Number of read requests responded to by this memory
24 system.physmem.num_writes::writebacks 100 # Number of write requests responded to by this memory
25 system.physmem.num_writes::total 100 # Number of write requests responded to by this memory
26 system.physmem.bw_read::cpu.inst 140419 # Total read bandwidth from this memory (bytes/s)
27 system.physmem.bw_read::cpu.data 5114207 # Total read bandwidth from this memory (bytes/s)
28 system.physmem.bw_read::total 5254627 # Total read bandwidth from this memory (bytes/s)
29 system.physmem.bw_inst_read::cpu.inst 140419 # Instruction read bandwidth from this memory (bytes/s)
30 system.physmem.bw_inst_read::total 140419 # Instruction read bandwidth from this memory (bytes/s)
31 system.physmem.bw_write::writebacks 17487 # Write bandwidth from this memory (bytes/s)
32 system.physmem.bw_write::total 17487 # Write bandwidth from this memory (bytes/s)
33 system.physmem.bw_total::writebacks 17487 # Total bandwidth to/from this memory (bytes/s)
34 system.physmem.bw_total::cpu.inst 140419 # Total bandwidth to/from this memory (bytes/s)
35 system.physmem.bw_total::cpu.data 5114207 # Total bandwidth to/from this memory (bytes/s)
36 system.physmem.bw_total::total 5272114 # Total bandwidth to/from this memory (bytes/s)
37 system.membus.throughput 5272114 # Throughput (bytes/s)
38 system.membus.trans_dist::ReadReq 1025 # Transaction distribution
39 system.membus.trans_dist::ReadResp 1025 # Transaction distribution
40 system.membus.trans_dist::Writeback 100 # Transaction distribution
41 system.membus.trans_dist::ReadExReq 29024 # Transaction distribution
42 system.membus.trans_dist::ReadExResp 29024 # Transaction distribution
43 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 60198 # Packet count per connected master and slave (bytes)
44 system.membus.pkt_count_system.cpu.l2cache.mem_side::total 60198 # Packet count per connected master and slave (bytes)
45 system.membus.pkt_count::system.physmem.port 60198 # Packet count per connected master and slave (bytes)
46 system.membus.pkt_count::total 60198 # Packet count per connected master and slave (bytes)
47 system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1929536 # Cumulative packet size per connected master and slave (bytes)
48 system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 1929536 # Cumulative packet size per connected master and slave (bytes)
49 system.membus.tot_pkt_size::system.physmem.port 1929536 # Cumulative packet size per connected master and slave (bytes)
50 system.membus.tot_pkt_size::total 1929536 # Cumulative packet size per connected master and slave (bytes)
51 system.membus.data_through_bus 1929536 # Total data (bytes)
52 system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
53 system.membus.reqLayer0.occupancy 30980000 # Layer occupancy (ticks)
54 system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
55 system.membus.respLayer1.occupancy 270472000 # Layer occupancy (ticks)
56 system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
57 system.cpu.workload.num_syscalls 444 # Number of system calls
58 system.cpu.numCycles 731978130 # number of cpu cycles simulated
59 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
60 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
61 system.cpu.committedInsts 157988548 # Number of instructions committed
62 system.cpu.committedOps 278192465 # Number of ops (including micro ops) committed
63 system.cpu.num_int_alu_accesses 278186175 # Number of integer alu accesses
64 system.cpu.num_fp_alu_accesses 40 # Number of float alu accesses
65 system.cpu.num_func_calls 8475189 # number of times a function call or return occured
66 system.cpu.num_conditional_control_insts 18628007 # number of instructions that are conditional controls
67 system.cpu.num_int_insts 278186175 # number of integer instructions
68 system.cpu.num_fp_insts 40 # number of float instructions
69 system.cpu.num_int_register_reads 739520003 # number of times the integer registers were read
70 system.cpu.num_int_register_writes 279212721 # number of times the integer registers were written
71 system.cpu.num_fp_register_reads 40 # number of times the floating registers were read
72 system.cpu.num_fp_register_writes 26 # number of times the floating registers were written
73 system.cpu.num_mem_refs 122219137 # number of memory refs
74 system.cpu.num_load_insts 90779385 # Number of load instructions
75 system.cpu.num_store_insts 31439752 # Number of store instructions
76 system.cpu.num_idle_cycles 0 # Number of idle cycles
77 system.cpu.num_busy_cycles 731978130 # Number of busy cycles
78 system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
79 system.cpu.idle_fraction 0 # Percentage of idle cycles
80 system.cpu.icache.replacements 24 # number of replacements
81 system.cpu.icache.tagsinuse 665.632508 # Cycle average of tags in use
82 system.cpu.icache.total_refs 217695357 # Total number of references to valid blocks.
83 system.cpu.icache.sampled_refs 808 # Sample count of references to valid blocks.
84 system.cpu.icache.avg_refs 269424.946782 # Average number of references to valid blocks.
85 system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
86 system.cpu.icache.occ_blocks::cpu.inst 665.632508 # Average occupied blocks per requestor
87 system.cpu.icache.occ_percent::cpu.inst 0.325016 # Average percentage of cache occupancy
88 system.cpu.icache.occ_percent::total 0.325016 # Average percentage of cache occupancy
89 system.cpu.icache.ReadReq_hits::cpu.inst 217695357 # number of ReadReq hits
90 system.cpu.icache.ReadReq_hits::total 217695357 # number of ReadReq hits
91 system.cpu.icache.demand_hits::cpu.inst 217695357 # number of demand (read+write) hits
92 system.cpu.icache.demand_hits::total 217695357 # number of demand (read+write) hits
93 system.cpu.icache.overall_hits::cpu.inst 217695357 # number of overall hits
94 system.cpu.icache.overall_hits::total 217695357 # number of overall hits
95 system.cpu.icache.ReadReq_misses::cpu.inst 808 # number of ReadReq misses
96 system.cpu.icache.ReadReq_misses::total 808 # number of ReadReq misses
97 system.cpu.icache.demand_misses::cpu.inst 808 # number of demand (read+write) misses
98 system.cpu.icache.demand_misses::total 808 # number of demand (read+write) misses
99 system.cpu.icache.overall_misses::cpu.inst 808 # number of overall misses
100 system.cpu.icache.overall_misses::total 808 # number of overall misses
101 system.cpu.icache.ReadReq_miss_latency::cpu.inst 44230000 # number of ReadReq miss cycles
102 system.cpu.icache.ReadReq_miss_latency::total 44230000 # number of ReadReq miss cycles
103 system.cpu.icache.demand_miss_latency::cpu.inst 44230000 # number of demand (read+write) miss cycles
104 system.cpu.icache.demand_miss_latency::total 44230000 # number of demand (read+write) miss cycles
105 system.cpu.icache.overall_miss_latency::cpu.inst 44230000 # number of overall miss cycles
106 system.cpu.icache.overall_miss_latency::total 44230000 # number of overall miss cycles
107 system.cpu.icache.ReadReq_accesses::cpu.inst 217696165 # number of ReadReq accesses(hits+misses)
108 system.cpu.icache.ReadReq_accesses::total 217696165 # number of ReadReq accesses(hits+misses)
109 system.cpu.icache.demand_accesses::cpu.inst 217696165 # number of demand (read+write) accesses
110 system.cpu.icache.demand_accesses::total 217696165 # number of demand (read+write) accesses
111 system.cpu.icache.overall_accesses::cpu.inst 217696165 # number of overall (read+write) accesses
112 system.cpu.icache.overall_accesses::total 217696165 # number of overall (read+write) accesses
113 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses
114 system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses
115 system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses
116 system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses
117 system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses
118 system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses
119 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54740.099010 # average ReadReq miss latency
120 system.cpu.icache.ReadReq_avg_miss_latency::total 54740.099010 # average ReadReq miss latency
121 system.cpu.icache.demand_avg_miss_latency::cpu.inst 54740.099010 # average overall miss latency
122 system.cpu.icache.demand_avg_miss_latency::total 54740.099010 # average overall miss latency
123 system.cpu.icache.overall_avg_miss_latency::cpu.inst 54740.099010 # average overall miss latency
124 system.cpu.icache.overall_avg_miss_latency::total 54740.099010 # average overall miss latency
125 system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
126 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
127 system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
128 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
129 system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
130 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
131 system.cpu.icache.fast_writes 0 # number of fast writes performed
132 system.cpu.icache.cache_copies 0 # number of cache copies performed
133 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 808 # number of ReadReq MSHR misses
134 system.cpu.icache.ReadReq_mshr_misses::total 808 # number of ReadReq MSHR misses
135 system.cpu.icache.demand_mshr_misses::cpu.inst 808 # number of demand (read+write) MSHR misses
136 system.cpu.icache.demand_mshr_misses::total 808 # number of demand (read+write) MSHR misses
137 system.cpu.icache.overall_mshr_misses::cpu.inst 808 # number of overall MSHR misses
138 system.cpu.icache.overall_mshr_misses::total 808 # number of overall MSHR misses
139 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 42614000 # number of ReadReq MSHR miss cycles
140 system.cpu.icache.ReadReq_mshr_miss_latency::total 42614000 # number of ReadReq MSHR miss cycles
141 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 42614000 # number of demand (read+write) MSHR miss cycles
142 system.cpu.icache.demand_mshr_miss_latency::total 42614000 # number of demand (read+write) MSHR miss cycles
143 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 42614000 # number of overall MSHR miss cycles
144 system.cpu.icache.overall_mshr_miss_latency::total 42614000 # number of overall MSHR miss cycles
145 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses
146 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses
147 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses
148 system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses
149 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses
150 system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses
151 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52740.099010 # average ReadReq mshr miss latency
152 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52740.099010 # average ReadReq mshr miss latency
153 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52740.099010 # average overall mshr miss latency
154 system.cpu.icache.demand_avg_mshr_miss_latency::total 52740.099010 # average overall mshr miss latency
155 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52740.099010 # average overall mshr miss latency
156 system.cpu.icache.overall_avg_mshr_miss_latency::total 52740.099010 # average overall mshr miss latency
157 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
158 system.cpu.l2cache.replacements 318 # number of replacements
159 system.cpu.l2cache.tagsinuse 20041.899765 # Cycle average of tags in use
160 system.cpu.l2cache.total_refs 3992419 # Total number of references to valid blocks.
161 system.cpu.l2cache.sampled_refs 30026 # Sample count of references to valid blocks.
162 system.cpu.l2cache.avg_refs 132.965397 # Average number of references to valid blocks.
163 system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
164 system.cpu.l2cache.occ_blocks::writebacks 19330.353164 # Average occupied blocks per requestor
165 system.cpu.l2cache.occ_blocks::cpu.inst 557.646382 # Average occupied blocks per requestor
166 system.cpu.l2cache.occ_blocks::cpu.data 153.900219 # Average occupied blocks per requestor
167 system.cpu.l2cache.occ_percent::writebacks 0.589916 # Average percentage of cache occupancy
168 system.cpu.l2cache.occ_percent::cpu.inst 0.017018 # Average percentage of cache occupancy
169 system.cpu.l2cache.occ_percent::cpu.data 0.004697 # Average percentage of cache occupancy
170 system.cpu.l2cache.occ_percent::total 0.611630 # Average percentage of cache occupancy
171 system.cpu.l2cache.ReadReq_hits::cpu.inst 5 # number of ReadReq hits
172 system.cpu.l2cache.ReadReq_hits::cpu.data 1960498 # number of ReadReq hits
173 system.cpu.l2cache.ReadReq_hits::total 1960503 # number of ReadReq hits
174 system.cpu.l2cache.Writeback_hits::writebacks 2062484 # number of Writeback hits
175 system.cpu.l2cache.Writeback_hits::total 2062484 # number of Writeback hits
176 system.cpu.l2cache.ReadExReq_hits::cpu.data 77085 # number of ReadExReq hits
177 system.cpu.l2cache.ReadExReq_hits::total 77085 # number of ReadExReq hits
178 system.cpu.l2cache.demand_hits::cpu.inst 5 # number of demand (read+write) hits
179 system.cpu.l2cache.demand_hits::cpu.data 2037583 # number of demand (read+write) hits
180 system.cpu.l2cache.demand_hits::total 2037588 # number of demand (read+write) hits
181 system.cpu.l2cache.overall_hits::cpu.inst 5 # number of overall hits
182 system.cpu.l2cache.overall_hits::cpu.data 2037583 # number of overall hits
183 system.cpu.l2cache.overall_hits::total 2037588 # number of overall hits
184 system.cpu.l2cache.ReadReq_misses::cpu.inst 803 # number of ReadReq misses
185 system.cpu.l2cache.ReadReq_misses::cpu.data 222 # number of ReadReq misses
186 system.cpu.l2cache.ReadReq_misses::total 1025 # number of ReadReq misses
187 system.cpu.l2cache.ReadExReq_misses::cpu.data 29024 # number of ReadExReq misses
188 system.cpu.l2cache.ReadExReq_misses::total 29024 # number of ReadExReq misses
189 system.cpu.l2cache.demand_misses::cpu.inst 803 # number of demand (read+write) misses
190 system.cpu.l2cache.demand_misses::cpu.data 29246 # number of demand (read+write) misses
191 system.cpu.l2cache.demand_misses::total 30049 # number of demand (read+write) misses
192 system.cpu.l2cache.overall_misses::cpu.inst 803 # number of overall misses
193 system.cpu.l2cache.overall_misses::cpu.data 29246 # number of overall misses
194 system.cpu.l2cache.overall_misses::total 30049 # number of overall misses
195 system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 41756000 # number of ReadReq miss cycles
196 system.cpu.l2cache.ReadReq_miss_latency::cpu.data 11544000 # number of ReadReq miss cycles
197 system.cpu.l2cache.ReadReq_miss_latency::total 53300000 # number of ReadReq miss cycles
198 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1509279000 # number of ReadExReq miss cycles
199 system.cpu.l2cache.ReadExReq_miss_latency::total 1509279000 # number of ReadExReq miss cycles
200 system.cpu.l2cache.demand_miss_latency::cpu.inst 41756000 # number of demand (read+write) miss cycles
201 system.cpu.l2cache.demand_miss_latency::cpu.data 1520823000 # number of demand (read+write) miss cycles
202 system.cpu.l2cache.demand_miss_latency::total 1562579000 # number of demand (read+write) miss cycles
203 system.cpu.l2cache.overall_miss_latency::cpu.inst 41756000 # number of overall miss cycles
204 system.cpu.l2cache.overall_miss_latency::cpu.data 1520823000 # number of overall miss cycles
205 system.cpu.l2cache.overall_miss_latency::total 1562579000 # number of overall miss cycles
206 system.cpu.l2cache.ReadReq_accesses::cpu.inst 808 # number of ReadReq accesses(hits+misses)
207 system.cpu.l2cache.ReadReq_accesses::cpu.data 1960720 # number of ReadReq accesses(hits+misses)
208 system.cpu.l2cache.ReadReq_accesses::total 1961528 # number of ReadReq accesses(hits+misses)
209 system.cpu.l2cache.Writeback_accesses::writebacks 2062484 # number of Writeback accesses(hits+misses)
210 system.cpu.l2cache.Writeback_accesses::total 2062484 # number of Writeback accesses(hits+misses)
211 system.cpu.l2cache.ReadExReq_accesses::cpu.data 106109 # number of ReadExReq accesses(hits+misses)
212 system.cpu.l2cache.ReadExReq_accesses::total 106109 # number of ReadExReq accesses(hits+misses)
213 system.cpu.l2cache.demand_accesses::cpu.inst 808 # number of demand (read+write) accesses
214 system.cpu.l2cache.demand_accesses::cpu.data 2066829 # number of demand (read+write) accesses
215 system.cpu.l2cache.demand_accesses::total 2067637 # number of demand (read+write) accesses
216 system.cpu.l2cache.overall_accesses::cpu.inst 808 # number of overall (read+write) accesses
217 system.cpu.l2cache.overall_accesses::cpu.data 2066829 # number of overall (read+write) accesses
218 system.cpu.l2cache.overall_accesses::total 2067637 # number of overall (read+write) accesses
219 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.993812 # miss rate for ReadReq accesses
220 system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000113 # miss rate for ReadReq accesses
221 system.cpu.l2cache.ReadReq_miss_rate::total 0.000523 # miss rate for ReadReq accesses
222 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.273530 # miss rate for ReadExReq accesses
223 system.cpu.l2cache.ReadExReq_miss_rate::total 0.273530 # miss rate for ReadExReq accesses
224 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993812 # miss rate for demand accesses
225 system.cpu.l2cache.demand_miss_rate::cpu.data 0.014150 # miss rate for demand accesses
226 system.cpu.l2cache.demand_miss_rate::total 0.014533 # miss rate for demand accesses
227 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993812 # miss rate for overall accesses
228 system.cpu.l2cache.overall_miss_rate::cpu.data 0.014150 # miss rate for overall accesses
229 system.cpu.l2cache.overall_miss_rate::total 0.014533 # miss rate for overall accesses
230 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
231 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
232 system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
233 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52001.068082 # average ReadExReq miss latency
234 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52001.068082 # average ReadExReq miss latency
235 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
236 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52001.059974 # average overall miss latency
237 system.cpu.l2cache.demand_avg_miss_latency::total 52001.031648 # average overall miss latency
238 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
239 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52001.059974 # average overall miss latency
240 system.cpu.l2cache.overall_avg_miss_latency::total 52001.031648 # average overall miss latency
241 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
242 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
243 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
244 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
245 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
246 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
247 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
248 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
249 system.cpu.l2cache.writebacks::writebacks 100 # number of writebacks
250 system.cpu.l2cache.writebacks::total 100 # number of writebacks
251 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 803 # number of ReadReq MSHR misses
252 system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 222 # number of ReadReq MSHR misses
253 system.cpu.l2cache.ReadReq_mshr_misses::total 1025 # number of ReadReq MSHR misses
254 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 29024 # number of ReadExReq MSHR misses
255 system.cpu.l2cache.ReadExReq_mshr_misses::total 29024 # number of ReadExReq MSHR misses
256 system.cpu.l2cache.demand_mshr_misses::cpu.inst 803 # number of demand (read+write) MSHR misses
257 system.cpu.l2cache.demand_mshr_misses::cpu.data 29246 # number of demand (read+write) MSHR misses
258 system.cpu.l2cache.demand_mshr_misses::total 30049 # number of demand (read+write) MSHR misses
259 system.cpu.l2cache.overall_mshr_misses::cpu.inst 803 # number of overall MSHR misses
260 system.cpu.l2cache.overall_mshr_misses::cpu.data 29246 # number of overall MSHR misses
261 system.cpu.l2cache.overall_mshr_misses::total 30049 # number of overall MSHR misses
262 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 32120000 # number of ReadReq MSHR miss cycles
263 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8880000 # number of ReadReq MSHR miss cycles
264 system.cpu.l2cache.ReadReq_mshr_miss_latency::total 41000000 # number of ReadReq MSHR miss cycles
265 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1160960000 # number of ReadExReq MSHR miss cycles
266 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1160960000 # number of ReadExReq MSHR miss cycles
267 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 32120000 # number of demand (read+write) MSHR miss cycles
268 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1169840000 # number of demand (read+write) MSHR miss cycles
269 system.cpu.l2cache.demand_mshr_miss_latency::total 1201960000 # number of demand (read+write) MSHR miss cycles
270 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 32120000 # number of overall MSHR miss cycles
271 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1169840000 # number of overall MSHR miss cycles
272 system.cpu.l2cache.overall_mshr_miss_latency::total 1201960000 # number of overall MSHR miss cycles
273 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993812 # mshr miss rate for ReadReq accesses
274 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000113 # mshr miss rate for ReadReq accesses
275 system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000523 # mshr miss rate for ReadReq accesses
276 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.273530 # mshr miss rate for ReadExReq accesses
277 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.273530 # mshr miss rate for ReadExReq accesses
278 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993812 # mshr miss rate for demand accesses
279 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014150 # mshr miss rate for demand accesses
280 system.cpu.l2cache.demand_mshr_miss_rate::total 0.014533 # mshr miss rate for demand accesses
281 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993812 # mshr miss rate for overall accesses
282 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014150 # mshr miss rate for overall accesses
283 system.cpu.l2cache.overall_mshr_miss_rate::total 0.014533 # mshr miss rate for overall accesses
284 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
285 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
286 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
287 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
288 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
289 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
290 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
291 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
292 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
293 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
294 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
295 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
296 system.cpu.dcache.replacements 2062733 # number of replacements
297 system.cpu.dcache.tagsinuse 4076.488619 # Cycle average of tags in use
298 system.cpu.dcache.total_refs 120152370 # Total number of references to valid blocks.
299 system.cpu.dcache.sampled_refs 2066829 # Sample count of references to valid blocks.
300 system.cpu.dcache.avg_refs 58.133677 # Average number of references to valid blocks.
301 system.cpu.dcache.warmup_cycle 126079701000 # Cycle when the warmup percentage was hit.
302 system.cpu.dcache.occ_blocks::cpu.data 4076.488619 # Average occupied blocks per requestor
303 system.cpu.dcache.occ_percent::cpu.data 0.995236 # Average percentage of cache occupancy
304 system.cpu.dcache.occ_percent::total 0.995236 # Average percentage of cache occupancy
305 system.cpu.dcache.ReadReq_hits::cpu.data 88818727 # number of ReadReq hits
306 system.cpu.dcache.ReadReq_hits::total 88818727 # number of ReadReq hits
307 system.cpu.dcache.WriteReq_hits::cpu.data 31333643 # number of WriteReq hits
308 system.cpu.dcache.WriteReq_hits::total 31333643 # number of WriteReq hits
309 system.cpu.dcache.demand_hits::cpu.data 120152370 # number of demand (read+write) hits
310 system.cpu.dcache.demand_hits::total 120152370 # number of demand (read+write) hits
311 system.cpu.dcache.overall_hits::cpu.data 120152370 # number of overall hits
312 system.cpu.dcache.overall_hits::total 120152370 # number of overall hits
313 system.cpu.dcache.ReadReq_misses::cpu.data 1960720 # number of ReadReq misses
314 system.cpu.dcache.ReadReq_misses::total 1960720 # number of ReadReq misses
315 system.cpu.dcache.WriteReq_misses::cpu.data 106109 # number of WriteReq misses
316 system.cpu.dcache.WriteReq_misses::total 106109 # number of WriteReq misses
317 system.cpu.dcache.demand_misses::cpu.data 2066829 # number of demand (read+write) misses
318 system.cpu.dcache.demand_misses::total 2066829 # number of demand (read+write) misses
319 system.cpu.dcache.overall_misses::cpu.data 2066829 # number of overall misses
320 system.cpu.dcache.overall_misses::total 2066829 # number of overall misses
321 system.cpu.dcache.ReadReq_miss_latency::cpu.data 25498684000 # number of ReadReq miss cycles
322 system.cpu.dcache.ReadReq_miss_latency::total 25498684000 # number of ReadReq miss cycles
323 system.cpu.dcache.WriteReq_miss_latency::cpu.data 2598456000 # number of WriteReq miss cycles
324 system.cpu.dcache.WriteReq_miss_latency::total 2598456000 # number of WriteReq miss cycles
325 system.cpu.dcache.demand_miss_latency::cpu.data 28097140000 # number of demand (read+write) miss cycles
326 system.cpu.dcache.demand_miss_latency::total 28097140000 # number of demand (read+write) miss cycles
327 system.cpu.dcache.overall_miss_latency::cpu.data 28097140000 # number of overall miss cycles
328 system.cpu.dcache.overall_miss_latency::total 28097140000 # number of overall miss cycles
329 system.cpu.dcache.ReadReq_accesses::cpu.data 90779447 # number of ReadReq accesses(hits+misses)
330 system.cpu.dcache.ReadReq_accesses::total 90779447 # number of ReadReq accesses(hits+misses)
331 system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses)
332 system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses)
333 system.cpu.dcache.demand_accesses::cpu.data 122219199 # number of demand (read+write) accesses
334 system.cpu.dcache.demand_accesses::total 122219199 # number of demand (read+write) accesses
335 system.cpu.dcache.overall_accesses::cpu.data 122219199 # number of overall (read+write) accesses
336 system.cpu.dcache.overall_accesses::total 122219199 # number of overall (read+write) accesses
337 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.021599 # miss rate for ReadReq accesses
338 system.cpu.dcache.ReadReq_miss_rate::total 0.021599 # miss rate for ReadReq accesses
339 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003375 # miss rate for WriteReq accesses
340 system.cpu.dcache.WriteReq_miss_rate::total 0.003375 # miss rate for WriteReq accesses
341 system.cpu.dcache.demand_miss_rate::cpu.data 0.016911 # miss rate for demand accesses
342 system.cpu.dcache.demand_miss_rate::total 0.016911 # miss rate for demand accesses
343 system.cpu.dcache.overall_miss_rate::cpu.data 0.016911 # miss rate for overall accesses
344 system.cpu.dcache.overall_miss_rate::total 0.016911 # miss rate for overall accesses
345 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13004.755396 # average ReadReq miss latency
346 system.cpu.dcache.ReadReq_avg_miss_latency::total 13004.755396 # average ReadReq miss latency
347 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24488.554223 # average WriteReq miss latency
348 system.cpu.dcache.WriteReq_avg_miss_latency::total 24488.554223 # average WriteReq miss latency
349 system.cpu.dcache.demand_avg_miss_latency::cpu.data 13594.322510 # average overall miss latency
350 system.cpu.dcache.demand_avg_miss_latency::total 13594.322510 # average overall miss latency
351 system.cpu.dcache.overall_avg_miss_latency::cpu.data 13594.322510 # average overall miss latency
352 system.cpu.dcache.overall_avg_miss_latency::total 13594.322510 # average overall miss latency
353 system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
354 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
355 system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
356 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
357 system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
358 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
359 system.cpu.dcache.fast_writes 0 # number of fast writes performed
360 system.cpu.dcache.cache_copies 0 # number of cache copies performed
361 system.cpu.dcache.writebacks::writebacks 2062484 # number of writebacks
362 system.cpu.dcache.writebacks::total 2062484 # number of writebacks
363 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1960720 # number of ReadReq MSHR misses
364 system.cpu.dcache.ReadReq_mshr_misses::total 1960720 # number of ReadReq MSHR misses
365 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 106109 # number of WriteReq MSHR misses
366 system.cpu.dcache.WriteReq_mshr_misses::total 106109 # number of WriteReq MSHR misses
367 system.cpu.dcache.demand_mshr_misses::cpu.data 2066829 # number of demand (read+write) MSHR misses
368 system.cpu.dcache.demand_mshr_misses::total 2066829 # number of demand (read+write) MSHR misses
369 system.cpu.dcache.overall_mshr_misses::cpu.data 2066829 # number of overall MSHR misses
370 system.cpu.dcache.overall_mshr_misses::total 2066829 # number of overall MSHR misses
371 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21577244000 # number of ReadReq MSHR miss cycles
372 system.cpu.dcache.ReadReq_mshr_miss_latency::total 21577244000 # number of ReadReq MSHR miss cycles
373 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2386238000 # number of WriteReq MSHR miss cycles
374 system.cpu.dcache.WriteReq_mshr_miss_latency::total 2386238000 # number of WriteReq MSHR miss cycles
375 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23963482000 # number of demand (read+write) MSHR miss cycles
376 system.cpu.dcache.demand_mshr_miss_latency::total 23963482000 # number of demand (read+write) MSHR miss cycles
377 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23963482000 # number of overall MSHR miss cycles
378 system.cpu.dcache.overall_mshr_miss_latency::total 23963482000 # number of overall MSHR miss cycles
379 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.021599 # mshr miss rate for ReadReq accesses
380 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.021599 # mshr miss rate for ReadReq accesses
381 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003375 # mshr miss rate for WriteReq accesses
382 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.003375 # mshr miss rate for WriteReq accesses
383 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016911 # mshr miss rate for demand accesses
384 system.cpu.dcache.demand_mshr_miss_rate::total 0.016911 # mshr miss rate for demand accesses
385 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016911 # mshr miss rate for overall accesses
386 system.cpu.dcache.overall_mshr_miss_rate::total 0.016911 # mshr miss rate for overall accesses
387 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11004.755396 # average ReadReq mshr miss latency
388 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11004.755396 # average ReadReq mshr miss latency
389 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22488.554223 # average WriteReq mshr miss latency
390 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22488.554223 # average WriteReq mshr miss latency
391 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11594.322510 # average overall mshr miss latency
392 system.cpu.dcache.demand_avg_mshr_miss_latency::total 11594.322510 # average overall mshr miss latency
393 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11594.322510 # average overall mshr miss latency
394 system.cpu.dcache.overall_avg_mshr_miss_latency::total 11594.322510 # average overall mshr miss latency
395 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
396 system.cpu.toL2Bus.throughput 722228529 # Throughput (bytes/s)
397 system.cpu.toL2Bus.trans_dist::ReadReq 1961528 # Transaction distribution
398 system.cpu.toL2Bus.trans_dist::ReadResp 1961528 # Transaction distribution
399 system.cpu.toL2Bus.trans_dist::Writeback 2062484 # Transaction distribution
400 system.cpu.toL2Bus.trans_dist::ReadExReq 106109 # Transaction distribution
401 system.cpu.toL2Bus.trans_dist::ReadExResp 106109 # Transaction distribution
402 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1616 # Packet count per connected master and slave (bytes)
403 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 6196142 # Packet count per connected master and slave (bytes)
404 system.cpu.toL2Bus.pkt_count 6197758 # Packet count per connected master and slave (bytes)
405 system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 51712 # Cumulative packet size per connected master and slave (bytes)
406 system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 264276032 # Cumulative packet size per connected master and slave (bytes)
407 system.cpu.toL2Bus.tot_pkt_size 264327744 # Cumulative packet size per connected master and slave (bytes)
408 system.cpu.toL2Bus.data_through_bus 264327744 # Total data (bytes)
409 system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
410 system.cpu.toL2Bus.reqLayer0.occupancy 4127544500 # Layer occupancy (ticks)
411 system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%)
412 system.cpu.toL2Bus.respLayer0.occupancy 1212000 # Layer occupancy (ticks)
413 system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
414 system.cpu.toL2Bus.respLayer1.occupancy 3100243500 # Layer occupancy (ticks)
415 system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%)
417 ---------- End Simulation Statistics ----------
projects / gem5.git / blob