2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.362632 # Number of seconds simulated
4 sim_ticks 362631828500 # Number of ticks simulated
5 final_tick 362631828500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 285981 # Simulator instruction rate (inst/s)
8 host_op_rate 309756 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 204718125 # Simulator tick rate (ticks/s)
10 host_mem_usage 275016 # Number of bytes of host memory used
11 host_seconds 1771.37 # Real time elapsed on the host
12 sim_insts 506579366 # Number of instructions simulated
13 sim_ops 548692589 # Number of ops (including micro ops) simulated
14 system.voltage_domain.voltage 1 # Voltage in Volts
15 system.clk_domain.clock 1000 # Clock period in ticks
16 system.physmem.bytes_read::cpu.inst 179456 # Number of bytes read from this memory
17 system.physmem.bytes_read::cpu.data 9032064 # Number of bytes read from this memory
18 system.physmem.bytes_read::total 9211520 # Number of bytes read from this memory
19 system.physmem.bytes_inst_read::cpu.inst 179456 # Number of instructions bytes read from this memory
20 system.physmem.bytes_inst_read::total 179456 # Number of instructions bytes read from this memory
21 system.physmem.bytes_written::writebacks 6221440 # Number of bytes written to this memory
22 system.physmem.bytes_written::total 6221440 # Number of bytes written to this memory
23 system.physmem.num_reads::cpu.inst 2804 # Number of read requests responded to by this memory
24 system.physmem.num_reads::cpu.data 141126 # Number of read requests responded to by this memory
25 system.physmem.num_reads::total 143930 # Number of read requests responded to by this memory
26 system.physmem.num_writes::writebacks 97210 # Number of write requests responded to by this memory
27 system.physmem.num_writes::total 97210 # Number of write requests responded to by this memory
28 system.physmem.bw_read::cpu.inst 494871 # Total read bandwidth from this memory (bytes/s)
29 system.physmem.bw_read::cpu.data 24906981 # Total read bandwidth from this memory (bytes/s)
30 system.physmem.bw_read::total 25401852 # Total read bandwidth from this memory (bytes/s)
31 system.physmem.bw_inst_read::cpu.inst 494871 # Instruction read bandwidth from this memory (bytes/s)
32 system.physmem.bw_inst_read::total 494871 # Instruction read bandwidth from this memory (bytes/s)
33 system.physmem.bw_write::writebacks 17156354 # Write bandwidth from this memory (bytes/s)
34 system.physmem.bw_write::total 17156354 # Write bandwidth from this memory (bytes/s)
35 system.physmem.bw_total::writebacks 17156354 # Total bandwidth to/from this memory (bytes/s)
36 system.physmem.bw_total::cpu.inst 494871 # Total bandwidth to/from this memory (bytes/s)
37 system.physmem.bw_total::cpu.data 24906981 # Total bandwidth to/from this memory (bytes/s)
38 system.physmem.bw_total::total 42558206 # Total bandwidth to/from this memory (bytes/s)
39 system.physmem.readReqs 143930 # Number of read requests accepted
40 system.physmem.writeReqs 97210 # Number of write requests accepted
41 system.physmem.readBursts 143930 # Number of DRAM read bursts, including those serviced by the write queue
42 system.physmem.writeBursts 97210 # Number of DRAM write bursts, including those merged in the write queue
43 system.physmem.bytesReadDRAM 9204736 # Total number of bytes read from DRAM
44 system.physmem.bytesReadWrQ 6784 # Total number of bytes read from write queue
45 system.physmem.bytesWritten 6219456 # Total number of bytes written to DRAM
46 system.physmem.bytesReadSys 9211520 # Total read bytes from the system interface side
47 system.physmem.bytesWrittenSys 6221440 # Total written bytes from the system interface side
48 system.physmem.servicedByWrQ 106 # Number of DRAM read bursts serviced by the write queue
49 system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
50 system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
51 system.physmem.perBankRdBursts::0 9406 # Per bank write bursts
52 system.physmem.perBankRdBursts::1 8921 # Per bank write bursts
53 system.physmem.perBankRdBursts::2 8949 # Per bank write bursts
54 system.physmem.perBankRdBursts::3 8657 # Per bank write bursts
55 system.physmem.perBankRdBursts::4 9384 # Per bank write bursts
56 system.physmem.perBankRdBursts::5 9355 # Per bank write bursts
57 system.physmem.perBankRdBursts::6 8962 # Per bank write bursts
58 system.physmem.perBankRdBursts::7 8101 # Per bank write bursts
59 system.physmem.perBankRdBursts::8 8596 # Per bank write bursts
60 system.physmem.perBankRdBursts::9 8628 # Per bank write bursts
61 system.physmem.perBankRdBursts::10 8740 # Per bank write bursts
62 system.physmem.perBankRdBursts::11 9454 # Per bank write bursts
63 system.physmem.perBankRdBursts::12 9340 # Per bank write bursts
64 system.physmem.perBankRdBursts::13 9510 # Per bank write bursts
65 system.physmem.perBankRdBursts::14 8709 # Per bank write bursts
66 system.physmem.perBankRdBursts::15 9112 # Per bank write bursts
67 system.physmem.perBankWrBursts::0 6249 # Per bank write bursts
68 system.physmem.perBankWrBursts::1 6105 # Per bank write bursts
69 system.physmem.perBankWrBursts::2 6032 # Per bank write bursts
70 system.physmem.perBankWrBursts::3 5882 # Per bank write bursts
71 system.physmem.perBankWrBursts::4 6237 # Per bank write bursts
72 system.physmem.perBankWrBursts::5 6240 # Per bank write bursts
73 system.physmem.perBankWrBursts::6 6051 # Per bank write bursts
74 system.physmem.perBankWrBursts::7 5508 # Per bank write bursts
75 system.physmem.perBankWrBursts::8 5781 # Per bank write bursts
76 system.physmem.perBankWrBursts::9 5861 # Per bank write bursts
77 system.physmem.perBankWrBursts::10 5978 # Per bank write bursts
78 system.physmem.perBankWrBursts::11 6494 # Per bank write bursts
79 system.physmem.perBankWrBursts::12 6355 # Per bank write bursts
80 system.physmem.perBankWrBursts::13 6320 # Per bank write bursts
81 system.physmem.perBankWrBursts::14 6000 # Per bank write bursts
82 system.physmem.perBankWrBursts::15 6086 # Per bank write bursts
83 system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
84 system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
85 system.physmem.totGap 362631802500 # Total gap between requests
86 system.physmem.readPktSize::0 0 # Read request sizes (log2)
87 system.physmem.readPktSize::1 0 # Read request sizes (log2)
88 system.physmem.readPktSize::2 0 # Read request sizes (log2)
89 system.physmem.readPktSize::3 0 # Read request sizes (log2)
90 system.physmem.readPktSize::4 0 # Read request sizes (log2)
91 system.physmem.readPktSize::5 0 # Read request sizes (log2)
92 system.physmem.readPktSize::6 143930 # Read request sizes (log2)
93 system.physmem.writePktSize::0 0 # Write request sizes (log2)
94 system.physmem.writePktSize::1 0 # Write request sizes (log2)
95 system.physmem.writePktSize::2 0 # Write request sizes (log2)
96 system.physmem.writePktSize::3 0 # Write request sizes (log2)
97 system.physmem.writePktSize::4 0 # Write request sizes (log2)
98 system.physmem.writePktSize::5 0 # Write request sizes (log2)
99 system.physmem.writePktSize::6 97210 # Write request sizes (log2)
100 system.physmem.rdQLenPdf::0 143484 # What read queue length does an incoming req see
101 system.physmem.rdQLenPdf::1 320 # What read queue length does an incoming req see
102 system.physmem.rdQLenPdf::2 20 # What read queue length does an incoming req see
103 system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
104 system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
105 system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
106 system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
107 system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
108 system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
109 system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
110 system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
111 system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
112 system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
113 system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
114 system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
115 system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
116 system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
117 system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
118 system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
119 system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
120 system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
121 system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
122 system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
123 system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
124 system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
125 system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
126 system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
127 system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
128 system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
129 system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
130 system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
131 system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
132 system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
133 system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
134 system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
135 system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
136 system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
137 system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
138 system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
139 system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
140 system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
141 system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
142 system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
143 system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
144 system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
145 system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
146 system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
147 system.physmem.wrQLenPdf::15 2964 # What write queue length does an incoming req see
148 system.physmem.wrQLenPdf::16 3137 # What write queue length does an incoming req see
149 system.physmem.wrQLenPdf::17 5566 # What write queue length does an incoming req see
150 system.physmem.wrQLenPdf::18 5692 # What write queue length does an incoming req see
151 system.physmem.wrQLenPdf::19 5699 # What write queue length does an incoming req see
152 system.physmem.wrQLenPdf::20 5705 # What write queue length does an incoming req see
153 system.physmem.wrQLenPdf::21 5705 # What write queue length does an incoming req see
154 system.physmem.wrQLenPdf::22 5703 # What write queue length does an incoming req see
155 system.physmem.wrQLenPdf::23 5710 # What write queue length does an incoming req see
156 system.physmem.wrQLenPdf::24 5731 # What write queue length does an incoming req see
157 system.physmem.wrQLenPdf::25 5739 # What write queue length does an incoming req see
158 system.physmem.wrQLenPdf::26 5733 # What write queue length does an incoming req see
159 system.physmem.wrQLenPdf::27 5740 # What write queue length does an incoming req see
160 system.physmem.wrQLenPdf::28 5717 # What write queue length does an incoming req see
161 system.physmem.wrQLenPdf::29 5686 # What write queue length does an incoming req see
162 system.physmem.wrQLenPdf::30 5684 # What write queue length does an incoming req see
163 system.physmem.wrQLenPdf::31 5636 # What write queue length does an incoming req see
164 system.physmem.wrQLenPdf::32 5622 # What write queue length does an incoming req see
165 system.physmem.wrQLenPdf::33 14 # What write queue length does an incoming req see
166 system.physmem.wrQLenPdf::34 6 # What write queue length does an incoming req see
167 system.physmem.wrQLenPdf::35 3 # What write queue length does an incoming req see
168 system.physmem.wrQLenPdf::36 1 # What write queue length does an incoming req see
169 system.physmem.wrQLenPdf::37 1 # What write queue length does an incoming req see
170 system.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see
171 system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
172 system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
173 system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
174 system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
175 system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
176 system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
177 system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
178 system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
179 system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
180 system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
181 system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
182 system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
183 system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
184 system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
185 system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
186 system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
187 system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
188 system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
189 system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
190 system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
191 system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
192 system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
193 system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
194 system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
195 system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
196 system.physmem.bytesPerActivate::samples 65461 # Bytes accessed per row activation
197 system.physmem.bytesPerActivate::mean 235.617299 # Bytes accessed per row activation
198 system.physmem.bytesPerActivate::gmean 156.242018 # Bytes accessed per row activation
199 system.physmem.bytesPerActivate::stdev 241.589954 # Bytes accessed per row activation
200 system.physmem.bytesPerActivate::0-127 24858 37.97% 37.97% # Bytes accessed per row activation
201 system.physmem.bytesPerActivate::128-255 18413 28.13% 66.10% # Bytes accessed per row activation
202 system.physmem.bytesPerActivate::256-383 6961 10.63% 76.74% # Bytes accessed per row activation
203 system.physmem.bytesPerActivate::384-511 7914 12.09% 88.83% # Bytes accessed per row activation
204 system.physmem.bytesPerActivate::512-639 2009 3.07% 91.89% # Bytes accessed per row activation
205 system.physmem.bytesPerActivate::640-767 1136 1.74% 93.63% # Bytes accessed per row activation
206 system.physmem.bytesPerActivate::768-895 792 1.21% 94.84% # Bytes accessed per row activation
207 system.physmem.bytesPerActivate::896-1023 657 1.00% 95.84% # Bytes accessed per row activation
208 system.physmem.bytesPerActivate::1024-1151 2721 4.16% 100.00% # Bytes accessed per row activation
209 system.physmem.bytesPerActivate::total 65461 # Bytes accessed per row activation
210 system.physmem.rdPerTurnAround::samples 5611 # Reads before turning the bus around for writes
211 system.physmem.rdPerTurnAround::mean 25.630191 # Reads before turning the bus around for writes
212 system.physmem.rdPerTurnAround::stdev 380.618779 # Reads before turning the bus around for writes
213 system.physmem.rdPerTurnAround::0-1023 5609 99.96% 99.96% # Reads before turning the bus around for writes
214 system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.98% # Reads before turning the bus around for writes
215 system.physmem.rdPerTurnAround::27648-28671 1 0.02% 100.00% # Reads before turning the bus around for writes
216 system.physmem.rdPerTurnAround::total 5611 # Reads before turning the bus around for writes
217 system.physmem.wrPerTurnAround::samples 5611 # Writes before turning the bus around for reads
218 system.physmem.wrPerTurnAround::mean 17.319373 # Writes before turning the bus around for reads
219 system.physmem.wrPerTurnAround::gmean 17.223479 # Writes before turning the bus around for reads
220 system.physmem.wrPerTurnAround::stdev 2.351913 # Writes before turning the bus around for reads
221 system.physmem.wrPerTurnAround::16-17 2643 47.10% 47.10% # Writes before turning the bus around for reads
222 system.physmem.wrPerTurnAround::18-19 2820 50.26% 97.36% # Writes before turning the bus around for reads
223 system.physmem.wrPerTurnAround::20-21 52 0.93% 98.29% # Writes before turning the bus around for reads
224 system.physmem.wrPerTurnAround::22-23 28 0.50% 98.79% # Writes before turning the bus around for reads
225 system.physmem.wrPerTurnAround::24-25 21 0.37% 99.16% # Writes before turning the bus around for reads
226 system.physmem.wrPerTurnAround::26-27 8 0.14% 99.30% # Writes before turning the bus around for reads
227 system.physmem.wrPerTurnAround::28-29 6 0.11% 99.41% # Writes before turning the bus around for reads
228 system.physmem.wrPerTurnAround::30-31 9 0.16% 99.57% # Writes before turning the bus around for reads
229 system.physmem.wrPerTurnAround::32-33 4 0.07% 99.64% # Writes before turning the bus around for reads
230 system.physmem.wrPerTurnAround::34-35 6 0.11% 99.75% # Writes before turning the bus around for reads
231 system.physmem.wrPerTurnAround::36-37 5 0.09% 99.84% # Writes before turning the bus around for reads
232 system.physmem.wrPerTurnAround::40-41 1 0.02% 99.86% # Writes before turning the bus around for reads
233 system.physmem.wrPerTurnAround::42-43 3 0.05% 99.91% # Writes before turning the bus around for reads
234 system.physmem.wrPerTurnAround::44-45 2 0.04% 99.95% # Writes before turning the bus around for reads
235 system.physmem.wrPerTurnAround::70-71 1 0.02% 99.96% # Writes before turning the bus around for reads
236 system.physmem.wrPerTurnAround::72-73 1 0.02% 99.98% # Writes before turning the bus around for reads
237 system.physmem.wrPerTurnAround::90-91 1 0.02% 100.00% # Writes before turning the bus around for reads
238 system.physmem.wrPerTurnAround::total 5611 # Writes before turning the bus around for reads
239 system.physmem.totQLat 1538291500 # Total ticks spent queuing
240 system.physmem.totMemAccLat 4234991500 # Total ticks spent from burst creation until serviced by the DRAM
241 system.physmem.totBusLat 719120000 # Total ticks spent in databus transfers
242 system.physmem.avgQLat 10695.65 # Average queueing delay per DRAM burst
243 system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
244 system.physmem.avgMemAccLat 29445.65 # Average memory access latency per DRAM burst
245 system.physmem.avgRdBW 25.38 # Average DRAM read bandwidth in MiByte/s
246 system.physmem.avgWrBW 17.15 # Average achieved write bandwidth in MiByte/s
247 system.physmem.avgRdBWSys 25.40 # Average system read bandwidth in MiByte/s
248 system.physmem.avgWrBWSys 17.16 # Average system write bandwidth in MiByte/s
249 system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
250 system.physmem.busUtil 0.33 # Data bus utilization in percentage
251 system.physmem.busUtilRead 0.20 # Data bus utilization in percentage for reads
252 system.physmem.busUtilWrite 0.13 # Data bus utilization in percentage for writes
253 system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing
254 system.physmem.avgWrQLen 19.56 # Average write queue length when enqueuing
255 system.physmem.readRowHits 110801 # Number of row buffer hits during reads
256 system.physmem.writeRowHits 64737 # Number of row buffer hits during writes
257 system.physmem.readRowHitRate 77.04 # Row buffer hit rate for reads
258 system.physmem.writeRowHitRate 66.60 # Row buffer hit rate for writes
259 system.physmem.avgGap 1503822.69 # Average gap between requests
260 system.physmem.pageHitRate 72.83 # Row buffer hit rate, read and write combined
261 system.physmem_0.actEnergy 249185160 # Energy for activate commands per rank (pJ)
262 system.physmem_0.preEnergy 135964125 # Energy for precharge commands per rank (pJ)
263 system.physmem_0.readEnergy 559455000 # Energy for read commands per rank (pJ)
264 system.physmem_0.writeEnergy 312906240 # Energy for write commands per rank (pJ)
265 system.physmem_0.refreshEnergy 23685164880 # Energy for refresh commands per rank (pJ)
266 system.physmem_0.actBackEnergy 47417547600 # Energy for active background per rank (pJ)
267 system.physmem_0.preBackEnergy 175983265500 # Energy for precharge background per rank (pJ)
268 system.physmem_0.totalEnergy 248343488505 # Total energy per rank (pJ)
269 system.physmem_0.averagePower 684.841129 # Core power per rank (mW)
270 system.physmem_0.memoryStateTime::IDLE 292457177000 # Time in different power states
271 system.physmem_0.memoryStateTime::REF 12108980000 # Time in different power states
272 system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
273 system.physmem_0.memoryStateTime::ACT 58063198250 # Time in different power states
274 system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
275 system.physmem_1.actEnergy 245586600 # Energy for activate commands per rank (pJ)
276 system.physmem_1.preEnergy 134000625 # Energy for precharge commands per rank (pJ)
277 system.physmem_1.readEnergy 562138200 # Energy for read commands per rank (pJ)
278 system.physmem_1.writeEnergy 316684080 # Energy for write commands per rank (pJ)
279 system.physmem_1.refreshEnergy 23685164880 # Energy for refresh commands per rank (pJ)
280 system.physmem_1.actBackEnergy 46768401675 # Energy for active background per rank (pJ)
281 system.physmem_1.preBackEnergy 176552684250 # Energy for precharge background per rank (pJ)
282 system.physmem_1.totalEnergy 248264660310 # Total energy per rank (pJ)
283 system.physmem_1.averagePower 684.623774 # Core power per rank (mW)
284 system.physmem_1.memoryStateTime::IDLE 293406599500 # Time in different power states
285 system.physmem_1.memoryStateTime::REF 12108980000 # Time in different power states
286 system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
287 system.physmem_1.memoryStateTime::ACT 57113763250 # Time in different power states
288 system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
289 system.cpu.branchPred.lookups 131880511 # Number of BP lookups
290 system.cpu.branchPred.condPredicted 98032974 # Number of conditional branches predicted
291 system.cpu.branchPred.condIncorrect 5909980 # Number of conditional branches incorrect
292 system.cpu.branchPred.BTBLookups 68420287 # Number of BTB lookups
293 system.cpu.branchPred.BTBHits 60518878 # Number of BTB hits
294 system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
295 system.cpu.branchPred.BTBHitPct 88.451658 # BTB Hit Percentage
296 system.cpu.branchPred.usedRAS 9982385 # Number of times the RAS was used to get a target.
297 system.cpu.branchPred.RASInCorrect 18500 # Number of incorrect RAS predictions.
298 system.cpu.branchPred.indirectLookups 3889648 # Number of indirect predictor lookups.
299 system.cpu.branchPred.indirectHits 3881527 # Number of indirect target hits.
300 system.cpu.branchPred.indirectMisses 8121 # Number of indirect misses.
301 system.cpu.branchPredindirectMispredicted 53795 # Number of mispredicted indirect branches.
302 system.cpu_clk_domain.clock 500 # Clock period in ticks
303 system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
304 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
305 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
306 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
307 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
308 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
309 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
310 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
311 system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
312 system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
313 system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
314 system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
315 system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
316 system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
317 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
318 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
319 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
320 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
321 system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
322 system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
323 system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
324 system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
325 system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
326 system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
327 system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
328 system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
329 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
330 system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
331 system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
332 system.cpu.dtb.walker.walks 0 # Table walker walks requested
333 system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
334 system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
335 system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
336 system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
337 system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
338 system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
339 system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
340 system.cpu.dtb.inst_hits 0 # ITB inst hits
341 system.cpu.dtb.inst_misses 0 # ITB inst misses
342 system.cpu.dtb.read_hits 0 # DTB read hits
343 system.cpu.dtb.read_misses 0 # DTB read misses
344 system.cpu.dtb.write_hits 0 # DTB write hits
345 system.cpu.dtb.write_misses 0 # DTB write misses
346 system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
347 system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
348 system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
349 system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
350 system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
351 system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
352 system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
353 system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
354 system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
355 system.cpu.dtb.read_accesses 0 # DTB read accesses
356 system.cpu.dtb.write_accesses 0 # DTB write accesses
357 system.cpu.dtb.inst_accesses 0 # ITB inst accesses
358 system.cpu.dtb.hits 0 # DTB hits
359 system.cpu.dtb.misses 0 # DTB misses
360 system.cpu.dtb.accesses 0 # DTB accesses
361 system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
362 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
363 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
364 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
365 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
366 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
367 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
368 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
369 system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
370 system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
371 system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
372 system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
373 system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
374 system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
375 system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
376 system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
377 system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
378 system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
379 system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
380 system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
381 system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
382 system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
383 system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
384 system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
385 system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
386 system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
387 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
388 system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
389 system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
390 system.cpu.itb.walker.walks 0 # Table walker walks requested
391 system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
392 system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
393 system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
394 system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
395 system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
396 system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
397 system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
398 system.cpu.itb.inst_hits 0 # ITB inst hits
399 system.cpu.itb.inst_misses 0 # ITB inst misses
400 system.cpu.itb.read_hits 0 # DTB read hits
401 system.cpu.itb.read_misses 0 # DTB read misses
402 system.cpu.itb.write_hits 0 # DTB write hits
403 system.cpu.itb.write_misses 0 # DTB write misses
404 system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
405 system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
406 system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
407 system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
408 system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
409 system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
410 system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
411 system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
412 system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
413 system.cpu.itb.read_accesses 0 # DTB read accesses
414 system.cpu.itb.write_accesses 0 # DTB write accesses
415 system.cpu.itb.inst_accesses 0 # ITB inst accesses
416 system.cpu.itb.hits 0 # DTB hits
417 system.cpu.itb.misses 0 # DTB misses
418 system.cpu.itb.accesses 0 # DTB accesses
419 system.cpu.workload.num_syscalls 548 # Number of system calls
420 system.cpu.numCycles 725263657 # number of cpu cycles simulated
421 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
422 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
423 system.cpu.committedInsts 506579366 # Number of instructions committed
424 system.cpu.committedOps 548692589 # Number of ops (including micro ops) committed
425 system.cpu.discardedOps 12911806 # Number of ops (including micro ops) which were discarded before commit
426 system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
427 system.cpu.cpi 1.431688 # CPI: cycles per instruction
428 system.cpu.ipc 0.698476 # IPC: instructions per cycle
429 system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
430 system.cpu.op_class_0::IntAlu 375609862 68.46% 68.46% # Class of committed instruction
431 system.cpu.op_class_0::IntMult 339219 0.06% 68.52% # Class of committed instruction
432 system.cpu.op_class_0::IntDiv 0 0.00% 68.52% # Class of committed instruction
433 system.cpu.op_class_0::FloatAdd 0 0.00% 68.52% # Class of committed instruction
434 system.cpu.op_class_0::FloatCmp 0 0.00% 68.52% # Class of committed instruction
435 system.cpu.op_class_0::FloatCvt 0 0.00% 68.52% # Class of committed instruction
436 system.cpu.op_class_0::FloatMult 0 0.00% 68.52% # Class of committed instruction
437 system.cpu.op_class_0::FloatDiv 0 0.00% 68.52% # Class of committed instruction
438 system.cpu.op_class_0::FloatSqrt 0 0.00% 68.52% # Class of committed instruction
439 system.cpu.op_class_0::SimdAdd 0 0.00% 68.52% # Class of committed instruction
440 system.cpu.op_class_0::SimdAddAcc 0 0.00% 68.52% # Class of committed instruction
441 system.cpu.op_class_0::SimdAlu 0 0.00% 68.52% # Class of committed instruction
442 system.cpu.op_class_0::SimdCmp 0 0.00% 68.52% # Class of committed instruction
443 system.cpu.op_class_0::SimdCvt 0 0.00% 68.52% # Class of committed instruction
444 system.cpu.op_class_0::SimdMisc 0 0.00% 68.52% # Class of committed instruction
445 system.cpu.op_class_0::SimdMult 0 0.00% 68.52% # Class of committed instruction
446 system.cpu.op_class_0::SimdMultAcc 0 0.00% 68.52% # Class of committed instruction
447 system.cpu.op_class_0::SimdShift 0 0.00% 68.52% # Class of committed instruction
448 system.cpu.op_class_0::SimdShiftAcc 0 0.00% 68.52% # Class of committed instruction
449 system.cpu.op_class_0::SimdSqrt 0 0.00% 68.52% # Class of committed instruction
450 system.cpu.op_class_0::SimdFloatAdd 0 0.00% 68.52% # Class of committed instruction
451 system.cpu.op_class_0::SimdFloatAlu 0 0.00% 68.52% # Class of committed instruction
452 system.cpu.op_class_0::SimdFloatCmp 0 0.00% 68.52% # Class of committed instruction
453 system.cpu.op_class_0::SimdFloatCvt 0 0.00% 68.52% # Class of committed instruction
454 system.cpu.op_class_0::SimdFloatDiv 0 0.00% 68.52% # Class of committed instruction
455 system.cpu.op_class_0::SimdFloatMisc 3 0.00% 68.52% # Class of committed instruction
456 system.cpu.op_class_0::SimdFloatMult 0 0.00% 68.52% # Class of committed instruction
457 system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 68.52% # Class of committed instruction
458 system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 68.52% # Class of committed instruction
459 system.cpu.op_class_0::MemRead 115883283 21.12% 89.64% # Class of committed instruction
460 system.cpu.op_class_0::MemWrite 56860222 10.36% 100.00% # Class of committed instruction
461 system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
462 system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
463 system.cpu.op_class_0::total 548692589 # Class of committed instruction
464 system.cpu.tickCycles 688919604 # Number of cycles that the object actually ticked
465 system.cpu.idleCycles 36344053 # Total number of cycles that the object has spent stopped
466 system.cpu.dcache.tags.replacements 1141477 # number of replacements
467 system.cpu.dcache.tags.tagsinuse 4070.722142 # Cycle average of tags in use
468 system.cpu.dcache.tags.total_refs 170992714 # Total number of references to valid blocks.
469 system.cpu.dcache.tags.sampled_refs 1145573 # Sample count of references to valid blocks.
470 system.cpu.dcache.tags.avg_refs 149.263918 # Average number of references to valid blocks.
471 system.cpu.dcache.tags.warmup_cycle 4896334500 # Cycle when the warmup percentage was hit.
472 system.cpu.dcache.tags.occ_blocks::cpu.data 4070.722142 # Average occupied blocks per requestor
473 system.cpu.dcache.tags.occ_percent::cpu.data 0.993829 # Average percentage of cache occupancy
474 system.cpu.dcache.tags.occ_percent::total 0.993829 # Average percentage of cache occupancy
475 system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
476 system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id
477 system.cpu.dcache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id
478 system.cpu.dcache.tags.age_task_id_blocks_1024::2 553 # Occupied blocks per task id
479 system.cpu.dcache.tags.age_task_id_blocks_1024::3 3497 # Occupied blocks per task id
480 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
481 system.cpu.dcache.tags.tag_accesses 346245015 # Number of tag accesses
482 system.cpu.dcache.tags.data_accesses 346245015 # Number of data accesses
483 system.cpu.dcache.ReadReq_hits::cpu.data 114475063 # number of ReadReq hits
484 system.cpu.dcache.ReadReq_hits::total 114475063 # number of ReadReq hits
485 system.cpu.dcache.WriteReq_hits::cpu.data 53537828 # number of WriteReq hits
486 system.cpu.dcache.WriteReq_hits::total 53537828 # number of WriteReq hits
487 system.cpu.dcache.SoftPFReq_hits::cpu.data 2741 # number of SoftPFReq hits
488 system.cpu.dcache.SoftPFReq_hits::total 2741 # number of SoftPFReq hits
489 system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488541 # number of LoadLockedReq hits
490 system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits
491 system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits
492 system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits
493 system.cpu.dcache.demand_hits::cpu.data 168012891 # number of demand (read+write) hits
494 system.cpu.dcache.demand_hits::total 168012891 # number of demand (read+write) hits
495 system.cpu.dcache.overall_hits::cpu.data 168015632 # number of overall hits
496 system.cpu.dcache.overall_hits::total 168015632 # number of overall hits
497 system.cpu.dcache.ReadReq_misses::cpu.data 855770 # number of ReadReq misses
498 system.cpu.dcache.ReadReq_misses::total 855770 # number of ReadReq misses
499 system.cpu.dcache.WriteReq_misses::cpu.data 701221 # number of WriteReq misses
500 system.cpu.dcache.WriteReq_misses::total 701221 # number of WriteReq misses
501 system.cpu.dcache.SoftPFReq_misses::cpu.data 16 # number of SoftPFReq misses
502 system.cpu.dcache.SoftPFReq_misses::total 16 # number of SoftPFReq misses
503 system.cpu.dcache.demand_misses::cpu.data 1556991 # number of demand (read+write) misses
504 system.cpu.dcache.demand_misses::total 1556991 # number of demand (read+write) misses
505 system.cpu.dcache.overall_misses::cpu.data 1557007 # number of overall misses
506 system.cpu.dcache.overall_misses::total 1557007 # number of overall misses
507 system.cpu.dcache.ReadReq_miss_latency::cpu.data 14058873500 # number of ReadReq miss cycles
508 system.cpu.dcache.ReadReq_miss_latency::total 14058873500 # number of ReadReq miss cycles
509 system.cpu.dcache.WriteReq_miss_latency::cpu.data 21921294000 # number of WriteReq miss cycles
510 system.cpu.dcache.WriteReq_miss_latency::total 21921294000 # number of WriteReq miss cycles
511 system.cpu.dcache.demand_miss_latency::cpu.data 35980167500 # number of demand (read+write) miss cycles
512 system.cpu.dcache.demand_miss_latency::total 35980167500 # number of demand (read+write) miss cycles
513 system.cpu.dcache.overall_miss_latency::cpu.data 35980167500 # number of overall miss cycles
514 system.cpu.dcache.overall_miss_latency::total 35980167500 # number of overall miss cycles
515 system.cpu.dcache.ReadReq_accesses::cpu.data 115330833 # number of ReadReq accesses(hits+misses)
516 system.cpu.dcache.ReadReq_accesses::total 115330833 # number of ReadReq accesses(hits+misses)
517 system.cpu.dcache.WriteReq_accesses::cpu.data 54239049 # number of WriteReq accesses(hits+misses)
518 system.cpu.dcache.WriteReq_accesses::total 54239049 # number of WriteReq accesses(hits+misses)
519 system.cpu.dcache.SoftPFReq_accesses::cpu.data 2757 # number of SoftPFReq accesses(hits+misses)
520 system.cpu.dcache.SoftPFReq_accesses::total 2757 # number of SoftPFReq accesses(hits+misses)
521 system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488541 # number of LoadLockedReq accesses(hits+misses)
522 system.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses)
523 system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses)
524 system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses)
525 system.cpu.dcache.demand_accesses::cpu.data 169569882 # number of demand (read+write) accesses
526 system.cpu.dcache.demand_accesses::total 169569882 # number of demand (read+write) accesses
527 system.cpu.dcache.overall_accesses::cpu.data 169572639 # number of overall (read+write) accesses
528 system.cpu.dcache.overall_accesses::total 169572639 # number of overall (read+write) accesses
529 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.007420 # miss rate for ReadReq accesses
530 system.cpu.dcache.ReadReq_miss_rate::total 0.007420 # miss rate for ReadReq accesses
531 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.012928 # miss rate for WriteReq accesses
532 system.cpu.dcache.WriteReq_miss_rate::total 0.012928 # miss rate for WriteReq accesses
533 system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.005803 # miss rate for SoftPFReq accesses
534 system.cpu.dcache.SoftPFReq_miss_rate::total 0.005803 # miss rate for SoftPFReq accesses
535 system.cpu.dcache.demand_miss_rate::cpu.data 0.009182 # miss rate for demand accesses
536 system.cpu.dcache.demand_miss_rate::total 0.009182 # miss rate for demand accesses
537 system.cpu.dcache.overall_miss_rate::cpu.data 0.009182 # miss rate for overall accesses
538 system.cpu.dcache.overall_miss_rate::total 0.009182 # miss rate for overall accesses
539 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16428.331795 # average ReadReq miss latency
540 system.cpu.dcache.ReadReq_avg_miss_latency::total 16428.331795 # average ReadReq miss latency
541 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31261.605115 # average WriteReq miss latency
542 system.cpu.dcache.WriteReq_avg_miss_latency::total 31261.605115 # average WriteReq miss latency
543 system.cpu.dcache.demand_avg_miss_latency::cpu.data 23108.783224 # average overall miss latency
544 system.cpu.dcache.demand_avg_miss_latency::total 23108.783224 # average overall miss latency
545 system.cpu.dcache.overall_avg_miss_latency::cpu.data 23108.545755 # average overall miss latency
546 system.cpu.dcache.overall_avg_miss_latency::total 23108.545755 # average overall miss latency
547 system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
548 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
549 system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
550 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
551 system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
552 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
553 system.cpu.dcache.fast_writes 0 # number of fast writes performed
554 system.cpu.dcache.cache_copies 0 # number of cache copies performed
555 system.cpu.dcache.writebacks::writebacks 1069336 # number of writebacks
556 system.cpu.dcache.writebacks::total 1069336 # number of writebacks
557 system.cpu.dcache.ReadReq_mshr_hits::cpu.data 66650 # number of ReadReq MSHR hits
558 system.cpu.dcache.ReadReq_mshr_hits::total 66650 # number of ReadReq MSHR hits
559 system.cpu.dcache.WriteReq_mshr_hits::cpu.data 344781 # number of WriteReq MSHR hits
560 system.cpu.dcache.WriteReq_mshr_hits::total 344781 # number of WriteReq MSHR hits
561 system.cpu.dcache.demand_mshr_hits::cpu.data 411431 # number of demand (read+write) MSHR hits
562 system.cpu.dcache.demand_mshr_hits::total 411431 # number of demand (read+write) MSHR hits
563 system.cpu.dcache.overall_mshr_hits::cpu.data 411431 # number of overall MSHR hits
564 system.cpu.dcache.overall_mshr_hits::total 411431 # number of overall MSHR hits
565 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 789120 # number of ReadReq MSHR misses
566 system.cpu.dcache.ReadReq_mshr_misses::total 789120 # number of ReadReq MSHR misses
567 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356440 # number of WriteReq MSHR misses
568 system.cpu.dcache.WriteReq_mshr_misses::total 356440 # number of WriteReq MSHR misses
569 system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 13 # number of SoftPFReq MSHR misses
570 system.cpu.dcache.SoftPFReq_mshr_misses::total 13 # number of SoftPFReq MSHR misses
571 system.cpu.dcache.demand_mshr_misses::cpu.data 1145560 # number of demand (read+write) MSHR misses
572 system.cpu.dcache.demand_mshr_misses::total 1145560 # number of demand (read+write) MSHR misses
573 system.cpu.dcache.overall_mshr_misses::cpu.data 1145573 # number of overall MSHR misses
574 system.cpu.dcache.overall_mshr_misses::total 1145573 # number of overall MSHR misses
575 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12372328000 # number of ReadReq MSHR miss cycles
576 system.cpu.dcache.ReadReq_mshr_miss_latency::total 12372328000 # number of ReadReq MSHR miss cycles
577 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11135047500 # number of WriteReq MSHR miss cycles
578 system.cpu.dcache.WriteReq_mshr_miss_latency::total 11135047500 # number of WriteReq MSHR miss cycles
579 system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1042000 # number of SoftPFReq MSHR miss cycles
580 system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1042000 # number of SoftPFReq MSHR miss cycles
581 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23507375500 # number of demand (read+write) MSHR miss cycles
582 system.cpu.dcache.demand_mshr_miss_latency::total 23507375500 # number of demand (read+write) MSHR miss cycles
583 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23508417500 # number of overall MSHR miss cycles
584 system.cpu.dcache.overall_mshr_miss_latency::total 23508417500 # number of overall MSHR miss cycles
585 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006842 # mshr miss rate for ReadReq accesses
586 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006842 # mshr miss rate for ReadReq accesses
587 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006572 # mshr miss rate for WriteReq accesses
588 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006572 # mshr miss rate for WriteReq accesses
589 system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.004715 # mshr miss rate for SoftPFReq accesses
590 system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.004715 # mshr miss rate for SoftPFReq accesses
591 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006756 # mshr miss rate for demand accesses
592 system.cpu.dcache.demand_mshr_miss_rate::total 0.006756 # mshr miss rate for demand accesses
593 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006756 # mshr miss rate for overall accesses
594 system.cpu.dcache.overall_mshr_miss_rate::total 0.006756 # mshr miss rate for overall accesses
595 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15678.639497 # average ReadReq mshr miss latency
596 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15678.639497 # average ReadReq mshr miss latency
597 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31239.612558 # average WriteReq mshr miss latency
598 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31239.612558 # average WriteReq mshr miss latency
599 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 80153.846154 # average SoftPFReq mshr miss latency
600 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 80153.846154 # average SoftPFReq mshr miss latency
601 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20520.422763 # average overall mshr miss latency
602 system.cpu.dcache.demand_avg_mshr_miss_latency::total 20520.422763 # average overall mshr miss latency
603 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20521.099485 # average overall mshr miss latency
604 system.cpu.dcache.overall_avg_mshr_miss_latency::total 20521.099485 # average overall mshr miss latency
605 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
606 system.cpu.icache.tags.replacements 18130 # number of replacements
607 system.cpu.icache.tags.tagsinuse 1186.413401 # Cycle average of tags in use
608 system.cpu.icache.tags.total_refs 198770599 # Total number of references to valid blocks.
609 system.cpu.icache.tags.sampled_refs 20001 # Sample count of references to valid blocks.
610 system.cpu.icache.tags.avg_refs 9938.033048 # Average number of references to valid blocks.
611 system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
612 system.cpu.icache.tags.occ_blocks::cpu.inst 1186.413401 # Average occupied blocks per requestor
613 system.cpu.icache.tags.occ_percent::cpu.inst 0.579303 # Average percentage of cache occupancy
614 system.cpu.icache.tags.occ_percent::total 0.579303 # Average percentage of cache occupancy
615 system.cpu.icache.tags.occ_task_id_blocks::1024 1871 # Occupied blocks per task id
616 system.cpu.icache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id
617 system.cpu.icache.tags.age_task_id_blocks_1024::1 63 # Occupied blocks per task id
618 system.cpu.icache.tags.age_task_id_blocks_1024::2 58 # Occupied blocks per task id
619 system.cpu.icache.tags.age_task_id_blocks_1024::3 312 # Occupied blocks per task id
620 system.cpu.icache.tags.age_task_id_blocks_1024::4 1397 # Occupied blocks per task id
621 system.cpu.icache.tags.occ_task_id_percent::1024 0.913574 # Percentage of cache occupancy per task id
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623 system.cpu.icache.tags.data_accesses 397601201 # Number of data accesses
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626 system.cpu.icache.demand_hits::cpu.inst 198770599 # number of demand (read+write) hits
627 system.cpu.icache.demand_hits::total 198770599 # number of demand (read+write) hits
628 system.cpu.icache.overall_hits::cpu.inst 198770599 # number of overall hits
629 system.cpu.icache.overall_hits::total 198770599 # number of overall hits
630 system.cpu.icache.ReadReq_misses::cpu.inst 20001 # number of ReadReq misses
631 system.cpu.icache.ReadReq_misses::total 20001 # number of ReadReq misses
632 system.cpu.icache.demand_misses::cpu.inst 20001 # number of demand (read+write) misses
633 system.cpu.icache.demand_misses::total 20001 # number of demand (read+write) misses
634 system.cpu.icache.overall_misses::cpu.inst 20001 # number of overall misses
635 system.cpu.icache.overall_misses::total 20001 # number of overall misses
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637 system.cpu.icache.ReadReq_miss_latency::total 455038500 # number of ReadReq miss cycles
638 system.cpu.icache.demand_miss_latency::cpu.inst 455038500 # number of demand (read+write) miss cycles
639 system.cpu.icache.demand_miss_latency::total 455038500 # number of demand (read+write) miss cycles
640 system.cpu.icache.overall_miss_latency::cpu.inst 455038500 # number of overall miss cycles
641 system.cpu.icache.overall_miss_latency::total 455038500 # number of overall miss cycles
642 system.cpu.icache.ReadReq_accesses::cpu.inst 198790600 # number of ReadReq accesses(hits+misses)
643 system.cpu.icache.ReadReq_accesses::total 198790600 # number of ReadReq accesses(hits+misses)
644 system.cpu.icache.demand_accesses::cpu.inst 198790600 # number of demand (read+write) accesses
645 system.cpu.icache.demand_accesses::total 198790600 # number of demand (read+write) accesses
646 system.cpu.icache.overall_accesses::cpu.inst 198790600 # number of overall (read+write) accesses
647 system.cpu.icache.overall_accesses::total 198790600 # number of overall (read+write) accesses
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649 system.cpu.icache.ReadReq_miss_rate::total 0.000101 # miss rate for ReadReq accesses
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651 system.cpu.icache.demand_miss_rate::total 0.000101 # miss rate for demand accesses
652 system.cpu.icache.overall_miss_rate::cpu.inst 0.000101 # miss rate for overall accesses
653 system.cpu.icache.overall_miss_rate::total 0.000101 # miss rate for overall accesses
654 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22750.787461 # average ReadReq miss latency
655 system.cpu.icache.ReadReq_avg_miss_latency::total 22750.787461 # average ReadReq miss latency
656 system.cpu.icache.demand_avg_miss_latency::cpu.inst 22750.787461 # average overall miss latency
657 system.cpu.icache.demand_avg_miss_latency::total 22750.787461 # average overall miss latency
658 system.cpu.icache.overall_avg_miss_latency::cpu.inst 22750.787461 # average overall miss latency
659 system.cpu.icache.overall_avg_miss_latency::total 22750.787461 # average overall miss latency
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661 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
662 system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
663 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
664 system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
665 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
666 system.cpu.icache.fast_writes 0 # number of fast writes performed
667 system.cpu.icache.cache_copies 0 # number of cache copies performed
668 system.cpu.icache.writebacks::writebacks 18130 # number of writebacks
669 system.cpu.icache.writebacks::total 18130 # number of writebacks
670 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 20001 # number of ReadReq MSHR misses
671 system.cpu.icache.ReadReq_mshr_misses::total 20001 # number of ReadReq MSHR misses
672 system.cpu.icache.demand_mshr_misses::cpu.inst 20001 # number of demand (read+write) MSHR misses
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674 system.cpu.icache.overall_mshr_misses::cpu.inst 20001 # number of overall MSHR misses
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677 system.cpu.icache.ReadReq_mshr_miss_latency::total 435037500 # number of ReadReq MSHR miss cycles
678 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 435037500 # number of demand (read+write) MSHR miss cycles
679 system.cpu.icache.demand_mshr_miss_latency::total 435037500 # number of demand (read+write) MSHR miss cycles
680 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 435037500 # number of overall MSHR miss cycles
681 system.cpu.icache.overall_mshr_miss_latency::total 435037500 # number of overall MSHR miss cycles
682 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000101 # mshr miss rate for ReadReq accesses
683 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000101 # mshr miss rate for ReadReq accesses
684 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000101 # mshr miss rate for demand accesses
685 system.cpu.icache.demand_mshr_miss_rate::total 0.000101 # mshr miss rate for demand accesses
686 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000101 # mshr miss rate for overall accesses
687 system.cpu.icache.overall_mshr_miss_rate::total 0.000101 # mshr miss rate for overall accesses
688 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21750.787461 # average ReadReq mshr miss latency
689 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21750.787461 # average ReadReq mshr miss latency
690 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21750.787461 # average overall mshr miss latency
691 system.cpu.icache.demand_avg_mshr_miss_latency::total 21750.787461 # average overall mshr miss latency
692 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21750.787461 # average overall mshr miss latency
693 system.cpu.icache.overall_avg_mshr_miss_latency::total 21750.787461 # average overall mshr miss latency
694 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
695 system.cpu.l2cache.tags.replacements 112376 # number of replacements
696 system.cpu.l2cache.tags.tagsinuse 27628.930561 # Cycle average of tags in use
697 system.cpu.l2cache.tags.total_refs 1772118 # Total number of references to valid blocks.
698 system.cpu.l2cache.tags.sampled_refs 143588 # Sample count of references to valid blocks.
699 system.cpu.l2cache.tags.avg_refs 12.341686 # Average number of references to valid blocks.
700 system.cpu.l2cache.tags.warmup_cycle 163251686000 # Cycle when the warmup percentage was hit.
701 system.cpu.l2cache.tags.occ_blocks::writebacks 23500.584340 # Average occupied blocks per requestor
702 system.cpu.l2cache.tags.occ_blocks::cpu.inst 308.787313 # Average occupied blocks per requestor
703 system.cpu.l2cache.tags.occ_blocks::cpu.data 3819.558908 # Average occupied blocks per requestor
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705 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.009423 # Average percentage of cache occupancy
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707 system.cpu.l2cache.tags.occ_percent::total 0.843168 # Average percentage of cache occupancy
708 system.cpu.l2cache.tags.occ_task_id_blocks::1024 31212 # Occupied blocks per task id
709 system.cpu.l2cache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id
710 system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id
711 system.cpu.l2cache.tags.age_task_id_blocks_1024::2 324 # Occupied blocks per task id
712 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4939 # Occupied blocks per task id
713 system.cpu.l2cache.tags.age_task_id_blocks_1024::4 25849 # Occupied blocks per task id
714 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.952515 # Percentage of cache occupancy per task id
715 system.cpu.l2cache.tags.tag_accesses 19061751 # Number of tag accesses
716 system.cpu.l2cache.tags.data_accesses 19061751 # Number of data accesses
717 system.cpu.l2cache.WritebackDirty_hits::writebacks 1069336 # number of WritebackDirty hits
718 system.cpu.l2cache.WritebackDirty_hits::total 1069336 # number of WritebackDirty hits
719 system.cpu.l2cache.WritebackClean_hits::writebacks 17893 # number of WritebackClean hits
720 system.cpu.l2cache.WritebackClean_hits::total 17893 # number of WritebackClean hits
721 system.cpu.l2cache.ReadExReq_hits::cpu.data 255742 # number of ReadExReq hits
722 system.cpu.l2cache.ReadExReq_hits::total 255742 # number of ReadExReq hits
723 system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 17196 # number of ReadCleanReq hits
724 system.cpu.l2cache.ReadCleanReq_hits::total 17196 # number of ReadCleanReq hits
725 system.cpu.l2cache.ReadSharedReq_hits::cpu.data 748691 # number of ReadSharedReq hits
726 system.cpu.l2cache.ReadSharedReq_hits::total 748691 # number of ReadSharedReq hits
727 system.cpu.l2cache.demand_hits::cpu.inst 17196 # number of demand (read+write) hits
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731 system.cpu.l2cache.overall_hits::cpu.data 1004433 # number of overall hits
732 system.cpu.l2cache.overall_hits::total 1021629 # number of overall hits
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734 system.cpu.l2cache.ReadExReq_misses::total 100949 # number of ReadExReq misses
735 system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2805 # number of ReadCleanReq misses
736 system.cpu.l2cache.ReadCleanReq_misses::total 2805 # number of ReadCleanReq misses
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738 system.cpu.l2cache.ReadSharedReq_misses::total 40191 # number of ReadSharedReq misses
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743 system.cpu.l2cache.overall_misses::cpu.data 141140 # number of overall misses
744 system.cpu.l2cache.overall_misses::total 143945 # number of overall misses
745 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7917540500 # number of ReadExReq miss cycles
746 system.cpu.l2cache.ReadExReq_miss_latency::total 7917540500 # number of ReadExReq miss cycles
747 system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 223778500 # number of ReadCleanReq miss cycles
748 system.cpu.l2cache.ReadCleanReq_miss_latency::total 223778500 # number of ReadCleanReq miss cycles
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750 system.cpu.l2cache.ReadSharedReq_miss_latency::total 3305085000 # number of ReadSharedReq miss cycles
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756 system.cpu.l2cache.overall_miss_latency::total 11446404000 # number of overall miss cycles
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758 system.cpu.l2cache.WritebackDirty_accesses::total 1069336 # number of WritebackDirty accesses(hits+misses)
759 system.cpu.l2cache.WritebackClean_accesses::writebacks 17893 # number of WritebackClean accesses(hits+misses)
760 system.cpu.l2cache.WritebackClean_accesses::total 17893 # number of WritebackClean accesses(hits+misses)
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782 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.140243 # miss rate for overall accesses
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786 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78431.093919 # average ReadExReq miss latency
787 system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 79778.431373 # average ReadCleanReq miss latency
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789 system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82234.455475 # average ReadSharedReq miss latency
790 system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82234.455475 # average ReadSharedReq miss latency
791 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79778.431373 # average overall miss latency
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794 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79778.431373 # average overall miss latency
795 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79514.138444 # average overall miss latency
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804 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
805 system.cpu.l2cache.writebacks::writebacks 97210 # number of writebacks
806 system.cpu.l2cache.writebacks::total 97210 # number of writebacks
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819 system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2804 # number of ReadCleanReq MSHR misses
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827 system.cpu.l2cache.overall_mshr_misses::cpu.data 141126 # number of overall MSHR misses
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830 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6908050500 # number of ReadExReq MSHR miss cycles
831 system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 195670500 # number of ReadCleanReq MSHR miss cycles
832 system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 195670500 # number of ReadCleanReq MSHR miss cycles
833 system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2902356000 # number of ReadSharedReq MSHR miss cycles
834 system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2902356000 # number of ReadSharedReq MSHR miss cycles
835 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 195670500 # number of demand (read+write) MSHR miss cycles
836 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9810406500 # number of demand (read+write) MSHR miss cycles
837 system.cpu.l2cache.demand_mshr_miss_latency::total 10006077000 # number of demand (read+write) MSHR miss cycles
838 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 195670500 # number of overall MSHR miss cycles
839 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9810406500 # number of overall MSHR miss cycles
840 system.cpu.l2cache.overall_mshr_miss_latency::total 10006077000 # number of overall MSHR miss cycles
841 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.283015 # mshr miss rate for ReadExReq accesses
842 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.283015 # mshr miss rate for ReadExReq accesses
843 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.140193 # mshr miss rate for ReadCleanReq accesses
844 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.140193 # mshr miss rate for ReadCleanReq accesses
845 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.050929 # mshr miss rate for ReadSharedReq accesses
846 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.050929 # mshr miss rate for ReadSharedReq accesses
847 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.140193 # mshr miss rate for demand accesses
848 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.123192 # mshr miss rate for demand accesses
849 system.cpu.l2cache.demand_mshr_miss_rate::total 0.123484 # mshr miss rate for demand accesses
850 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.140193 # mshr miss rate for overall accesses
851 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.123192 # mshr miss rate for overall accesses
852 system.cpu.l2cache.overall_mshr_miss_rate::total 0.123484 # mshr miss rate for overall accesses
853 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68431.093919 # average ReadExReq mshr miss latency
854 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68431.093919 # average ReadExReq mshr miss latency
855 system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69782.631954 # average ReadCleanReq mshr miss latency
856 system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69782.631954 # average ReadCleanReq mshr miss latency
857 system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72239.241357 # average ReadSharedReq mshr miss latency
858 system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72239.241357 # average ReadSharedReq mshr miss latency
859 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69782.631954 # average overall mshr miss latency
860 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69515.231070 # average overall mshr miss latency
861 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69520.440492 # average overall mshr miss latency
862 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69782.631954 # average overall mshr miss latency
863 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69515.231070 # average overall mshr miss latency
864 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69520.440492 # average overall mshr miss latency
865 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
866 system.cpu.toL2Bus.snoop_filter.tot_requests 2325181 # Total number of requests made to the snoop filter.
867 system.cpu.toL2Bus.snoop_filter.hit_single_requests 1159677 # Number of requests hitting in the snoop filter with a single holder of the requested data.
868 system.cpu.toL2Bus.snoop_filter.hit_multi_requests 4997 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
869 system.cpu.toL2Bus.snoop_filter.tot_snoops 2608 # Total number of snoops made to the snoop filter.
870 system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2605 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
871 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 3 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
872 system.cpu.toL2Bus.trans_dist::ReadResp 808883 # Transaction distribution
873 system.cpu.toL2Bus.trans_dist::WritebackDirty 1166546 # Transaction distribution
874 system.cpu.toL2Bus.trans_dist::WritebackClean 18130 # Transaction distribution
875 system.cpu.toL2Bus.trans_dist::CleanEvict 87307 # Transaction distribution
876 system.cpu.toL2Bus.trans_dist::ReadExReq 356691 # Transaction distribution
877 system.cpu.toL2Bus.trans_dist::ReadExResp 356691 # Transaction distribution
878 system.cpu.toL2Bus.trans_dist::ReadCleanReq 20001 # Transaction distribution
879 system.cpu.toL2Bus.trans_dist::ReadSharedReq 788882 # Transaction distribution
880 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 58132 # Packet count per connected master and slave (bytes)
881 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3432623 # Packet count per connected master and slave (bytes)
882 system.cpu.toL2Bus.pkt_count::total 3490755 # Packet count per connected master and slave (bytes)
883 system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2440384 # Cumulative packet size per connected master and slave (bytes)
884 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141754176 # Cumulative packet size per connected master and slave (bytes)
885 system.cpu.toL2Bus.pkt_size::total 144194560 # Cumulative packet size per connected master and slave (bytes)
886 system.cpu.toL2Bus.snoops 112376 # Total snoops (count)
887 system.cpu.toL2Bus.snoop_fanout::samples 1277950 # Request fanout histogram
888 system.cpu.toL2Bus.snoop_fanout::mean 0.006008 # Request fanout histogram
889 system.cpu.toL2Bus.snoop_fanout::stdev 0.077309 # Request fanout histogram
890 system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
891 system.cpu.toL2Bus.snoop_fanout::0 1270275 99.40% 99.40% # Request fanout histogram
892 system.cpu.toL2Bus.snoop_fanout::1 7672 0.60% 100.00% # Request fanout histogram
893 system.cpu.toL2Bus.snoop_fanout::2 3 0.00% 100.00% # Request fanout histogram
894 system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
895 system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
896 system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
897 system.cpu.toL2Bus.snoop_fanout::total 1277950 # Request fanout histogram
898 system.cpu.toL2Bus.reqLayer0.occupancy 2250056500 # Layer occupancy (ticks)
899 system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%)
900 system.cpu.toL2Bus.respLayer0.occupancy 30027947 # Layer occupancy (ticks)
901 system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
902 system.cpu.toL2Bus.respLayer1.occupancy 1718367983 # Layer occupancy (ticks)
903 system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%)
904 system.membus.trans_dist::ReadResp 42981 # Transaction distribution
905 system.membus.trans_dist::WritebackDirty 97210 # Transaction distribution
906 system.membus.trans_dist::CleanEvict 12558 # Transaction distribution
907 system.membus.trans_dist::ReadExReq 100949 # Transaction distribution
908 system.membus.trans_dist::ReadExResp 100949 # Transaction distribution
909 system.membus.trans_dist::ReadSharedReq 42981 # Transaction distribution
910 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 397628 # Packet count per connected master and slave (bytes)
911 system.membus.pkt_count::total 397628 # Packet count per connected master and slave (bytes)
912 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15432960 # Cumulative packet size per connected master and slave (bytes)
913 system.membus.pkt_size::total 15432960 # Cumulative packet size per connected master and slave (bytes)
914 system.membus.snoops 0 # Total snoops (count)
915 system.membus.snoop_fanout::samples 253698 # Request fanout histogram
916 system.membus.snoop_fanout::mean 0 # Request fanout histogram
917 system.membus.snoop_fanout::stdev 0 # Request fanout histogram
918 system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
919 system.membus.snoop_fanout::0 253698 100.00% 100.00% # Request fanout histogram
920 system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
921 system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
922 system.membus.snoop_fanout::min_value 0 # Request fanout histogram
923 system.membus.snoop_fanout::max_value 0 # Request fanout histogram
924 system.membus.snoop_fanout::total 253698 # Request fanout histogram
925 system.membus.reqLayer0.occupancy 685564500 # Layer occupancy (ticks)
926 system.membus.reqLayer0.utilization 0.2 # Layer utilization (%)
927 system.membus.respLayer1.occupancy 763995250 # Layer occupancy (ticks)
928 system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
930 ---------- End Simulation Statistics ----------
projects / gem5.git / blob