tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini

   1 [root]
   2 type=Root
   3 children=system
   4 eventq_index=0
   5 full_system=false
   6 sim_quantum=0
   7 time_sync_enable=false
   8 time_sync_period=100000000000
   9 time_sync_spin_threshold=100000000
  10
  11 [system]
  12 type=System
  13 children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
  14 boot_osflags=a
  15 cache_line_size=64
  16 clk_domain=system.clk_domain
  17 eventq_index=0
  18 init_param=0
  19 kernel=
  20 kernel_addr_check=true
  21 load_addr_mask=1099511627775
  22 load_offset=0
  23 mem_mode=timing
  24 mem_ranges=
  25 memories=system.physmem
  26 num_work_ids=16
  27 readfile=
  28 symbolfile=
  29 work_begin_ckpt_count=0
  30 work_begin_cpu_id_exit=-1
  31 work_begin_exit_count=0
  32 work_cpus_ckpt_count=0
  33 work_end_ckpt_count=0
  34 work_end_exit_count=0
  35 work_item_id=-1
  36 system_port=system.membus.slave[0]
  37
  38 [system.clk_domain]
  39 type=SrcClockDomain
  40 clock=1000
  41 domain_id=-1
  42 eventq_index=0
  43 init_perf_level=0
  44 voltage_domain=system.voltage_domain
  45
  46 [system.cpu]
  47 type=DerivO3CPU
  48 children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload
  49 LFSTSize=1024
  50 LQEntries=16
  51 LSQCheckLoads=true
  52 LSQDepCheckShift=0
  53 SQEntries=16
  54 SSITSize=1024
  55 activity=0
  56 backComSize=5
  57 branchPred=system.cpu.branchPred
  58 cachePorts=200
  59 checker=Null
  60 clk_domain=system.cpu_clk_domain
  61 commitToDecodeDelay=1
  62 commitToFetchDelay=1
  63 commitToIEWDelay=1
  64 commitToRenameDelay=1
  65 commitWidth=8
  66 cpu_id=0
  67 decodeToFetchDelay=1
  68 decodeToRenameDelay=2
  69 decodeWidth=3
  70 dispatchWidth=6
  71 do_checkpoint_insts=true
  72 do_quiesce=true
  73 do_statistics_insts=true
  74 dstage2_mmu=system.cpu.dstage2_mmu
  75 dtb=system.cpu.dtb
  76 eventq_index=0
  77 fetchBufferSize=16
  78 fetchQueueSize=32
  79 fetchToDecodeDelay=3
  80 fetchTrapLatency=1
  81 fetchWidth=3
  82 forwardComSize=5
  83 fuPool=system.cpu.fuPool
  84 function_trace=false
  85 function_trace_start=0
  86 iewToCommitDelay=1
  87 iewToDecodeDelay=1
  88 iewToFetchDelay=1
  89 iewToRenameDelay=1
  90 interrupts=system.cpu.interrupts
  91 isa=system.cpu.isa
  92 issueToExecuteDelay=1
  93 issueWidth=8
  94 istage2_mmu=system.cpu.istage2_mmu
  95 itb=system.cpu.itb
  96 max_insts_all_threads=0
  97 max_insts_any_thread=0
  98 max_loads_all_threads=0
  99 max_loads_any_thread=0
 100 needsTSO=false
 101 numIQEntries=32
 102 numPhysCCRegs=640
 103 numPhysFloatRegs=192
 104 numPhysIntRegs=128
 105 numROBEntries=40
 106 numRobs=1
 107 numThreads=1
 108 profile=0
 109 progress_interval=0
 110 renameToDecodeDelay=1
 111 renameToFetchDelay=1
 112 renameToIEWDelay=1
 113 renameToROBDelay=1
 114 renameWidth=3
 115 simpoint_start_insts=
 116 smtCommitPolicy=RoundRobin
 117 smtFetchPolicy=SingleThread
 118 smtIQPolicy=Partitioned
 119 smtIQThreshold=100
 120 smtLSQPolicy=Partitioned
 121 smtLSQThreshold=100
 122 smtNumFetchingThreads=1
 123 smtROBPolicy=Partitioned
 124 smtROBThreshold=100
 125 socket_id=0
 126 squashWidth=8
 127 store_set_clear_period=250000
 128 switched_out=false
 129 system=system
 130 tracer=system.cpu.tracer
 131 trapLatency=13
 132 wbWidth=8
 133 workload=system.cpu.workload
 134 dcache_port=system.cpu.dcache.cpu_side
 135 icache_port=system.cpu.icache.cpu_side
 136
 137 [system.cpu.branchPred]
 138 type=BranchPredictor
 139 BTBEntries=2048
 140 BTBTagSize=18
 141 RASSize=16
 142 choiceCtrBits=2
 143 choicePredictorSize=8192
 144 eventq_index=0
 145 globalCtrBits=2
 146 globalPredictorSize=8192
 147 instShiftAmt=2
 148 localCtrBits=2
 149 localHistoryTableSize=2048
 150 localPredictorSize=2048
 151 numThreads=1
 152 predType=bi-mode
 153
 154 [system.cpu.dcache]
 155 type=BaseCache
 156 children=tags
 157 addr_ranges=0:18446744073709551615
 158 assoc=2
 159 clk_domain=system.cpu_clk_domain
 160 eventq_index=0
 161 forward_snoops=true
 162 hit_latency=2
 163 is_top_level=true
 164 max_miss_count=0
 165 mshrs=6
 166 prefetch_on_access=false
 167 prefetcher=Null
 168 response_latency=2
 169 sequential_access=false
 170 size=32768
 171 system=system
 172 tags=system.cpu.dcache.tags
 173 tgts_per_mshr=8
 174 two_queue=false
 175 write_buffers=16
 176 cpu_side=system.cpu.dcache_port
 177 mem_side=system.cpu.toL2Bus.slave[1]
 178
 179 [system.cpu.dcache.tags]
 180 type=LRU
 181 assoc=2
 182 block_size=64
 183 clk_domain=system.cpu_clk_domain
 184 eventq_index=0
 185 hit_latency=2
 186 sequential_access=false
 187 size=32768
 188
 189 [system.cpu.dstage2_mmu]
 190 type=ArmStage2MMU
 191 children=stage2_tlb
 192 eventq_index=0
 193 stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
 194 tlb=system.cpu.dtb
 195
 196 [system.cpu.dstage2_mmu.stage2_tlb]
 197 type=ArmTLB
 198 children=walker
 199 eventq_index=0
 200 is_stage2=true
 201 size=32
 202 walker=system.cpu.dstage2_mmu.stage2_tlb.walker
 203
 204 [system.cpu.dstage2_mmu.stage2_tlb.walker]
 205 type=ArmTableWalker
 206 clk_domain=system.cpu_clk_domain
 207 eventq_index=0
 208 is_stage2=true
 209 num_squash_per_cycle=2
 210 sys=system
 211 port=system.cpu.toL2Bus.slave[5]
 212
 213 [system.cpu.dtb]
 214 type=ArmTLB
 215 children=walker
 216 eventq_index=0
 217 is_stage2=false
 218 size=64
 219 walker=system.cpu.dtb.walker
 220
 221 [system.cpu.dtb.walker]
 222 type=ArmTableWalker
 223 clk_domain=system.cpu_clk_domain
 224 eventq_index=0
 225 is_stage2=false
 226 num_squash_per_cycle=2
 227 sys=system
 228 port=system.cpu.toL2Bus.slave[3]
 229
 230 [system.cpu.fuPool]
 231 type=FUPool
 232 children=FUList0 FUList1 FUList2 FUList3 FUList4
 233 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4
 234 eventq_index=0
 235
 236 [system.cpu.fuPool.FUList0]
 237 type=FUDesc
 238 children=opList
 239 count=2
 240 eventq_index=0
 241 opList=system.cpu.fuPool.FUList0.opList
 242
 243 [system.cpu.fuPool.FUList0.opList]
 244 type=OpDesc
 245 eventq_index=0
 246 issueLat=1
 247 opClass=IntAlu
 248 opLat=1
 249
 250 [system.cpu.fuPool.FUList1]
 251 type=FUDesc
 252 children=opList0 opList1 opList2
 253 count=1
 254 eventq_index=0
 255 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 system.cpu.fuPool.FUList1.opList2
 256
 257 [system.cpu.fuPool.FUList1.opList0]
 258 type=OpDesc
 259 eventq_index=0
 260 issueLat=1
 261 opClass=IntMult
 262 opLat=3
 263
 264 [system.cpu.fuPool.FUList1.opList1]
 265 type=OpDesc
 266 eventq_index=0
 267 issueLat=12
 268 opClass=IntDiv
 269 opLat=12
 270
 271 [system.cpu.fuPool.FUList1.opList2]
 272 type=OpDesc
 273 eventq_index=0
 274 issueLat=1
 275 opClass=IprAccess
 276 opLat=3
 277
 278 [system.cpu.fuPool.FUList2]
 279 type=FUDesc
 280 children=opList
 281 count=1
 282 eventq_index=0
 283 opList=system.cpu.fuPool.FUList2.opList
 284
 285 [system.cpu.fuPool.FUList2.opList]
 286 type=OpDesc
 287 eventq_index=0
 288 issueLat=1
 289 opClass=MemRead
 290 opLat=2
 291
 292 [system.cpu.fuPool.FUList3]
 293 type=FUDesc
 294 children=opList
 295 count=1
 296 eventq_index=0
 297 opList=system.cpu.fuPool.FUList3.opList
 298
 299 [system.cpu.fuPool.FUList3.opList]
 300 type=OpDesc
 301 eventq_index=0
 302 issueLat=1
 303 opClass=MemWrite
 304 opLat=2
 305
 306 [system.cpu.fuPool.FUList4]
 307 type=FUDesc
 308 children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25
 309 count=2
 310 eventq_index=0
 311 opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25
 312
 313 [system.cpu.fuPool.FUList4.opList00]
 314 type=OpDesc
 315 eventq_index=0
 316 issueLat=1
 317 opClass=SimdAdd
 318 opLat=4
 319
 320 [system.cpu.fuPool.FUList4.opList01]
 321 type=OpDesc
 322 eventq_index=0
 323 issueLat=1
 324 opClass=SimdAddAcc
 325 opLat=4
 326
 327 [system.cpu.fuPool.FUList4.opList02]
 328 type=OpDesc
 329 eventq_index=0
 330 issueLat=1
 331 opClass=SimdAlu
 332 opLat=4
 333
 334 [system.cpu.fuPool.FUList4.opList03]
 335 type=OpDesc
 336 eventq_index=0
 337 issueLat=1
 338 opClass=SimdCmp
 339 opLat=4
 340
 341 [system.cpu.fuPool.FUList4.opList04]
 342 type=OpDesc
 343 eventq_index=0
 344 issueLat=1
 345 opClass=SimdCvt
 346 opLat=3
 347
 348 [system.cpu.fuPool.FUList4.opList05]
 349 type=OpDesc
 350 eventq_index=0
 351 issueLat=1
 352 opClass=SimdMisc
 353 opLat=3
 354
 355 [system.cpu.fuPool.FUList4.opList06]
 356 type=OpDesc
 357 eventq_index=0
 358 issueLat=1
 359 opClass=SimdMult
 360 opLat=5
 361
 362 [system.cpu.fuPool.FUList4.opList07]
 363 type=OpDesc
 364 eventq_index=0
 365 issueLat=1
 366 opClass=SimdMultAcc
 367 opLat=5
 368
 369 [system.cpu.fuPool.FUList4.opList08]
 370 type=OpDesc
 371 eventq_index=0
 372 issueLat=1
 373 opClass=SimdShift
 374 opLat=3
 375
 376 [system.cpu.fuPool.FUList4.opList09]
 377 type=OpDesc
 378 eventq_index=0
 379 issueLat=1
 380 opClass=SimdShiftAcc
 381 opLat=3
 382
 383 [system.cpu.fuPool.FUList4.opList10]
 384 type=OpDesc
 385 eventq_index=0
 386 issueLat=1
 387 opClass=SimdSqrt
 388 opLat=9
 389
 390 [system.cpu.fuPool.FUList4.opList11]
 391 type=OpDesc
 392 eventq_index=0
 393 issueLat=1
 394 opClass=SimdFloatAdd
 395 opLat=5
 396
 397 [system.cpu.fuPool.FUList4.opList12]
 398 type=OpDesc
 399 eventq_index=0
 400 issueLat=1
 401 opClass=SimdFloatAlu
 402 opLat=5
 403
 404 [system.cpu.fuPool.FUList4.opList13]
 405 type=OpDesc
 406 eventq_index=0
 407 issueLat=1
 408 opClass=SimdFloatCmp
 409 opLat=3
 410
 411 [system.cpu.fuPool.FUList4.opList14]
 412 type=OpDesc
 413 eventq_index=0
 414 issueLat=1
 415 opClass=SimdFloatCvt
 416 opLat=3
 417
 418 [system.cpu.fuPool.FUList4.opList15]
 419 type=OpDesc
 420 eventq_index=0
 421 issueLat=1
 422 opClass=SimdFloatDiv
 423 opLat=3
 424
 425 [system.cpu.fuPool.FUList4.opList16]
 426 type=OpDesc
 427 eventq_index=0
 428 issueLat=1
 429 opClass=SimdFloatMisc
 430 opLat=3
 431
 432 [system.cpu.fuPool.FUList4.opList17]
 433 type=OpDesc
 434 eventq_index=0
 435 issueLat=1
 436 opClass=SimdFloatMult
 437 opLat=3
 438
 439 [system.cpu.fuPool.FUList4.opList18]
 440 type=OpDesc
 441 eventq_index=0
 442 issueLat=1
 443 opClass=SimdFloatMultAcc
 444 opLat=1
 445
 446 [system.cpu.fuPool.FUList4.opList19]
 447 type=OpDesc
 448 eventq_index=0
 449 issueLat=1
 450 opClass=SimdFloatSqrt
 451 opLat=9
 452
 453 [system.cpu.fuPool.FUList4.opList20]
 454 type=OpDesc
 455 eventq_index=0
 456 issueLat=1
 457 opClass=FloatAdd
 458 opLat=5
 459
 460 [system.cpu.fuPool.FUList4.opList21]
 461 type=OpDesc
 462 eventq_index=0
 463 issueLat=1
 464 opClass=FloatCmp
 465 opLat=5
 466
 467 [system.cpu.fuPool.FUList4.opList22]
 468 type=OpDesc
 469 eventq_index=0
 470 issueLat=1
 471 opClass=FloatCvt
 472 opLat=5
 473
 474 [system.cpu.fuPool.FUList4.opList23]
 475 type=OpDesc
 476 eventq_index=0
 477 issueLat=9
 478 opClass=FloatDiv
 479 opLat=9
 480
 481 [system.cpu.fuPool.FUList4.opList24]
 482 type=OpDesc
 483 eventq_index=0
 484 issueLat=33
 485 opClass=FloatSqrt
 486 opLat=33
 487
 488 [system.cpu.fuPool.FUList4.opList25]
 489 type=OpDesc
 490 eventq_index=0
 491 issueLat=1
 492 opClass=FloatMult
 493 opLat=4
 494
 495 [system.cpu.icache]
 496 type=BaseCache
 497 children=tags
 498 addr_ranges=0:18446744073709551615
 499 assoc=2
 500 clk_domain=system.cpu_clk_domain
 501 eventq_index=0
 502 forward_snoops=true
 503 hit_latency=1
 504 is_top_level=true
 505 max_miss_count=0
 506 mshrs=2
 507 prefetch_on_access=false
 508 prefetcher=Null
 509 response_latency=1
 510 sequential_access=false
 511 size=32768
 512 system=system
 513 tags=system.cpu.icache.tags
 514 tgts_per_mshr=8
 515 two_queue=false
 516 write_buffers=8
 517 cpu_side=system.cpu.icache_port
 518 mem_side=system.cpu.toL2Bus.slave[0]
 519
 520 [system.cpu.icache.tags]
 521 type=LRU
 522 assoc=2
 523 block_size=64
 524 clk_domain=system.cpu_clk_domain
 525 eventq_index=0
 526 hit_latency=1
 527 sequential_access=false
 528 size=32768
 529
 530 [system.cpu.interrupts]
 531 type=ArmInterrupts
 532 eventq_index=0
 533
 534 [system.cpu.isa]
 535 type=ArmISA
 536 eventq_index=0
 537 fpsid=1090793632
 538 id_aa64afr0_el1=0
 539 id_aa64afr1_el1=0
 540 id_aa64dfr0_el1=1052678
 541 id_aa64dfr1_el1=0
 542 id_aa64isar0_el1=0
 543 id_aa64isar1_el1=0
 544 id_aa64mmfr0_el1=15728642
 545 id_aa64mmfr1_el1=0
 546 id_aa64pfr0_el1=17
 547 id_aa64pfr1_el1=0
 548 id_isar0=34607377
 549 id_isar1=34677009
 550 id_isar2=555950401
 551 id_isar3=17899825
 552 id_isar4=268501314
 553 id_isar5=0
 554 id_mmfr0=270536963
 555 id_mmfr1=0
 556 id_mmfr2=19070976
 557 id_mmfr3=34611729
 558 id_pfr0=49
 559 id_pfr1=4113
 560 midr=1091551472
 561 system=system
 562
 563 [system.cpu.istage2_mmu]
 564 type=ArmStage2MMU
 565 children=stage2_tlb
 566 eventq_index=0
 567 stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
 568 tlb=system.cpu.itb
 569
 570 [system.cpu.istage2_mmu.stage2_tlb]
 571 type=ArmTLB
 572 children=walker
 573 eventq_index=0
 574 is_stage2=true
 575 size=32
 576 walker=system.cpu.istage2_mmu.stage2_tlb.walker
 577
 578 [system.cpu.istage2_mmu.stage2_tlb.walker]
 579 type=ArmTableWalker
 580 clk_domain=system.cpu_clk_domain
 581 eventq_index=0
 582 is_stage2=true
 583 num_squash_per_cycle=2
 584 sys=system
 585 port=system.cpu.toL2Bus.slave[4]
 586
 587 [system.cpu.itb]
 588 type=ArmTLB
 589 children=walker
 590 eventq_index=0
 591 is_stage2=false
 592 size=64
 593 walker=system.cpu.itb.walker
 594
 595 [system.cpu.itb.walker]
 596 type=ArmTableWalker
 597 clk_domain=system.cpu_clk_domain
 598 eventq_index=0
 599 is_stage2=false
 600 num_squash_per_cycle=2
 601 sys=system
 602 port=system.cpu.toL2Bus.slave[2]
 603
 604 [system.cpu.l2cache]
 605 type=BaseCache
 606 children=prefetcher tags
 607 addr_ranges=0:18446744073709551615
 608 assoc=16
 609 clk_domain=system.cpu_clk_domain
 610 eventq_index=0
 611 forward_snoops=true
 612 hit_latency=12
 613 is_top_level=false
 614 max_miss_count=0
 615 mshrs=16
 616 prefetch_on_access=true
 617 prefetcher=system.cpu.l2cache.prefetcher
 618 response_latency=12
 619 sequential_access=false
 620 size=1048576
 621 system=system
 622 tags=system.cpu.l2cache.tags
 623 tgts_per_mshr=8
 624 two_queue=false
 625 write_buffers=8
 626 cpu_side=system.cpu.toL2Bus.master[0]
 627 mem_side=system.membus.slave[1]
 628
 629 [system.cpu.l2cache.prefetcher]
 630 type=StridePrefetcher
 631 clk_domain=system.cpu_clk_domain
 632 cross_pages=false
 633 data_accesses_only=false
 634 degree=8
 635 eventq_index=0
 636 inst_tagged=true
 637 latency=1
 638 on_miss_only=false
 639 on_prefetch=true
 640 on_read_only=false
 641 serial_squash=false
 642 size=100
 643 sys=system
 644 use_master_id=true
 645
 646 [system.cpu.l2cache.tags]
 647 type=RandomRepl
 648 assoc=16
 649 block_size=64
 650 clk_domain=system.cpu_clk_domain
 651 eventq_index=0
 652 hit_latency=12
 653 sequential_access=false
 654 size=1048576
 655
 656 [system.cpu.toL2Bus]
 657 type=CoherentXBar
 658 clk_domain=system.cpu_clk_domain
 659 eventq_index=0
 660 header_cycles=1
 661 snoop_filter=Null
 662 system=system
 663 use_default_range=false
 664 width=32
 665 master=system.cpu.l2cache.cpu_side
 666 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
 667
 668 [system.cpu.tracer]
 669 type=ExeTracer
 670 eventq_index=0
 671
 672 [system.cpu.workload]
 673 type=LiveProcess
 674 cmd=parser 2.1.dict -batch
 675 cwd=build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing
 676 egid=100
 677 env=
 678 errout=cerr
 679 euid=100
 680 eventq_index=0
 681 executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/parser
 682 gid=100
 683 input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in
 684 max_stack_size=67108864
 685 output=cout
 686 pid=100
 687 ppid=99
 688 simpoint=114600000000
 689 system=system
 690 uid=100
 691 useArchPT=false
 692
 693 [system.cpu_clk_domain]
 694 type=SrcClockDomain
 695 clock=500
 696 domain_id=-1
 697 eventq_index=0
 698 init_perf_level=0
 699 voltage_domain=system.voltage_domain
 700
 701 [system.dvfs_handler]
 702 type=DVFSHandler
 703 domains=
 704 enable=false
 705 eventq_index=0
 706 sys_clk_domain=system.clk_domain
 707 transition_latency=100000000
 708
 709 [system.membus]
 710 type=CoherentXBar
 711 clk_domain=system.clk_domain
 712 eventq_index=0
 713 header_cycles=1
 714 snoop_filter=Null
 715 system=system
 716 use_default_range=false
 717 width=8
 718 master=system.physmem.port
 719 slave=system.system_port system.cpu.l2cache.mem_side
 720
 721 [system.physmem]
 722 type=DRAMCtrl
 723 IDD0=0.075000
 724 IDD02=0.000000
 725 IDD2N=0.050000
 726 IDD2N2=0.000000
 727 IDD2P0=0.000000
 728 IDD2P02=0.000000
 729 IDD2P1=0.000000
 730 IDD2P12=0.000000
 731 IDD3N=0.057000
 732 IDD3N2=0.000000
 733 IDD3P0=0.000000
 734 IDD3P02=0.000000
 735 IDD3P1=0.000000
 736 IDD3P12=0.000000
 737 IDD4R=0.187000
 738 IDD4R2=0.000000
 739 IDD4W=0.165000
 740 IDD4W2=0.000000
 741 IDD5=0.220000
 742 IDD52=0.000000
 743 IDD6=0.000000
 744 IDD62=0.000000
 745 VDD=1.500000
 746 VDD2=0.000000
 747 activation_limit=4
 748 addr_mapping=RoRaBaChCo
 749 bank_groups_per_rank=0
 750 banks_per_rank=8
 751 burst_length=8
 752 channels=1
 753 clk_domain=system.clk_domain
 754 conf_table_reported=true
 755 device_bus_width=8
 756 device_rowbuffer_size=1024
 757 devices_per_rank=8
 758 dll=true
 759 eventq_index=0
 760 in_addr_map=true
 761 max_accesses_per_row=16
 762 mem_sched_policy=frfcfs
 763 min_writes_per_switch=16
 764 null=false
 765 page_policy=open_adaptive
 766 range=0:134217727
 767 ranks_per_channel=2
 768 read_buffer_size=32
 769 static_backend_latency=10000
 770 static_frontend_latency=10000
 771 tBURST=5000
 772 tCCD_L=0
 773 tCK=1250
 774 tCL=13750
 775 tCS=2500
 776 tRAS=35000
 777 tRCD=13750
 778 tREFI=7800000
 779 tRFC=260000
 780 tRP=13750
 781 tRRD=6000
 782 tRRD_L=0
 783 tRTP=7500
 784 tRTW=2500
 785 tWR=15000
 786 tWTR=7500
 787 tXAW=30000
 788 tXP=0
 789 tXPDLL=0
 790 tXS=0
 791 tXSDLL=0
 792 write_buffer_size=64
 793 write_high_thresh_perc=85
 794 write_low_thresh_perc=50
 795 port=system.membus.master[0]
 796
 797 [system.voltage_domain]
 798 type=VoltageDomain
 799 eventq_index=0
 800 voltage=1.000000
 801