tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini

   1 [root]
   2 type=Root
   3 children=system
   4 eventq_index=0
   5 full_system=false
   6 sim_quantum=0
   7 time_sync_enable=false
   8 time_sync_period=100000000000
   9 time_sync_spin_threshold=100000000
  10
  11 [system]
  12 type=System
  13 children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
  14 boot_osflags=a
  15 cache_line_size=64
  16 clk_domain=system.clk_domain
  17 eventq_index=0
  18 init_param=0
  19 kernel=
  20 load_addr_mask=1099511627775
  21 load_offset=0
  22 mem_mode=timing
  23 mem_ranges=
  24 memories=system.physmem
  25 num_work_ids=16
  26 readfile=
  27 symbolfile=
  28 work_begin_ckpt_count=0
  29 work_begin_cpu_id_exit=-1
  30 work_begin_exit_count=0
  31 work_cpus_ckpt_count=0
  32 work_end_ckpt_count=0
  33 work_end_exit_count=0
  34 work_item_id=-1
  35 system_port=system.membus.slave[0]
  36
  37 [system.clk_domain]
  38 type=SrcClockDomain
  39 clock=1000
  40 eventq_index=0
  41 voltage_domain=system.voltage_domain
  42
  43 [system.cpu]
  44 type=DerivO3CPU
  45 children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload
  46 LFSTSize=1024
  47 LQEntries=32
  48 LSQCheckLoads=true
  49 LSQDepCheckShift=4
  50 SQEntries=32
  51 SSITSize=1024
  52 activity=0
  53 backComSize=5
  54 branchPred=system.cpu.branchPred
  55 cachePorts=200
  56 checker=Null
  57 clk_domain=system.cpu_clk_domain
  58 commitToDecodeDelay=1
  59 commitToFetchDelay=1
  60 commitToIEWDelay=1
  61 commitToRenameDelay=1
  62 commitWidth=8
  63 cpu_id=0
  64 decodeToFetchDelay=1
  65 decodeToRenameDelay=1
  66 decodeWidth=8
  67 dispatchWidth=8
  68 do_checkpoint_insts=true
  69 do_quiesce=true
  70 do_statistics_insts=true
  71 dstage2_mmu=system.cpu.dstage2_mmu
  72 dtb=system.cpu.dtb
  73 eventq_index=0
  74 fetchBufferSize=64
  75 fetchToDecodeDelay=1
  76 fetchTrapLatency=1
  77 fetchWidth=8
  78 forwardComSize=5
  79 fuPool=system.cpu.fuPool
  80 function_trace=false
  81 function_trace_start=0
  82 iewToCommitDelay=1
  83 iewToDecodeDelay=1
  84 iewToFetchDelay=1
  85 iewToRenameDelay=1
  86 interrupts=system.cpu.interrupts
  87 isa=system.cpu.isa
  88 issueToExecuteDelay=1
  89 issueWidth=8
  90 istage2_mmu=system.cpu.istage2_mmu
  91 itb=system.cpu.itb
  92 max_insts_all_threads=0
  93 max_insts_any_thread=0
  94 max_loads_all_threads=0
  95 max_loads_any_thread=0
  96 needsTSO=false
  97 numIQEntries=64
  98 numPhysCCRegs=0
  99 numPhysFloatRegs=256
 100 numPhysIntRegs=256
 101 numROBEntries=192
 102 numRobs=1
 103 numThreads=1
 104 profile=0
 105 progress_interval=0
 106 renameToDecodeDelay=1
 107 renameToFetchDelay=1
 108 renameToIEWDelay=2
 109 renameToROBDelay=1
 110 renameWidth=8
 111 simpoint_start_insts=
 112 smtCommitPolicy=RoundRobin
 113 smtFetchPolicy=SingleThread
 114 smtIQPolicy=Partitioned
 115 smtIQThreshold=100
 116 smtLSQPolicy=Partitioned
 117 smtLSQThreshold=100
 118 smtNumFetchingThreads=1
 119 smtROBPolicy=Partitioned
 120 smtROBThreshold=100
 121 squashWidth=8
 122 store_set_clear_period=250000
 123 switched_out=false
 124 system=system
 125 tracer=system.cpu.tracer
 126 trapLatency=13
 127 wbDepth=1
 128 wbWidth=8
 129 workload=system.cpu.workload
 130 dcache_port=system.cpu.dcache.cpu_side
 131 icache_port=system.cpu.icache.cpu_side
 132
 133 [system.cpu.branchPred]
 134 type=BranchPredictor
 135 BTBEntries=4096
 136 BTBTagSize=16
 137 RASSize=16
 138 choiceCtrBits=2
 139 choicePredictorSize=8192
 140 eventq_index=0
 141 globalCtrBits=2
 142 globalPredictorSize=8192
 143 instShiftAmt=2
 144 localCtrBits=2
 145 localHistoryTableSize=2048
 146 localPredictorSize=2048
 147 numThreads=1
 148 predType=tournament
 149
 150 [system.cpu.dcache]
 151 type=BaseCache
 152 children=tags
 153 addr_ranges=0:18446744073709551615
 154 assoc=2
 155 clk_domain=system.cpu_clk_domain
 156 eventq_index=0
 157 forward_snoops=true
 158 hit_latency=2
 159 is_top_level=true
 160 max_miss_count=0
 161 mshrs=4
 162 prefetch_on_access=false
 163 prefetcher=Null
 164 response_latency=2
 165 sequential_access=false
 166 size=262144
 167 system=system
 168 tags=system.cpu.dcache.tags
 169 tgts_per_mshr=20
 170 two_queue=false
 171 write_buffers=8
 172 cpu_side=system.cpu.dcache_port
 173 mem_side=system.cpu.toL2Bus.slave[1]
 174
 175 [system.cpu.dcache.tags]
 176 type=LRU
 177 assoc=2
 178 block_size=64
 179 clk_domain=system.cpu_clk_domain
 180 eventq_index=0
 181 hit_latency=2
 182 sequential_access=false
 183 size=262144
 184
 185 [system.cpu.dstage2_mmu]
 186 type=ArmStage2MMU
 187 children=stage2_tlb
 188 eventq_index=0
 189 stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
 190 tlb=system.cpu.dtb
 191
 192 [system.cpu.dstage2_mmu.stage2_tlb]
 193 type=ArmTLB
 194 children=walker
 195 eventq_index=0
 196 is_stage2=true
 197 size=32
 198 walker=system.cpu.dstage2_mmu.stage2_tlb.walker
 199
 200 [system.cpu.dstage2_mmu.stage2_tlb.walker]
 201 type=ArmTableWalker
 202 clk_domain=system.cpu_clk_domain
 203 eventq_index=0
 204 is_stage2=true
 205 num_squash_per_cycle=2
 206 sys=system
 207 port=system.cpu.toL2Bus.slave[5]
 208
 209 [system.cpu.dtb]
 210 type=ArmTLB
 211 children=walker
 212 eventq_index=0
 213 is_stage2=false
 214 size=64
 215 walker=system.cpu.dtb.walker
 216
 217 [system.cpu.dtb.walker]
 218 type=ArmTableWalker
 219 clk_domain=system.cpu_clk_domain
 220 eventq_index=0
 221 is_stage2=false
 222 num_squash_per_cycle=2
 223 sys=system
 224 port=system.cpu.toL2Bus.slave[3]
 225
 226 [system.cpu.fuPool]
 227 type=FUPool
 228 children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
 229 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
 230 eventq_index=0
 231
 232 [system.cpu.fuPool.FUList0]
 233 type=FUDesc
 234 children=opList
 235 count=6
 236 eventq_index=0
 237 opList=system.cpu.fuPool.FUList0.opList
 238
 239 [system.cpu.fuPool.FUList0.opList]
 240 type=OpDesc
 241 eventq_index=0
 242 issueLat=1
 243 opClass=IntAlu
 244 opLat=1
 245
 246 [system.cpu.fuPool.FUList1]
 247 type=FUDesc
 248 children=opList0 opList1
 249 count=2
 250 eventq_index=0
 251 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
 252
 253 [system.cpu.fuPool.FUList1.opList0]
 254 type=OpDesc
 255 eventq_index=0
 256 issueLat=1
 257 opClass=IntMult
 258 opLat=3
 259
 260 [system.cpu.fuPool.FUList1.opList1]
 261 type=OpDesc
 262 eventq_index=0
 263 issueLat=19
 264 opClass=IntDiv
 265 opLat=20
 266
 267 [system.cpu.fuPool.FUList2]
 268 type=FUDesc
 269 children=opList0 opList1 opList2
 270 count=4
 271 eventq_index=0
 272 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
 273
 274 [system.cpu.fuPool.FUList2.opList0]
 275 type=OpDesc
 276 eventq_index=0
 277 issueLat=1
 278 opClass=FloatAdd
 279 opLat=2
 280
 281 [system.cpu.fuPool.FUList2.opList1]
 282 type=OpDesc
 283 eventq_index=0
 284 issueLat=1
 285 opClass=FloatCmp
 286 opLat=2
 287
 288 [system.cpu.fuPool.FUList2.opList2]
 289 type=OpDesc
 290 eventq_index=0
 291 issueLat=1
 292 opClass=FloatCvt
 293 opLat=2
 294
 295 [system.cpu.fuPool.FUList3]
 296 type=FUDesc
 297 children=opList0 opList1 opList2
 298 count=2
 299 eventq_index=0
 300 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
 301
 302 [system.cpu.fuPool.FUList3.opList0]
 303 type=OpDesc
 304 eventq_index=0
 305 issueLat=1
 306 opClass=FloatMult
 307 opLat=4
 308
 309 [system.cpu.fuPool.FUList3.opList1]
 310 type=OpDesc
 311 eventq_index=0
 312 issueLat=12
 313 opClass=FloatDiv
 314 opLat=12
 315
 316 [system.cpu.fuPool.FUList3.opList2]
 317 type=OpDesc
 318 eventq_index=0
 319 issueLat=24
 320 opClass=FloatSqrt
 321 opLat=24
 322
 323 [system.cpu.fuPool.FUList4]
 324 type=FUDesc
 325 children=opList
 326 count=0
 327 eventq_index=0
 328 opList=system.cpu.fuPool.FUList4.opList
 329
 330 [system.cpu.fuPool.FUList4.opList]
 331 type=OpDesc
 332 eventq_index=0
 333 issueLat=1
 334 opClass=MemRead
 335 opLat=1
 336
 337 [system.cpu.fuPool.FUList5]
 338 type=FUDesc
 339 children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
 340 count=4
 341 eventq_index=0
 342 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
 343
 344 [system.cpu.fuPool.FUList5.opList00]
 345 type=OpDesc
 346 eventq_index=0
 347 issueLat=1
 348 opClass=SimdAdd
 349 opLat=1
 350
 351 [system.cpu.fuPool.FUList5.opList01]
 352 type=OpDesc
 353 eventq_index=0
 354 issueLat=1
 355 opClass=SimdAddAcc
 356 opLat=1
 357
 358 [system.cpu.fuPool.FUList5.opList02]
 359 type=OpDesc
 360 eventq_index=0
 361 issueLat=1
 362 opClass=SimdAlu
 363 opLat=1
 364
 365 [system.cpu.fuPool.FUList5.opList03]
 366 type=OpDesc
 367 eventq_index=0
 368 issueLat=1
 369 opClass=SimdCmp
 370 opLat=1
 371
 372 [system.cpu.fuPool.FUList5.opList04]
 373 type=OpDesc
 374 eventq_index=0
 375 issueLat=1
 376 opClass=SimdCvt
 377 opLat=1
 378
 379 [system.cpu.fuPool.FUList5.opList05]
 380 type=OpDesc
 381 eventq_index=0
 382 issueLat=1
 383 opClass=SimdMisc
 384 opLat=1
 385
 386 [system.cpu.fuPool.FUList5.opList06]
 387 type=OpDesc
 388 eventq_index=0
 389 issueLat=1
 390 opClass=SimdMult
 391 opLat=1
 392
 393 [system.cpu.fuPool.FUList5.opList07]
 394 type=OpDesc
 395 eventq_index=0
 396 issueLat=1
 397 opClass=SimdMultAcc
 398 opLat=1
 399
 400 [system.cpu.fuPool.FUList5.opList08]
 401 type=OpDesc
 402 eventq_index=0
 403 issueLat=1
 404 opClass=SimdShift
 405 opLat=1
 406
 407 [system.cpu.fuPool.FUList5.opList09]
 408 type=OpDesc
 409 eventq_index=0
 410 issueLat=1
 411 opClass=SimdShiftAcc
 412 opLat=1
 413
 414 [system.cpu.fuPool.FUList5.opList10]
 415 type=OpDesc
 416 eventq_index=0
 417 issueLat=1
 418 opClass=SimdSqrt
 419 opLat=1
 420
 421 [system.cpu.fuPool.FUList5.opList11]
 422 type=OpDesc
 423 eventq_index=0
 424 issueLat=1
 425 opClass=SimdFloatAdd
 426 opLat=1
 427
 428 [system.cpu.fuPool.FUList5.opList12]
 429 type=OpDesc
 430 eventq_index=0
 431 issueLat=1
 432 opClass=SimdFloatAlu
 433 opLat=1
 434
 435 [system.cpu.fuPool.FUList5.opList13]
 436 type=OpDesc
 437 eventq_index=0
 438 issueLat=1
 439 opClass=SimdFloatCmp
 440 opLat=1
 441
 442 [system.cpu.fuPool.FUList5.opList14]
 443 type=OpDesc
 444 eventq_index=0
 445 issueLat=1
 446 opClass=SimdFloatCvt
 447 opLat=1
 448
 449 [system.cpu.fuPool.FUList5.opList15]
 450 type=OpDesc
 451 eventq_index=0
 452 issueLat=1
 453 opClass=SimdFloatDiv
 454 opLat=1
 455
 456 [system.cpu.fuPool.FUList5.opList16]
 457 type=OpDesc
 458 eventq_index=0
 459 issueLat=1
 460 opClass=SimdFloatMisc
 461 opLat=1
 462
 463 [system.cpu.fuPool.FUList5.opList17]
 464 type=OpDesc
 465 eventq_index=0
 466 issueLat=1
 467 opClass=SimdFloatMult
 468 opLat=1
 469
 470 [system.cpu.fuPool.FUList5.opList18]
 471 type=OpDesc
 472 eventq_index=0
 473 issueLat=1
 474 opClass=SimdFloatMultAcc
 475 opLat=1
 476
 477 [system.cpu.fuPool.FUList5.opList19]
 478 type=OpDesc
 479 eventq_index=0
 480 issueLat=1
 481 opClass=SimdFloatSqrt
 482 opLat=1
 483
 484 [system.cpu.fuPool.FUList6]
 485 type=FUDesc
 486 children=opList
 487 count=0
 488 eventq_index=0
 489 opList=system.cpu.fuPool.FUList6.opList
 490
 491 [system.cpu.fuPool.FUList6.opList]
 492 type=OpDesc
 493 eventq_index=0
 494 issueLat=1
 495 opClass=MemWrite
 496 opLat=1
 497
 498 [system.cpu.fuPool.FUList7]
 499 type=FUDesc
 500 children=opList0 opList1
 501 count=4
 502 eventq_index=0
 503 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
 504
 505 [system.cpu.fuPool.FUList7.opList0]
 506 type=OpDesc
 507 eventq_index=0
 508 issueLat=1
 509 opClass=MemRead
 510 opLat=1
 511
 512 [system.cpu.fuPool.FUList7.opList1]
 513 type=OpDesc
 514 eventq_index=0
 515 issueLat=1
 516 opClass=MemWrite
 517 opLat=1
 518
 519 [system.cpu.fuPool.FUList8]
 520 type=FUDesc
 521 children=opList
 522 count=1
 523 eventq_index=0
 524 opList=system.cpu.fuPool.FUList8.opList
 525
 526 [system.cpu.fuPool.FUList8.opList]
 527 type=OpDesc
 528 eventq_index=0
 529 issueLat=3
 530 opClass=IprAccess
 531 opLat=3
 532
 533 [system.cpu.icache]
 534 type=BaseCache
 535 children=tags
 536 addr_ranges=0:18446744073709551615
 537 assoc=2
 538 clk_domain=system.cpu_clk_domain
 539 eventq_index=0
 540 forward_snoops=true
 541 hit_latency=2
 542 is_top_level=true
 543 max_miss_count=0
 544 mshrs=4
 545 prefetch_on_access=false
 546 prefetcher=Null
 547 response_latency=2
 548 sequential_access=false
 549 size=131072
 550 system=system
 551 tags=system.cpu.icache.tags
 552 tgts_per_mshr=20
 553 two_queue=false
 554 write_buffers=8
 555 cpu_side=system.cpu.icache_port
 556 mem_side=system.cpu.toL2Bus.slave[0]
 557
 558 [system.cpu.icache.tags]
 559 type=LRU
 560 assoc=2
 561 block_size=64
 562 clk_domain=system.cpu_clk_domain
 563 eventq_index=0
 564 hit_latency=2
 565 sequential_access=false
 566 size=131072
 567
 568 [system.cpu.interrupts]
 569 type=ArmInterrupts
 570 eventq_index=0
 571
 572 [system.cpu.isa]
 573 type=ArmISA
 574 eventq_index=0
 575 fpsid=1090793632
 576 id_aa64afr0_el1=0
 577 id_aa64afr1_el1=0
 578 id_aa64dfr0_el1=1052678
 579 id_aa64dfr1_el1=0
 580 id_aa64isar0_el1=0
 581 id_aa64isar1_el1=0
 582 id_aa64mmfr0_el1=15728642
 583 id_aa64mmfr1_el1=0
 584 id_aa64pfr0_el1=17
 585 id_aa64pfr1_el1=0
 586 id_isar0=34607377
 587 id_isar1=34677009
 588 id_isar2=555950401
 589 id_isar3=17899825
 590 id_isar4=268501314
 591 id_isar5=0
 592 id_mmfr0=270536963
 593 id_mmfr1=0
 594 id_mmfr2=19070976
 595 id_mmfr3=34611729
 596 id_pfr0=49
 597 id_pfr1=4113
 598 midr=1091551472
 599 system=system
 600
 601 [system.cpu.istage2_mmu]
 602 type=ArmStage2MMU
 603 children=stage2_tlb
 604 eventq_index=0
 605 stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
 606 tlb=system.cpu.itb
 607
 608 [system.cpu.istage2_mmu.stage2_tlb]
 609 type=ArmTLB
 610 children=walker
 611 eventq_index=0
 612 is_stage2=true
 613 size=32
 614 walker=system.cpu.istage2_mmu.stage2_tlb.walker
 615
 616 [system.cpu.istage2_mmu.stage2_tlb.walker]
 617 type=ArmTableWalker
 618 clk_domain=system.cpu_clk_domain
 619 eventq_index=0
 620 is_stage2=true
 621 num_squash_per_cycle=2
 622 sys=system
 623 port=system.cpu.toL2Bus.slave[4]
 624
 625 [system.cpu.itb]
 626 type=ArmTLB
 627 children=walker
 628 eventq_index=0
 629 is_stage2=false
 630 size=64
 631 walker=system.cpu.itb.walker
 632
 633 [system.cpu.itb.walker]
 634 type=ArmTableWalker
 635 clk_domain=system.cpu_clk_domain
 636 eventq_index=0
 637 is_stage2=false
 638 num_squash_per_cycle=2
 639 sys=system
 640 port=system.cpu.toL2Bus.slave[2]
 641
 642 [system.cpu.l2cache]
 643 type=BaseCache
 644 children=tags
 645 addr_ranges=0:18446744073709551615
 646 assoc=8
 647 clk_domain=system.cpu_clk_domain
 648 eventq_index=0
 649 forward_snoops=true
 650 hit_latency=20
 651 is_top_level=false
 652 max_miss_count=0
 653 mshrs=20
 654 prefetch_on_access=false
 655 prefetcher=Null
 656 response_latency=20
 657 sequential_access=false
 658 size=2097152
 659 system=system
 660 tags=system.cpu.l2cache.tags
 661 tgts_per_mshr=12
 662 two_queue=false
 663 write_buffers=8
 664 cpu_side=system.cpu.toL2Bus.master[0]
 665 mem_side=system.membus.slave[1]
 666
 667 [system.cpu.l2cache.tags]
 668 type=LRU
 669 assoc=8
 670 block_size=64
 671 clk_domain=system.cpu_clk_domain
 672 eventq_index=0
 673 hit_latency=20
 674 sequential_access=false
 675 size=2097152
 676
 677 [system.cpu.toL2Bus]
 678 type=CoherentBus
 679 clk_domain=system.cpu_clk_domain
 680 eventq_index=0
 681 header_cycles=1
 682 system=system
 683 use_default_range=false
 684 width=32
 685 master=system.cpu.l2cache.cpu_side
 686 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
 687
 688 [system.cpu.tracer]
 689 type=ExeTracer
 690 eventq_index=0
 691
 692 [system.cpu.workload]
 693 type=LiveProcess
 694 cmd=parser 2.1.dict -batch
 695 cwd=build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing
 696 egid=100
 697 env=
 698 errout=cerr
 699 euid=100
 700 eventq_index=0
 701 executable=/dist/cpu2000/binaries/arm/linux/parser
 702 gid=100
 703 input=/dist/cpu2000/data/parser/mdred/input/parser.in
 704 max_stack_size=67108864
 705 output=cout
 706 pid=100
 707 ppid=99
 708 simpoint=114600000000
 709 system=system
 710 uid=100
 711
 712 [system.cpu_clk_domain]
 713 type=SrcClockDomain
 714 clock=500
 715 eventq_index=0
 716 voltage_domain=system.voltage_domain
 717
 718 [system.membus]
 719 type=CoherentBus
 720 clk_domain=system.clk_domain
 721 eventq_index=0
 722 header_cycles=1
 723 system=system
 724 use_default_range=false
 725 width=8
 726 master=system.physmem.port
 727 slave=system.system_port system.cpu.l2cache.mem_side
 728
 729 [system.physmem]
 730 type=SimpleDRAM
 731 activation_limit=4
 732 addr_mapping=RaBaChCo
 733 banks_per_rank=8
 734 burst_length=8
 735 channels=1
 736 clk_domain=system.clk_domain
 737 conf_table_reported=true
 738 device_bus_width=8
 739 device_rowbuffer_size=1024
 740 devices_per_rank=8
 741 eventq_index=0
 742 in_addr_map=true
 743 mem_sched_policy=frfcfs
 744 null=false
 745 page_policy=open
 746 range=0:134217727
 747 ranks_per_channel=2
 748 read_buffer_size=32
 749 static_backend_latency=10000
 750 static_frontend_latency=10000
 751 tBURST=5000
 752 tCL=13750
 753 tRAS=35000
 754 tRCD=13750
 755 tREFI=7800000
 756 tRFC=300000
 757 tRP=13750
 758 tRRD=6250
 759 tWTR=7500
 760 tXAW=40000
 761 write_buffer_size=32
 762 write_high_thresh_perc=70
 763 write_low_thresh_perc=0
 764 port=system.membus.master[0]
 765
 766 [system.voltage_domain]
 767 type=VoltageDomain
 768 eventq_index=0
 769 voltage=1.000000
 770