2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.290499 # Number of seconds simulated
4 sim_ticks 290498972000 # Number of ticks simulated
5 final_tick 290498972000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 2826052 # Simulator instruction rate (inst/s)
8 host_op_rate 3185244 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 1620598119 # Simulator tick rate (ticks/s)
10 host_mem_usage 217292 # Number of bytes of host memory used
11 host_seconds 179.25 # Real time elapsed on the host
12 sim_insts 506581615 # Number of instructions simulated
13 sim_ops 570968176 # Number of ops (including micro ops) simulated
14 system.physmem.bytes_read 2489298238 # Number of bytes read from this memory
15 system.physmem.bytes_inst_read 2066445536 # Number of instructions bytes read from this memory
16 system.physmem.bytes_written 216067624 # Number of bytes written to this memory
17 system.physmem.num_reads 641840242 # Number of read requests responded to by this memory
18 system.physmem.num_writes 55727847 # Number of write requests responded to by this memory
19 system.physmem.num_other 0 # Number of other requests responded to by this memory
20 system.physmem.bw_read 8569043191 # Total read bandwidth from this memory (bytes/s)
21 system.physmem.bw_inst_read 7113434935 # Instruction read bandwidth from this memory (bytes/s)
22 system.physmem.bw_write 743781028 # Write bandwidth from this memory (bytes/s)
23 system.physmem.bw_total 9312824219 # Total bandwidth to/from this memory (bytes/s)
24 system.cpu.dtb.inst_hits 0 # ITB inst hits
25 system.cpu.dtb.inst_misses 0 # ITB inst misses
26 system.cpu.dtb.read_hits 0 # DTB read hits
27 system.cpu.dtb.read_misses 0 # DTB read misses
28 system.cpu.dtb.write_hits 0 # DTB write hits
29 system.cpu.dtb.write_misses 0 # DTB write misses
30 system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
31 system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
32 system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
33 system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
34 system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
35 system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
36 system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
37 system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
38 system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
39 system.cpu.dtb.read_accesses 0 # DTB read accesses
40 system.cpu.dtb.write_accesses 0 # DTB write accesses
41 system.cpu.dtb.inst_accesses 0 # ITB inst accesses
42 system.cpu.dtb.hits 0 # DTB hits
43 system.cpu.dtb.misses 0 # DTB misses
44 system.cpu.dtb.accesses 0 # DTB accesses
45 system.cpu.itb.inst_hits 0 # ITB inst hits
46 system.cpu.itb.inst_misses 0 # ITB inst misses
47 system.cpu.itb.read_hits 0 # DTB read hits
48 system.cpu.itb.read_misses 0 # DTB read misses
49 system.cpu.itb.write_hits 0 # DTB write hits
50 system.cpu.itb.write_misses 0 # DTB write misses
51 system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
52 system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
53 system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
54 system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
55 system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
56 system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
57 system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
58 system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
59 system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
60 system.cpu.itb.read_accesses 0 # DTB read accesses
61 system.cpu.itb.write_accesses 0 # DTB write accesses
62 system.cpu.itb.inst_accesses 0 # ITB inst accesses
63 system.cpu.itb.hits 0 # DTB hits
64 system.cpu.itb.misses 0 # DTB misses
65 system.cpu.itb.accesses 0 # DTB accesses
66 system.cpu.workload.num_syscalls 548 # Number of system calls
67 system.cpu.numCycles 580997945 # number of cpu cycles simulated
68 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
69 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
70 system.cpu.committedInsts 506581615 # Number of instructions committed
71 system.cpu.committedOps 570968176 # Number of ops (including micro ops) committed
72 system.cpu.num_int_alu_accesses 470727703 # Number of integer alu accesses
73 system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
74 system.cpu.num_func_calls 15725605 # number of times a function call or return occured
75 system.cpu.num_conditional_control_insts 94894805 # number of instructions that are conditional controls
76 system.cpu.num_int_insts 470727703 # number of integer instructions
77 system.cpu.num_fp_insts 16 # number of float instructions
78 system.cpu.num_int_register_reads 2465023721 # number of times the integer registers were read
79 system.cpu.num_int_register_writes 646169365 # number of times the integer registers were written
80 system.cpu.num_fp_register_reads 16 # number of times the floating registers were read
81 system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
82 system.cpu.num_mem_refs 182890035 # number of memory refs
83 system.cpu.num_load_insts 126029556 # Number of load instructions
84 system.cpu.num_store_insts 56860479 # Number of store instructions
85 system.cpu.num_idle_cycles 0 # Number of idle cycles
86 system.cpu.num_busy_cycles 580997945 # Number of busy cycles
87 system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
88 system.cpu.idle_fraction 0 # Percentage of idle cycles
90 ---------- End Simulation Statistics ----------
projects / gem5.git / blob