tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini

   1 [root]
   2 type=Root
   3 children=system
   4 full_system=false
   5 time_sync_enable=false
   6 time_sync_period=100000000000
   7 time_sync_spin_threshold=100000000
   8
   9 [system]
  10 type=System
  11 children=cpu membus physmem
  12 boot_osflags=a
  13 init_param=0
  14 kernel=
  15 load_addr_mask=1099511627775
  16 mem_mode=atomic
  17 memories=system.physmem
  18 num_work_ids=16
  19 physmem=system.physmem
  20 readfile=
  21 symbolfile=
  22 work_begin_ckpt_count=0
  23 work_begin_cpu_id_exit=-1
  24 work_begin_exit_count=0
  25 work_cpus_ckpt_count=0
  26 work_end_ckpt_count=0
  27 work_end_exit_count=0
  28 work_item_id=-1
  29 system_port=system.membus.port[0]
  30
  31 [system.cpu]
  32 type=DerivO3CPU
  33 children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
  34 BTBEntries=4096
  35 BTBTagSize=16
  36 LFSTSize=1024
  37 LQEntries=32
  38 LSQCheckLoads=true
  39 LSQDepCheckShift=4
  40 RASSize=16
  41 SQEntries=32
  42 SSITSize=1024
  43 activity=0
  44 backComSize=5
  45 cachePorts=200
  46 checker=Null
  47 choiceCtrBits=2
  48 choicePredictorSize=8192
  49 clock=500
  50 commitToDecodeDelay=1
  51 commitToFetchDelay=1
  52 commitToIEWDelay=1
  53 commitToRenameDelay=1
  54 commitWidth=8
  55 cpu_id=0
  56 decodeToFetchDelay=1
  57 decodeToRenameDelay=1
  58 decodeWidth=8
  59 defer_registration=false
  60 dispatchWidth=8
  61 do_checkpoint_insts=true
  62 do_quiesce=true
  63 do_statistics_insts=true
  64 dtb=system.cpu.dtb
  65 fetchToDecodeDelay=1
  66 fetchTrapLatency=1
  67 fetchWidth=8
  68 forwardComSize=5
  69 fuPool=system.cpu.fuPool
  70 function_trace=false
  71 function_trace_start=0
  72 globalCtrBits=2
  73 globalHistoryBits=13
  74 globalPredictorSize=8192
  75 iewToCommitDelay=1
  76 iewToDecodeDelay=1
  77 iewToFetchDelay=1
  78 iewToRenameDelay=1
  79 instShiftAmt=2
  80 interrupts=system.cpu.interrupts
  81 issueToExecuteDelay=1
  82 issueWidth=8
  83 itb=system.cpu.itb
  84 localCtrBits=2
  85 localHistoryBits=11
  86 localHistoryTableSize=2048
  87 localPredictorSize=2048
  88 max_insts_all_threads=0
  89 max_insts_any_thread=0
  90 max_loads_all_threads=0
  91 max_loads_any_thread=0
  92 needsTSO=true
  93 numIQEntries=64
  94 numPhysFloatRegs=256
  95 numPhysIntRegs=256
  96 numROBEntries=192
  97 numRobs=1
  98 numThreads=1
  99 phase=0
 100 predType=tournament
 101 profile=0
 102 progress_interval=0
 103 renameToDecodeDelay=1
 104 renameToFetchDelay=1
 105 renameToIEWDelay=2
 106 renameToROBDelay=1
 107 renameWidth=8
 108 smtCommitPolicy=RoundRobin
 109 smtFetchPolicy=SingleThread
 110 smtIQPolicy=Partitioned
 111 smtIQThreshold=100
 112 smtLSQPolicy=Partitioned
 113 smtLSQThreshold=100
 114 smtNumFetchingThreads=1
 115 smtROBPolicy=Partitioned
 116 smtROBThreshold=100
 117 squashWidth=8
 118 store_set_clear_period=250000
 119 system=system
 120 tracer=system.cpu.tracer
 121 trapLatency=13
 122 wbDepth=1
 123 wbWidth=8
 124 workload=system.cpu.workload
 125 dcache_port=system.cpu.dcache.cpu_side
 126 icache_port=system.cpu.icache.cpu_side
 127
 128 [system.cpu.dcache]
 129 type=BaseCache
 130 addr_range=0:18446744073709551615
 131 assoc=2
 132 block_size=64
 133 forward_snoops=true
 134 hash_delay=1
 135 is_top_level=true
 136 latency=1000
 137 max_miss_count=0
 138 mshrs=10
 139 prefetch_on_access=false
 140 prefetcher=Null
 141 prioritizeRequests=false
 142 repl=Null
 143 size=262144
 144 subblock_size=0
 145 system=system
 146 tgts_per_mshr=20
 147 trace_addr=0
 148 two_queue=false
 149 write_buffers=8
 150 cpu_side=system.cpu.dcache_port
 151 mem_side=system.cpu.toL2Bus.port[1]
 152
 153 [system.cpu.dtb]
 154 type=X86TLB
 155 children=walker
 156 size=64
 157 walker=system.cpu.dtb.walker
 158
 159 [system.cpu.dtb.walker]
 160 type=X86PagetableWalker
 161 system=system
 162 port=system.cpu.toL2Bus.port[3]
 163
 164 [system.cpu.fuPool]
 165 type=FUPool
 166 children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
 167 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
 168
 169 [system.cpu.fuPool.FUList0]
 170 type=FUDesc
 171 children=opList
 172 count=6
 173 opList=system.cpu.fuPool.FUList0.opList
 174
 175 [system.cpu.fuPool.FUList0.opList]
 176 type=OpDesc
 177 issueLat=1
 178 opClass=IntAlu
 179 opLat=1
 180
 181 [system.cpu.fuPool.FUList1]
 182 type=FUDesc
 183 children=opList0 opList1
 184 count=2
 185 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
 186
 187 [system.cpu.fuPool.FUList1.opList0]
 188 type=OpDesc
 189 issueLat=1
 190 opClass=IntMult
 191 opLat=3
 192
 193 [system.cpu.fuPool.FUList1.opList1]
 194 type=OpDesc
 195 issueLat=19
 196 opClass=IntDiv
 197 opLat=20
 198
 199 [system.cpu.fuPool.FUList2]
 200 type=FUDesc
 201 children=opList0 opList1 opList2
 202 count=4
 203 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
 204
 205 [system.cpu.fuPool.FUList2.opList0]
 206 type=OpDesc
 207 issueLat=1
 208 opClass=FloatAdd
 209 opLat=2
 210
 211 [system.cpu.fuPool.FUList2.opList1]
 212 type=OpDesc
 213 issueLat=1
 214 opClass=FloatCmp
 215 opLat=2
 216
 217 [system.cpu.fuPool.FUList2.opList2]
 218 type=OpDesc
 219 issueLat=1
 220 opClass=FloatCvt
 221 opLat=2
 222
 223 [system.cpu.fuPool.FUList3]
 224 type=FUDesc
 225 children=opList0 opList1 opList2
 226 count=2
 227 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
 228
 229 [system.cpu.fuPool.FUList3.opList0]
 230 type=OpDesc
 231 issueLat=1
 232 opClass=FloatMult
 233 opLat=4
 234
 235 [system.cpu.fuPool.FUList3.opList1]
 236 type=OpDesc
 237 issueLat=12
 238 opClass=FloatDiv
 239 opLat=12
 240
 241 [system.cpu.fuPool.FUList3.opList2]
 242 type=OpDesc
 243 issueLat=24
 244 opClass=FloatSqrt
 245 opLat=24
 246
 247 [system.cpu.fuPool.FUList4]
 248 type=FUDesc
 249 children=opList
 250 count=0
 251 opList=system.cpu.fuPool.FUList4.opList
 252
 253 [system.cpu.fuPool.FUList4.opList]
 254 type=OpDesc
 255 issueLat=1
 256 opClass=MemRead
 257 opLat=1
 258
 259 [system.cpu.fuPool.FUList5]
 260 type=FUDesc
 261 children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
 262 count=4
 263 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
 264
 265 [system.cpu.fuPool.FUList5.opList00]
 266 type=OpDesc
 267 issueLat=1
 268 opClass=SimdAdd
 269 opLat=1
 270
 271 [system.cpu.fuPool.FUList5.opList01]
 272 type=OpDesc
 273 issueLat=1
 274 opClass=SimdAddAcc
 275 opLat=1
 276
 277 [system.cpu.fuPool.FUList5.opList02]
 278 type=OpDesc
 279 issueLat=1
 280 opClass=SimdAlu
 281 opLat=1
 282
 283 [system.cpu.fuPool.FUList5.opList03]
 284 type=OpDesc
 285 issueLat=1
 286 opClass=SimdCmp
 287 opLat=1
 288
 289 [system.cpu.fuPool.FUList5.opList04]
 290 type=OpDesc
 291 issueLat=1
 292 opClass=SimdCvt
 293 opLat=1
 294
 295 [system.cpu.fuPool.FUList5.opList05]
 296 type=OpDesc
 297 issueLat=1
 298 opClass=SimdMisc
 299 opLat=1
 300
 301 [system.cpu.fuPool.FUList5.opList06]
 302 type=OpDesc
 303 issueLat=1
 304 opClass=SimdMult
 305 opLat=1
 306
 307 [system.cpu.fuPool.FUList5.opList07]
 308 type=OpDesc
 309 issueLat=1
 310 opClass=SimdMultAcc
 311 opLat=1
 312
 313 [system.cpu.fuPool.FUList5.opList08]
 314 type=OpDesc
 315 issueLat=1
 316 opClass=SimdShift
 317 opLat=1
 318
 319 [system.cpu.fuPool.FUList5.opList09]
 320 type=OpDesc
 321 issueLat=1
 322 opClass=SimdShiftAcc
 323 opLat=1
 324
 325 [system.cpu.fuPool.FUList5.opList10]
 326 type=OpDesc
 327 issueLat=1
 328 opClass=SimdSqrt
 329 opLat=1
 330
 331 [system.cpu.fuPool.FUList5.opList11]
 332 type=OpDesc
 333 issueLat=1
 334 opClass=SimdFloatAdd
 335 opLat=1
 336
 337 [system.cpu.fuPool.FUList5.opList12]
 338 type=OpDesc
 339 issueLat=1
 340 opClass=SimdFloatAlu
 341 opLat=1
 342
 343 [system.cpu.fuPool.FUList5.opList13]
 344 type=OpDesc
 345 issueLat=1
 346 opClass=SimdFloatCmp
 347 opLat=1
 348
 349 [system.cpu.fuPool.FUList5.opList14]
 350 type=OpDesc
 351 issueLat=1
 352 opClass=SimdFloatCvt
 353 opLat=1
 354
 355 [system.cpu.fuPool.FUList5.opList15]
 356 type=OpDesc
 357 issueLat=1
 358 opClass=SimdFloatDiv
 359 opLat=1
 360
 361 [system.cpu.fuPool.FUList5.opList16]
 362 type=OpDesc
 363 issueLat=1
 364 opClass=SimdFloatMisc
 365 opLat=1
 366
 367 [system.cpu.fuPool.FUList5.opList17]
 368 type=OpDesc
 369 issueLat=1
 370 opClass=SimdFloatMult
 371 opLat=1
 372
 373 [system.cpu.fuPool.FUList5.opList18]
 374 type=OpDesc
 375 issueLat=1
 376 opClass=SimdFloatMultAcc
 377 opLat=1
 378
 379 [system.cpu.fuPool.FUList5.opList19]
 380 type=OpDesc
 381 issueLat=1
 382 opClass=SimdFloatSqrt
 383 opLat=1
 384
 385 [system.cpu.fuPool.FUList6]
 386 type=FUDesc
 387 children=opList
 388 count=0
 389 opList=system.cpu.fuPool.FUList6.opList
 390
 391 [system.cpu.fuPool.FUList6.opList]
 392 type=OpDesc
 393 issueLat=1
 394 opClass=MemWrite
 395 opLat=1
 396
 397 [system.cpu.fuPool.FUList7]
 398 type=FUDesc
 399 children=opList0 opList1
 400 count=4
 401 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
 402
 403 [system.cpu.fuPool.FUList7.opList0]
 404 type=OpDesc
 405 issueLat=1
 406 opClass=MemRead
 407 opLat=1
 408
 409 [system.cpu.fuPool.FUList7.opList1]
 410 type=OpDesc
 411 issueLat=1
 412 opClass=MemWrite
 413 opLat=1
 414
 415 [system.cpu.fuPool.FUList8]
 416 type=FUDesc
 417 children=opList
 418 count=1
 419 opList=system.cpu.fuPool.FUList8.opList
 420
 421 [system.cpu.fuPool.FUList8.opList]
 422 type=OpDesc
 423 issueLat=3
 424 opClass=IprAccess
 425 opLat=3
 426
 427 [system.cpu.icache]
 428 type=BaseCache
 429 addr_range=0:18446744073709551615
 430 assoc=2
 431 block_size=64
 432 forward_snoops=true
 433 hash_delay=1
 434 is_top_level=true
 435 latency=1000
 436 max_miss_count=0
 437 mshrs=10
 438 prefetch_on_access=false
 439 prefetcher=Null
 440 prioritizeRequests=false
 441 repl=Null
 442 size=131072
 443 subblock_size=0
 444 system=system
 445 tgts_per_mshr=20
 446 trace_addr=0
 447 two_queue=false
 448 write_buffers=8
 449 cpu_side=system.cpu.icache_port
 450 mem_side=system.cpu.toL2Bus.port[0]
 451
 452 [system.cpu.interrupts]
 453 type=X86LocalApic
 454 int_latency=1000
 455 pio_addr=2305843009213693952
 456 pio_latency=1000
 457 system=system
 458 int_port=system.membus.port[4]
 459 pio=system.membus.port[3]
 460
 461 [system.cpu.itb]
 462 type=X86TLB
 463 children=walker
 464 size=64
 465 walker=system.cpu.itb.walker
 466
 467 [system.cpu.itb.walker]
 468 type=X86PagetableWalker
 469 system=system
 470 port=system.cpu.toL2Bus.port[2]
 471
 472 [system.cpu.l2cache]
 473 type=BaseCache
 474 addr_range=0:18446744073709551615
 475 assoc=2
 476 block_size=64
 477 forward_snoops=true
 478 hash_delay=1
 479 is_top_level=false
 480 latency=1000
 481 max_miss_count=0
 482 mshrs=10
 483 prefetch_on_access=false
 484 prefetcher=Null
 485 prioritizeRequests=false
 486 repl=Null
 487 size=2097152
 488 subblock_size=0
 489 system=system
 490 tgts_per_mshr=5
 491 trace_addr=0
 492 two_queue=false
 493 write_buffers=8
 494 cpu_side=system.cpu.toL2Bus.port[4]
 495 mem_side=system.membus.port[2]
 496
 497 [system.cpu.toL2Bus]
 498 type=Bus
 499 block_size=64
 500 bus_id=0
 501 clock=1000
 502 header_cycles=1
 503 use_default_range=false
 504 width=64
 505 port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side
 506
 507 [system.cpu.tracer]
 508 type=ExeTracer
 509
 510 [system.cpu.workload]
 511 type=LiveProcess
 512 cmd=parser 2.1.dict -batch
 513 cwd=build/X86/tests/fast/long/se/20.parser/x86/linux/o3-timing
 514 egid=100
 515 env=
 516 errout=cerr
 517 euid=100
 518 executable=/dist/m5/cpu2000/binaries/x86/linux/parser
 519 gid=100
 520 input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
 521 max_stack_size=67108864
 522 output=cout
 523 pid=100
 524 ppid=99
 525 simpoint=114600000000
 526 system=system
 527 uid=100
 528
 529 [system.membus]
 530 type=Bus
 531 block_size=64
 532 bus_id=0
 533 clock=1000
 534 header_cycles=1
 535 use_default_range=false
 536 width=64
 537 port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side system.cpu.interrupts.pio system.cpu.interrupts.int_port
 538
 539 [system.physmem]
 540 type=PhysicalMemory
 541 file=
 542 latency=30000
 543 latency_var=0
 544 null=false
 545 range=0:134217727
 546 zero=false
 547 port=system.membus.port[1]
 548