2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.451833 # Number of seconds simulated
4 sim_ticks 451832922000 # Number of ticks simulated
5 final_tick 451832922000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 67045 # Simulator instruction rate (inst/s)
8 host_op_rate 123974 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 36635806 # Simulator tick rate (ticks/s)
10 host_mem_usage 390776 # Number of bytes of host memory used
11 host_seconds 12333.10 # Real time elapsed on the host
12 sim_insts 826877109 # Number of instructions simulated
13 sim_ops 1528988701 # Number of ops (including micro ops) simulated
14 system.physmem.bytes_read::cpu.inst 202816 # Number of bytes read from this memory
15 system.physmem.bytes_read::cpu.data 24482112 # Number of bytes read from this memory
16 system.physmem.bytes_read::total 24684928 # Number of bytes read from this memory
17 system.physmem.bytes_inst_read::cpu.inst 202816 # Number of instructions bytes read from this memory
18 system.physmem.bytes_inst_read::total 202816 # Number of instructions bytes read from this memory
19 system.physmem.bytes_written::writebacks 18794304 # Number of bytes written to this memory
20 system.physmem.bytes_written::total 18794304 # Number of bytes written to this memory
21 system.physmem.num_reads::cpu.inst 3169 # Number of read requests responded to by this memory
22 system.physmem.num_reads::cpu.data 382533 # Number of read requests responded to by this memory
23 system.physmem.num_reads::total 385702 # Number of read requests responded to by this memory
24 system.physmem.num_writes::writebacks 293661 # Number of write requests responded to by this memory
25 system.physmem.num_writes::total 293661 # Number of write requests responded to by this memory
26 system.physmem.bw_read::cpu.inst 448874 # Total read bandwidth from this memory (bytes/s)
27 system.physmem.bw_read::cpu.data 54183993 # Total read bandwidth from this memory (bytes/s)
28 system.physmem.bw_read::total 54632867 # Total read bandwidth from this memory (bytes/s)
29 system.physmem.bw_inst_read::cpu.inst 448874 # Instruction read bandwidth from this memory (bytes/s)
30 system.physmem.bw_inst_read::total 448874 # Instruction read bandwidth from this memory (bytes/s)
31 system.physmem.bw_write::writebacks 41595694 # Write bandwidth from this memory (bytes/s)
32 system.physmem.bw_write::total 41595694 # Write bandwidth from this memory (bytes/s)
33 system.physmem.bw_total::writebacks 41595694 # Total bandwidth to/from this memory (bytes/s)
34 system.physmem.bw_total::cpu.inst 448874 # Total bandwidth to/from this memory (bytes/s)
35 system.physmem.bw_total::cpu.data 54183993 # Total bandwidth to/from this memory (bytes/s)
36 system.physmem.bw_total::total 96228561 # Total bandwidth to/from this memory (bytes/s)
37 system.physmem.readReqs 385702 # Total number of read requests seen
38 system.physmem.writeReqs 293661 # Total number of write requests seen
39 system.physmem.cpureqs 815428 # Reqs generatd by CPU via cache - shady
40 system.physmem.bytesRead 24684928 # Total number of bytes read from memory
41 system.physmem.bytesWritten 18794304 # Total number of bytes written to memory
42 system.physmem.bytesConsumedRd 24684928 # bytesRead derated as per pkt->getSize()
43 system.physmem.bytesConsumedWr 18794304 # bytesWritten derated as per pkt->getSize()
44 system.physmem.servicedByWrQ 138 # Number of read reqs serviced by write Q
45 system.physmem.neitherReadNorWrite 136028 # Reqs where no action is needed
46 system.physmem.perBankRdReqs::0 23108 # Track reads on a per bank basis
47 system.physmem.perBankRdReqs::1 24460 # Track reads on a per bank basis
48 system.physmem.perBankRdReqs::2 23977 # Track reads on a per bank basis
49 system.physmem.perBankRdReqs::3 22639 # Track reads on a per bank basis
50 system.physmem.perBankRdReqs::4 23451 # Track reads on a per bank basis
51 system.physmem.perBankRdReqs::5 24452 # Track reads on a per bank basis
52 system.physmem.perBankRdReqs::6 24479 # Track reads on a per bank basis
53 system.physmem.perBankRdReqs::7 24189 # Track reads on a per bank basis
54 system.physmem.perBankRdReqs::8 24310 # Track reads on a per bank basis
55 system.physmem.perBankRdReqs::9 25055 # Track reads on a per bank basis
56 system.physmem.perBankRdReqs::10 24328 # Track reads on a per bank basis
57 system.physmem.perBankRdReqs::11 24340 # Track reads on a per bank basis
58 system.physmem.perBankRdReqs::12 24467 # Track reads on a per bank basis
59 system.physmem.perBankRdReqs::13 23420 # Track reads on a per bank basis
60 system.physmem.perBankRdReqs::14 24898 # Track reads on a per bank basis
61 system.physmem.perBankRdReqs::15 23991 # Track reads on a per bank basis
62 system.physmem.perBankWrReqs::0 17770 # Track writes on a per bank basis
63 system.physmem.perBankWrReqs::1 18792 # Track writes on a per bank basis
64 system.physmem.perBankWrReqs::2 18332 # Track writes on a per bank basis
65 system.physmem.perBankWrReqs::3 17557 # Track writes on a per bank basis
66 system.physmem.perBankWrReqs::4 18019 # Track writes on a per bank basis
67 system.physmem.perBankWrReqs::5 18441 # Track writes on a per bank basis
68 system.physmem.perBankWrReqs::6 18303 # Track writes on a per bank basis
69 system.physmem.perBankWrReqs::7 18298 # Track writes on a per bank basis
70 system.physmem.perBankWrReqs::8 18726 # Track writes on a per bank basis
71 system.physmem.perBankWrReqs::9 19016 # Track writes on a per bank basis
72 system.physmem.perBankWrReqs::10 18442 # Track writes on a per bank basis
73 system.physmem.perBankWrReqs::11 18563 # Track writes on a per bank basis
74 system.physmem.perBankWrReqs::12 18552 # Track writes on a per bank basis
75 system.physmem.perBankWrReqs::13 17871 # Track writes on a per bank basis
76 system.physmem.perBankWrReqs::14 18864 # Track writes on a per bank basis
77 system.physmem.perBankWrReqs::15 18115 # Track writes on a per bank basis
78 system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
79 system.physmem.numWrRetry 37 # Number of times wr buffer was full causing retry
80 system.physmem.totGap 451832896000 # Total gap between requests
81 system.physmem.readPktSize::0 0 # Categorize read packet sizes
82 system.physmem.readPktSize::1 0 # Categorize read packet sizes
83 system.physmem.readPktSize::2 0 # Categorize read packet sizes
84 system.physmem.readPktSize::3 0 # Categorize read packet sizes
85 system.physmem.readPktSize::4 0 # Categorize read packet sizes
86 system.physmem.readPktSize::5 0 # Categorize read packet sizes
87 system.physmem.readPktSize::6 385702 # Categorize read packet sizes
88 system.physmem.writePktSize::0 0 # Categorize write packet sizes
89 system.physmem.writePktSize::1 0 # Categorize write packet sizes
90 system.physmem.writePktSize::2 0 # Categorize write packet sizes
91 system.physmem.writePktSize::3 0 # Categorize write packet sizes
92 system.physmem.writePktSize::4 0 # Categorize write packet sizes
93 system.physmem.writePktSize::5 0 # Categorize write packet sizes
94 system.physmem.writePktSize::6 293661 # Categorize write packet sizes
95 system.physmem.rdQLenPdf::0 380831 # What read queue length does an incoming req see
96 system.physmem.rdQLenPdf::1 4356 # What read queue length does an incoming req see
97 system.physmem.rdQLenPdf::2 329 # What read queue length does an incoming req see
98 system.physmem.rdQLenPdf::3 44 # What read queue length does an incoming req see
99 system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see
100 system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
101 system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
102 system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
103 system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
104 system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
105 system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
106 system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
107 system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
108 system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
109 system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
110 system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
111 system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
112 system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
113 system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
114 system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
115 system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
116 system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
117 system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
118 system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
119 system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
120 system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
121 system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
122 system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
123 system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
124 system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
125 system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
126 system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
127 system.physmem.wrQLenPdf::0 12709 # What write queue length does an incoming req see
128 system.physmem.wrQLenPdf::1 12717 # What write queue length does an incoming req see
129 system.physmem.wrQLenPdf::2 12719 # What write queue length does an incoming req see
130 system.physmem.wrQLenPdf::3 12722 # What write queue length does an incoming req see
131 system.physmem.wrQLenPdf::4 12722 # What write queue length does an incoming req see
132 system.physmem.wrQLenPdf::5 12723 # What write queue length does an incoming req see
133 system.physmem.wrQLenPdf::6 12725 # What write queue length does an incoming req see
134 system.physmem.wrQLenPdf::7 12728 # What write queue length does an incoming req see
135 system.physmem.wrQLenPdf::8 12729 # What write queue length does an incoming req see
136 system.physmem.wrQLenPdf::9 12768 # What write queue length does an incoming req see
137 system.physmem.wrQLenPdf::10 12768 # What write queue length does an incoming req see
138 system.physmem.wrQLenPdf::11 12768 # What write queue length does an incoming req see
139 system.physmem.wrQLenPdf::12 12768 # What write queue length does an incoming req see
140 system.physmem.wrQLenPdf::13 12768 # What write queue length does an incoming req see
141 system.physmem.wrQLenPdf::14 12768 # What write queue length does an incoming req see
142 system.physmem.wrQLenPdf::15 12768 # What write queue length does an incoming req see
143 system.physmem.wrQLenPdf::16 12768 # What write queue length does an incoming req see
144 system.physmem.wrQLenPdf::17 12768 # What write queue length does an incoming req see
145 system.physmem.wrQLenPdf::18 12768 # What write queue length does an incoming req see
146 system.physmem.wrQLenPdf::19 12768 # What write queue length does an incoming req see
147 system.physmem.wrQLenPdf::20 12767 # What write queue length does an incoming req see
148 system.physmem.wrQLenPdf::21 12767 # What write queue length does an incoming req see
149 system.physmem.wrQLenPdf::22 12767 # What write queue length does an incoming req see
150 system.physmem.wrQLenPdf::23 59 # What write queue length does an incoming req see
151 system.physmem.wrQLenPdf::24 51 # What write queue length does an incoming req see
152 system.physmem.wrQLenPdf::25 49 # What write queue length does an incoming req see
153 system.physmem.wrQLenPdf::26 46 # What write queue length does an incoming req see
154 system.physmem.wrQLenPdf::27 46 # What write queue length does an incoming req see
155 system.physmem.wrQLenPdf::28 45 # What write queue length does an incoming req see
156 system.physmem.wrQLenPdf::29 43 # What write queue length does an incoming req see
157 system.physmem.wrQLenPdf::30 40 # What write queue length does an incoming req see
158 system.physmem.wrQLenPdf::31 39 # What write queue length does an incoming req see
159 system.physmem.totQLat 3445991500 # Total cycles spent in queuing delays
160 system.physmem.totMemAccLat 12040169000 # Sum of mem lat for all requests
161 system.physmem.totBusLat 1927820000 # Total cycles spent in databus access
162 system.physmem.totBankLat 6666357500 # Total cycles spent in bank access
163 system.physmem.avgQLat 8937.53 # Average queueing delay per request
164 system.physmem.avgBankLat 17289.89 # Average bank access latency per request
165 system.physmem.avgBusLat 5000.00 # Average bus latency per request
166 system.physmem.avgMemAccLat 31227.42 # Average memory access latency
167 system.physmem.avgRdBW 54.63 # Average achieved read bandwidth in MB/s
168 system.physmem.avgWrBW 41.60 # Average achieved write bandwidth in MB/s
169 system.physmem.avgConsumedRdBW 54.63 # Average consumed read bandwidth in MB/s
170 system.physmem.avgConsumedWrBW 41.60 # Average consumed write bandwidth in MB/s
171 system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
172 system.physmem.busUtil 0.75 # Data bus utilization in percentage
173 system.physmem.avgRdQLen 0.03 # Average read queue length over time
174 system.physmem.avgWrQLen 8.94 # Average write queue length over time
175 system.physmem.readRowHits 331871 # Number of row buffer hits during reads
176 system.physmem.writeRowHits 191829 # Number of row buffer hits during writes
177 system.physmem.readRowHitRate 86.07 # Row buffer hit rate for reads
178 system.physmem.writeRowHitRate 65.32 # Row buffer hit rate for writes
179 system.physmem.avgGap 665083.17 # Average gap between requests
180 system.cpu.branchPred.lookups 205621718 # Number of BP lookups
181 system.cpu.branchPred.condPredicted 205621718 # Number of conditional branches predicted
182 system.cpu.branchPred.condIncorrect 9907083 # Number of conditional branches incorrect
183 system.cpu.branchPred.BTBLookups 117077740 # Number of BTB lookups
184 system.cpu.branchPred.BTBHits 114695478 # Number of BTB hits
185 system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
186 system.cpu.branchPred.BTBHitPct 97.965231 # BTB Hit Percentage
187 system.cpu.branchPred.usedRAS 25073647 # Number of times the RAS was used to get a target.
188 system.cpu.branchPred.RASInCorrect 1800250 # Number of incorrect RAS predictions.
189 system.cpu.workload.num_syscalls 551 # Number of system calls
190 system.cpu.numCycles 903825131 # number of cpu cycles simulated
191 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
192 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
193 system.cpu.fetch.icacheStallCycles 167418043 # Number of cycles fetch is stalled on an Icache miss
194 system.cpu.fetch.Insts 1132282338 # Number of instructions fetch has processed
195 system.cpu.fetch.Branches 205621718 # Number of branches that fetch encountered
196 system.cpu.fetch.predictedBranches 139769125 # Number of branches that fetch has predicted taken
197 system.cpu.fetch.Cycles 352430400 # Number of cycles fetch has run and was not squashing or blocked
198 system.cpu.fetch.SquashCycles 71153000 # Number of cycles fetch has spent squashing
199 system.cpu.fetch.BlockedCycles 297148174 # Number of cycles fetch has spent blocked
200 system.cpu.fetch.MiscStallCycles 48797 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
201 system.cpu.fetch.PendingTrapStallCycles 255592 # Number of stall cycles due to pending traps
202 system.cpu.fetch.IcacheWaitRetryStallCycles 33 # Number of stall cycles due to full MSHR
203 system.cpu.fetch.CacheLines 162064992 # Number of cache lines fetched
204 system.cpu.fetch.IcacheSquashes 2572532 # Number of outstanding Icache misses that were squashed
205 system.cpu.fetch.rateDist::samples 878293133 # Number of instructions fetched each cycle (Total)
206 system.cpu.fetch.rateDist::mean 2.398381 # Number of instructions fetched each cycle (Total)
207 system.cpu.fetch.rateDist::stdev 3.331165 # Number of instructions fetched each cycle (Total)
208 system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
209 system.cpu.fetch.rateDist::0 529920988 60.34% 60.34% # Number of instructions fetched each cycle (Total)
210 system.cpu.fetch.rateDist::1 23389932 2.66% 63.00% # Number of instructions fetched each cycle (Total)
211 system.cpu.fetch.rateDist::2 25306191 2.88% 65.88% # Number of instructions fetched each cycle (Total)
212 system.cpu.fetch.rateDist::3 27947555 3.18% 69.06% # Number of instructions fetched each cycle (Total)
213 system.cpu.fetch.rateDist::4 17765128 2.02% 71.08% # Number of instructions fetched each cycle (Total)
214 system.cpu.fetch.rateDist::5 22905202 2.61% 73.69% # Number of instructions fetched each cycle (Total)
215 system.cpu.fetch.rateDist::6 29375609 3.34% 77.04% # Number of instructions fetched each cycle (Total)
216 system.cpu.fetch.rateDist::7 26663527 3.04% 80.07% # Number of instructions fetched each cycle (Total)
217 system.cpu.fetch.rateDist::8 175019001 19.93% 100.00% # Number of instructions fetched each cycle (Total)
218 system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
219 system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
220 system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
221 system.cpu.fetch.rateDist::total 878293133 # Number of instructions fetched each cycle (Total)
222 system.cpu.fetch.branchRate 0.227502 # Number of branch fetches per cycle
223 system.cpu.fetch.rate 1.252767 # Number of inst fetches per cycle
224 system.cpu.decode.IdleCycles 222360951 # Number of cycles decode is idle
225 system.cpu.decode.BlockedCycles 252528998 # Number of cycles decode is blocked
226 system.cpu.decode.RunCycles 295744531 # Number of cycles decode is running
227 system.cpu.decode.UnblockCycles 46666559 # Number of cycles decode is unblocking
228 system.cpu.decode.SquashCycles 60992094 # Number of cycles decode is squashing
229 system.cpu.decode.DecodedInsts 2071948592 # Number of instructions handled by decode
230 system.cpu.rename.SquashCycles 60992094 # Number of cycles rename is squashing
231 system.cpu.rename.IdleCycles 255743691 # Number of cycles rename is idle
232 system.cpu.rename.BlockCycles 109858014 # Number of cycles rename is blocking
233 system.cpu.rename.serializeStallCycles 17204 # count of cycles rename stalled for serializing inst
234 system.cpu.rename.RunCycles 306968990 # Number of cycles rename is running
235 system.cpu.rename.UnblockCycles 144713140 # Number of cycles rename is unblocking
236 system.cpu.rename.RenamedInsts 2035757004 # Number of instructions processed by rename
237 system.cpu.rename.ROBFullEvents 14813 # Number of times rename has blocked due to ROB full
238 system.cpu.rename.IQFullEvents 25048489 # Number of times rename has blocked due to IQ full
239 system.cpu.rename.LSQFullEvents 104458594 # Number of times rename has blocked due to LSQ full
240 system.cpu.rename.FullRegisterEvents 180 # Number of times there has been no free registers
241 system.cpu.rename.RenamedOperands 2138803025 # Number of destination operands rename has renamed
242 system.cpu.rename.RenameLookups 5151932301 # Number of register rename lookups that rename has made
243 system.cpu.rename.int_rename_lookups 5151817228 # Number of integer rename lookups
244 system.cpu.rename.fp_rename_lookups 115073 # Number of floating rename lookups
245 system.cpu.rename.CommittedMaps 1614040854 # Number of HB maps that are committed
246 system.cpu.rename.UndoneMaps 524762171 # Number of HB maps that are undone due to squashing
247 system.cpu.rename.serializingInsts 1163 # count of serializing insts renamed
248 system.cpu.rename.tempSerializingInsts 1096 # count of temporary serializing insts renamed
249 system.cpu.rename.skidInsts 344343454 # count of insts added to the skid buffer
250 system.cpu.memDep0.insertedLoads 496005535 # Number of loads inserted to the mem dependence unit.
251 system.cpu.memDep0.insertedStores 194479256 # Number of stores inserted to the mem dependence unit.
252 system.cpu.memDep0.conflictingLoads 195803959 # Number of conflicting loads.
253 system.cpu.memDep0.conflictingStores 55147463 # Number of conflicting stores.
254 system.cpu.iq.iqInstsAdded 1975947809 # Number of instructions added to the IQ (excludes non-spec)
255 system.cpu.iq.iqNonSpecInstsAdded 16072 # Number of non-speculative instructions added to the IQ
256 system.cpu.iq.iqInstsIssued 1772430246 # Number of instructions issued
257 system.cpu.iq.iqSquashedInstsIssued 489293 # Number of squashed instructions issued
258 system.cpu.iq.iqSquashedInstsExamined 442088890 # Number of squashed instructions iterated over during squash; mainly for profiling
259 system.cpu.iq.iqSquashedOperandsExamined 735772933 # Number of squashed operands that are examined and possibly removed from graph
260 system.cpu.iq.iqSquashedNonSpecRemoved 15520 # Number of squashed non-spec instructions that were removed
261 system.cpu.iq.issued_per_cycle::samples 878293133 # Number of insts issued each cycle
262 system.cpu.iq.issued_per_cycle::mean 2.018040 # Number of insts issued each cycle
263 system.cpu.iq.issued_per_cycle::stdev 1.884895 # Number of insts issued each cycle
264 system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
265 system.cpu.iq.issued_per_cycle::0 263200988 29.97% 29.97% # Number of insts issued each cycle
266 system.cpu.iq.issued_per_cycle::1 149900664 17.07% 47.03% # Number of insts issued each cycle
267 system.cpu.iq.issued_per_cycle::2 137095286 15.61% 62.64% # Number of insts issued each cycle
268 system.cpu.iq.issued_per_cycle::3 132054982 15.04% 77.68% # Number of insts issued each cycle
269 system.cpu.iq.issued_per_cycle::4 91669420 10.44% 88.12% # Number of insts issued each cycle
270 system.cpu.iq.issued_per_cycle::5 56193413 6.40% 94.51% # Number of insts issued each cycle
271 system.cpu.iq.issued_per_cycle::6 34492530 3.93% 98.44% # Number of insts issued each cycle
272 system.cpu.iq.issued_per_cycle::7 11912661 1.36% 99.80% # Number of insts issued each cycle
273 system.cpu.iq.issued_per_cycle::8 1773189 0.20% 100.00% # Number of insts issued each cycle
274 system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
275 system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
276 system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
277 system.cpu.iq.issued_per_cycle::total 878293133 # Number of insts issued each cycle
278 system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
279 system.cpu.iq.fu_full::IntAlu 4998230 32.74% 32.74% # attempts to use FU when none available
280 system.cpu.iq.fu_full::IntMult 0 0.00% 32.74% # attempts to use FU when none available
281 system.cpu.iq.fu_full::IntDiv 0 0.00% 32.74% # attempts to use FU when none available
282 system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.74% # attempts to use FU when none available
283 system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.74% # attempts to use FU when none available
284 system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.74% # attempts to use FU when none available
285 system.cpu.iq.fu_full::FloatMult 0 0.00% 32.74% # attempts to use FU when none available
286 system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.74% # attempts to use FU when none available
287 system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.74% # attempts to use FU when none available
288 system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.74% # attempts to use FU when none available
289 system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.74% # attempts to use FU when none available
290 system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.74% # attempts to use FU when none available
291 system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.74% # attempts to use FU when none available
292 system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.74% # attempts to use FU when none available
293 system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.74% # attempts to use FU when none available
294 system.cpu.iq.fu_full::SimdMult 0 0.00% 32.74% # attempts to use FU when none available
295 system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.74% # attempts to use FU when none available
296 system.cpu.iq.fu_full::SimdShift 0 0.00% 32.74% # attempts to use FU when none available
297 system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.74% # attempts to use FU when none available
298 system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.74% # attempts to use FU when none available
299 system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.74% # attempts to use FU when none available
300 system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.74% # attempts to use FU when none available
301 system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.74% # attempts to use FU when none available
302 system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.74% # attempts to use FU when none available
303 system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.74% # attempts to use FU when none available
304 system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.74% # attempts to use FU when none available
305 system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.74% # attempts to use FU when none available
306 system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.74% # attempts to use FU when none available
307 system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.74% # attempts to use FU when none available
308 system.cpu.iq.fu_full::MemRead 7655755 50.14% 82.88% # attempts to use FU when none available
309 system.cpu.iq.fu_full::MemWrite 2613853 17.12% 100.00% # attempts to use FU when none available
310 system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
311 system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
312 system.cpu.iq.FU_type_0::No_OpClass 2627910 0.15% 0.15% # Type of FU issued
313 system.cpu.iq.FU_type_0::IntAlu 1165981895 65.78% 65.93% # Type of FU issued
314 system.cpu.iq.FU_type_0::IntMult 352516 0.02% 65.95% # Type of FU issued
315 system.cpu.iq.FU_type_0::IntDiv 3880818 0.22% 66.17% # Type of FU issued
316 system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 66.17% # Type of FU issued
317 system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.17% # Type of FU issued
318 system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.17% # Type of FU issued
319 system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.17% # Type of FU issued
320 system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.17% # Type of FU issued
321 system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.17% # Type of FU issued
322 system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.17% # Type of FU issued
323 system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.17% # Type of FU issued
324 system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.17% # Type of FU issued
325 system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.17% # Type of FU issued
326 system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.17% # Type of FU issued
327 system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.17% # Type of FU issued
328 system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.17% # Type of FU issued
329 system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.17% # Type of FU issued
330 system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.17% # Type of FU issued
331 system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.17% # Type of FU issued
332 system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.17% # Type of FU issued
333 system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.17% # Type of FU issued
334 system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.17% # Type of FU issued
335 system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.17% # Type of FU issued
336 system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.17% # Type of FU issued
337 system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.17% # Type of FU issued
338 system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.17% # Type of FU issued
339 system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.17% # Type of FU issued
340 system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.17% # Type of FU issued
341 system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.17% # Type of FU issued
342 system.cpu.iq.FU_type_0::MemRead 429341212 24.22% 90.39% # Type of FU issued
343 system.cpu.iq.FU_type_0::MemWrite 170245895 9.61% 100.00% # Type of FU issued
344 system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
345 system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
346 system.cpu.iq.FU_type_0::total 1772430246 # Type of FU issued
347 system.cpu.iq.rate 1.961032 # Inst issue rate
348 system.cpu.iq.fu_busy_cnt 15267838 # FU busy when requested
349 system.cpu.iq.fu_busy_rate 0.008614 # FU busy rate (busy events/executed inst)
350 system.cpu.iq.int_inst_queue_reads 4438895750 # Number of integer instruction queue reads
351 system.cpu.iq.int_inst_queue_writes 2418277528 # Number of integer instruction queue writes
352 system.cpu.iq.int_inst_queue_wakeup_accesses 1745063548 # Number of integer instruction queue wakeup accesses
353 system.cpu.iq.fp_inst_queue_reads 15006 # Number of floating instruction queue reads
354 system.cpu.iq.fp_inst_queue_writes 33162 # Number of floating instruction queue writes
355 system.cpu.iq.fp_inst_queue_wakeup_accesses 3630 # Number of floating instruction queue wakeup accesses
356 system.cpu.iq.int_alu_accesses 1785062995 # Number of integer alu accesses
357 system.cpu.iq.fp_alu_accesses 7179 # Number of floating point alu accesses
358 system.cpu.iew.lsq.thread0.forwLoads 172239839 # Number of loads that had data forwarded from stores
359 system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
360 system.cpu.iew.lsq.thread0.squashedLoads 111903378 # Number of loads squashed
361 system.cpu.iew.lsq.thread0.ignoredResponses 383433 # Number of memory responses ignored because the instruction is squashed
362 system.cpu.iew.lsq.thread0.memOrderViolation 329474 # Number of memory ordering violations
363 system.cpu.iew.lsq.thread0.squashedStores 45320259 # Number of stores squashed
364 system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
365 system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
366 system.cpu.iew.lsq.thread0.rescheduledLoads 14682 # Number of loads that were rescheduled
367 system.cpu.iew.lsq.thread0.cacheBlocked 568 # Number of times an access to memory failed due to the cache being blocked
368 system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
369 system.cpu.iew.iewSquashCycles 60992094 # Number of cycles IEW is squashing
370 system.cpu.iew.iewBlockCycles 64075051 # Number of cycles IEW is blocking
371 system.cpu.iew.iewUnblockCycles 7111223 # Number of cycles IEW is unblocking
372 system.cpu.iew.iewDispatchedInsts 1975963881 # Number of instructions dispatched to IQ
373 system.cpu.iew.iewDispSquashedInsts 801543 # Number of squashed instructions skipped by dispatch
374 system.cpu.iew.iewDispLoadInsts 496005535 # Number of dispatched load instructions
375 system.cpu.iew.iewDispStoreInsts 194480445 # Number of dispatched store instructions
376 system.cpu.iew.iewDispNonSpecInsts 3509 # Number of dispatched non-speculative instructions
377 system.cpu.iew.iewIQFullEvents 4460880 # Number of times the IQ has become full, causing a stall
378 system.cpu.iew.iewLSQFullEvents 83569 # Number of times the LSQ has become full, causing a stall
379 system.cpu.iew.memOrderViolationEvents 329474 # Number of memory order violations
380 system.cpu.iew.predictedTakenIncorrect 5903386 # Number of branches that were predicted taken incorrectly
381 system.cpu.iew.predictedNotTakenIncorrect 4417104 # Number of branches that were predicted not taken incorrectly
382 system.cpu.iew.branchMispredicts 10320490 # Number of branch mispredicts detected at execute
383 system.cpu.iew.iewExecutedInsts 1753197001 # Number of executed instructions
384 system.cpu.iew.iewExecLoadInsts 424204757 # Number of load instructions executed
385 system.cpu.iew.iewExecSquashedInsts 19233245 # Number of squashed instructions skipped in execute
386 system.cpu.iew.exec_swp 0 # number of swp insts executed
387 system.cpu.iew.exec_nop 0 # number of nop insts executed
388 system.cpu.iew.exec_refs 591004689 # number of memory reference insts executed
389 system.cpu.iew.exec_branches 167488871 # Number of branches executed
390 system.cpu.iew.exec_stores 166799932 # Number of stores executed
391 system.cpu.iew.exec_rate 1.939752 # Inst execution rate
392 system.cpu.iew.wb_sent 1749947599 # cumulative count of insts sent to commit
393 system.cpu.iew.wb_count 1745067178 # cumulative count of insts written-back
394 system.cpu.iew.wb_producers 1326505641 # num instructions producing a value
395 system.cpu.iew.wb_consumers 1948512890 # num instructions consuming a value
396 system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
397 system.cpu.iew.wb_rate 1.930758 # insts written-back per cycle
398 system.cpu.iew.wb_fanout 0.680778 # average fanout of values written-back
399 system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
400 system.cpu.commit.commitSquashedInsts 447002783 # The number of squashed insts skipped by commit
401 system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards
402 system.cpu.commit.branchMispredicts 9936450 # The number of times a branch was mispredicted
403 system.cpu.commit.committed_per_cycle::samples 817301039 # Number of insts commited each cycle
404 system.cpu.commit.committed_per_cycle::mean 1.870778 # Number of insts commited each cycle
405 system.cpu.commit.committed_per_cycle::stdev 2.444599 # Number of insts commited each cycle
406 system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
407 system.cpu.commit.committed_per_cycle::0 326881530 40.00% 40.00% # Number of insts commited each cycle
408 system.cpu.commit.committed_per_cycle::1 191845418 23.47% 63.47% # Number of insts commited each cycle
409 system.cpu.commit.committed_per_cycle::2 62847977 7.69% 71.16% # Number of insts commited each cycle
410 system.cpu.commit.committed_per_cycle::3 92272413 11.29% 82.45% # Number of insts commited each cycle
411 system.cpu.commit.committed_per_cycle::4 25036529 3.06% 85.51% # Number of insts commited each cycle
412 system.cpu.commit.committed_per_cycle::5 27653799 3.38% 88.89% # Number of insts commited each cycle
413 system.cpu.commit.committed_per_cycle::6 9274477 1.13% 90.03% # Number of insts commited each cycle
414 system.cpu.commit.committed_per_cycle::7 11343051 1.39% 91.42% # Number of insts commited each cycle
415 system.cpu.commit.committed_per_cycle::8 70145845 8.58% 100.00% # Number of insts commited each cycle
416 system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
417 system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
418 system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
419 system.cpu.commit.committed_per_cycle::total 817301039 # Number of insts commited each cycle
420 system.cpu.commit.committedInsts 826877109 # Number of instructions committed
421 system.cpu.commit.committedOps 1528988701 # Number of ops (including micro ops) committed
422 system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
423 system.cpu.commit.refs 533262343 # Number of memory references committed
424 system.cpu.commit.loads 384102157 # Number of loads committed
425 system.cpu.commit.membars 0 # Number of memory barriers committed
426 system.cpu.commit.branches 149758583 # Number of branches committed
427 system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
428 system.cpu.commit.int_insts 1528317561 # Number of committed integer instructions.
429 system.cpu.commit.function_calls 17673145 # Number of function calls committed.
430 system.cpu.commit.bw_lim_events 70145845 # number cycles where commit BW limit reached
431 system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
432 system.cpu.rob.rob_reads 2723146678 # The number of ROB reads
433 system.cpu.rob.rob_writes 4013137574 # The number of ROB writes
434 system.cpu.timesIdled 3358951 # Number of times that the entire CPU went into an idle state and unscheduled itself
435 system.cpu.idleCycles 25531998 # Total number of cycles that the CPU has spent unscheduled due to idling
436 system.cpu.committedInsts 826877109 # Number of Instructions Simulated
437 system.cpu.committedOps 1528988701 # Number of Ops (including micro ops) Simulated
438 system.cpu.committedInsts_total 826877109 # Number of Instructions Simulated
439 system.cpu.cpi 1.093059 # CPI: Cycles Per Instruction
440 system.cpu.cpi_total 1.093059 # CPI: Total CPI of All Threads
441 system.cpu.ipc 0.914864 # IPC: Instructions Per Cycle
442 system.cpu.ipc_total 0.914864 # IPC: Total IPC of All Threads
443 system.cpu.int_regfile_reads 3313860690 # number of integer regfile reads
444 system.cpu.int_regfile_writes 1826087017 # number of integer regfile writes
445 system.cpu.fp_regfile_reads 3611 # number of floating regfile reads
446 system.cpu.fp_regfile_writes 20 # number of floating regfile writes
447 system.cpu.misc_regfile_reads 964797382 # number of misc regfile reads
448 system.cpu.misc_regfile_writes 1 # number of misc regfile writes
449 system.cpu.icache.replacements 5491 # number of replacements
450 system.cpu.icache.tagsinuse 1036.603099 # Cycle average of tags in use
451 system.cpu.icache.total_refs 161916606 # Total number of references to valid blocks.
452 system.cpu.icache.sampled_refs 7071 # Sample count of references to valid blocks.
453 system.cpu.icache.avg_refs 22898.685617 # Average number of references to valid blocks.
454 system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
455 system.cpu.icache.occ_blocks::cpu.inst 1036.603099 # Average occupied blocks per requestor
456 system.cpu.icache.occ_percent::cpu.inst 0.506154 # Average percentage of cache occupancy
457 system.cpu.icache.occ_percent::total 0.506154 # Average percentage of cache occupancy
458 system.cpu.icache.ReadReq_hits::cpu.inst 161918575 # number of ReadReq hits
459 system.cpu.icache.ReadReq_hits::total 161918575 # number of ReadReq hits
460 system.cpu.icache.demand_hits::cpu.inst 161918575 # number of demand (read+write) hits
461 system.cpu.icache.demand_hits::total 161918575 # number of demand (read+write) hits
462 system.cpu.icache.overall_hits::cpu.inst 161918575 # number of overall hits
463 system.cpu.icache.overall_hits::total 161918575 # number of overall hits
464 system.cpu.icache.ReadReq_misses::cpu.inst 146417 # number of ReadReq misses
465 system.cpu.icache.ReadReq_misses::total 146417 # number of ReadReq misses
466 system.cpu.icache.demand_misses::cpu.inst 146417 # number of demand (read+write) misses
467 system.cpu.icache.demand_misses::total 146417 # number of demand (read+write) misses
468 system.cpu.icache.overall_misses::cpu.inst 146417 # number of overall misses
469 system.cpu.icache.overall_misses::total 146417 # number of overall misses
470 system.cpu.icache.ReadReq_miss_latency::cpu.inst 875142000 # number of ReadReq miss cycles
471 system.cpu.icache.ReadReq_miss_latency::total 875142000 # number of ReadReq miss cycles
472 system.cpu.icache.demand_miss_latency::cpu.inst 875142000 # number of demand (read+write) miss cycles
473 system.cpu.icache.demand_miss_latency::total 875142000 # number of demand (read+write) miss cycles
474 system.cpu.icache.overall_miss_latency::cpu.inst 875142000 # number of overall miss cycles
475 system.cpu.icache.overall_miss_latency::total 875142000 # number of overall miss cycles
476 system.cpu.icache.ReadReq_accesses::cpu.inst 162064992 # number of ReadReq accesses(hits+misses)
477 system.cpu.icache.ReadReq_accesses::total 162064992 # number of ReadReq accesses(hits+misses)
478 system.cpu.icache.demand_accesses::cpu.inst 162064992 # number of demand (read+write) accesses
479 system.cpu.icache.demand_accesses::total 162064992 # number of demand (read+write) accesses
480 system.cpu.icache.overall_accesses::cpu.inst 162064992 # number of overall (read+write) accesses
481 system.cpu.icache.overall_accesses::total 162064992 # number of overall (read+write) accesses
482 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000903 # miss rate for ReadReq accesses
483 system.cpu.icache.ReadReq_miss_rate::total 0.000903 # miss rate for ReadReq accesses
484 system.cpu.icache.demand_miss_rate::cpu.inst 0.000903 # miss rate for demand accesses
485 system.cpu.icache.demand_miss_rate::total 0.000903 # miss rate for demand accesses
486 system.cpu.icache.overall_miss_rate::cpu.inst 0.000903 # miss rate for overall accesses
487 system.cpu.icache.overall_miss_rate::total 0.000903 # miss rate for overall accesses
488 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 5977.051845 # average ReadReq miss latency
489 system.cpu.icache.ReadReq_avg_miss_latency::total 5977.051845 # average ReadReq miss latency
490 system.cpu.icache.demand_avg_miss_latency::cpu.inst 5977.051845 # average overall miss latency
491 system.cpu.icache.demand_avg_miss_latency::total 5977.051845 # average overall miss latency
492 system.cpu.icache.overall_avg_miss_latency::cpu.inst 5977.051845 # average overall miss latency
493 system.cpu.icache.overall_avg_miss_latency::total 5977.051845 # average overall miss latency
494 system.cpu.icache.blocked_cycles::no_mshrs 1375 # number of cycles access was blocked
495 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
496 system.cpu.icache.blocked::no_mshrs 6 # number of cycles access was blocked
497 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
498 system.cpu.icache.avg_blocked_cycles::no_mshrs 229.166667 # average number of cycles each access was blocked
499 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
500 system.cpu.icache.fast_writes 0 # number of fast writes performed
501 system.cpu.icache.cache_copies 0 # number of cache copies performed
502 system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1845 # number of ReadReq MSHR hits
503 system.cpu.icache.ReadReq_mshr_hits::total 1845 # number of ReadReq MSHR hits
504 system.cpu.icache.demand_mshr_hits::cpu.inst 1845 # number of demand (read+write) MSHR hits
505 system.cpu.icache.demand_mshr_hits::total 1845 # number of demand (read+write) MSHR hits
506 system.cpu.icache.overall_mshr_hits::cpu.inst 1845 # number of overall MSHR hits
507 system.cpu.icache.overall_mshr_hits::total 1845 # number of overall MSHR hits
508 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 144572 # number of ReadReq MSHR misses
509 system.cpu.icache.ReadReq_mshr_misses::total 144572 # number of ReadReq MSHR misses
510 system.cpu.icache.demand_mshr_misses::cpu.inst 144572 # number of demand (read+write) MSHR misses
511 system.cpu.icache.demand_mshr_misses::total 144572 # number of demand (read+write) MSHR misses
512 system.cpu.icache.overall_mshr_misses::cpu.inst 144572 # number of overall MSHR misses
513 system.cpu.icache.overall_mshr_misses::total 144572 # number of overall MSHR misses
514 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 521583500 # number of ReadReq MSHR miss cycles
515 system.cpu.icache.ReadReq_mshr_miss_latency::total 521583500 # number of ReadReq MSHR miss cycles
516 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 521583500 # number of demand (read+write) MSHR miss cycles
517 system.cpu.icache.demand_mshr_miss_latency::total 521583500 # number of demand (read+write) MSHR miss cycles
518 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 521583500 # number of overall MSHR miss cycles
519 system.cpu.icache.overall_mshr_miss_latency::total 521583500 # number of overall MSHR miss cycles
520 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000892 # mshr miss rate for ReadReq accesses
521 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000892 # mshr miss rate for ReadReq accesses
522 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000892 # mshr miss rate for demand accesses
523 system.cpu.icache.demand_mshr_miss_rate::total 0.000892 # mshr miss rate for demand accesses
524 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000892 # mshr miss rate for overall accesses
525 system.cpu.icache.overall_mshr_miss_rate::total 0.000892 # mshr miss rate for overall accesses
526 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 3607.776748 # average ReadReq mshr miss latency
527 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 3607.776748 # average ReadReq mshr miss latency
528 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 3607.776748 # average overall mshr miss latency
529 system.cpu.icache.demand_avg_mshr_miss_latency::total 3607.776748 # average overall mshr miss latency
530 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 3607.776748 # average overall mshr miss latency
531 system.cpu.icache.overall_avg_mshr_miss_latency::total 3607.776748 # average overall mshr miss latency
532 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
533 system.cpu.l2cache.replacements 353019 # number of replacements
534 system.cpu.l2cache.tagsinuse 29665.542211 # Cycle average of tags in use
535 system.cpu.l2cache.total_refs 3698954 # Total number of references to valid blocks.
536 system.cpu.l2cache.sampled_refs 385379 # Sample count of references to valid blocks.
537 system.cpu.l2cache.avg_refs 9.598224 # Average number of references to valid blocks.
538 system.cpu.l2cache.warmup_cycle 196543776500 # Cycle when the warmup percentage was hit.
539 system.cpu.l2cache.occ_blocks::writebacks 21121.895278 # Average occupied blocks per requestor
540 system.cpu.l2cache.occ_blocks::cpu.inst 226.041869 # Average occupied blocks per requestor
541 system.cpu.l2cache.occ_blocks::cpu.data 8317.605064 # Average occupied blocks per requestor
542 system.cpu.l2cache.occ_percent::writebacks 0.644589 # Average percentage of cache occupancy
543 system.cpu.l2cache.occ_percent::cpu.inst 0.006898 # Average percentage of cache occupancy
544 system.cpu.l2cache.occ_percent::cpu.data 0.253833 # Average percentage of cache occupancy
545 system.cpu.l2cache.occ_percent::total 0.905321 # Average percentage of cache occupancy
546 system.cpu.l2cache.ReadReq_hits::cpu.inst 3851 # number of ReadReq hits
547 system.cpu.l2cache.ReadReq_hits::cpu.data 1587691 # number of ReadReq hits
548 system.cpu.l2cache.ReadReq_hits::total 1591542 # number of ReadReq hits
549 system.cpu.l2cache.Writeback_hits::writebacks 2331818 # number of Writeback hits
550 system.cpu.l2cache.Writeback_hits::total 2331818 # number of Writeback hits
551 system.cpu.l2cache.UpgradeReq_hits::cpu.data 1456 # number of UpgradeReq hits
552 system.cpu.l2cache.UpgradeReq_hits::total 1456 # number of UpgradeReq hits
553 system.cpu.l2cache.ReadExReq_hits::cpu.data 565593 # number of ReadExReq hits
554 system.cpu.l2cache.ReadExReq_hits::total 565593 # number of ReadExReq hits
555 system.cpu.l2cache.demand_hits::cpu.inst 3851 # number of demand (read+write) hits
556 system.cpu.l2cache.demand_hits::cpu.data 2153284 # number of demand (read+write) hits
557 system.cpu.l2cache.demand_hits::total 2157135 # number of demand (read+write) hits
558 system.cpu.l2cache.overall_hits::cpu.inst 3851 # number of overall hits
559 system.cpu.l2cache.overall_hits::cpu.data 2153284 # number of overall hits
560 system.cpu.l2cache.overall_hits::total 2157135 # number of overall hits
561 system.cpu.l2cache.ReadReq_misses::cpu.inst 3170 # number of ReadReq misses
562 system.cpu.l2cache.ReadReq_misses::cpu.data 175625 # number of ReadReq misses
563 system.cpu.l2cache.ReadReq_misses::total 178795 # number of ReadReq misses
564 system.cpu.l2cache.UpgradeReq_misses::cpu.data 135999 # number of UpgradeReq misses
565 system.cpu.l2cache.UpgradeReq_misses::total 135999 # number of UpgradeReq misses
566 system.cpu.l2cache.ReadExReq_misses::cpu.data 206937 # number of ReadExReq misses
567 system.cpu.l2cache.ReadExReq_misses::total 206937 # number of ReadExReq misses
568 system.cpu.l2cache.demand_misses::cpu.inst 3170 # number of demand (read+write) misses
569 system.cpu.l2cache.demand_misses::cpu.data 382562 # number of demand (read+write) misses
570 system.cpu.l2cache.demand_misses::total 385732 # number of demand (read+write) misses
571 system.cpu.l2cache.overall_misses::cpu.inst 3170 # number of overall misses
572 system.cpu.l2cache.overall_misses::cpu.data 382562 # number of overall misses
573 system.cpu.l2cache.overall_misses::total 385732 # number of overall misses
574 system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 197656000 # number of ReadReq miss cycles
575 system.cpu.l2cache.ReadReq_miss_latency::cpu.data 10096367454 # number of ReadReq miss cycles
576 system.cpu.l2cache.ReadReq_miss_latency::total 10294023454 # number of ReadReq miss cycles
577 system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 6513500 # number of UpgradeReq miss cycles
578 system.cpu.l2cache.UpgradeReq_miss_latency::total 6513500 # number of UpgradeReq miss cycles
579 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10430438500 # number of ReadExReq miss cycles
580 system.cpu.l2cache.ReadExReq_miss_latency::total 10430438500 # number of ReadExReq miss cycles
581 system.cpu.l2cache.demand_miss_latency::cpu.inst 197656000 # number of demand (read+write) miss cycles
582 system.cpu.l2cache.demand_miss_latency::cpu.data 20526805954 # number of demand (read+write) miss cycles
583 system.cpu.l2cache.demand_miss_latency::total 20724461954 # number of demand (read+write) miss cycles
584 system.cpu.l2cache.overall_miss_latency::cpu.inst 197656000 # number of overall miss cycles
585 system.cpu.l2cache.overall_miss_latency::cpu.data 20526805954 # number of overall miss cycles
586 system.cpu.l2cache.overall_miss_latency::total 20724461954 # number of overall miss cycles
587 system.cpu.l2cache.ReadReq_accesses::cpu.inst 7021 # number of ReadReq accesses(hits+misses)
588 system.cpu.l2cache.ReadReq_accesses::cpu.data 1763316 # number of ReadReq accesses(hits+misses)
589 system.cpu.l2cache.ReadReq_accesses::total 1770337 # number of ReadReq accesses(hits+misses)
590 system.cpu.l2cache.Writeback_accesses::writebacks 2331818 # number of Writeback accesses(hits+misses)
591 system.cpu.l2cache.Writeback_accesses::total 2331818 # number of Writeback accesses(hits+misses)
592 system.cpu.l2cache.UpgradeReq_accesses::cpu.data 137455 # number of UpgradeReq accesses(hits+misses)
593 system.cpu.l2cache.UpgradeReq_accesses::total 137455 # number of UpgradeReq accesses(hits+misses)
594 system.cpu.l2cache.ReadExReq_accesses::cpu.data 772530 # number of ReadExReq accesses(hits+misses)
595 system.cpu.l2cache.ReadExReq_accesses::total 772530 # number of ReadExReq accesses(hits+misses)
596 system.cpu.l2cache.demand_accesses::cpu.inst 7021 # number of demand (read+write) accesses
597 system.cpu.l2cache.demand_accesses::cpu.data 2535846 # number of demand (read+write) accesses
598 system.cpu.l2cache.demand_accesses::total 2542867 # number of demand (read+write) accesses
599 system.cpu.l2cache.overall_accesses::cpu.inst 7021 # number of overall (read+write) accesses
600 system.cpu.l2cache.overall_accesses::cpu.data 2535846 # number of overall (read+write) accesses
601 system.cpu.l2cache.overall_accesses::total 2542867 # number of overall (read+write) accesses
602 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.451503 # miss rate for ReadReq accesses
603 system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.099599 # miss rate for ReadReq accesses
604 system.cpu.l2cache.ReadReq_miss_rate::total 0.100995 # miss rate for ReadReq accesses
605 system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.989407 # miss rate for UpgradeReq accesses
606 system.cpu.l2cache.UpgradeReq_miss_rate::total 0.989407 # miss rate for UpgradeReq accesses
607 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.267869 # miss rate for ReadExReq accesses
608 system.cpu.l2cache.ReadExReq_miss_rate::total 0.267869 # miss rate for ReadExReq accesses
609 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.451503 # miss rate for demand accesses
610 system.cpu.l2cache.demand_miss_rate::cpu.data 0.150862 # miss rate for demand accesses
611 system.cpu.l2cache.demand_miss_rate::total 0.151692 # miss rate for demand accesses
612 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.451503 # miss rate for overall accesses
613 system.cpu.l2cache.overall_miss_rate::cpu.data 0.150862 # miss rate for overall accesses
614 system.cpu.l2cache.overall_miss_rate::total 0.151692 # miss rate for overall accesses
615 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 62352.050473 # average ReadReq miss latency
616 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 57488.213261 # average ReadReq miss latency
617 system.cpu.l2cache.ReadReq_avg_miss_latency::total 57574.448133 # average ReadReq miss latency
618 system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 47.893735 # average UpgradeReq miss latency
619 system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 47.893735 # average UpgradeReq miss latency
620 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50403.932115 # average ReadExReq miss latency
621 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50403.932115 # average ReadExReq miss latency
622 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 62352.050473 # average overall miss latency
623 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 53656.154961 # average overall miss latency
624 system.cpu.l2cache.demand_avg_miss_latency::total 53727.619057 # average overall miss latency
625 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 62352.050473 # average overall miss latency
626 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 53656.154961 # average overall miss latency
627 system.cpu.l2cache.overall_avg_miss_latency::total 53727.619057 # average overall miss latency
628 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
629 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
630 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
631 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
632 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
633 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
634 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
635 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
636 system.cpu.l2cache.writebacks::writebacks 293661 # number of writebacks
637 system.cpu.l2cache.writebacks::total 293661 # number of writebacks
638 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3170 # number of ReadReq MSHR misses
639 system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 175625 # number of ReadReq MSHR misses
640 system.cpu.l2cache.ReadReq_mshr_misses::total 178795 # number of ReadReq MSHR misses
641 system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 135999 # number of UpgradeReq MSHR misses
642 system.cpu.l2cache.UpgradeReq_mshr_misses::total 135999 # number of UpgradeReq MSHR misses
643 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206937 # number of ReadExReq MSHR misses
644 system.cpu.l2cache.ReadExReq_mshr_misses::total 206937 # number of ReadExReq MSHR misses
645 system.cpu.l2cache.demand_mshr_misses::cpu.inst 3170 # number of demand (read+write) MSHR misses
646 system.cpu.l2cache.demand_mshr_misses::cpu.data 382562 # number of demand (read+write) MSHR misses
647 system.cpu.l2cache.demand_mshr_misses::total 385732 # number of demand (read+write) MSHR misses
648 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3170 # number of overall MSHR misses
649 system.cpu.l2cache.overall_mshr_misses::cpu.data 382562 # number of overall MSHR misses
650 system.cpu.l2cache.overall_mshr_misses::total 385732 # number of overall MSHR misses
651 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 158250747 # number of ReadReq MSHR miss cycles
652 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 7922707780 # number of ReadReq MSHR miss cycles
653 system.cpu.l2cache.ReadReq_mshr_miss_latency::total 8080958527 # number of ReadReq MSHR miss cycles
654 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1364143324 # number of UpgradeReq MSHR miss cycles
655 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1364143324 # number of UpgradeReq MSHR miss cycles
656 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7842004636 # number of ReadExReq MSHR miss cycles
657 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7842004636 # number of ReadExReq MSHR miss cycles
658 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 158250747 # number of demand (read+write) MSHR miss cycles
659 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15764712416 # number of demand (read+write) MSHR miss cycles
660 system.cpu.l2cache.demand_mshr_miss_latency::total 15922963163 # number of demand (read+write) MSHR miss cycles
661 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 158250747 # number of overall MSHR miss cycles
662 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15764712416 # number of overall MSHR miss cycles
663 system.cpu.l2cache.overall_mshr_miss_latency::total 15922963163 # number of overall MSHR miss cycles
664 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.451503 # mshr miss rate for ReadReq accesses
665 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.099599 # mshr miss rate for ReadReq accesses
666 system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.100995 # mshr miss rate for ReadReq accesses
667 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.989407 # mshr miss rate for UpgradeReq accesses
668 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.989407 # mshr miss rate for UpgradeReq accesses
669 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.267869 # mshr miss rate for ReadExReq accesses
670 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.267869 # mshr miss rate for ReadExReq accesses
671 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.451503 # mshr miss rate for demand accesses
672 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150862 # mshr miss rate for demand accesses
673 system.cpu.l2cache.demand_mshr_miss_rate::total 0.151692 # mshr miss rate for demand accesses
674 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.451503 # mshr miss rate for overall accesses
675 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150862 # mshr miss rate for overall accesses
676 system.cpu.l2cache.overall_mshr_miss_rate::total 0.151692 # mshr miss rate for overall accesses
677 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 49921.371293 # average ReadReq mshr miss latency
678 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 45111.503374 # average ReadReq mshr miss latency
679 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 45196.781381 # average ReadReq mshr miss latency
680 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10030.539372 # average UpgradeReq mshr miss latency
681 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10030.539372 # average UpgradeReq mshr miss latency
682 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 37895.613815 # average ReadExReq mshr miss latency
683 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 37895.613815 # average ReadExReq mshr miss latency
684 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49921.371293 # average overall mshr miss latency
685 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 41208.254913 # average overall mshr miss latency
686 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 41279.860533 # average overall mshr miss latency
687 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49921.371293 # average overall mshr miss latency
688 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 41208.254913 # average overall mshr miss latency
689 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41279.860533 # average overall mshr miss latency
690 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
691 system.cpu.dcache.replacements 2531750 # number of replacements
692 system.cpu.dcache.tagsinuse 4088.641557 # Cycle average of tags in use
693 system.cpu.dcache.total_refs 396440107 # Total number of references to valid blocks.
694 system.cpu.dcache.sampled_refs 2535846 # Sample count of references to valid blocks.
695 system.cpu.dcache.avg_refs 156.334457 # Average number of references to valid blocks.
696 system.cpu.dcache.warmup_cycle 1679431000 # Cycle when the warmup percentage was hit.
697 system.cpu.dcache.occ_blocks::cpu.data 4088.641557 # Average occupied blocks per requestor
698 system.cpu.dcache.occ_percent::cpu.data 0.998204 # Average percentage of cache occupancy
699 system.cpu.dcache.occ_percent::total 0.998204 # Average percentage of cache occupancy
700 system.cpu.dcache.ReadReq_hits::cpu.data 247707841 # number of ReadReq hits
701 system.cpu.dcache.ReadReq_hits::total 247707841 # number of ReadReq hits
702 system.cpu.dcache.WriteReq_hits::cpu.data 148233543 # number of WriteReq hits
703 system.cpu.dcache.WriteReq_hits::total 148233543 # number of WriteReq hits
704 system.cpu.dcache.demand_hits::cpu.data 395941384 # number of demand (read+write) hits
705 system.cpu.dcache.demand_hits::total 395941384 # number of demand (read+write) hits
706 system.cpu.dcache.overall_hits::cpu.data 395941384 # number of overall hits
707 system.cpu.dcache.overall_hits::total 395941384 # number of overall hits
708 system.cpu.dcache.ReadReq_misses::cpu.data 2871315 # number of ReadReq misses
709 system.cpu.dcache.ReadReq_misses::total 2871315 # number of ReadReq misses
710 system.cpu.dcache.WriteReq_misses::cpu.data 926659 # number of WriteReq misses
711 system.cpu.dcache.WriteReq_misses::total 926659 # number of WriteReq misses
712 system.cpu.dcache.demand_misses::cpu.data 3797974 # number of demand (read+write) misses
713 system.cpu.dcache.demand_misses::total 3797974 # number of demand (read+write) misses
714 system.cpu.dcache.overall_misses::cpu.data 3797974 # number of overall misses
715 system.cpu.dcache.overall_misses::total 3797974 # number of overall misses
716 system.cpu.dcache.ReadReq_miss_latency::cpu.data 51373394500 # number of ReadReq miss cycles
717 system.cpu.dcache.ReadReq_miss_latency::total 51373394500 # number of ReadReq miss cycles
718 system.cpu.dcache.WriteReq_miss_latency::cpu.data 21994238500 # number of WriteReq miss cycles
719 system.cpu.dcache.WriteReq_miss_latency::total 21994238500 # number of WriteReq miss cycles
720 system.cpu.dcache.demand_miss_latency::cpu.data 73367633000 # number of demand (read+write) miss cycles
721 system.cpu.dcache.demand_miss_latency::total 73367633000 # number of demand (read+write) miss cycles
722 system.cpu.dcache.overall_miss_latency::cpu.data 73367633000 # number of overall miss cycles
723 system.cpu.dcache.overall_miss_latency::total 73367633000 # number of overall miss cycles
724 system.cpu.dcache.ReadReq_accesses::cpu.data 250579156 # number of ReadReq accesses(hits+misses)
725 system.cpu.dcache.ReadReq_accesses::total 250579156 # number of ReadReq accesses(hits+misses)
726 system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses)
727 system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses)
728 system.cpu.dcache.demand_accesses::cpu.data 399739358 # number of demand (read+write) accesses
729 system.cpu.dcache.demand_accesses::total 399739358 # number of demand (read+write) accesses
730 system.cpu.dcache.overall_accesses::cpu.data 399739358 # number of overall (read+write) accesses
731 system.cpu.dcache.overall_accesses::total 399739358 # number of overall (read+write) accesses
732 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011459 # miss rate for ReadReq accesses
733 system.cpu.dcache.ReadReq_miss_rate::total 0.011459 # miss rate for ReadReq accesses
734 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006213 # miss rate for WriteReq accesses
735 system.cpu.dcache.WriteReq_miss_rate::total 0.006213 # miss rate for WriteReq accesses
736 system.cpu.dcache.demand_miss_rate::cpu.data 0.009501 # miss rate for demand accesses
737 system.cpu.dcache.demand_miss_rate::total 0.009501 # miss rate for demand accesses
738 system.cpu.dcache.overall_miss_rate::cpu.data 0.009501 # miss rate for overall accesses
739 system.cpu.dcache.overall_miss_rate::total 0.009501 # miss rate for overall accesses
740 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17891.939582 # average ReadReq miss latency
741 system.cpu.dcache.ReadReq_avg_miss_latency::total 17891.939582 # average ReadReq miss latency
742 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23734.986117 # average WriteReq miss latency
743 system.cpu.dcache.WriteReq_avg_miss_latency::total 23734.986117 # average WriteReq miss latency
744 system.cpu.dcache.demand_avg_miss_latency::cpu.data 19317.571158 # average overall miss latency
745 system.cpu.dcache.demand_avg_miss_latency::total 19317.571158 # average overall miss latency
746 system.cpu.dcache.overall_avg_miss_latency::cpu.data 19317.571158 # average overall miss latency
747 system.cpu.dcache.overall_avg_miss_latency::total 19317.571158 # average overall miss latency
748 system.cpu.dcache.blocked_cycles::no_mshrs 6008 # number of cycles access was blocked
749 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
750 system.cpu.dcache.blocked::no_mshrs 680 # number of cycles access was blocked
751 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
752 system.cpu.dcache.avg_blocked_cycles::no_mshrs 8.835294 # average number of cycles each access was blocked
753 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
754 system.cpu.dcache.fast_writes 0 # number of fast writes performed
755 system.cpu.dcache.cache_copies 0 # number of cache copies performed
756 system.cpu.dcache.writebacks::writebacks 2331818 # number of writebacks
757 system.cpu.dcache.writebacks::total 2331818 # number of writebacks
758 system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1107712 # number of ReadReq MSHR hits
759 system.cpu.dcache.ReadReq_mshr_hits::total 1107712 # number of ReadReq MSHR hits
760 system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16962 # number of WriteReq MSHR hits
761 system.cpu.dcache.WriteReq_mshr_hits::total 16962 # number of WriteReq MSHR hits
762 system.cpu.dcache.demand_mshr_hits::cpu.data 1124674 # number of demand (read+write) MSHR hits
763 system.cpu.dcache.demand_mshr_hits::total 1124674 # number of demand (read+write) MSHR hits
764 system.cpu.dcache.overall_mshr_hits::cpu.data 1124674 # number of overall MSHR hits
765 system.cpu.dcache.overall_mshr_hits::total 1124674 # number of overall MSHR hits
766 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1763603 # number of ReadReq MSHR misses
767 system.cpu.dcache.ReadReq_mshr_misses::total 1763603 # number of ReadReq MSHR misses
768 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 909697 # number of WriteReq MSHR misses
769 system.cpu.dcache.WriteReq_mshr_misses::total 909697 # number of WriteReq MSHR misses
770 system.cpu.dcache.demand_mshr_misses::cpu.data 2673300 # number of demand (read+write) MSHR misses
771 system.cpu.dcache.demand_mshr_misses::total 2673300 # number of demand (read+write) MSHR misses
772 system.cpu.dcache.overall_mshr_misses::cpu.data 2673300 # number of overall MSHR misses
773 system.cpu.dcache.overall_mshr_misses::total 2673300 # number of overall MSHR misses
774 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 27774523500 # number of ReadReq MSHR miss cycles
775 system.cpu.dcache.ReadReq_mshr_miss_latency::total 27774523500 # number of ReadReq MSHR miss cycles
776 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 19972622500 # number of WriteReq MSHR miss cycles
777 system.cpu.dcache.WriteReq_mshr_miss_latency::total 19972622500 # number of WriteReq MSHR miss cycles
778 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 47747146000 # number of demand (read+write) MSHR miss cycles
779 system.cpu.dcache.demand_mshr_miss_latency::total 47747146000 # number of demand (read+write) MSHR miss cycles
780 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 47747146000 # number of overall MSHR miss cycles
781 system.cpu.dcache.overall_mshr_miss_latency::total 47747146000 # number of overall MSHR miss cycles
782 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007038 # mshr miss rate for ReadReq accesses
783 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007038 # mshr miss rate for ReadReq accesses
784 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006099 # mshr miss rate for WriteReq accesses
785 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006099 # mshr miss rate for WriteReq accesses
786 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006688 # mshr miss rate for demand accesses
787 system.cpu.dcache.demand_mshr_miss_rate::total 0.006688 # mshr miss rate for demand accesses
788 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006688 # mshr miss rate for overall accesses
789 system.cpu.dcache.overall_mshr_miss_rate::total 0.006688 # mshr miss rate for overall accesses
790 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15748.739087 # average ReadReq mshr miss latency
791 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15748.739087 # average ReadReq mshr miss latency
792 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 21955.247187 # average WriteReq mshr miss latency
793 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 21955.247187 # average WriteReq mshr miss latency
794 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17860.751132 # average overall mshr miss latency
795 system.cpu.dcache.demand_avg_mshr_miss_latency::total 17860.751132 # average overall mshr miss latency
796 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17860.751132 # average overall mshr miss latency
797 system.cpu.dcache.overall_avg_mshr_miss_latency::total 17860.751132 # average overall mshr miss latency
798 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
800 ---------- End Simulation Statistics ----------
projects / gem5.git / blob