2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.458513 # Number of seconds simulated
4 sim_ticks 458512999500 # Number of ticks simulated
5 final_tick 458512999500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 75448 # Simulator instruction rate (inst/s)
8 host_op_rate 139512 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 41836736 # Simulator tick rate (ticks/s)
10 host_mem_usage 384056 # Number of bytes of host memory used
11 host_seconds 10959.58 # Real time elapsed on the host
12 sim_insts 826877109 # Number of instructions simulated
13 sim_ops 1528988701 # Number of ops (including micro ops) simulated
14 system.voltage_domain.voltage 1 # Voltage in Volts
15 system.clk_domain.clock 1000 # Clock period in ticks
16 system.physmem.bytes_read::cpu.inst 201856 # Number of bytes read from this memory
17 system.physmem.bytes_read::cpu.data 24474368 # Number of bytes read from this memory
18 system.physmem.bytes_read::total 24676224 # Number of bytes read from this memory
19 system.physmem.bytes_inst_read::cpu.inst 201856 # Number of instructions bytes read from this memory
20 system.physmem.bytes_inst_read::total 201856 # Number of instructions bytes read from this memory
21 system.physmem.bytes_written::writebacks 18792384 # Number of bytes written to this memory
22 system.physmem.bytes_written::total 18792384 # Number of bytes written to this memory
23 system.physmem.num_reads::cpu.inst 3154 # Number of read requests responded to by this memory
24 system.physmem.num_reads::cpu.data 382412 # Number of read requests responded to by this memory
25 system.physmem.num_reads::total 385566 # Number of read requests responded to by this memory
26 system.physmem.num_writes::writebacks 293631 # Number of write requests responded to by this memory
27 system.physmem.num_writes::total 293631 # Number of write requests responded to by this memory
28 system.physmem.bw_read::cpu.inst 440241 # Total read bandwidth from this memory (bytes/s)
29 system.physmem.bw_read::cpu.data 53377697 # Total read bandwidth from this memory (bytes/s)
30 system.physmem.bw_read::total 53817938 # Total read bandwidth from this memory (bytes/s)
31 system.physmem.bw_inst_read::cpu.inst 440241 # Instruction read bandwidth from this memory (bytes/s)
32 system.physmem.bw_inst_read::total 440241 # Instruction read bandwidth from this memory (bytes/s)
33 system.physmem.bw_write::writebacks 40985499 # Write bandwidth from this memory (bytes/s)
34 system.physmem.bw_write::total 40985499 # Write bandwidth from this memory (bytes/s)
35 system.physmem.bw_total::writebacks 40985499 # Total bandwidth to/from this memory (bytes/s)
36 system.physmem.bw_total::cpu.inst 440241 # Total bandwidth to/from this memory (bytes/s)
37 system.physmem.bw_total::cpu.data 53377697 # Total bandwidth to/from this memory (bytes/s)
38 system.physmem.bw_total::total 94803436 # Total bandwidth to/from this memory (bytes/s)
39 system.physmem.readReqs 385568 # Number of read requests accepted
40 system.physmem.writeReqs 293631 # Number of write requests accepted
41 system.physmem.readBursts 385568 # Number of DRAM read bursts, including those serviced by the write queue
42 system.physmem.writeBursts 293631 # Number of DRAM write bursts, including those merged in the write queue
43 system.physmem.bytesReadDRAM 24654400 # Total number of bytes read from DRAM
44 system.physmem.bytesReadWrQ 21952 # Total number of bytes read from write queue
45 system.physmem.bytesWritten 18790528 # Total number of bytes written to DRAM
46 system.physmem.bytesReadSys 24676352 # Total read bytes from the system interface side
47 system.physmem.bytesWrittenSys 18792384 # Total written bytes from the system interface side
48 system.physmem.servicedByWrQ 343 # Number of DRAM read bursts serviced by the write queue
49 system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
50 system.physmem.neitherReadNorWriteReqs 136756 # Number of requests that are neither read nor write
51 system.physmem.perBankRdBursts::0 24002 # Per bank write bursts
52 system.physmem.perBankRdBursts::1 26346 # Per bank write bursts
53 system.physmem.perBankRdBursts::2 24809 # Per bank write bursts
54 system.physmem.perBankRdBursts::3 24514 # Per bank write bursts
55 system.physmem.perBankRdBursts::4 23427 # Per bank write bursts
56 system.physmem.perBankRdBursts::5 23679 # Per bank write bursts
57 system.physmem.perBankRdBursts::6 24437 # Per bank write bursts
58 system.physmem.perBankRdBursts::7 24240 # Per bank write bursts
59 system.physmem.perBankRdBursts::8 23642 # Per bank write bursts
60 system.physmem.perBankRdBursts::9 23833 # Per bank write bursts
61 system.physmem.perBankRdBursts::10 24803 # Per bank write bursts
62 system.physmem.perBankRdBursts::11 23968 # Per bank write bursts
63 system.physmem.perBankRdBursts::12 23115 # Per bank write bursts
64 system.physmem.perBankRdBursts::13 22838 # Per bank write bursts
65 system.physmem.perBankRdBursts::14 23649 # Per bank write bursts
66 system.physmem.perBankRdBursts::15 23923 # Per bank write bursts
67 system.physmem.perBankWrBursts::0 18533 # Per bank write bursts
68 system.physmem.perBankWrBursts::1 19811 # Per bank write bursts
69 system.physmem.perBankWrBursts::2 18961 # Per bank write bursts
70 system.physmem.perBankWrBursts::3 18917 # Per bank write bursts
71 system.physmem.perBankWrBursts::4 18087 # Per bank write bursts
72 system.physmem.perBankWrBursts::5 18414 # Per bank write bursts
73 system.physmem.perBankWrBursts::6 18972 # Per bank write bursts
74 system.physmem.perBankWrBursts::7 18944 # Per bank write bursts
75 system.physmem.perBankWrBursts::8 18562 # Per bank write bursts
76 system.physmem.perBankWrBursts::9 18116 # Per bank write bursts
77 system.physmem.perBankWrBursts::10 18832 # Per bank write bursts
78 system.physmem.perBankWrBursts::11 17714 # Per bank write bursts
79 system.physmem.perBankWrBursts::12 17339 # Per bank write bursts
80 system.physmem.perBankWrBursts::13 16924 # Per bank write bursts
81 system.physmem.perBankWrBursts::14 17682 # Per bank write bursts
82 system.physmem.perBankWrBursts::15 17794 # Per bank write bursts
83 system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
84 system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
85 system.physmem.totGap 458512983000 # Total gap between requests
86 system.physmem.readPktSize::0 0 # Read request sizes (log2)
87 system.physmem.readPktSize::1 0 # Read request sizes (log2)
88 system.physmem.readPktSize::2 0 # Read request sizes (log2)
89 system.physmem.readPktSize::3 0 # Read request sizes (log2)
90 system.physmem.readPktSize::4 0 # Read request sizes (log2)
91 system.physmem.readPktSize::5 0 # Read request sizes (log2)
92 system.physmem.readPktSize::6 385568 # Read request sizes (log2)
93 system.physmem.writePktSize::0 0 # Write request sizes (log2)
94 system.physmem.writePktSize::1 0 # Write request sizes (log2)
95 system.physmem.writePktSize::2 0 # Write request sizes (log2)
96 system.physmem.writePktSize::3 0 # Write request sizes (log2)
97 system.physmem.writePktSize::4 0 # Write request sizes (log2)
98 system.physmem.writePktSize::5 0 # Write request sizes (log2)
99 system.physmem.writePktSize::6 293631 # Write request sizes (log2)
100 system.physmem.rdQLenPdf::0 380696 # What read queue length does an incoming req see
101 system.physmem.rdQLenPdf::1 4209 # What read queue length does an incoming req see
102 system.physmem.rdQLenPdf::2 287 # What read queue length does an incoming req see
103 system.physmem.rdQLenPdf::3 29 # What read queue length does an incoming req see
104 system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see
105 system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
106 system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
107 system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
108 system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
109 system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
110 system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
111 system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
112 system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
113 system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
114 system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
115 system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
116 system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
117 system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
118 system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
119 system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
120 system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
121 system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
122 system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
123 system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
124 system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
125 system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
126 system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
127 system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
128 system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
129 system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
130 system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
131 system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
132 system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
133 system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
134 system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
135 system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
136 system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
137 system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
138 system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
139 system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
140 system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
141 system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
142 system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
143 system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
144 system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
145 system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
146 system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
147 system.physmem.wrQLenPdf::15 6409 # What write queue length does an incoming req see
148 system.physmem.wrQLenPdf::16 6808 # What write queue length does an incoming req see
149 system.physmem.wrQLenPdf::17 16841 # What write queue length does an incoming req see
150 system.physmem.wrQLenPdf::18 17378 # What write queue length does an incoming req see
151 system.physmem.wrQLenPdf::19 17552 # What write queue length does an incoming req see
152 system.physmem.wrQLenPdf::20 17536 # What write queue length does an incoming req see
153 system.physmem.wrQLenPdf::21 17527 # What write queue length does an incoming req see
154 system.physmem.wrQLenPdf::22 17556 # What write queue length does an incoming req see
155 system.physmem.wrQLenPdf::23 17556 # What write queue length does an incoming req see
156 system.physmem.wrQLenPdf::24 17549 # What write queue length does an incoming req see
157 system.physmem.wrQLenPdf::25 17549 # What write queue length does an incoming req see
158 system.physmem.wrQLenPdf::26 17561 # What write queue length does an incoming req see
159 system.physmem.wrQLenPdf::27 17726 # What write queue length does an incoming req see
160 system.physmem.wrQLenPdf::28 17619 # What write queue length does an incoming req see
161 system.physmem.wrQLenPdf::29 17583 # What write queue length does an incoming req see
162 system.physmem.wrQLenPdf::30 17768 # What write queue length does an incoming req see
163 system.physmem.wrQLenPdf::31 17495 # What write queue length does an incoming req see
164 system.physmem.wrQLenPdf::32 17431 # What write queue length does an incoming req see
165 system.physmem.wrQLenPdf::33 32 # What write queue length does an incoming req see
166 system.physmem.wrQLenPdf::34 21 # What write queue length does an incoming req see
167 system.physmem.wrQLenPdf::35 15 # What write queue length does an incoming req see
168 system.physmem.wrQLenPdf::36 9 # What write queue length does an incoming req see
169 system.physmem.wrQLenPdf::37 6 # What write queue length does an incoming req see
170 system.physmem.wrQLenPdf::38 7 # What write queue length does an incoming req see
171 system.physmem.wrQLenPdf::39 6 # What write queue length does an incoming req see
172 system.physmem.wrQLenPdf::40 5 # What write queue length does an incoming req see
173 system.physmem.wrQLenPdf::41 3 # What write queue length does an incoming req see
174 system.physmem.wrQLenPdf::42 6 # What write queue length does an incoming req see
175 system.physmem.wrQLenPdf::43 3 # What write queue length does an incoming req see
176 system.physmem.wrQLenPdf::44 9 # What write queue length does an incoming req see
177 system.physmem.wrQLenPdf::45 7 # What write queue length does an incoming req see
178 system.physmem.wrQLenPdf::46 9 # What write queue length does an incoming req see
179 system.physmem.wrQLenPdf::47 8 # What write queue length does an incoming req see
180 system.physmem.wrQLenPdf::48 8 # What write queue length does an incoming req see
181 system.physmem.wrQLenPdf::49 4 # What write queue length does an incoming req see
182 system.physmem.wrQLenPdf::50 6 # What write queue length does an incoming req see
183 system.physmem.wrQLenPdf::51 3 # What write queue length does an incoming req see
184 system.physmem.wrQLenPdf::52 3 # What write queue length does an incoming req see
185 system.physmem.wrQLenPdf::53 2 # What write queue length does an incoming req see
186 system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
187 system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
188 system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
189 system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
190 system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
191 system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
192 system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
193 system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
194 system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
195 system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
196 system.physmem.bytesPerActivate::samples 146743 # Bytes accessed per row activation
197 system.physmem.bytesPerActivate::mean 296.052173 # Bytes accessed per row activation
198 system.physmem.bytesPerActivate::gmean 174.726027 # Bytes accessed per row activation
199 system.physmem.bytesPerActivate::stdev 323.657452 # Bytes accessed per row activation
200 system.physmem.bytesPerActivate::0-127 54056 36.84% 36.84% # Bytes accessed per row activation
201 system.physmem.bytesPerActivate::128-255 40668 27.71% 64.55% # Bytes accessed per row activation
202 system.physmem.bytesPerActivate::256-383 13398 9.13% 73.68% # Bytes accessed per row activation
203 system.physmem.bytesPerActivate::384-511 7234 4.93% 78.61% # Bytes accessed per row activation
204 system.physmem.bytesPerActivate::512-639 5377 3.66% 82.28% # Bytes accessed per row activation
205 system.physmem.bytesPerActivate::640-767 3862 2.63% 84.91% # Bytes accessed per row activation
206 system.physmem.bytesPerActivate::768-895 3026 2.06% 86.97% # Bytes accessed per row activation
207 system.physmem.bytesPerActivate::896-1023 2779 1.89% 88.86% # Bytes accessed per row activation
208 system.physmem.bytesPerActivate::1024-1151 16343 11.14% 100.00% # Bytes accessed per row activation
209 system.physmem.bytesPerActivate::total 146743 # Bytes accessed per row activation
210 system.physmem.rdPerTurnAround::samples 17400 # Reads before turning the bus around for writes
211 system.physmem.rdPerTurnAround::mean 22.138621 # Reads before turning the bus around for writes
212 system.physmem.rdPerTurnAround::stdev 209.351810 # Reads before turning the bus around for writes
213 system.physmem.rdPerTurnAround::0-1023 17386 99.92% 99.92% # Reads before turning the bus around for writes
214 system.physmem.rdPerTurnAround::1024-2047 9 0.05% 99.97% # Reads before turning the bus around for writes
215 system.physmem.rdPerTurnAround::2048-3071 3 0.02% 99.99% # Reads before turning the bus around for writes
216 system.physmem.rdPerTurnAround::3072-4095 1 0.01% 99.99% # Reads before turning the bus around for writes
217 system.physmem.rdPerTurnAround::25600-26623 1 0.01% 100.00% # Reads before turning the bus around for writes
218 system.physmem.rdPerTurnAround::total 17400 # Reads before turning the bus around for writes
219 system.physmem.wrPerTurnAround::samples 17400 # Writes before turning the bus around for reads
220 system.physmem.wrPerTurnAround::mean 16.873678 # Writes before turning the bus around for reads
221 system.physmem.wrPerTurnAround::gmean 16.805032 # Writes before turning the bus around for reads
222 system.physmem.wrPerTurnAround::stdev 2.403017 # Writes before turning the bus around for reads
223 system.physmem.wrPerTurnAround::16-19 17211 98.91% 98.91% # Writes before turning the bus around for reads
224 system.physmem.wrPerTurnAround::20-23 144 0.83% 99.74% # Writes before turning the bus around for reads
225 system.physmem.wrPerTurnAround::24-27 22 0.13% 99.87% # Writes before turning the bus around for reads
226 system.physmem.wrPerTurnAround::28-31 3 0.02% 99.89% # Writes before turning the bus around for reads
227 system.physmem.wrPerTurnAround::32-35 3 0.02% 99.90% # Writes before turning the bus around for reads
228 system.physmem.wrPerTurnAround::36-39 1 0.01% 99.91% # Writes before turning the bus around for reads
229 system.physmem.wrPerTurnAround::40-43 2 0.01% 99.92% # Writes before turning the bus around for reads
230 system.physmem.wrPerTurnAround::48-51 1 0.01% 99.93% # Writes before turning the bus around for reads
231 system.physmem.wrPerTurnAround::52-55 2 0.01% 99.94% # Writes before turning the bus around for reads
232 system.physmem.wrPerTurnAround::56-59 2 0.01% 99.95% # Writes before turning the bus around for reads
233 system.physmem.wrPerTurnAround::60-63 1 0.01% 99.95% # Writes before turning the bus around for reads
234 system.physmem.wrPerTurnAround::64-67 1 0.01% 99.96% # Writes before turning the bus around for reads
235 system.physmem.wrPerTurnAround::72-75 1 0.01% 99.97% # Writes before turning the bus around for reads
236 system.physmem.wrPerTurnAround::76-79 1 0.01% 99.97% # Writes before turning the bus around for reads
237 system.physmem.wrPerTurnAround::84-87 2 0.01% 99.98% # Writes before turning the bus around for reads
238 system.physmem.wrPerTurnAround::108-111 2 0.01% 99.99% # Writes before turning the bus around for reads
239 system.physmem.wrPerTurnAround::192-195 1 0.01% 100.00% # Writes before turning the bus around for reads
240 system.physmem.wrPerTurnAround::total 17400 # Writes before turning the bus around for reads
241 system.physmem.totQLat 4188887000 # Total ticks spent queuing
242 system.physmem.totMemAccLat 11411855750 # Total ticks spent from burst creation until serviced by the DRAM
243 system.physmem.totBusLat 1926125000 # Total ticks spent in databus transfers
244 system.physmem.avgQLat 10873.87 # Average queueing delay per DRAM burst
245 system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
246 system.physmem.avgMemAccLat 29623.87 # Average memory access latency per DRAM burst
247 system.physmem.avgRdBW 53.77 # Average DRAM read bandwidth in MiByte/s
248 system.physmem.avgWrBW 40.98 # Average achieved write bandwidth in MiByte/s
249 system.physmem.avgRdBWSys 53.82 # Average system read bandwidth in MiByte/s
250 system.physmem.avgWrBWSys 40.99 # Average system write bandwidth in MiByte/s
251 system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
252 system.physmem.busUtil 0.74 # Data bus utilization in percentage
253 system.physmem.busUtilRead 0.42 # Data bus utilization in percentage for reads
254 system.physmem.busUtilWrite 0.32 # Data bus utilization in percentage for writes
255 system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing
256 system.physmem.avgWrQLen 21.82 # Average write queue length when enqueuing
257 system.physmem.readRowHits 316892 # Number of row buffer hits during reads
258 system.physmem.writeRowHits 215180 # Number of row buffer hits during writes
259 system.physmem.readRowHitRate 82.26 # Row buffer hit rate for reads
260 system.physmem.writeRowHitRate 73.28 # Row buffer hit rate for writes
261 system.physmem.avgGap 675079.00 # Average gap between requests
262 system.physmem.pageHitRate 78.38 # Row buffer hit rate, read and write combined
263 system.physmem.memoryStateTime::IDLE 318092069500 # Time in different power states
264 system.physmem.memoryStateTime::REF 15310620000 # Time in different power states
265 system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
266 system.physmem.memoryStateTime::ACT 125106520750 # Time in different power states
267 system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
268 system.membus.throughput 94803436 # Throughput (bytes/s)
269 system.membus.trans_dist::ReadReq 178732 # Transaction distribution
270 system.membus.trans_dist::ReadResp 178730 # Transaction distribution
271 system.membus.trans_dist::Writeback 293631 # Transaction distribution
272 system.membus.trans_dist::UpgradeReq 136756 # Transaction distribution
273 system.membus.trans_dist::UpgradeResp 136756 # Transaction distribution
274 system.membus.trans_dist::ReadExReq 206836 # Transaction distribution
275 system.membus.trans_dist::ReadExResp 206836 # Transaction distribution
276 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1338277 # Packet count per connected master and slave (bytes)
277 system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1338277 # Packet count per connected master and slave (bytes)
278 system.membus.pkt_count::total 1338277 # Packet count per connected master and slave (bytes)
279 system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43468608 # Cumulative packet size per connected master and slave (bytes)
280 system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 43468608 # Cumulative packet size per connected master and slave (bytes)
281 system.membus.tot_pkt_size::total 43468608 # Cumulative packet size per connected master and slave (bytes)
282 system.membus.data_through_bus 43468608 # Total data (bytes)
283 system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
284 system.membus.reqLayer0.occupancy 3392871500 # Layer occupancy (ticks)
285 system.membus.reqLayer0.utilization 0.7 # Layer utilization (%)
286 system.membus.respLayer1.occupancy 3899245261 # Layer occupancy (ticks)
287 system.membus.respLayer1.utilization 0.9 # Layer utilization (%)
288 system.cpu_clk_domain.clock 500 # Clock period in ticks
289 system.cpu.branchPred.lookups 205578466 # Number of BP lookups
290 system.cpu.branchPred.condPredicted 205578466 # Number of conditional branches predicted
291 system.cpu.branchPred.condIncorrect 9901534 # Number of conditional branches incorrect
292 system.cpu.branchPred.BTBLookups 117029392 # Number of BTB lookups
293 system.cpu.branchPred.BTBHits 114680074 # Number of BTB hits
294 system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
295 system.cpu.branchPred.BTBHitPct 97.992540 # BTB Hit Percentage
296 system.cpu.branchPred.usedRAS 25067972 # Number of times the RAS was used to get a target.
297 system.cpu.branchPred.RASInCorrect 1805738 # Number of incorrect RAS predictions.
298 system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
299 system.cpu.workload.num_syscalls 551 # Number of system calls
300 system.cpu.numCycles 917184655 # number of cpu cycles simulated
301 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
302 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
303 system.cpu.fetch.icacheStallCycles 167397549 # Number of cycles fetch is stalled on an Icache miss
304 system.cpu.fetch.Insts 1131555944 # Number of instructions fetch has processed
305 system.cpu.fetch.Branches 205578466 # Number of branches that fetch encountered
306 system.cpu.fetch.predictedBranches 139748046 # Number of branches that fetch has predicted taken
307 system.cpu.fetch.Cycles 352223186 # Number of cycles fetch has run and was not squashing or blocked
308 system.cpu.fetch.SquashCycles 71069558 # Number of cycles fetch has spent squashing
309 system.cpu.fetch.BlockedCycles 304555909 # Number of cycles fetch has spent blocked
310 system.cpu.fetch.MiscStallCycles 47998 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
311 system.cpu.fetch.PendingTrapStallCycles 253720 # Number of stall cycles due to pending traps
312 system.cpu.fetch.IcacheWaitRetryStallCycles 58 # Number of stall cycles due to full MSHR
313 system.cpu.fetch.CacheLines 161997167 # Number of cache lines fetched
314 system.cpu.fetch.IcacheSquashes 2518791 # Number of outstanding Icache misses that were squashed
315 system.cpu.fetch.rateDist::samples 885395126 # Number of instructions fetched each cycle (Total)
316 system.cpu.fetch.rateDist::mean 2.377906 # Number of instructions fetched each cycle (Total)
317 system.cpu.fetch.rateDist::stdev 3.324319 # Number of instructions fetched each cycle (Total)
318 system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
319 system.cpu.fetch.rateDist::0 537236750 60.68% 60.68% # Number of instructions fetched each cycle (Total)
320 system.cpu.fetch.rateDist::1 23398648 2.64% 63.32% # Number of instructions fetched each cycle (Total)
321 system.cpu.fetch.rateDist::2 25254202 2.85% 66.17% # Number of instructions fetched each cycle (Total)
322 system.cpu.fetch.rateDist::3 27875613 3.15% 69.32% # Number of instructions fetched each cycle (Total)
323 system.cpu.fetch.rateDist::4 17735392 2.00% 71.32% # Number of instructions fetched each cycle (Total)
324 system.cpu.fetch.rateDist::5 22920767 2.59% 73.91% # Number of instructions fetched each cycle (Total)
325 system.cpu.fetch.rateDist::6 29423422 3.32% 77.24% # Number of instructions fetched each cycle (Total)
326 system.cpu.fetch.rateDist::7 26636426 3.01% 80.24% # Number of instructions fetched each cycle (Total)
327 system.cpu.fetch.rateDist::8 174913906 19.76% 100.00% # Number of instructions fetched each cycle (Total)
328 system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
329 system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
330 system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
331 system.cpu.fetch.rateDist::total 885395126 # Number of instructions fetched each cycle (Total)
332 system.cpu.fetch.branchRate 0.224141 # Number of branch fetches per cycle
333 system.cpu.fetch.rate 1.233728 # Number of inst fetches per cycle
334 system.cpu.decode.IdleCycles 222654978 # Number of cycles decode is idle
335 system.cpu.decode.BlockedCycles 259567656 # Number of cycles decode is blocked
336 system.cpu.decode.RunCycles 295344640 # Number of cycles decode is running
337 system.cpu.decode.UnblockCycles 46911146 # Number of cycles decode is unblocking
338 system.cpu.decode.SquashCycles 60916706 # Number of cycles decode is squashing
339 system.cpu.decode.DecodedInsts 2071122559 # Number of instructions handled by decode
340 system.cpu.decode.SquashedInsts 3 # Number of squashed instructions handled by decode
341 system.cpu.rename.SquashCycles 60916706 # Number of cycles rename is squashing
342 system.cpu.rename.IdleCycles 256101136 # Number of cycles rename is idle
343 system.cpu.rename.BlockCycles 115302026 # Number of cycles rename is blocking
344 system.cpu.rename.serializeStallCycles 17668 # count of cycles rename stalled for serializing inst
345 system.cpu.rename.RunCycles 306678759 # Number of cycles rename is running
346 system.cpu.rename.UnblockCycles 146378831 # Number of cycles rename is unblocking
347 system.cpu.rename.RenamedInsts 2034998452 # Number of instructions processed by rename
348 system.cpu.rename.ROBFullEvents 20313 # Number of times rename has blocked due to ROB full
349 system.cpu.rename.IQFullEvents 24722090 # Number of times rename has blocked due to IQ full
350 system.cpu.rename.LSQFullEvents 106340501 # Number of times rename has blocked due to LSQ full
351 system.cpu.rename.RenamedOperands 2137925960 # Number of destination operands rename has renamed
352 system.cpu.rename.RenameLookups 5150186774 # Number of register rename lookups that rename has made
353 system.cpu.rename.int_rename_lookups 3273147321 # Number of integer rename lookups
354 system.cpu.rename.fp_rename_lookups 41991 # Number of floating rename lookups
355 system.cpu.rename.CommittedMaps 1614040854 # Number of HB maps that are committed
356 system.cpu.rename.UndoneMaps 523885106 # Number of HB maps that are undone due to squashing
357 system.cpu.rename.serializingInsts 1288 # count of serializing insts renamed
358 system.cpu.rename.tempSerializingInsts 1219 # count of temporary serializing insts renamed
359 system.cpu.rename.skidInsts 345625652 # count of insts added to the skid buffer
360 system.cpu.memDep0.insertedLoads 495840221 # Number of loads inserted to the mem dependence unit.
361 system.cpu.memDep0.insertedStores 194409464 # Number of stores inserted to the mem dependence unit.
362 system.cpu.memDep0.conflictingLoads 195351813 # Number of conflicting loads.
363 system.cpu.memDep0.conflictingStores 54649414 # Number of conflicting stores.
364 system.cpu.iq.iqInstsAdded 1975275020 # Number of instructions added to the IQ (excludes non-spec)
365 system.cpu.iq.iqNonSpecInstsAdded 13975 # Number of non-speculative instructions added to the IQ
366 system.cpu.iq.iqInstsIssued 1772033700 # Number of instructions issued
367 system.cpu.iq.iqSquashedInstsIssued 489443 # Number of squashed instructions issued
368 system.cpu.iq.iqSquashedInstsExamined 441377933 # Number of squashed instructions iterated over during squash; mainly for profiling
369 system.cpu.iq.iqSquashedOperandsExamined 734704744 # Number of squashed operands that are examined and possibly removed from graph
370 system.cpu.iq.iqSquashedNonSpecRemoved 13423 # Number of squashed non-spec instructions that were removed
371 system.cpu.iq.issued_per_cycle::samples 885395126 # Number of insts issued each cycle
372 system.cpu.iq.issued_per_cycle::mean 2.001404 # Number of insts issued each cycle
373 system.cpu.iq.issued_per_cycle::stdev 1.883479 # Number of insts issued each cycle
374 system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
375 system.cpu.iq.issued_per_cycle::0 268930520 30.37% 30.37% # Number of insts issued each cycle
376 system.cpu.iq.issued_per_cycle::1 151513258 17.11% 47.49% # Number of insts issued each cycle
377 system.cpu.iq.issued_per_cycle::2 137639902 15.55% 63.03% # Number of insts issued each cycle
378 system.cpu.iq.issued_per_cycle::3 131544541 14.86% 77.89% # Number of insts issued each cycle
379 system.cpu.iq.issued_per_cycle::4 91741507 10.36% 88.25% # Number of insts issued each cycle
380 system.cpu.iq.issued_per_cycle::5 55934371 6.32% 94.57% # Number of insts issued each cycle
381 system.cpu.iq.issued_per_cycle::6 34425935 3.89% 98.46% # Number of insts issued each cycle
382 system.cpu.iq.issued_per_cycle::7 11907214 1.34% 99.80% # Number of insts issued each cycle
383 system.cpu.iq.issued_per_cycle::8 1757878 0.20% 100.00% # Number of insts issued each cycle
384 system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
385 system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
386 system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
387 system.cpu.iq.issued_per_cycle::total 885395126 # Number of insts issued each cycle
388 system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
389 system.cpu.iq.fu_full::IntAlu 4908226 32.44% 32.44% # attempts to use FU when none available
390 system.cpu.iq.fu_full::IntMult 0 0.00% 32.44% # attempts to use FU when none available
391 system.cpu.iq.fu_full::IntDiv 0 0.00% 32.44% # attempts to use FU when none available
392 system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.44% # attempts to use FU when none available
393 system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.44% # attempts to use FU when none available
394 system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.44% # attempts to use FU when none available
395 system.cpu.iq.fu_full::FloatMult 0 0.00% 32.44% # attempts to use FU when none available
396 system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.44% # attempts to use FU when none available
397 system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.44% # attempts to use FU when none available
398 system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.44% # attempts to use FU when none available
399 system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.44% # attempts to use FU when none available
400 system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.44% # attempts to use FU when none available
401 system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.44% # attempts to use FU when none available
402 system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.44% # attempts to use FU when none available
403 system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.44% # attempts to use FU when none available
404 system.cpu.iq.fu_full::SimdMult 0 0.00% 32.44% # attempts to use FU when none available
405 system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.44% # attempts to use FU when none available
406 system.cpu.iq.fu_full::SimdShift 0 0.00% 32.44% # attempts to use FU when none available
407 system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.44% # attempts to use FU when none available
408 system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.44% # attempts to use FU when none available
409 system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.44% # attempts to use FU when none available
410 system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.44% # attempts to use FU when none available
411 system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.44% # attempts to use FU when none available
412 system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.44% # attempts to use FU when none available
413 system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.44% # attempts to use FU when none available
414 system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.44% # attempts to use FU when none available
415 system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.44% # attempts to use FU when none available
416 system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.44% # attempts to use FU when none available
417 system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.44% # attempts to use FU when none available
418 system.cpu.iq.fu_full::MemRead 7617033 50.35% 82.79% # attempts to use FU when none available
419 system.cpu.iq.fu_full::MemWrite 2603803 17.21% 100.00% # attempts to use FU when none available
420 system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
421 system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
422 system.cpu.iq.FU_type_0::No_OpClass 2622809 0.15% 0.15% # Type of FU issued
423 system.cpu.iq.FU_type_0::IntAlu 1165654727 65.78% 65.93% # Type of FU issued
424 system.cpu.iq.FU_type_0::IntMult 353604 0.02% 65.95% # Type of FU issued
425 system.cpu.iq.FU_type_0::IntDiv 3880790 0.22% 66.17% # Type of FU issued
426 system.cpu.iq.FU_type_0::FloatAdd 51 0.00% 66.17% # Type of FU issued
427 system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.17% # Type of FU issued
428 system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.17% # Type of FU issued
429 system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.17% # Type of FU issued
430 system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.17% # Type of FU issued
431 system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.17% # Type of FU issued
432 system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.17% # Type of FU issued
433 system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.17% # Type of FU issued
434 system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.17% # Type of FU issued
435 system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.17% # Type of FU issued
436 system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.17% # Type of FU issued
437 system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.17% # Type of FU issued
438 system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.17% # Type of FU issued
439 system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.17% # Type of FU issued
440 system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.17% # Type of FU issued
441 system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.17% # Type of FU issued
442 system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.17% # Type of FU issued
443 system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.17% # Type of FU issued
444 system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.17% # Type of FU issued
445 system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.17% # Type of FU issued
446 system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.17% # Type of FU issued
447 system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.17% # Type of FU issued
448 system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.17% # Type of FU issued
449 system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.17% # Type of FU issued
450 system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.17% # Type of FU issued
451 system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.17% # Type of FU issued
452 system.cpu.iq.FU_type_0::MemRead 429257765 24.22% 90.39% # Type of FU issued
453 system.cpu.iq.FU_type_0::MemWrite 170263954 9.61% 100.00% # Type of FU issued
454 system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
455 system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
456 system.cpu.iq.FU_type_0::total 1772033700 # Type of FU issued
457 system.cpu.iq.rate 1.932036 # Inst issue rate
458 system.cpu.iq.fu_busy_cnt 15129062 # FU busy when requested
459 system.cpu.iq.fu_busy_rate 0.008538 # FU busy rate (busy events/executed inst)
460 system.cpu.iq.int_inst_queue_reads 4445065609 # Number of integer instruction queue reads
461 system.cpu.iq.int_inst_queue_writes 2416869316 # Number of integer instruction queue writes
462 system.cpu.iq.int_inst_queue_wakeup_accesses 1744809668 # Number of integer instruction queue wakeup accesses
463 system.cpu.iq.fp_inst_queue_reads 15422 # Number of floating instruction queue reads
464 system.cpu.iq.fp_inst_queue_writes 52952 # Number of floating instruction queue writes
465 system.cpu.iq.fp_inst_queue_wakeup_accesses 3677 # Number of floating instruction queue wakeup accesses
466 system.cpu.iq.int_alu_accesses 1784532643 # Number of integer alu accesses
467 system.cpu.iq.fp_alu_accesses 7310 # Number of floating point alu accesses
468 system.cpu.iew.lsq.thread0.forwLoads 172476568 # Number of loads that had data forwarded from stores
469 system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
470 system.cpu.iew.lsq.thread0.squashedLoads 111739174 # Number of loads squashed
471 system.cpu.iew.lsq.thread0.ignoredResponses 389536 # Number of memory responses ignored because the instruction is squashed
472 system.cpu.iew.lsq.thread0.memOrderViolation 327115 # Number of memory ordering violations
473 system.cpu.iew.lsq.thread0.squashedStores 45249278 # Number of stores squashed
474 system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
475 system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
476 system.cpu.iew.lsq.thread0.rescheduledLoads 14923 # Number of loads that were rescheduled
477 system.cpu.iew.lsq.thread0.cacheBlocked 606 # Number of times an access to memory failed due to the cache being blocked
478 system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
479 system.cpu.iew.iewSquashCycles 60916706 # Number of cycles IEW is squashing
480 system.cpu.iew.iewBlockCycles 67511680 # Number of cycles IEW is blocking
481 system.cpu.iew.iewUnblockCycles 7160873 # Number of cycles IEW is unblocking
482 system.cpu.iew.iewDispatchedInsts 1975288995 # Number of instructions dispatched to IQ
483 system.cpu.iew.iewDispSquashedInsts 782662 # Number of squashed instructions skipped by dispatch
484 system.cpu.iew.iewDispLoadInsts 495841331 # Number of dispatched load instructions
485 system.cpu.iew.iewDispStoreInsts 194409464 # Number of dispatched store instructions
486 system.cpu.iew.iewDispNonSpecInsts 3475 # Number of dispatched non-speculative instructions
487 system.cpu.iew.iewIQFullEvents 4447984 # Number of times the IQ has become full, causing a stall
488 system.cpu.iew.iewLSQFullEvents 83109 # Number of times the LSQ has become full, causing a stall
489 system.cpu.iew.memOrderViolationEvents 327115 # Number of memory order violations
490 system.cpu.iew.predictedTakenIncorrect 5905027 # Number of branches that were predicted taken incorrectly
491 system.cpu.iew.predictedNotTakenIncorrect 4421064 # Number of branches that were predicted not taken incorrectly
492 system.cpu.iew.branchMispredicts 10326091 # Number of branch mispredicts detected at execute
493 system.cpu.iew.iewExecutedInsts 1752917365 # Number of executed instructions
494 system.cpu.iew.iewExecLoadInsts 424127416 # Number of load instructions executed
495 system.cpu.iew.iewExecSquashedInsts 19116335 # Number of squashed instructions skipped in execute
496 system.cpu.iew.exec_swp 0 # number of swp insts executed
497 system.cpu.iew.exec_nop 0 # number of nop insts executed
498 system.cpu.iew.exec_refs 590948442 # number of memory reference insts executed
499 system.cpu.iew.exec_branches 167460417 # Number of branches executed
500 system.cpu.iew.exec_stores 166821026 # Number of stores executed
501 system.cpu.iew.exec_rate 1.911194 # Inst execution rate
502 system.cpu.iew.wb_sent 1749660983 # cumulative count of insts sent to commit
503 system.cpu.iew.wb_count 1744813345 # cumulative count of insts written-back
504 system.cpu.iew.wb_producers 1324821434 # num instructions producing a value
505 system.cpu.iew.wb_consumers 1945562364 # num instructions consuming a value
506 system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
507 system.cpu.iew.wb_rate 1.902358 # insts written-back per cycle
508 system.cpu.iew.wb_fanout 0.680945 # average fanout of values written-back
509 system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
510 system.cpu.commit.commitSquashedInsts 446329306 # The number of squashed insts skipped by commit
511 system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards
512 system.cpu.commit.branchMispredicts 9930052 # The number of times a branch was mispredicted
513 system.cpu.commit.committed_per_cycle::samples 824478420 # Number of insts commited each cycle
514 system.cpu.commit.committed_per_cycle::mean 1.854492 # Number of insts commited each cycle
515 system.cpu.commit.committed_per_cycle::stdev 2.436428 # Number of insts commited each cycle
516 system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
517 system.cpu.commit.committed_per_cycle::0 332514113 40.33% 40.33% # Number of insts commited each cycle
518 system.cpu.commit.committed_per_cycle::1 193200456 23.43% 63.76% # Number of insts commited each cycle
519 system.cpu.commit.committed_per_cycle::2 63249703 7.67% 71.43% # Number of insts commited each cycle
520 system.cpu.commit.committed_per_cycle::3 92516022 11.22% 82.66% # Number of insts commited each cycle
521 system.cpu.commit.committed_per_cycle::4 24944995 3.03% 85.68% # Number of insts commited each cycle
522 system.cpu.commit.committed_per_cycle::5 27441019 3.33% 89.01% # Number of insts commited each cycle
523 system.cpu.commit.committed_per_cycle::6 9353308 1.13% 90.14% # Number of insts commited each cycle
524 system.cpu.commit.committed_per_cycle::7 11434582 1.39% 91.53% # Number of insts commited each cycle
525 system.cpu.commit.committed_per_cycle::8 69824222 8.47% 100.00% # Number of insts commited each cycle
526 system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
527 system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
528 system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
529 system.cpu.commit.committed_per_cycle::total 824478420 # Number of insts commited each cycle
530 system.cpu.commit.committedInsts 826877109 # Number of instructions committed
531 system.cpu.commit.committedOps 1528988701 # Number of ops (including micro ops) committed
532 system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
533 system.cpu.commit.refs 533262343 # Number of memory references committed
534 system.cpu.commit.loads 384102157 # Number of loads committed
535 system.cpu.commit.membars 0 # Number of memory barriers committed
536 system.cpu.commit.branches 149758583 # Number of branches committed
537 system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
538 system.cpu.commit.int_insts 1526605509 # Number of committed integer instructions.
539 system.cpu.commit.function_calls 17673145 # Number of function calls committed.
540 system.cpu.commit.op_class_0::No_OpClass 1819099 0.12% 0.12% # Class of committed instruction
541 system.cpu.commit.op_class_0::IntAlu 989721889 64.73% 64.85% # Class of committed instruction
542 system.cpu.commit.op_class_0::IntMult 306834 0.02% 64.87% # Class of committed instruction
543 system.cpu.commit.op_class_0::IntDiv 3878536 0.25% 65.12% # Class of committed instruction
544 system.cpu.commit.op_class_0::FloatAdd 0 0.00% 65.12% # Class of committed instruction
545 system.cpu.commit.op_class_0::FloatCmp 0 0.00% 65.12% # Class of committed instruction
546 system.cpu.commit.op_class_0::FloatCvt 0 0.00% 65.12% # Class of committed instruction
547 system.cpu.commit.op_class_0::FloatMult 0 0.00% 65.12% # Class of committed instruction
548 system.cpu.commit.op_class_0::FloatDiv 0 0.00% 65.12% # Class of committed instruction
549 system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 65.12% # Class of committed instruction
550 system.cpu.commit.op_class_0::SimdAdd 0 0.00% 65.12% # Class of committed instruction
551 system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 65.12% # Class of committed instruction
552 system.cpu.commit.op_class_0::SimdAlu 0 0.00% 65.12% # Class of committed instruction
553 system.cpu.commit.op_class_0::SimdCmp 0 0.00% 65.12% # Class of committed instruction
554 system.cpu.commit.op_class_0::SimdCvt 0 0.00% 65.12% # Class of committed instruction
555 system.cpu.commit.op_class_0::SimdMisc 0 0.00% 65.12% # Class of committed instruction
556 system.cpu.commit.op_class_0::SimdMult 0 0.00% 65.12% # Class of committed instruction
557 system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 65.12% # Class of committed instruction
558 system.cpu.commit.op_class_0::SimdShift 0 0.00% 65.12% # Class of committed instruction
559 system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 65.12% # Class of committed instruction
560 system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 65.12% # Class of committed instruction
561 system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 65.12% # Class of committed instruction
562 system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 65.12% # Class of committed instruction
563 system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 65.12% # Class of committed instruction
564 system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 65.12% # Class of committed instruction
565 system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 65.12% # Class of committed instruction
566 system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 65.12% # Class of committed instruction
567 system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 65.12% # Class of committed instruction
568 system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.12% # Class of committed instruction
569 system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.12% # Class of committed instruction
570 system.cpu.commit.op_class_0::MemRead 384102157 25.12% 90.24% # Class of committed instruction
571 system.cpu.commit.op_class_0::MemWrite 149160186 9.76% 100.00% # Class of committed instruction
572 system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
573 system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
574 system.cpu.commit.op_class_0::total 1528988701 # Class of committed instruction
575 system.cpu.commit.bw_lim_events 69824222 # number cycles where commit BW limit reached
576 system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
577 system.cpu.rob.rob_reads 2729972205 # The number of ROB reads
578 system.cpu.rob.rob_writes 4011712950 # The number of ROB writes
579 system.cpu.timesIdled 3360559 # Number of times that the entire CPU went into an idle state and unscheduled itself
580 system.cpu.idleCycles 31789529 # Total number of cycles that the CPU has spent unscheduled due to idling
581 system.cpu.committedInsts 826877109 # Number of Instructions Simulated
582 system.cpu.committedOps 1528988701 # Number of Ops (including micro ops) Simulated
583 system.cpu.cpi 1.109215 # CPI: Cycles Per Instruction
584 system.cpu.cpi_total 1.109215 # CPI: Total CPI of All Threads
585 system.cpu.ipc 0.901538 # IPC: Instructions Per Cycle
586 system.cpu.ipc_total 0.901538 # IPC: Total IPC of All Threads
587 system.cpu.int_regfile_reads 2716307472 # number of integer regfile reads
588 system.cpu.int_regfile_writes 1420359444 # number of integer regfile writes
589 system.cpu.fp_regfile_reads 3689 # number of floating regfile reads
590 system.cpu.fp_regfile_writes 68 # number of floating regfile writes
591 system.cpu.cc_regfile_reads 597203936 # number of cc regfile reads
592 system.cpu.cc_regfile_writes 405421760 # number of cc regfile writes
593 system.cpu.misc_regfile_reads 964666021 # number of misc regfile reads
594 system.cpu.misc_regfile_writes 1 # number of misc regfile writes
595 system.cpu.toL2Bus.throughput 699262879 # Throughput (bytes/s)
596 system.cpu.toL2Bus.trans_dist::ReadReq 1907311 # Transaction distribution
597 system.cpu.toL2Bus.trans_dist::ReadResp 1907308 # Transaction distribution
598 system.cpu.toL2Bus.trans_dist::Writeback 2330645 # Transaction distribution
599 system.cpu.toL2Bus.trans_dist::UpgradeReq 138184 # Transaction distribution
600 system.cpu.toL2Bus.trans_dist::UpgradeResp 138184 # Transaction distribution
601 system.cpu.toL2Bus.trans_dist::ReadExReq 771752 # Transaction distribution
602 system.cpu.toL2Bus.trans_dist::ReadExResp 771752 # Transaction distribution
603 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 151977 # Packet count per connected master and slave (bytes)
604 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7674879 # Packet count per connected master and slave (bytes)
605 system.cpu.toL2Bus.pkt_count::total 7826856 # Packet count per connected master and slave (bytes)
606 system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 438272 # Cumulative packet size per connected master and slave (bytes)
607 system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311332928 # Cumulative packet size per connected master and slave (bytes)
608 system.cpu.toL2Bus.tot_pkt_size::total 311771200 # Cumulative packet size per connected master and slave (bytes)
609 system.cpu.toL2Bus.data_through_bus 311771200 # Total data (bytes)
610 system.cpu.toL2Bus.snoop_data_through_bus 8849920 # Total snoop data (bytes)
611 system.cpu.toL2Bus.reqLayer0.occupancy 4908820525 # Layer occupancy (ticks)
612 system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%)
613 system.cpu.toL2Bus.respLayer0.occupancy 218162491 # Layer occupancy (ticks)
614 system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
615 system.cpu.toL2Bus.respLayer1.occupancy 3952575691 # Layer occupancy (ticks)
616 system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%)
617 system.cpu.icache.tags.replacements 5306 # number of replacements
618 system.cpu.icache.tags.tagsinuse 1035.768369 # Cycle average of tags in use
619 system.cpu.icache.tags.total_refs 161848074 # Total number of references to valid blocks.
620 system.cpu.icache.tags.sampled_refs 6885 # Sample count of references to valid blocks.
621 system.cpu.icache.tags.avg_refs 23507.345534 # Average number of references to valid blocks.
622 system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
623 system.cpu.icache.tags.occ_blocks::cpu.inst 1035.768369 # Average occupied blocks per requestor
624 system.cpu.icache.tags.occ_percent::cpu.inst 0.505746 # Average percentage of cache occupancy
625 system.cpu.icache.tags.occ_percent::total 0.505746 # Average percentage of cache occupancy
626 system.cpu.icache.tags.occ_task_id_blocks::1024 1579 # Occupied blocks per task id
627 system.cpu.icache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id
628 system.cpu.icache.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id
629 system.cpu.icache.tags.age_task_id_blocks_1024::2 44 # Occupied blocks per task id
630 system.cpu.icache.tags.age_task_id_blocks_1024::3 250 # Occupied blocks per task id
631 system.cpu.icache.tags.age_task_id_blocks_1024::4 1221 # Occupied blocks per task id
632 system.cpu.icache.tags.occ_task_id_percent::1024 0.770996 # Percentage of cache occupancy per task id
633 system.cpu.icache.tags.tag_accesses 324139462 # Number of tag accesses
634 system.cpu.icache.tags.data_accesses 324139462 # Number of data accesses
635 system.cpu.icache.ReadReq_hits::cpu.inst 161850058 # number of ReadReq hits
636 system.cpu.icache.ReadReq_hits::total 161850058 # number of ReadReq hits
637 system.cpu.icache.demand_hits::cpu.inst 161850058 # number of demand (read+write) hits
638 system.cpu.icache.demand_hits::total 161850058 # number of demand (read+write) hits
639 system.cpu.icache.overall_hits::cpu.inst 161850058 # number of overall hits
640 system.cpu.icache.overall_hits::total 161850058 # number of overall hits
641 system.cpu.icache.ReadReq_misses::cpu.inst 147109 # number of ReadReq misses
642 system.cpu.icache.ReadReq_misses::total 147109 # number of ReadReq misses
643 system.cpu.icache.demand_misses::cpu.inst 147109 # number of demand (read+write) misses
644 system.cpu.icache.demand_misses::total 147109 # number of demand (read+write) misses
645 system.cpu.icache.overall_misses::cpu.inst 147109 # number of overall misses
646 system.cpu.icache.overall_misses::total 147109 # number of overall misses
647 system.cpu.icache.ReadReq_miss_latency::cpu.inst 933905482 # number of ReadReq miss cycles
648 system.cpu.icache.ReadReq_miss_latency::total 933905482 # number of ReadReq miss cycles
649 system.cpu.icache.demand_miss_latency::cpu.inst 933905482 # number of demand (read+write) miss cycles
650 system.cpu.icache.demand_miss_latency::total 933905482 # number of demand (read+write) miss cycles
651 system.cpu.icache.overall_miss_latency::cpu.inst 933905482 # number of overall miss cycles
652 system.cpu.icache.overall_miss_latency::total 933905482 # number of overall miss cycles
653 system.cpu.icache.ReadReq_accesses::cpu.inst 161997167 # number of ReadReq accesses(hits+misses)
654 system.cpu.icache.ReadReq_accesses::total 161997167 # number of ReadReq accesses(hits+misses)
655 system.cpu.icache.demand_accesses::cpu.inst 161997167 # number of demand (read+write) accesses
656 system.cpu.icache.demand_accesses::total 161997167 # number of demand (read+write) accesses
657 system.cpu.icache.overall_accesses::cpu.inst 161997167 # number of overall (read+write) accesses
658 system.cpu.icache.overall_accesses::total 161997167 # number of overall (read+write) accesses
659 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000908 # miss rate for ReadReq accesses
660 system.cpu.icache.ReadReq_miss_rate::total 0.000908 # miss rate for ReadReq accesses
661 system.cpu.icache.demand_miss_rate::cpu.inst 0.000908 # miss rate for demand accesses
662 system.cpu.icache.demand_miss_rate::total 0.000908 # miss rate for demand accesses
663 system.cpu.icache.overall_miss_rate::cpu.inst 0.000908 # miss rate for overall accesses
664 system.cpu.icache.overall_miss_rate::total 0.000908 # miss rate for overall accesses
665 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6348.391207 # average ReadReq miss latency
666 system.cpu.icache.ReadReq_avg_miss_latency::total 6348.391207 # average ReadReq miss latency
667 system.cpu.icache.demand_avg_miss_latency::cpu.inst 6348.391207 # average overall miss latency
668 system.cpu.icache.demand_avg_miss_latency::total 6348.391207 # average overall miss latency
669 system.cpu.icache.overall_avg_miss_latency::cpu.inst 6348.391207 # average overall miss latency
670 system.cpu.icache.overall_avg_miss_latency::total 6348.391207 # average overall miss latency
671 system.cpu.icache.blocked_cycles::no_mshrs 500 # number of cycles access was blocked
672 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
673 system.cpu.icache.blocked::no_mshrs 9 # number of cycles access was blocked
674 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
675 system.cpu.icache.avg_blocked_cycles::no_mshrs 55.555556 # average number of cycles each access was blocked
676 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
677 system.cpu.icache.fast_writes 0 # number of fast writes performed
678 system.cpu.icache.cache_copies 0 # number of cache copies performed
679 system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1980 # number of ReadReq MSHR hits
680 system.cpu.icache.ReadReq_mshr_hits::total 1980 # number of ReadReq MSHR hits
681 system.cpu.icache.demand_mshr_hits::cpu.inst 1980 # number of demand (read+write) MSHR hits
682 system.cpu.icache.demand_mshr_hits::total 1980 # number of demand (read+write) MSHR hits
683 system.cpu.icache.overall_mshr_hits::cpu.inst 1980 # number of overall MSHR hits
684 system.cpu.icache.overall_mshr_hits::total 1980 # number of overall MSHR hits
685 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 145129 # number of ReadReq MSHR misses
686 system.cpu.icache.ReadReq_mshr_misses::total 145129 # number of ReadReq MSHR misses
687 system.cpu.icache.demand_mshr_misses::cpu.inst 145129 # number of demand (read+write) MSHR misses
688 system.cpu.icache.demand_mshr_misses::total 145129 # number of demand (read+write) MSHR misses
689 system.cpu.icache.overall_mshr_misses::cpu.inst 145129 # number of overall MSHR misses
690 system.cpu.icache.overall_mshr_misses::total 145129 # number of overall MSHR misses
691 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 558373758 # number of ReadReq MSHR miss cycles
692 system.cpu.icache.ReadReq_mshr_miss_latency::total 558373758 # number of ReadReq MSHR miss cycles
693 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 558373758 # number of demand (read+write) MSHR miss cycles
694 system.cpu.icache.demand_mshr_miss_latency::total 558373758 # number of demand (read+write) MSHR miss cycles
695 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 558373758 # number of overall MSHR miss cycles
696 system.cpu.icache.overall_mshr_miss_latency::total 558373758 # number of overall MSHR miss cycles
697 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000896 # mshr miss rate for ReadReq accesses
698 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000896 # mshr miss rate for ReadReq accesses
699 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000896 # mshr miss rate for demand accesses
700 system.cpu.icache.demand_mshr_miss_rate::total 0.000896 # mshr miss rate for demand accesses
701 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000896 # mshr miss rate for overall accesses
702 system.cpu.icache.overall_mshr_miss_rate::total 0.000896 # mshr miss rate for overall accesses
703 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 3847.430617 # average ReadReq mshr miss latency
704 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 3847.430617 # average ReadReq mshr miss latency
705 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 3847.430617 # average overall mshr miss latency
706 system.cpu.icache.demand_avg_mshr_miss_latency::total 3847.430617 # average overall mshr miss latency
707 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 3847.430617 # average overall mshr miss latency
708 system.cpu.icache.overall_avg_mshr_miss_latency::total 3847.430617 # average overall mshr miss latency
709 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
710 system.cpu.l2cache.tags.replacements 352885 # number of replacements
711 system.cpu.l2cache.tags.tagsinuse 29666.734110 # Cycle average of tags in use
712 system.cpu.l2cache.tags.total_refs 3697072 # Total number of references to valid blocks.
713 system.cpu.l2cache.tags.sampled_refs 385254 # Sample count of references to valid blocks.
714 system.cpu.l2cache.tags.avg_refs 9.596453 # Average number of references to valid blocks.
715 system.cpu.l2cache.tags.warmup_cycle 198759422000 # Cycle when the warmup percentage was hit.
716 system.cpu.l2cache.tags.occ_blocks::writebacks 21121.357308 # Average occupied blocks per requestor
717 system.cpu.l2cache.tags.occ_blocks::cpu.inst 222.494139 # Average occupied blocks per requestor
718 system.cpu.l2cache.tags.occ_blocks::cpu.data 8322.882663 # Average occupied blocks per requestor
719 system.cpu.l2cache.tags.occ_percent::writebacks 0.644573 # Average percentage of cache occupancy
720 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.006790 # Average percentage of cache occupancy
721 system.cpu.l2cache.tags.occ_percent::cpu.data 0.253994 # Average percentage of cache occupancy
722 system.cpu.l2cache.tags.occ_percent::total 0.905357 # Average percentage of cache occupancy
723 system.cpu.l2cache.tags.occ_task_id_blocks::1024 32369 # Occupied blocks per task id
724 system.cpu.l2cache.tags.age_task_id_blocks_1024::0 79 # Occupied blocks per task id
725 system.cpu.l2cache.tags.age_task_id_blocks_1024::2 244 # Occupied blocks per task id
726 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 11715 # Occupied blocks per task id
727 system.cpu.l2cache.tags.age_task_id_blocks_1024::4 20331 # Occupied blocks per task id
728 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987823 # Percentage of cache occupancy per task id
729 system.cpu.l2cache.tags.tag_accesses 41235634 # Number of tag accesses
730 system.cpu.l2cache.tags.data_accesses 41235634 # Number of data accesses
731 system.cpu.l2cache.ReadReq_hits::cpu.inst 3694 # number of ReadReq hits
732 system.cpu.l2cache.ReadReq_hits::cpu.data 1586604 # number of ReadReq hits
733 system.cpu.l2cache.ReadReq_hits::total 1590298 # number of ReadReq hits
734 system.cpu.l2cache.Writeback_hits::writebacks 2330645 # number of Writeback hits
735 system.cpu.l2cache.Writeback_hits::total 2330645 # number of Writeback hits
736 system.cpu.l2cache.UpgradeReq_hits::cpu.data 1450 # number of UpgradeReq hits
737 system.cpu.l2cache.UpgradeReq_hits::total 1450 # number of UpgradeReq hits
738 system.cpu.l2cache.ReadExReq_hits::cpu.data 564894 # number of ReadExReq hits
739 system.cpu.l2cache.ReadExReq_hits::total 564894 # number of ReadExReq hits
740 system.cpu.l2cache.demand_hits::cpu.inst 3694 # number of demand (read+write) hits
741 system.cpu.l2cache.demand_hits::cpu.data 2151498 # number of demand (read+write) hits
742 system.cpu.l2cache.demand_hits::total 2155192 # number of demand (read+write) hits
743 system.cpu.l2cache.overall_hits::cpu.inst 3694 # number of overall hits
744 system.cpu.l2cache.overall_hits::cpu.data 2151498 # number of overall hits
745 system.cpu.l2cache.overall_hits::total 2155192 # number of overall hits
746 system.cpu.l2cache.ReadReq_misses::cpu.inst 3155 # number of ReadReq misses
747 system.cpu.l2cache.ReadReq_misses::cpu.data 175578 # number of ReadReq misses
748 system.cpu.l2cache.ReadReq_misses::total 178733 # number of ReadReq misses
749 system.cpu.l2cache.UpgradeReq_misses::cpu.data 136734 # number of UpgradeReq misses
750 system.cpu.l2cache.UpgradeReq_misses::total 136734 # number of UpgradeReq misses
751 system.cpu.l2cache.ReadExReq_misses::cpu.data 206858 # number of ReadExReq misses
752 system.cpu.l2cache.ReadExReq_misses::total 206858 # number of ReadExReq misses
753 system.cpu.l2cache.demand_misses::cpu.inst 3155 # number of demand (read+write) misses
754 system.cpu.l2cache.demand_misses::cpu.data 382436 # number of demand (read+write) misses
755 system.cpu.l2cache.demand_misses::total 385591 # number of demand (read+write) misses
756 system.cpu.l2cache.overall_misses::cpu.inst 3155 # number of overall misses
757 system.cpu.l2cache.overall_misses::cpu.data 382436 # number of overall misses
758 system.cpu.l2cache.overall_misses::total 385591 # number of overall misses
759 system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 234254750 # number of ReadReq miss cycles
760 system.cpu.l2cache.ReadReq_miss_latency::cpu.data 12845252206 # number of ReadReq miss cycles
761 system.cpu.l2cache.ReadReq_miss_latency::total 13079506956 # number of ReadReq miss cycles
762 system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 6557218 # number of UpgradeReq miss cycles
763 system.cpu.l2cache.UpgradeReq_miss_latency::total 6557218 # number of UpgradeReq miss cycles
764 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 14818754478 # number of ReadExReq miss cycles
765 system.cpu.l2cache.ReadExReq_miss_latency::total 14818754478 # number of ReadExReq miss cycles
766 system.cpu.l2cache.demand_miss_latency::cpu.inst 234254750 # number of demand (read+write) miss cycles
767 system.cpu.l2cache.demand_miss_latency::cpu.data 27664006684 # number of demand (read+write) miss cycles
768 system.cpu.l2cache.demand_miss_latency::total 27898261434 # number of demand (read+write) miss cycles
769 system.cpu.l2cache.overall_miss_latency::cpu.inst 234254750 # number of overall miss cycles
770 system.cpu.l2cache.overall_miss_latency::cpu.data 27664006684 # number of overall miss cycles
771 system.cpu.l2cache.overall_miss_latency::total 27898261434 # number of overall miss cycles
772 system.cpu.l2cache.ReadReq_accesses::cpu.inst 6849 # number of ReadReq accesses(hits+misses)
773 system.cpu.l2cache.ReadReq_accesses::cpu.data 1762182 # number of ReadReq accesses(hits+misses)
774 system.cpu.l2cache.ReadReq_accesses::total 1769031 # number of ReadReq accesses(hits+misses)
775 system.cpu.l2cache.Writeback_accesses::writebacks 2330645 # number of Writeback accesses(hits+misses)
776 system.cpu.l2cache.Writeback_accesses::total 2330645 # number of Writeback accesses(hits+misses)
777 system.cpu.l2cache.UpgradeReq_accesses::cpu.data 138184 # number of UpgradeReq accesses(hits+misses)
778 system.cpu.l2cache.UpgradeReq_accesses::total 138184 # number of UpgradeReq accesses(hits+misses)
779 system.cpu.l2cache.ReadExReq_accesses::cpu.data 771752 # number of ReadExReq accesses(hits+misses)
780 system.cpu.l2cache.ReadExReq_accesses::total 771752 # number of ReadExReq accesses(hits+misses)
781 system.cpu.l2cache.demand_accesses::cpu.inst 6849 # number of demand (read+write) accesses
782 system.cpu.l2cache.demand_accesses::cpu.data 2533934 # number of demand (read+write) accesses
783 system.cpu.l2cache.demand_accesses::total 2540783 # number of demand (read+write) accesses
784 system.cpu.l2cache.overall_accesses::cpu.inst 6849 # number of overall (read+write) accesses
785 system.cpu.l2cache.overall_accesses::cpu.data 2533934 # number of overall (read+write) accesses
786 system.cpu.l2cache.overall_accesses::total 2540783 # number of overall (read+write) accesses
787 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.460651 # miss rate for ReadReq accesses
788 system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.099637 # miss rate for ReadReq accesses
789 system.cpu.l2cache.ReadReq_miss_rate::total 0.101034 # miss rate for ReadReq accesses
790 system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.989507 # miss rate for UpgradeReq accesses
791 system.cpu.l2cache.UpgradeReq_miss_rate::total 0.989507 # miss rate for UpgradeReq accesses
792 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.268037 # miss rate for ReadExReq accesses
793 system.cpu.l2cache.ReadExReq_miss_rate::total 0.268037 # miss rate for ReadExReq accesses
794 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.460651 # miss rate for demand accesses
795 system.cpu.l2cache.demand_miss_rate::cpu.data 0.150926 # miss rate for demand accesses
796 system.cpu.l2cache.demand_miss_rate::total 0.151761 # miss rate for demand accesses
797 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.460651 # miss rate for overall accesses
798 system.cpu.l2cache.overall_miss_rate::cpu.data 0.150926 # miss rate for overall accesses
799 system.cpu.l2cache.overall_miss_rate::total 0.151761 # miss rate for overall accesses
800 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74248.732171 # average ReadReq miss latency
801 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73159.804793 # average ReadReq miss latency
802 system.cpu.l2cache.ReadReq_avg_miss_latency::total 73179.026570 # average ReadReq miss latency
803 system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 47.956017 # average UpgradeReq miss latency
804 system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 47.956017 # average UpgradeReq miss latency
805 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71637.328399 # average ReadExReq miss latency
806 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71637.328399 # average ReadExReq miss latency
807 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74248.732171 # average overall miss latency
808 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72336.303810 # average overall miss latency
809 system.cpu.l2cache.demand_avg_miss_latency::total 72351.951768 # average overall miss latency
810 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74248.732171 # average overall miss latency
811 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72336.303810 # average overall miss latency
812 system.cpu.l2cache.overall_avg_miss_latency::total 72351.951768 # average overall miss latency
813 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
814 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
815 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
816 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
817 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
818 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
819 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
820 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
821 system.cpu.l2cache.writebacks::writebacks 293631 # number of writebacks
822 system.cpu.l2cache.writebacks::total 293631 # number of writebacks
823 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3155 # number of ReadReq MSHR misses
824 system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 175578 # number of ReadReq MSHR misses
825 system.cpu.l2cache.ReadReq_mshr_misses::total 178733 # number of ReadReq MSHR misses
826 system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 136734 # number of UpgradeReq MSHR misses
827 system.cpu.l2cache.UpgradeReq_mshr_misses::total 136734 # number of UpgradeReq MSHR misses
828 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206858 # number of ReadExReq MSHR misses
829 system.cpu.l2cache.ReadExReq_mshr_misses::total 206858 # number of ReadExReq MSHR misses
830 system.cpu.l2cache.demand_mshr_misses::cpu.inst 3155 # number of demand (read+write) MSHR misses
831 system.cpu.l2cache.demand_mshr_misses::cpu.data 382436 # number of demand (read+write) MSHR misses
832 system.cpu.l2cache.demand_mshr_misses::total 385591 # number of demand (read+write) MSHR misses
833 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3155 # number of overall MSHR misses
834 system.cpu.l2cache.overall_mshr_misses::cpu.data 382436 # number of overall MSHR misses
835 system.cpu.l2cache.overall_mshr_misses::total 385591 # number of overall MSHR misses
836 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 194803750 # number of ReadReq MSHR miss cycles
837 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 10608113206 # number of ReadReq MSHR miss cycles
838 system.cpu.l2cache.ReadReq_mshr_miss_latency::total 10802916956 # number of ReadReq MSHR miss cycles
839 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1371755972 # number of UpgradeReq MSHR miss cycles
840 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1371755972 # number of UpgradeReq MSHR miss cycles
841 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 12195917522 # number of ReadExReq MSHR miss cycles
842 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 12195917522 # number of ReadExReq MSHR miss cycles
843 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 194803750 # number of demand (read+write) MSHR miss cycles
844 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 22804030728 # number of demand (read+write) MSHR miss cycles
845 system.cpu.l2cache.demand_mshr_miss_latency::total 22998834478 # number of demand (read+write) MSHR miss cycles
846 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 194803750 # number of overall MSHR miss cycles
847 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 22804030728 # number of overall MSHR miss cycles
848 system.cpu.l2cache.overall_mshr_miss_latency::total 22998834478 # number of overall MSHR miss cycles
849 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.460651 # mshr miss rate for ReadReq accesses
850 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.099637 # mshr miss rate for ReadReq accesses
851 system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.101034 # mshr miss rate for ReadReq accesses
852 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.989507 # mshr miss rate for UpgradeReq accesses
853 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.989507 # mshr miss rate for UpgradeReq accesses
854 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.268037 # mshr miss rate for ReadExReq accesses
855 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.268037 # mshr miss rate for ReadExReq accesses
856 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.460651 # mshr miss rate for demand accesses
857 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150926 # mshr miss rate for demand accesses
858 system.cpu.l2cache.demand_mshr_miss_rate::total 0.151761 # mshr miss rate for demand accesses
859 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.460651 # mshr miss rate for overall accesses
860 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150926 # mshr miss rate for overall accesses
861 system.cpu.l2cache.overall_mshr_miss_rate::total 0.151761 # mshr miss rate for overall accesses
862 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61744.453249 # average ReadReq mshr miss latency
863 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60418.236943 # average ReadReq mshr miss latency
864 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60441.647351 # average ReadReq mshr miss latency
865 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10032.296079 # average UpgradeReq mshr miss latency
866 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10032.296079 # average UpgradeReq mshr miss latency
867 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58957.920516 # average ReadExReq mshr miss latency
868 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58957.920516 # average ReadExReq mshr miss latency
869 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61744.453249 # average overall mshr miss latency
870 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59628.358021 # average overall mshr miss latency
871 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59645.672430 # average overall mshr miss latency
872 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61744.453249 # average overall mshr miss latency
873 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59628.358021 # average overall mshr miss latency
874 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59645.672430 # average overall mshr miss latency
875 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
876 system.cpu.dcache.tags.replacements 2529836 # number of replacements
877 system.cpu.dcache.tags.tagsinuse 4088.247019 # Cycle average of tags in use
878 system.cpu.dcache.tags.total_refs 396128893 # Total number of references to valid blocks.
879 system.cpu.dcache.tags.sampled_refs 2533932 # Sample count of references to valid blocks.
880 system.cpu.dcache.tags.avg_refs 156.329725 # Average number of references to valid blocks.
881 system.cpu.dcache.tags.warmup_cycle 1791176250 # Cycle when the warmup percentage was hit.
882 system.cpu.dcache.tags.occ_blocks::cpu.data 4088.247019 # Average occupied blocks per requestor
883 system.cpu.dcache.tags.occ_percent::cpu.data 0.998107 # Average percentage of cache occupancy
884 system.cpu.dcache.tags.occ_percent::total 0.998107 # Average percentage of cache occupancy
885 system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
886 system.cpu.dcache.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id
887 system.cpu.dcache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id
888 system.cpu.dcache.tags.age_task_id_blocks_1024::2 741 # Occupied blocks per task id
889 system.cpu.dcache.tags.age_task_id_blocks_1024::3 3311 # Occupied blocks per task id
890 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
891 system.cpu.dcache.tags.tag_accesses 801380064 # Number of tag accesses
892 system.cpu.dcache.tags.data_accesses 801380064 # Number of data accesses
893 system.cpu.dcache.ReadReq_hits::cpu.data 247376910 # number of ReadReq hits
894 system.cpu.dcache.ReadReq_hits::total 247376910 # number of ReadReq hits
895 system.cpu.dcache.WriteReq_hits::cpu.data 148233547 # number of WriteReq hits
896 system.cpu.dcache.WriteReq_hits::total 148233547 # number of WriteReq hits
897 system.cpu.dcache.demand_hits::cpu.data 395610457 # number of demand (read+write) hits
898 system.cpu.dcache.demand_hits::total 395610457 # number of demand (read+write) hits
899 system.cpu.dcache.overall_hits::cpu.data 395610457 # number of overall hits
900 system.cpu.dcache.overall_hits::total 395610457 # number of overall hits
901 system.cpu.dcache.ReadReq_misses::cpu.data 2885954 # number of ReadReq misses
902 system.cpu.dcache.ReadReq_misses::total 2885954 # number of ReadReq misses
903 system.cpu.dcache.WriteReq_misses::cpu.data 926655 # number of WriteReq misses
904 system.cpu.dcache.WriteReq_misses::total 926655 # number of WriteReq misses
905 system.cpu.dcache.demand_misses::cpu.data 3812609 # number of demand (read+write) misses
906 system.cpu.dcache.demand_misses::total 3812609 # number of demand (read+write) misses
907 system.cpu.dcache.overall_misses::cpu.data 3812609 # number of overall misses
908 system.cpu.dcache.overall_misses::total 3812609 # number of overall misses
909 system.cpu.dcache.ReadReq_miss_latency::cpu.data 57615846746 # number of ReadReq miss cycles
910 system.cpu.dcache.ReadReq_miss_latency::total 57615846746 # number of ReadReq miss cycles
911 system.cpu.dcache.WriteReq_miss_latency::cpu.data 26561972442 # number of WriteReq miss cycles
912 system.cpu.dcache.WriteReq_miss_latency::total 26561972442 # number of WriteReq miss cycles
913 system.cpu.dcache.demand_miss_latency::cpu.data 84177819188 # number of demand (read+write) miss cycles
914 system.cpu.dcache.demand_miss_latency::total 84177819188 # number of demand (read+write) miss cycles
915 system.cpu.dcache.overall_miss_latency::cpu.data 84177819188 # number of overall miss cycles
916 system.cpu.dcache.overall_miss_latency::total 84177819188 # number of overall miss cycles
917 system.cpu.dcache.ReadReq_accesses::cpu.data 250262864 # number of ReadReq accesses(hits+misses)
918 system.cpu.dcache.ReadReq_accesses::total 250262864 # number of ReadReq accesses(hits+misses)
919 system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses)
920 system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses)
921 system.cpu.dcache.demand_accesses::cpu.data 399423066 # number of demand (read+write) accesses
922 system.cpu.dcache.demand_accesses::total 399423066 # number of demand (read+write) accesses
923 system.cpu.dcache.overall_accesses::cpu.data 399423066 # number of overall (read+write) accesses
924 system.cpu.dcache.overall_accesses::total 399423066 # number of overall (read+write) accesses
925 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011532 # miss rate for ReadReq accesses
926 system.cpu.dcache.ReadReq_miss_rate::total 0.011532 # miss rate for ReadReq accesses
927 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006212 # miss rate for WriteReq accesses
928 system.cpu.dcache.WriteReq_miss_rate::total 0.006212 # miss rate for WriteReq accesses
929 system.cpu.dcache.demand_miss_rate::cpu.data 0.009545 # miss rate for demand accesses
930 system.cpu.dcache.demand_miss_rate::total 0.009545 # miss rate for demand accesses
931 system.cpu.dcache.overall_miss_rate::cpu.data 0.009545 # miss rate for overall accesses
932 system.cpu.dcache.overall_miss_rate::total 0.009545 # miss rate for overall accesses
933 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19964.229072 # average ReadReq miss latency
934 system.cpu.dcache.ReadReq_avg_miss_latency::total 19964.229072 # average ReadReq miss latency
935 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28664.359920 # average WriteReq miss latency
936 system.cpu.dcache.WriteReq_avg_miss_latency::total 28664.359920 # average WriteReq miss latency
937 system.cpu.dcache.demand_avg_miss_latency::cpu.data 22078.796747 # average overall miss latency
938 system.cpu.dcache.demand_avg_miss_latency::total 22078.796747 # average overall miss latency
939 system.cpu.dcache.overall_avg_miss_latency::cpu.data 22078.796747 # average overall miss latency
940 system.cpu.dcache.overall_avg_miss_latency::total 22078.796747 # average overall miss latency
941 system.cpu.dcache.blocked_cycles::no_mshrs 6778 # number of cycles access was blocked
942 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
943 system.cpu.dcache.blocked::no_mshrs 684 # number of cycles access was blocked
944 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
945 system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.909357 # average number of cycles each access was blocked
946 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
947 system.cpu.dcache.fast_writes 0 # number of fast writes performed
948 system.cpu.dcache.cache_copies 0 # number of cache copies performed
949 system.cpu.dcache.writebacks::writebacks 2330645 # number of writebacks
950 system.cpu.dcache.writebacks::total 2330645 # number of writebacks
951 system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1123517 # number of ReadReq MSHR hits
952 system.cpu.dcache.ReadReq_mshr_hits::total 1123517 # number of ReadReq MSHR hits
953 system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16974 # number of WriteReq MSHR hits
954 system.cpu.dcache.WriteReq_mshr_hits::total 16974 # number of WriteReq MSHR hits
955 system.cpu.dcache.demand_mshr_hits::cpu.data 1140491 # number of demand (read+write) MSHR hits
956 system.cpu.dcache.demand_mshr_hits::total 1140491 # number of demand (read+write) MSHR hits
957 system.cpu.dcache.overall_mshr_hits::cpu.data 1140491 # number of overall MSHR hits
958 system.cpu.dcache.overall_mshr_hits::total 1140491 # number of overall MSHR hits
959 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1762437 # number of ReadReq MSHR misses
960 system.cpu.dcache.ReadReq_mshr_misses::total 1762437 # number of ReadReq MSHR misses
961 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 909681 # number of WriteReq MSHR misses
962 system.cpu.dcache.WriteReq_mshr_misses::total 909681 # number of WriteReq MSHR misses
963 system.cpu.dcache.demand_mshr_misses::cpu.data 2672118 # number of demand (read+write) MSHR misses
964 system.cpu.dcache.demand_mshr_misses::total 2672118 # number of demand (read+write) MSHR misses
965 system.cpu.dcache.overall_mshr_misses::cpu.data 2672118 # number of overall MSHR misses
966 system.cpu.dcache.overall_mshr_misses::total 2672118 # number of overall MSHR misses
967 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30508505001 # number of ReadReq MSHR miss cycles
968 system.cpu.dcache.ReadReq_mshr_miss_latency::total 30508505001 # number of ReadReq MSHR miss cycles
969 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 24438286308 # number of WriteReq MSHR miss cycles
970 system.cpu.dcache.WriteReq_mshr_miss_latency::total 24438286308 # number of WriteReq MSHR miss cycles
971 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 54946791309 # number of demand (read+write) MSHR miss cycles
972 system.cpu.dcache.demand_mshr_miss_latency::total 54946791309 # number of demand (read+write) MSHR miss cycles
973 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 54946791309 # number of overall MSHR miss cycles
974 system.cpu.dcache.overall_mshr_miss_latency::total 54946791309 # number of overall MSHR miss cycles
975 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007042 # mshr miss rate for ReadReq accesses
976 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007042 # mshr miss rate for ReadReq accesses
977 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006099 # mshr miss rate for WriteReq accesses
978 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006099 # mshr miss rate for WriteReq accesses
979 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006690 # mshr miss rate for demand accesses
980 system.cpu.dcache.demand_mshr_miss_rate::total 0.006690 # mshr miss rate for demand accesses
981 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006690 # mshr miss rate for overall accesses
982 system.cpu.dcache.overall_mshr_miss_rate::total 0.006690 # mshr miss rate for overall accesses
983 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17310.408827 # average ReadReq mshr miss latency
984 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17310.408827 # average ReadReq mshr miss latency
985 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26864.677077 # average WriteReq mshr miss latency
986 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26864.677077 # average WriteReq mshr miss latency
987 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20563.010806 # average overall mshr miss latency
988 system.cpu.dcache.demand_avg_mshr_miss_latency::total 20563.010806 # average overall mshr miss latency
989 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20563.010806 # average overall mshr miss latency
990 system.cpu.dcache.overall_avg_mshr_miss_latency::total 20563.010806 # average overall mshr miss latency
991 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
993 ---------- End Simulation Statistics ----------
projects / gem5.git / blob