2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.403750 # Number of seconds simulated
4 sim_ticks 403750101500 # Number of ticks simulated
5 final_tick 403750101500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 79008 # Simulator instruction rate (inst/s)
8 host_op_rate 146095 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 38578288 # Simulator tick rate (ticks/s)
10 host_mem_usage 372460 # Number of bytes of host memory used
11 host_seconds 10465.73 # Real time elapsed on the host
12 sim_insts 826877109 # Number of instructions simulated
13 sim_ops 1528988701 # Number of ops (including micro ops) simulated
14 system.voltage_domain.voltage 1 # Voltage in Volts
15 system.clk_domain.clock 1000 # Clock period in ticks
16 system.physmem.bytes_read::cpu.inst 163584 # Number of bytes read from this memory
17 system.physmem.bytes_read::cpu.data 24546112 # Number of bytes read from this memory
18 system.physmem.bytes_read::total 24709696 # Number of bytes read from this memory
19 system.physmem.bytes_inst_read::cpu.inst 163584 # Number of instructions bytes read from this memory
20 system.physmem.bytes_inst_read::total 163584 # Number of instructions bytes read from this memory
21 system.physmem.bytes_written::writebacks 18890432 # Number of bytes written to this memory
22 system.physmem.bytes_written::total 18890432 # Number of bytes written to this memory
23 system.physmem.num_reads::cpu.inst 2556 # Number of read requests responded to by this memory
24 system.physmem.num_reads::cpu.data 383533 # Number of read requests responded to by this memory
25 system.physmem.num_reads::total 386089 # Number of read requests responded to by this memory
26 system.physmem.num_writes::writebacks 295163 # Number of write requests responded to by this memory
27 system.physmem.num_writes::total 295163 # Number of write requests responded to by this memory
28 system.physmem.bw_read::cpu.inst 405162 # Total read bandwidth from this memory (bytes/s)
29 system.physmem.bw_read::cpu.data 60795309 # Total read bandwidth from this memory (bytes/s)
30 system.physmem.bw_read::total 61200470 # Total read bandwidth from this memory (bytes/s)
31 system.physmem.bw_inst_read::cpu.inst 405162 # Instruction read bandwidth from this memory (bytes/s)
32 system.physmem.bw_inst_read::total 405162 # Instruction read bandwidth from this memory (bytes/s)
33 system.physmem.bw_write::writebacks 46787436 # Write bandwidth from this memory (bytes/s)
34 system.physmem.bw_write::total 46787436 # Write bandwidth from this memory (bytes/s)
35 system.physmem.bw_total::writebacks 46787436 # Total bandwidth to/from this memory (bytes/s)
36 system.physmem.bw_total::cpu.inst 405162 # Total bandwidth to/from this memory (bytes/s)
37 system.physmem.bw_total::cpu.data 60795309 # Total bandwidth to/from this memory (bytes/s)
38 system.physmem.bw_total::total 107987906 # Total bandwidth to/from this memory (bytes/s)
39 system.physmem.readReqs 386089 # Number of read requests accepted
40 system.physmem.writeReqs 295163 # Number of write requests accepted
41 system.physmem.readBursts 386089 # Number of DRAM read bursts, including those serviced by the write queue
42 system.physmem.writeBursts 295163 # Number of DRAM write bursts, including those merged in the write queue
43 system.physmem.bytesReadDRAM 24690880 # Total number of bytes read from DRAM
44 system.physmem.bytesReadWrQ 18816 # Total number of bytes read from write queue
45 system.physmem.bytesWritten 18889216 # Total number of bytes written to DRAM
46 system.physmem.bytesReadSys 24709696 # Total read bytes from the system interface side
47 system.physmem.bytesWrittenSys 18890432 # Total written bytes from the system interface side
48 system.physmem.servicedByWrQ 294 # Number of DRAM read bursts serviced by the write queue
49 system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
50 system.physmem.neitherReadNorWriteReqs 250150 # Number of requests that are neither read nor write
51 system.physmem.perBankRdBursts::0 24088 # Per bank write bursts
52 system.physmem.perBankRdBursts::1 26446 # Per bank write bursts
53 system.physmem.perBankRdBursts::2 24837 # Per bank write bursts
54 system.physmem.perBankRdBursts::3 24496 # Per bank write bursts
55 system.physmem.perBankRdBursts::4 23228 # Per bank write bursts
56 system.physmem.perBankRdBursts::5 23719 # Per bank write bursts
57 system.physmem.perBankRdBursts::6 24505 # Per bank write bursts
58 system.physmem.perBankRdBursts::7 24301 # Per bank write bursts
59 system.physmem.perBankRdBursts::8 23634 # Per bank write bursts
60 system.physmem.perBankRdBursts::9 23532 # Per bank write bursts
61 system.physmem.perBankRdBursts::10 24794 # Per bank write bursts
62 system.physmem.perBankRdBursts::11 23986 # Per bank write bursts
63 system.physmem.perBankRdBursts::12 23318 # Per bank write bursts
64 system.physmem.perBankRdBursts::13 22932 # Per bank write bursts
65 system.physmem.perBankRdBursts::14 24086 # Per bank write bursts
66 system.physmem.perBankRdBursts::15 23893 # Per bank write bursts
67 system.physmem.perBankWrBursts::0 18617 # Per bank write bursts
68 system.physmem.perBankWrBursts::1 19942 # Per bank write bursts
69 system.physmem.perBankWrBursts::2 19199 # Per bank write bursts
70 system.physmem.perBankWrBursts::3 19026 # Per bank write bursts
71 system.physmem.perBankWrBursts::4 18119 # Per bank write bursts
72 system.physmem.perBankWrBursts::5 18516 # Per bank write bursts
73 system.physmem.perBankWrBursts::6 19139 # Per bank write bursts
74 system.physmem.perBankWrBursts::7 19093 # Per bank write bursts
75 system.physmem.perBankWrBursts::8 18647 # Per bank write bursts
76 system.physmem.perBankWrBursts::9 17956 # Per bank write bursts
77 system.physmem.perBankWrBursts::10 18916 # Per bank write bursts
78 system.physmem.perBankWrBursts::11 17762 # Per bank write bursts
79 system.physmem.perBankWrBursts::12 17409 # Per bank write bursts
80 system.physmem.perBankWrBursts::13 17014 # Per bank write bursts
81 system.physmem.perBankWrBursts::14 17906 # Per bank write bursts
82 system.physmem.perBankWrBursts::15 17883 # Per bank write bursts
83 system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
84 system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
85 system.physmem.totGap 403750059500 # Total gap between requests
86 system.physmem.readPktSize::0 0 # Read request sizes (log2)
87 system.physmem.readPktSize::1 0 # Read request sizes (log2)
88 system.physmem.readPktSize::2 0 # Read request sizes (log2)
89 system.physmem.readPktSize::3 0 # Read request sizes (log2)
90 system.physmem.readPktSize::4 0 # Read request sizes (log2)
91 system.physmem.readPktSize::5 0 # Read request sizes (log2)
92 system.physmem.readPktSize::6 386089 # Read request sizes (log2)
93 system.physmem.writePktSize::0 0 # Write request sizes (log2)
94 system.physmem.writePktSize::1 0 # Write request sizes (log2)
95 system.physmem.writePktSize::2 0 # Write request sizes (log2)
96 system.physmem.writePktSize::3 0 # Write request sizes (log2)
97 system.physmem.writePktSize::4 0 # Write request sizes (log2)
98 system.physmem.writePktSize::5 0 # Write request sizes (log2)
99 system.physmem.writePktSize::6 295163 # Write request sizes (log2)
100 system.physmem.rdQLenPdf::0 380878 # What read queue length does an incoming req see
101 system.physmem.rdQLenPdf::1 4562 # What read queue length does an incoming req see
102 system.physmem.rdQLenPdf::2 308 # What read queue length does an incoming req see
103 system.physmem.rdQLenPdf::3 33 # What read queue length does an incoming req see
104 system.physmem.rdQLenPdf::4 11 # What read queue length does an incoming req see
105 system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see
106 system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
107 system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
108 system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
109 system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
110 system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
111 system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
112 system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
113 system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
114 system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
115 system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
116 system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
117 system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
118 system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
119 system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
120 system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
121 system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
122 system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
123 system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
124 system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
125 system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
126 system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
127 system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
128 system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
129 system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
130 system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
131 system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
132 system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
133 system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
134 system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
135 system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
136 system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
137 system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
138 system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
139 system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
140 system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
141 system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
142 system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
143 system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
144 system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
145 system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
146 system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
147 system.physmem.wrQLenPdf::15 6189 # What write queue length does an incoming req see
148 system.physmem.wrQLenPdf::16 6615 # What write queue length does an incoming req see
149 system.physmem.wrQLenPdf::17 16935 # What write queue length does an incoming req see
150 system.physmem.wrQLenPdf::18 17522 # What write queue length does an incoming req see
151 system.physmem.wrQLenPdf::19 17619 # What write queue length does an incoming req see
152 system.physmem.wrQLenPdf::20 17642 # What write queue length does an incoming req see
153 system.physmem.wrQLenPdf::21 17656 # What write queue length does an incoming req see
154 system.physmem.wrQLenPdf::22 17655 # What write queue length does an incoming req see
155 system.physmem.wrQLenPdf::23 17709 # What write queue length does an incoming req see
156 system.physmem.wrQLenPdf::24 17672 # What write queue length does an incoming req see
157 system.physmem.wrQLenPdf::25 17720 # What write queue length does an incoming req see
158 system.physmem.wrQLenPdf::26 17697 # What write queue length does an incoming req see
159 system.physmem.wrQLenPdf::27 17763 # What write queue length does an incoming req see
160 system.physmem.wrQLenPdf::28 17761 # What write queue length does an incoming req see
161 system.physmem.wrQLenPdf::29 17758 # What write queue length does an incoming req see
162 system.physmem.wrQLenPdf::30 17932 # What write queue length does an incoming req see
163 system.physmem.wrQLenPdf::31 17615 # What write queue length does an incoming req see
164 system.physmem.wrQLenPdf::32 17541 # What write queue length does an incoming req see
165 system.physmem.wrQLenPdf::33 42 # What write queue length does an incoming req see
166 system.physmem.wrQLenPdf::34 22 # What write queue length does an incoming req see
167 system.physmem.wrQLenPdf::35 11 # What write queue length does an incoming req see
168 system.physmem.wrQLenPdf::36 6 # What write queue length does an incoming req see
169 system.physmem.wrQLenPdf::37 11 # What write queue length does an incoming req see
170 system.physmem.wrQLenPdf::38 6 # What write queue length does an incoming req see
171 system.physmem.wrQLenPdf::39 6 # What write queue length does an incoming req see
172 system.physmem.wrQLenPdf::40 5 # What write queue length does an incoming req see
173 system.physmem.wrQLenPdf::41 4 # What write queue length does an incoming req see
174 system.physmem.wrQLenPdf::42 8 # What write queue length does an incoming req see
175 system.physmem.wrQLenPdf::43 5 # What write queue length does an incoming req see
176 system.physmem.wrQLenPdf::44 6 # What write queue length does an incoming req see
177 system.physmem.wrQLenPdf::45 3 # What write queue length does an incoming req see
178 system.physmem.wrQLenPdf::46 2 # What write queue length does an incoming req see
179 system.physmem.wrQLenPdf::47 1 # What write queue length does an incoming req see
180 system.physmem.wrQLenPdf::48 1 # What write queue length does an incoming req see
181 system.physmem.wrQLenPdf::49 2 # What write queue length does an incoming req see
182 system.physmem.wrQLenPdf::50 1 # What write queue length does an incoming req see
183 system.physmem.wrQLenPdf::51 2 # What write queue length does an incoming req see
184 system.physmem.wrQLenPdf::52 1 # What write queue length does an incoming req see
185 system.physmem.wrQLenPdf::53 1 # What write queue length does an incoming req see
186 system.physmem.wrQLenPdf::54 1 # What write queue length does an incoming req see
187 system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
188 system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
189 system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
190 system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
191 system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
192 system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
193 system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
194 system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
195 system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
196 system.physmem.bytesPerActivate::samples 146856 # Bytes accessed per row activation
197 system.physmem.bytesPerActivate::mean 296.750885 # Bytes accessed per row activation
198 system.physmem.bytesPerActivate::gmean 175.556415 # Bytes accessed per row activation
199 system.physmem.bytesPerActivate::stdev 322.540822 # Bytes accessed per row activation
200 system.physmem.bytesPerActivate::0-127 54126 36.86% 36.86% # Bytes accessed per row activation
201 system.physmem.bytesPerActivate::128-255 39800 27.10% 63.96% # Bytes accessed per row activation
202 system.physmem.bytesPerActivate::256-383 13820 9.41% 73.37% # Bytes accessed per row activation
203 system.physmem.bytesPerActivate::384-511 7615 5.19% 78.55% # Bytes accessed per row activation
204 system.physmem.bytesPerActivate::512-639 5593 3.81% 82.36% # Bytes accessed per row activation
205 system.physmem.bytesPerActivate::640-767 4060 2.76% 85.13% # Bytes accessed per row activation
206 system.physmem.bytesPerActivate::768-895 2963 2.02% 87.14% # Bytes accessed per row activation
207 system.physmem.bytesPerActivate::896-1023 2671 1.82% 88.96% # Bytes accessed per row activation
208 system.physmem.bytesPerActivate::1024-1151 16208 11.04% 100.00% # Bytes accessed per row activation
209 system.physmem.bytesPerActivate::total 146856 # Bytes accessed per row activation
210 system.physmem.rdPerTurnAround::samples 17505 # Reads before turning the bus around for writes
211 system.physmem.rdPerTurnAround::mean 22.039017 # Reads before turning the bus around for writes
212 system.physmem.rdPerTurnAround::stdev 217.962707 # Reads before turning the bus around for writes
213 system.physmem.rdPerTurnAround::0-1023 17495 99.94% 99.94% # Reads before turning the bus around for writes
214 system.physmem.rdPerTurnAround::1024-2047 5 0.03% 99.97% # Reads before turning the bus around for writes
215 system.physmem.rdPerTurnAround::3072-4095 3 0.02% 99.99% # Reads before turning the bus around for writes
216 system.physmem.rdPerTurnAround::8192-9215 1 0.01% 99.99% # Reads before turning the bus around for writes
217 system.physmem.rdPerTurnAround::26624-27647 1 0.01% 100.00% # Reads before turning the bus around for writes
218 system.physmem.rdPerTurnAround::total 17505 # Reads before turning the bus around for writes
219 system.physmem.wrPerTurnAround::samples 17505 # Writes before turning the bus around for reads
220 system.physmem.wrPerTurnAround::mean 16.860554 # Writes before turning the bus around for reads
221 system.physmem.wrPerTurnAround::gmean 16.781765 # Writes before turning the bus around for reads
222 system.physmem.wrPerTurnAround::stdev 2.832914 # Writes before turning the bus around for reads
223 system.physmem.wrPerTurnAround::16-19 17316 98.92% 98.92% # Writes before turning the bus around for reads
224 system.physmem.wrPerTurnAround::20-23 135 0.77% 99.69% # Writes before turning the bus around for reads
225 system.physmem.wrPerTurnAround::24-27 27 0.15% 99.85% # Writes before turning the bus around for reads
226 system.physmem.wrPerTurnAround::28-31 7 0.04% 99.89% # Writes before turning the bus around for reads
227 system.physmem.wrPerTurnAround::32-35 3 0.02% 99.90% # Writes before turning the bus around for reads
228 system.physmem.wrPerTurnAround::36-39 3 0.02% 99.92% # Writes before turning the bus around for reads
229 system.physmem.wrPerTurnAround::40-43 1 0.01% 99.93% # Writes before turning the bus around for reads
230 system.physmem.wrPerTurnAround::48-51 1 0.01% 99.93% # Writes before turning the bus around for reads
231 system.physmem.wrPerTurnAround::52-55 1 0.01% 99.94% # Writes before turning the bus around for reads
232 system.physmem.wrPerTurnAround::60-63 2 0.01% 99.95% # Writes before turning the bus around for reads
233 system.physmem.wrPerTurnAround::68-71 1 0.01% 99.95% # Writes before turning the bus around for reads
234 system.physmem.wrPerTurnAround::84-87 1 0.01% 99.96% # Writes before turning the bus around for reads
235 system.physmem.wrPerTurnAround::96-99 1 0.01% 99.97% # Writes before turning the bus around for reads
236 system.physmem.wrPerTurnAround::104-107 1 0.01% 99.97% # Writes before turning the bus around for reads
237 system.physmem.wrPerTurnAround::108-111 1 0.01% 99.98% # Writes before turning the bus around for reads
238 system.physmem.wrPerTurnAround::124-127 2 0.01% 99.99% # Writes before turning the bus around for reads
239 system.physmem.wrPerTurnAround::140-143 1 0.01% 99.99% # Writes before turning the bus around for reads
240 system.physmem.wrPerTurnAround::216-219 1 0.01% 100.00% # Writes before turning the bus around for reads
241 system.physmem.wrPerTurnAround::total 17505 # Writes before turning the bus around for reads
242 system.physmem.totQLat 4284897750 # Total ticks spent queuing
243 system.physmem.totMemAccLat 11518554000 # Total ticks spent from burst creation until serviced by the DRAM
244 system.physmem.totBusLat 1928975000 # Total ticks spent in databus transfers
245 system.physmem.avgQLat 11106.67 # Average queueing delay per DRAM burst
246 system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
247 system.physmem.avgMemAccLat 29856.67 # Average memory access latency per DRAM burst
248 system.physmem.avgRdBW 61.15 # Average DRAM read bandwidth in MiByte/s
249 system.physmem.avgWrBW 46.78 # Average achieved write bandwidth in MiByte/s
250 system.physmem.avgRdBWSys 61.20 # Average system read bandwidth in MiByte/s
251 system.physmem.avgWrBWSys 46.79 # Average system write bandwidth in MiByte/s
252 system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
253 system.physmem.busUtil 0.84 # Data bus utilization in percentage
254 system.physmem.busUtilRead 0.48 # Data bus utilization in percentage for reads
255 system.physmem.busUtilWrite 0.37 # Data bus utilization in percentage for writes
256 system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing
257 system.physmem.avgWrQLen 20.88 # Average write queue length when enqueuing
258 system.physmem.readRowHits 318212 # Number of row buffer hits during reads
259 system.physmem.writeRowHits 215865 # Number of row buffer hits during writes
260 system.physmem.readRowHitRate 82.48 # Row buffer hit rate for reads
261 system.physmem.writeRowHitRate 73.13 # Row buffer hit rate for writes
262 system.physmem.avgGap 592658.90 # Average gap between requests
263 system.physmem.pageHitRate 78.43 # Row buffer hit rate, read and write combined
264 system.physmem_0.actEnergy 568406160 # Energy for activate commands per rank (pJ)
265 system.physmem_0.preEnergy 310142250 # Energy for precharge commands per rank (pJ)
266 system.physmem_0.readEnergy 1525828200 # Energy for read commands per rank (pJ)
267 system.physmem_0.writeEnergy 982679040 # Energy for write commands per rank (pJ)
268 system.physmem_0.refreshEnergy 26370870240 # Energy for refresh commands per rank (pJ)
269 system.physmem_0.actBackEnergy 62107024725 # Energy for active background per rank (pJ)
270 system.physmem_0.preBackEnergy 187769234250 # Energy for precharge background per rank (pJ)
271 system.physmem_0.totalEnergy 279634184865 # Total energy per rank (pJ)
272 system.physmem_0.averagePower 692.595037 # Core power per rank (mW)
273 system.physmem_0.memoryStateTime::IDLE 311821526250 # Time in different power states
274 system.physmem_0.memoryStateTime::REF 13482040000 # Time in different power states
275 system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
276 system.physmem_0.memoryStateTime::ACT 78445652750 # Time in different power states
277 system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
278 system.physmem_1.actEnergy 541726920 # Energy for activate commands per rank (pJ)
279 system.physmem_1.preEnergy 295585125 # Energy for precharge commands per rank (pJ)
280 system.physmem_1.readEnergy 1483162200 # Energy for read commands per rank (pJ)
281 system.physmem_1.writeEnergy 929646720 # Energy for write commands per rank (pJ)
282 system.physmem_1.refreshEnergy 26370870240 # Energy for refresh commands per rank (pJ)
283 system.physmem_1.actBackEnergy 60264291960 # Energy for active background per rank (pJ)
284 system.physmem_1.preBackEnergy 189385666500 # Energy for precharge background per rank (pJ)
285 system.physmem_1.totalEnergy 279270949665 # Total energy per rank (pJ)
286 system.physmem_1.averagePower 691.695380 # Core power per rank (mW)
287 system.physmem_1.memoryStateTime::IDLE 314524575500 # Time in different power states
288 system.physmem_1.memoryStateTime::REF 13482040000 # Time in different power states
289 system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
290 system.physmem_1.memoryStateTime::ACT 75741865750 # Time in different power states
291 system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
292 system.cpu.branchPred.lookups 219275491 # Number of BP lookups
293 system.cpu.branchPred.condPredicted 219275491 # Number of conditional branches predicted
294 system.cpu.branchPred.condIncorrect 8530842 # Number of conditional branches incorrect
295 system.cpu.branchPred.BTBLookups 123996876 # Number of BTB lookups
296 system.cpu.branchPred.BTBHits 121809369 # Number of BTB hits
297 system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
298 system.cpu.branchPred.BTBHitPct 98.235837 # BTB Hit Percentage
299 system.cpu.branchPred.usedRAS 27061771 # Number of times the RAS was used to get a target.
300 system.cpu.branchPred.RASInCorrect 1406477 # Number of incorrect RAS predictions.
301 system.cpu_clk_domain.clock 500 # Clock period in ticks
302 system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
303 system.cpu.workload.num_syscalls 551 # Number of system calls
304 system.cpu.numCycles 807500204 # number of cpu cycles simulated
305 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
306 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
307 system.cpu.fetch.icacheStallCycles 175896513 # Number of cycles fetch is stalled on an Icache miss
308 system.cpu.fetch.Insts 1208663738 # Number of instructions fetch has processed
309 system.cpu.fetch.Branches 219275491 # Number of branches that fetch encountered
310 system.cpu.fetch.predictedBranches 148871140 # Number of branches that fetch has predicted taken
311 system.cpu.fetch.Cycles 621734900 # Number of cycles fetch has run and was not squashing or blocked
312 system.cpu.fetch.SquashCycles 17770351 # Number of cycles fetch has spent squashing
313 system.cpu.fetch.TlbCycles 224 # Number of cycles fetch has spent waiting for tlb
314 system.cpu.fetch.MiscStallCycles 92919 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
315 system.cpu.fetch.PendingTrapStallCycles 734617 # Number of stall cycles due to pending traps
316 system.cpu.fetch.PendingQuiesceStallCycles 1497 # Number of stall cycles due to pending quiesce instructions
317 system.cpu.fetch.IcacheWaitRetryStallCycles 41 # Number of stall cycles due to full MSHR
318 system.cpu.fetch.CacheLines 170765697 # Number of cache lines fetched
319 system.cpu.fetch.IcacheSquashes 2319587 # Number of outstanding Icache misses that were squashed
320 system.cpu.fetch.ItlbSquashes 3 # Number of outstanding ITLB misses that were squashed
321 system.cpu.fetch.rateDist::samples 807345886 # Number of instructions fetched each cycle (Total)
322 system.cpu.fetch.rateDist::mean 2.785599 # Number of instructions fetched each cycle (Total)
323 system.cpu.fetch.rateDist::stdev 3.367664 # Number of instructions fetched each cycle (Total)
324 system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
325 system.cpu.fetch.rateDist::0 417315550 51.69% 51.69% # Number of instructions fetched each cycle (Total)
326 system.cpu.fetch.rateDist::1 32556197 4.03% 55.72% # Number of instructions fetched each cycle (Total)
327 system.cpu.fetch.rateDist::2 31914797 3.95% 59.68% # Number of instructions fetched each cycle (Total)
328 system.cpu.fetch.rateDist::3 32648264 4.04% 63.72% # Number of instructions fetched each cycle (Total)
329 system.cpu.fetch.rateDist::4 26601298 3.29% 67.01% # Number of instructions fetched each cycle (Total)
330 system.cpu.fetch.rateDist::5 26865092 3.33% 70.34% # Number of instructions fetched each cycle (Total)
331 system.cpu.fetch.rateDist::6 35140610 4.35% 74.69% # Number of instructions fetched each cycle (Total)
332 system.cpu.fetch.rateDist::7 31395380 3.89% 78.58% # Number of instructions fetched each cycle (Total)
333 system.cpu.fetch.rateDist::8 172908698 21.42% 100.00% # Number of instructions fetched each cycle (Total)
334 system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
335 system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
336 system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
337 system.cpu.fetch.rateDist::total 807345886 # Number of instructions fetched each cycle (Total)
338 system.cpu.fetch.branchRate 0.271549 # Number of branch fetches per cycle
339 system.cpu.fetch.rate 1.496797 # Number of inst fetches per cycle
340 system.cpu.decode.IdleCycles 120455538 # Number of cycles decode is idle
341 system.cpu.decode.BlockedCycles 370723147 # Number of cycles decode is blocked
342 system.cpu.decode.RunCycles 225174137 # Number of cycles decode is running
343 system.cpu.decode.UnblockCycles 82107889 # Number of cycles decode is unblocking
344 system.cpu.decode.SquashCycles 8885175 # Number of cycles decode is squashing
345 system.cpu.decode.DecodedInsts 2132090689 # Number of instructions handled by decode
346 system.cpu.rename.SquashCycles 8885175 # Number of cycles rename is squashing
347 system.cpu.rename.IdleCycles 152508786 # Number of cycles rename is idle
348 system.cpu.rename.BlockCycles 150703188 # Number of cycles rename is blocking
349 system.cpu.rename.serializeStallCycles 44276 # count of cycles rename stalled for serializing inst
350 system.cpu.rename.RunCycles 271505228 # Number of cycles rename is running
351 system.cpu.rename.UnblockCycles 223699233 # Number of cycles rename is unblocking
352 system.cpu.rename.RenamedInsts 2088450374 # Number of instructions processed by rename
353 system.cpu.rename.ROBFullEvents 134027 # Number of times rename has blocked due to ROB full
354 system.cpu.rename.IQFullEvents 138145056 # Number of times rename has blocked due to IQ full
355 system.cpu.rename.LQFullEvents 24847890 # Number of times rename has blocked due to LQ full
356 system.cpu.rename.SQFullEvents 50675847 # Number of times rename has blocked due to SQ full
357 system.cpu.rename.RenamedOperands 2190623948 # Number of destination operands rename has renamed
358 system.cpu.rename.RenameLookups 5277971052 # Number of register rename lookups that rename has made
359 system.cpu.rename.int_rename_lookups 3356955770 # Number of integer rename lookups
360 system.cpu.rename.fp_rename_lookups 59583 # Number of floating rename lookups
361 system.cpu.rename.CommittedMaps 1614040854 # Number of HB maps that are committed
362 system.cpu.rename.UndoneMaps 576583094 # Number of HB maps that are undone due to squashing
363 system.cpu.rename.serializingInsts 3244 # count of serializing insts renamed
364 system.cpu.rename.tempSerializingInsts 3058 # count of temporary serializing insts renamed
365 system.cpu.rename.skidInsts 422095496 # count of insts added to the skid buffer
366 system.cpu.memDep0.insertedLoads 507123971 # Number of loads inserted to the mem dependence unit.
367 system.cpu.memDep0.insertedStores 200816092 # Number of stores inserted to the mem dependence unit.
368 system.cpu.memDep0.conflictingLoads 229029695 # Number of conflicting loads.
369 system.cpu.memDep0.conflictingStores 68201156 # Number of conflicting stores.
370 system.cpu.iq.iqInstsAdded 2023089277 # Number of instructions added to the IQ (excludes non-spec)
371 system.cpu.iq.iqNonSpecInstsAdded 22810 # Number of non-speculative instructions added to the IQ
372 system.cpu.iq.iqInstsIssued 1789046992 # Number of instructions issued
373 system.cpu.iq.iqSquashedInstsIssued 413186 # Number of squashed instructions issued
374 system.cpu.iq.iqSquashedInstsExamined 494123386 # Number of squashed instructions iterated over during squash; mainly for profiling
375 system.cpu.iq.iqSquashedOperandsExamined 832685562 # Number of squashed operands that are examined and possibly removed from graph
376 system.cpu.iq.iqSquashedNonSpecRemoved 22258 # Number of squashed non-spec instructions that were removed
377 system.cpu.iq.issued_per_cycle::samples 807345886 # Number of insts issued each cycle
378 system.cpu.iq.issued_per_cycle::mean 2.215961 # Number of insts issued each cycle
379 system.cpu.iq.issued_per_cycle::stdev 2.071124 # Number of insts issued each cycle
380 system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
381 system.cpu.iq.issued_per_cycle::0 238839063 29.58% 29.58% # Number of insts issued each cycle
382 system.cpu.iq.issued_per_cycle::1 123555302 15.30% 44.89% # Number of insts issued each cycle
383 system.cpu.iq.issued_per_cycle::2 118726852 14.71% 59.59% # Number of insts issued each cycle
384 system.cpu.iq.issued_per_cycle::3 107721401 13.34% 72.94% # Number of insts issued each cycle
385 system.cpu.iq.issued_per_cycle::4 89742056 11.12% 84.05% # Number of insts issued each cycle
386 system.cpu.iq.issued_per_cycle::5 60203262 7.46% 91.51% # Number of insts issued each cycle
387 system.cpu.iq.issued_per_cycle::6 42304747 5.24% 96.75% # Number of insts issued each cycle
388 system.cpu.iq.issued_per_cycle::7 18964857 2.35% 99.10% # Number of insts issued each cycle
389 system.cpu.iq.issued_per_cycle::8 7288346 0.90% 100.00% # Number of insts issued each cycle
390 system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
391 system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
392 system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
393 system.cpu.iq.issued_per_cycle::total 807345886 # Number of insts issued each cycle
394 system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
395 system.cpu.iq.fu_full::IntAlu 11498108 42.65% 42.65% # attempts to use FU when none available
396 system.cpu.iq.fu_full::IntMult 0 0.00% 42.65% # attempts to use FU when none available
397 system.cpu.iq.fu_full::IntDiv 0 0.00% 42.65% # attempts to use FU when none available
398 system.cpu.iq.fu_full::FloatAdd 0 0.00% 42.65% # attempts to use FU when none available
399 system.cpu.iq.fu_full::FloatCmp 0 0.00% 42.65% # attempts to use FU when none available
400 system.cpu.iq.fu_full::FloatCvt 0 0.00% 42.65% # attempts to use FU when none available
401 system.cpu.iq.fu_full::FloatMult 0 0.00% 42.65% # attempts to use FU when none available
402 system.cpu.iq.fu_full::FloatDiv 0 0.00% 42.65% # attempts to use FU when none available
403 system.cpu.iq.fu_full::FloatSqrt 0 0.00% 42.65% # attempts to use FU when none available
404 system.cpu.iq.fu_full::SimdAdd 0 0.00% 42.65% # attempts to use FU when none available
405 system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 42.65% # attempts to use FU when none available
406 system.cpu.iq.fu_full::SimdAlu 0 0.00% 42.65% # attempts to use FU when none available
407 system.cpu.iq.fu_full::SimdCmp 0 0.00% 42.65% # attempts to use FU when none available
408 system.cpu.iq.fu_full::SimdCvt 0 0.00% 42.65% # attempts to use FU when none available
409 system.cpu.iq.fu_full::SimdMisc 0 0.00% 42.65% # attempts to use FU when none available
410 system.cpu.iq.fu_full::SimdMult 0 0.00% 42.65% # attempts to use FU when none available
411 system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 42.65% # attempts to use FU when none available
412 system.cpu.iq.fu_full::SimdShift 0 0.00% 42.65% # attempts to use FU when none available
413 system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 42.65% # attempts to use FU when none available
414 system.cpu.iq.fu_full::SimdSqrt 0 0.00% 42.65% # attempts to use FU when none available
415 system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 42.65% # attempts to use FU when none available
416 system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 42.65% # attempts to use FU when none available
417 system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 42.65% # attempts to use FU when none available
418 system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 42.65% # attempts to use FU when none available
419 system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 42.65% # attempts to use FU when none available
420 system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 42.65% # attempts to use FU when none available
421 system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 42.65% # attempts to use FU when none available
422 system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 42.65% # attempts to use FU when none available
423 system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 42.65% # attempts to use FU when none available
424 system.cpu.iq.fu_full::MemRead 12352662 45.82% 88.47% # attempts to use FU when none available
425 system.cpu.iq.fu_full::MemWrite 3109525 11.53% 100.00% # attempts to use FU when none available
426 system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
427 system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
428 system.cpu.iq.FU_type_0::No_OpClass 2715586 0.15% 0.15% # Type of FU issued
429 system.cpu.iq.FU_type_0::IntAlu 1183095329 66.13% 66.28% # Type of FU issued
430 system.cpu.iq.FU_type_0::IntMult 369789 0.02% 66.30% # Type of FU issued
431 system.cpu.iq.FU_type_0::IntDiv 3881135 0.22% 66.52% # Type of FU issued
432 system.cpu.iq.FU_type_0::FloatAdd 131 0.00% 66.52% # Type of FU issued
433 system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.52% # Type of FU issued
434 system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.52% # Type of FU issued
435 system.cpu.iq.FU_type_0::FloatMult 62 0.00% 66.52% # Type of FU issued
436 system.cpu.iq.FU_type_0::FloatDiv 375 0.00% 66.52% # Type of FU issued
437 system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.52% # Type of FU issued
438 system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.52% # Type of FU issued
439 system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.52% # Type of FU issued
440 system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.52% # Type of FU issued
441 system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.52% # Type of FU issued
442 system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.52% # Type of FU issued
443 system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.52% # Type of FU issued
444 system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.52% # Type of FU issued
445 system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.52% # Type of FU issued
446 system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.52% # Type of FU issued
447 system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.52% # Type of FU issued
448 system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.52% # Type of FU issued
449 system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.52% # Type of FU issued
450 system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.52% # Type of FU issued
451 system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.52% # Type of FU issued
452 system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.52% # Type of FU issued
453 system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.52% # Type of FU issued
454 system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.52% # Type of FU issued
455 system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.52% # Type of FU issued
456 system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.52% # Type of FU issued
457 system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.52% # Type of FU issued
458 system.cpu.iq.FU_type_0::MemRead 428554849 23.95% 90.47% # Type of FU issued
459 system.cpu.iq.FU_type_0::MemWrite 170429736 9.53% 100.00% # Type of FU issued
460 system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
461 system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
462 system.cpu.iq.FU_type_0::total 1789046992 # Type of FU issued
463 system.cpu.iq.rate 2.215538 # Inst issue rate
464 system.cpu.iq.fu_busy_cnt 26960295 # FU busy when requested
465 system.cpu.iq.fu_busy_rate 0.015070 # FU busy rate (busy events/executed inst)
466 system.cpu.iq.int_inst_queue_reads 4412783736 # Number of integer instruction queue reads
467 system.cpu.iq.int_inst_queue_writes 2517485001 # Number of integer instruction queue writes
468 system.cpu.iq.int_inst_queue_wakeup_accesses 1762397634 # Number of integer instruction queue wakeup accesses
469 system.cpu.iq.fp_inst_queue_reads 29615 # Number of floating instruction queue reads
470 system.cpu.iq.fp_inst_queue_writes 68960 # Number of floating instruction queue writes
471 system.cpu.iq.fp_inst_queue_wakeup_accesses 5614 # Number of floating instruction queue wakeup accesses
472 system.cpu.iq.int_alu_accesses 1813278705 # Number of integer alu accesses
473 system.cpu.iq.fp_alu_accesses 12996 # Number of floating point alu accesses
474 system.cpu.iew.lsq.thread0.forwLoads 186120882 # Number of loads that had data forwarded from stores
475 system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
476 system.cpu.iew.lsq.thread0.squashedLoads 123024315 # Number of loads squashed
477 system.cpu.iew.lsq.thread0.ignoredResponses 213288 # Number of memory responses ignored because the instruction is squashed
478 system.cpu.iew.lsq.thread0.memOrderViolation 372216 # Number of memory ordering violations
479 system.cpu.iew.lsq.thread0.squashedStores 51655906 # Number of stores squashed
480 system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
481 system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
482 system.cpu.iew.lsq.thread0.rescheduledLoads 23026 # Number of loads that were rescheduled
483 system.cpu.iew.lsq.thread0.cacheBlocked 1152 # Number of times an access to memory failed due to the cache being blocked
484 system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
485 system.cpu.iew.iewSquashCycles 8885175 # Number of cycles IEW is squashing
486 system.cpu.iew.iewBlockCycles 97857746 # Number of cycles IEW is blocking
487 system.cpu.iew.iewUnblockCycles 6188485 # Number of cycles IEW is unblocking
488 system.cpu.iew.iewDispatchedInsts 2023112087 # Number of instructions dispatched to IQ
489 system.cpu.iew.iewDispSquashedInsts 370282 # Number of squashed instructions skipped by dispatch
490 system.cpu.iew.iewDispLoadInsts 507126472 # Number of dispatched load instructions
491 system.cpu.iew.iewDispStoreInsts 200816092 # Number of dispatched store instructions
492 system.cpu.iew.iewDispNonSpecInsts 7124 # Number of dispatched non-speculative instructions
493 system.cpu.iew.iewIQFullEvents 1833420 # Number of times the IQ has become full, causing a stall
494 system.cpu.iew.iewLSQFullEvents 3447634 # Number of times the LSQ has become full, causing a stall
495 system.cpu.iew.memOrderViolationEvents 372216 # Number of memory order violations
496 system.cpu.iew.predictedTakenIncorrect 4845141 # Number of branches that were predicted taken incorrectly
497 system.cpu.iew.predictedNotTakenIncorrect 4138975 # Number of branches that were predicted not taken incorrectly
498 system.cpu.iew.branchMispredicts 8984116 # Number of branch mispredicts detected at execute
499 system.cpu.iew.iewExecutedInsts 1770027933 # Number of executed instructions
500 system.cpu.iew.iewExecLoadInsts 423156069 # Number of load instructions executed
501 system.cpu.iew.iewExecSquashedInsts 19019059 # Number of squashed instructions skipped in execute
502 system.cpu.iew.exec_swp 0 # number of swp insts executed
503 system.cpu.iew.exec_nop 0 # number of nop insts executed
504 system.cpu.iew.exec_refs 590393535 # number of memory reference insts executed
505 system.cpu.iew.exec_branches 168976878 # Number of branches executed
506 system.cpu.iew.exec_stores 167237466 # Number of stores executed
507 system.cpu.iew.exec_rate 2.191985 # Inst execution rate
508 system.cpu.iew.wb_sent 1766902573 # cumulative count of insts sent to commit
509 system.cpu.iew.wb_count 1762403248 # cumulative count of insts written-back
510 system.cpu.iew.wb_producers 1339734836 # num instructions producing a value
511 system.cpu.iew.wb_consumers 2050019870 # num instructions consuming a value
512 system.cpu.iew.wb_rate 2.182542 # insts written-back per cycle
513 system.cpu.iew.wb_fanout 0.653523 # average fanout of values written-back
514 system.cpu.commit.commitSquashedInsts 494186003 # The number of squashed insts skipped by commit
515 system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards
516 system.cpu.commit.branchMispredicts 8613223 # The number of times a branch was mispredicted
517 system.cpu.commit.committed_per_cycle::samples 740134628 # Number of insts commited each cycle
518 system.cpu.commit.committed_per_cycle::mean 2.065825 # Number of insts commited each cycle
519 system.cpu.commit.committed_per_cycle::stdev 2.576078 # Number of insts commited each cycle
520 system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
521 system.cpu.commit.committed_per_cycle::0 276181742 37.32% 37.32% # Number of insts commited each cycle
522 system.cpu.commit.committed_per_cycle::1 172028130 23.24% 60.56% # Number of insts commited each cycle
523 system.cpu.commit.committed_per_cycle::2 55891908 7.55% 68.11% # Number of insts commited each cycle
524 system.cpu.commit.committed_per_cycle::3 86294140 11.66% 79.77% # Number of insts commited each cycle
525 system.cpu.commit.committed_per_cycle::4 25858762 3.49% 83.26% # Number of insts commited each cycle
526 system.cpu.commit.committed_per_cycle::5 26505188 3.58% 86.84% # Number of insts commited each cycle
527 system.cpu.commit.committed_per_cycle::6 9830635 1.33% 88.17% # Number of insts commited each cycle
528 system.cpu.commit.committed_per_cycle::7 9003447 1.22% 89.39% # Number of insts commited each cycle
529 system.cpu.commit.committed_per_cycle::8 78540676 10.61% 100.00% # Number of insts commited each cycle
530 system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
531 system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
532 system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
533 system.cpu.commit.committed_per_cycle::total 740134628 # Number of insts commited each cycle
534 system.cpu.commit.committedInsts 826877109 # Number of instructions committed
535 system.cpu.commit.committedOps 1528988701 # Number of ops (including micro ops) committed
536 system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
537 system.cpu.commit.refs 533262343 # Number of memory references committed
538 system.cpu.commit.loads 384102157 # Number of loads committed
539 system.cpu.commit.membars 0 # Number of memory barriers committed
540 system.cpu.commit.branches 149758583 # Number of branches committed
541 system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
542 system.cpu.commit.int_insts 1526605509 # Number of committed integer instructions.
543 system.cpu.commit.function_calls 17673145 # Number of function calls committed.
544 system.cpu.commit.op_class_0::No_OpClass 1819099 0.12% 0.12% # Class of committed instruction
545 system.cpu.commit.op_class_0::IntAlu 989721889 64.73% 64.85% # Class of committed instruction
546 system.cpu.commit.op_class_0::IntMult 306834 0.02% 64.87% # Class of committed instruction
547 system.cpu.commit.op_class_0::IntDiv 3878536 0.25% 65.12% # Class of committed instruction
548 system.cpu.commit.op_class_0::FloatAdd 0 0.00% 65.12% # Class of committed instruction
549 system.cpu.commit.op_class_0::FloatCmp 0 0.00% 65.12% # Class of committed instruction
550 system.cpu.commit.op_class_0::FloatCvt 0 0.00% 65.12% # Class of committed instruction
551 system.cpu.commit.op_class_0::FloatMult 0 0.00% 65.12% # Class of committed instruction
552 system.cpu.commit.op_class_0::FloatDiv 0 0.00% 65.12% # Class of committed instruction
553 system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 65.12% # Class of committed instruction
554 system.cpu.commit.op_class_0::SimdAdd 0 0.00% 65.12% # Class of committed instruction
555 system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 65.12% # Class of committed instruction
556 system.cpu.commit.op_class_0::SimdAlu 0 0.00% 65.12% # Class of committed instruction
557 system.cpu.commit.op_class_0::SimdCmp 0 0.00% 65.12% # Class of committed instruction
558 system.cpu.commit.op_class_0::SimdCvt 0 0.00% 65.12% # Class of committed instruction
559 system.cpu.commit.op_class_0::SimdMisc 0 0.00% 65.12% # Class of committed instruction
560 system.cpu.commit.op_class_0::SimdMult 0 0.00% 65.12% # Class of committed instruction
561 system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 65.12% # Class of committed instruction
562 system.cpu.commit.op_class_0::SimdShift 0 0.00% 65.12% # Class of committed instruction
563 system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 65.12% # Class of committed instruction
564 system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 65.12% # Class of committed instruction
565 system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 65.12% # Class of committed instruction
566 system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 65.12% # Class of committed instruction
567 system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 65.12% # Class of committed instruction
568 system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 65.12% # Class of committed instruction
569 system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 65.12% # Class of committed instruction
570 system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 65.12% # Class of committed instruction
571 system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 65.12% # Class of committed instruction
572 system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.12% # Class of committed instruction
573 system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.12% # Class of committed instruction
574 system.cpu.commit.op_class_0::MemRead 384102157 25.12% 90.24% # Class of committed instruction
575 system.cpu.commit.op_class_0::MemWrite 149160186 9.76% 100.00% # Class of committed instruction
576 system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
577 system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
578 system.cpu.commit.op_class_0::total 1528988701 # Class of committed instruction
579 system.cpu.commit.bw_lim_events 78540676 # number cycles where commit BW limit reached
580 system.cpu.rob.rob_reads 2684768656 # The number of ROB reads
581 system.cpu.rob.rob_writes 4113734804 # The number of ROB writes
582 system.cpu.timesIdled 1976 # Number of times that the entire CPU went into an idle state and unscheduled itself
583 system.cpu.idleCycles 154318 # Total number of cycles that the CPU has spent unscheduled due to idling
584 system.cpu.committedInsts 826877109 # Number of Instructions Simulated
585 system.cpu.committedOps 1528988701 # Number of Ops (including micro ops) Simulated
586 system.cpu.cpi 0.976566 # CPI: Cycles Per Instruction
587 system.cpu.cpi_total 0.976566 # CPI: Total CPI of All Threads
588 system.cpu.ipc 1.023996 # IPC: Instructions Per Cycle
589 system.cpu.ipc_total 1.023996 # IPC: Total IPC of All Threads
590 system.cpu.int_regfile_reads 2722734844 # number of integer regfile reads
591 system.cpu.int_regfile_writes 1435842493 # number of integer regfile writes
592 system.cpu.fp_regfile_reads 5827 # number of floating regfile reads
593 system.cpu.fp_regfile_writes 544 # number of floating regfile writes
594 system.cpu.cc_regfile_reads 596643147 # number of cc regfile reads
595 system.cpu.cc_regfile_writes 405466657 # number of cc regfile writes
596 system.cpu.misc_regfile_reads 971667313 # number of misc regfile reads
597 system.cpu.misc_regfile_writes 1 # number of misc regfile writes
598 system.cpu.dcache.tags.replacements 2531012 # number of replacements
599 system.cpu.dcache.tags.tagsinuse 4087.814248 # Cycle average of tags in use
600 system.cpu.dcache.tags.total_refs 381842819 # Total number of references to valid blocks.
601 system.cpu.dcache.tags.sampled_refs 2535108 # Sample count of references to valid blocks.
602 system.cpu.dcache.tags.avg_refs 150.621914 # Average number of references to valid blocks.
603 system.cpu.dcache.tags.warmup_cycle 1673396500 # Cycle when the warmup percentage was hit.
604 system.cpu.dcache.tags.occ_blocks::cpu.data 4087.814248 # Average occupied blocks per requestor
605 system.cpu.dcache.tags.occ_percent::cpu.data 0.998002 # Average percentage of cache occupancy
606 system.cpu.dcache.tags.occ_percent::total 0.998002 # Average percentage of cache occupancy
607 system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
608 system.cpu.dcache.tags.age_task_id_blocks_1024::0 28 # Occupied blocks per task id
609 system.cpu.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id
610 system.cpu.dcache.tags.age_task_id_blocks_1024::2 871 # Occupied blocks per task id
611 system.cpu.dcache.tags.age_task_id_blocks_1024::3 3171 # Occupied blocks per task id
612 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
613 system.cpu.dcache.tags.tag_accesses 772778472 # Number of tag accesses
614 system.cpu.dcache.tags.data_accesses 772778472 # Number of data accesses
615 system.cpu.dcache.ReadReq_hits::cpu.data 233189012 # number of ReadReq hits
616 system.cpu.dcache.ReadReq_hits::total 233189012 # number of ReadReq hits
617 system.cpu.dcache.WriteReq_hits::cpu.data 148175395 # number of WriteReq hits
618 system.cpu.dcache.WriteReq_hits::total 148175395 # number of WriteReq hits
619 system.cpu.dcache.demand_hits::cpu.data 381364407 # number of demand (read+write) hits
620 system.cpu.dcache.demand_hits::total 381364407 # number of demand (read+write) hits
621 system.cpu.dcache.overall_hits::cpu.data 381364407 # number of overall hits
622 system.cpu.dcache.overall_hits::total 381364407 # number of overall hits
623 system.cpu.dcache.ReadReq_misses::cpu.data 2772468 # number of ReadReq misses
624 system.cpu.dcache.ReadReq_misses::total 2772468 # number of ReadReq misses
625 system.cpu.dcache.WriteReq_misses::cpu.data 984807 # number of WriteReq misses
626 system.cpu.dcache.WriteReq_misses::total 984807 # number of WriteReq misses
627 system.cpu.dcache.demand_misses::cpu.data 3757275 # number of demand (read+write) misses
628 system.cpu.dcache.demand_misses::total 3757275 # number of demand (read+write) misses
629 system.cpu.dcache.overall_misses::cpu.data 3757275 # number of overall misses
630 system.cpu.dcache.overall_misses::total 3757275 # number of overall misses
631 system.cpu.dcache.ReadReq_miss_latency::cpu.data 59137035000 # number of ReadReq miss cycles
632 system.cpu.dcache.ReadReq_miss_latency::total 59137035000 # number of ReadReq miss cycles
633 system.cpu.dcache.WriteReq_miss_latency::cpu.data 31243406496 # number of WriteReq miss cycles
634 system.cpu.dcache.WriteReq_miss_latency::total 31243406496 # number of WriteReq miss cycles
635 system.cpu.dcache.demand_miss_latency::cpu.data 90380441496 # number of demand (read+write) miss cycles
636 system.cpu.dcache.demand_miss_latency::total 90380441496 # number of demand (read+write) miss cycles
637 system.cpu.dcache.overall_miss_latency::cpu.data 90380441496 # number of overall miss cycles
638 system.cpu.dcache.overall_miss_latency::total 90380441496 # number of overall miss cycles
639 system.cpu.dcache.ReadReq_accesses::cpu.data 235961480 # number of ReadReq accesses(hits+misses)
640 system.cpu.dcache.ReadReq_accesses::total 235961480 # number of ReadReq accesses(hits+misses)
641 system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses)
642 system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses)
643 system.cpu.dcache.demand_accesses::cpu.data 385121682 # number of demand (read+write) accesses
644 system.cpu.dcache.demand_accesses::total 385121682 # number of demand (read+write) accesses
645 system.cpu.dcache.overall_accesses::cpu.data 385121682 # number of overall (read+write) accesses
646 system.cpu.dcache.overall_accesses::total 385121682 # number of overall (read+write) accesses
647 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011750 # miss rate for ReadReq accesses
648 system.cpu.dcache.ReadReq_miss_rate::total 0.011750 # miss rate for ReadReq accesses
649 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006602 # miss rate for WriteReq accesses
650 system.cpu.dcache.WriteReq_miss_rate::total 0.006602 # miss rate for WriteReq accesses
651 system.cpu.dcache.demand_miss_rate::cpu.data 0.009756 # miss rate for demand accesses
652 system.cpu.dcache.demand_miss_rate::total 0.009756 # miss rate for demand accesses
653 system.cpu.dcache.overall_miss_rate::cpu.data 0.009756 # miss rate for overall accesses
654 system.cpu.dcache.overall_miss_rate::total 0.009756 # miss rate for overall accesses
655 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21330.105523 # average ReadReq miss latency
656 system.cpu.dcache.ReadReq_avg_miss_latency::total 21330.105523 # average ReadReq miss latency
657 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31725.410660 # average WriteReq miss latency
658 system.cpu.dcache.WriteReq_avg_miss_latency::total 31725.410660 # average WriteReq miss latency
659 system.cpu.dcache.demand_avg_miss_latency::cpu.data 24054.784783 # average overall miss latency
660 system.cpu.dcache.demand_avg_miss_latency::total 24054.784783 # average overall miss latency
661 system.cpu.dcache.overall_avg_miss_latency::cpu.data 24054.784783 # average overall miss latency
662 system.cpu.dcache.overall_avg_miss_latency::total 24054.784783 # average overall miss latency
663 system.cpu.dcache.blocked_cycles::no_mshrs 9718 # number of cycles access was blocked
664 system.cpu.dcache.blocked_cycles::no_targets 22 # number of cycles access was blocked
665 system.cpu.dcache.blocked::no_mshrs 1069 # number of cycles access was blocked
666 system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked
667 system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.090739 # average number of cycles each access was blocked
668 system.cpu.dcache.avg_blocked_cycles::no_targets 11 # average number of cycles each access was blocked
669 system.cpu.dcache.fast_writes 0 # number of fast writes performed
670 system.cpu.dcache.cache_copies 0 # number of cache copies performed
671 system.cpu.dcache.writebacks::writebacks 2330580 # number of writebacks
672 system.cpu.dcache.writebacks::total 2330580 # number of writebacks
673 system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1007465 # number of ReadReq MSHR hits
674 system.cpu.dcache.ReadReq_mshr_hits::total 1007465 # number of ReadReq MSHR hits
675 system.cpu.dcache.WriteReq_mshr_hits::cpu.data 19412 # number of WriteReq MSHR hits
676 system.cpu.dcache.WriteReq_mshr_hits::total 19412 # number of WriteReq MSHR hits
677 system.cpu.dcache.demand_mshr_hits::cpu.data 1026877 # number of demand (read+write) MSHR hits
678 system.cpu.dcache.demand_mshr_hits::total 1026877 # number of demand (read+write) MSHR hits
679 system.cpu.dcache.overall_mshr_hits::cpu.data 1026877 # number of overall MSHR hits
680 system.cpu.dcache.overall_mshr_hits::total 1026877 # number of overall MSHR hits
681 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1765003 # number of ReadReq MSHR misses
682 system.cpu.dcache.ReadReq_mshr_misses::total 1765003 # number of ReadReq MSHR misses
683 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 965395 # number of WriteReq MSHR misses
684 system.cpu.dcache.WriteReq_mshr_misses::total 965395 # number of WriteReq MSHR misses
685 system.cpu.dcache.demand_mshr_misses::cpu.data 2730398 # number of demand (read+write) MSHR misses
686 system.cpu.dcache.demand_mshr_misses::total 2730398 # number of demand (read+write) MSHR misses
687 system.cpu.dcache.overall_mshr_misses::cpu.data 2730398 # number of overall MSHR misses
688 system.cpu.dcache.overall_mshr_misses::total 2730398 # number of overall MSHR misses
689 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33567375500 # number of ReadReq MSHR miss cycles
690 system.cpu.dcache.ReadReq_mshr_miss_latency::total 33567375500 # number of ReadReq MSHR miss cycles
691 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 30021732998 # number of WriteReq MSHR miss cycles
692 system.cpu.dcache.WriteReq_mshr_miss_latency::total 30021732998 # number of WriteReq MSHR miss cycles
693 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 63589108498 # number of demand (read+write) MSHR miss cycles
694 system.cpu.dcache.demand_mshr_miss_latency::total 63589108498 # number of demand (read+write) MSHR miss cycles
695 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 63589108498 # number of overall MSHR miss cycles
696 system.cpu.dcache.overall_mshr_miss_latency::total 63589108498 # number of overall MSHR miss cycles
697 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007480 # mshr miss rate for ReadReq accesses
698 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007480 # mshr miss rate for ReadReq accesses
699 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006472 # mshr miss rate for WriteReq accesses
700 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006472 # mshr miss rate for WriteReq accesses
701 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.007090 # mshr miss rate for demand accesses
702 system.cpu.dcache.demand_mshr_miss_rate::total 0.007090 # mshr miss rate for demand accesses
703 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.007090 # mshr miss rate for overall accesses
704 system.cpu.dcache.overall_mshr_miss_rate::total 0.007090 # mshr miss rate for overall accesses
705 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19018.310734 # average ReadReq mshr miss latency
706 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19018.310734 # average ReadReq mshr miss latency
707 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31097.874961 # average WriteReq mshr miss latency
708 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31097.874961 # average WriteReq mshr miss latency
709 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23289.318443 # average overall mshr miss latency
710 system.cpu.dcache.demand_avg_mshr_miss_latency::total 23289.318443 # average overall mshr miss latency
711 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23289.318443 # average overall mshr miss latency
712 system.cpu.dcache.overall_avg_mshr_miss_latency::total 23289.318443 # average overall mshr miss latency
713 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
714 system.cpu.icache.tags.replacements 6646 # number of replacements
715 system.cpu.icache.tags.tagsinuse 1037.831951 # Cycle average of tags in use
716 system.cpu.icache.tags.total_refs 170556730 # Total number of references to valid blocks.
717 system.cpu.icache.tags.sampled_refs 8257 # Sample count of references to valid blocks.
718 system.cpu.icache.tags.avg_refs 20656.016713 # Average number of references to valid blocks.
719 system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
720 system.cpu.icache.tags.occ_blocks::cpu.inst 1037.831951 # Average occupied blocks per requestor
721 system.cpu.icache.tags.occ_percent::cpu.inst 0.506754 # Average percentage of cache occupancy
722 system.cpu.icache.tags.occ_percent::total 0.506754 # Average percentage of cache occupancy
723 system.cpu.icache.tags.occ_task_id_blocks::1024 1611 # Occupied blocks per task id
724 system.cpu.icache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id
725 system.cpu.icache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id
726 system.cpu.icache.tags.age_task_id_blocks_1024::2 49 # Occupied blocks per task id
727 system.cpu.icache.tags.age_task_id_blocks_1024::3 323 # Occupied blocks per task id
728 system.cpu.icache.tags.age_task_id_blocks_1024::4 1153 # Occupied blocks per task id
729 system.cpu.icache.tags.occ_task_id_percent::1024 0.786621 # Percentage of cache occupancy per task id
730 system.cpu.icache.tags.tag_accesses 341735047 # Number of tag accesses
731 system.cpu.icache.tags.data_accesses 341735047 # Number of data accesses
732 system.cpu.icache.ReadReq_hits::cpu.inst 170559843 # number of ReadReq hits
733 system.cpu.icache.ReadReq_hits::total 170559843 # number of ReadReq hits
734 system.cpu.icache.demand_hits::cpu.inst 170559843 # number of demand (read+write) hits
735 system.cpu.icache.demand_hits::total 170559843 # number of demand (read+write) hits
736 system.cpu.icache.overall_hits::cpu.inst 170559843 # number of overall hits
737 system.cpu.icache.overall_hits::total 170559843 # number of overall hits
738 system.cpu.icache.ReadReq_misses::cpu.inst 205853 # number of ReadReq misses
739 system.cpu.icache.ReadReq_misses::total 205853 # number of ReadReq misses
740 system.cpu.icache.demand_misses::cpu.inst 205853 # number of demand (read+write) misses
741 system.cpu.icache.demand_misses::total 205853 # number of demand (read+write) misses
742 system.cpu.icache.overall_misses::cpu.inst 205853 # number of overall misses
743 system.cpu.icache.overall_misses::total 205853 # number of overall misses
744 system.cpu.icache.ReadReq_miss_latency::cpu.inst 1200128500 # number of ReadReq miss cycles
745 system.cpu.icache.ReadReq_miss_latency::total 1200128500 # number of ReadReq miss cycles
746 system.cpu.icache.demand_miss_latency::cpu.inst 1200128500 # number of demand (read+write) miss cycles
747 system.cpu.icache.demand_miss_latency::total 1200128500 # number of demand (read+write) miss cycles
748 system.cpu.icache.overall_miss_latency::cpu.inst 1200128500 # number of overall miss cycles
749 system.cpu.icache.overall_miss_latency::total 1200128500 # number of overall miss cycles
750 system.cpu.icache.ReadReq_accesses::cpu.inst 170765696 # number of ReadReq accesses(hits+misses)
751 system.cpu.icache.ReadReq_accesses::total 170765696 # number of ReadReq accesses(hits+misses)
752 system.cpu.icache.demand_accesses::cpu.inst 170765696 # number of demand (read+write) accesses
753 system.cpu.icache.demand_accesses::total 170765696 # number of demand (read+write) accesses
754 system.cpu.icache.overall_accesses::cpu.inst 170765696 # number of overall (read+write) accesses
755 system.cpu.icache.overall_accesses::total 170765696 # number of overall (read+write) accesses
756 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001205 # miss rate for ReadReq accesses
757 system.cpu.icache.ReadReq_miss_rate::total 0.001205 # miss rate for ReadReq accesses
758 system.cpu.icache.demand_miss_rate::cpu.inst 0.001205 # miss rate for demand accesses
759 system.cpu.icache.demand_miss_rate::total 0.001205 # miss rate for demand accesses
760 system.cpu.icache.overall_miss_rate::cpu.inst 0.001205 # miss rate for overall accesses
761 system.cpu.icache.overall_miss_rate::total 0.001205 # miss rate for overall accesses
762 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 5830.026767 # average ReadReq miss latency
763 system.cpu.icache.ReadReq_avg_miss_latency::total 5830.026767 # average ReadReq miss latency
764 system.cpu.icache.demand_avg_miss_latency::cpu.inst 5830.026767 # average overall miss latency
765 system.cpu.icache.demand_avg_miss_latency::total 5830.026767 # average overall miss latency
766 system.cpu.icache.overall_avg_miss_latency::cpu.inst 5830.026767 # average overall miss latency
767 system.cpu.icache.overall_avg_miss_latency::total 5830.026767 # average overall miss latency
768 system.cpu.icache.blocked_cycles::no_mshrs 1227 # number of cycles access was blocked
769 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
770 system.cpu.icache.blocked::no_mshrs 13 # number of cycles access was blocked
771 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
772 system.cpu.icache.avg_blocked_cycles::no_mshrs 94.384615 # average number of cycles each access was blocked
773 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
774 system.cpu.icache.fast_writes 0 # number of fast writes performed
775 system.cpu.icache.cache_copies 0 # number of cache copies performed
776 system.cpu.icache.writebacks::writebacks 6646 # number of writebacks
777 system.cpu.icache.writebacks::total 6646 # number of writebacks
778 system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2196 # number of ReadReq MSHR hits
779 system.cpu.icache.ReadReq_mshr_hits::total 2196 # number of ReadReq MSHR hits
780 system.cpu.icache.demand_mshr_hits::cpu.inst 2196 # number of demand (read+write) MSHR hits
781 system.cpu.icache.demand_mshr_hits::total 2196 # number of demand (read+write) MSHR hits
782 system.cpu.icache.overall_mshr_hits::cpu.inst 2196 # number of overall MSHR hits
783 system.cpu.icache.overall_mshr_hits::total 2196 # number of overall MSHR hits
784 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 203657 # number of ReadReq MSHR misses
785 system.cpu.icache.ReadReq_mshr_misses::total 203657 # number of ReadReq MSHR misses
786 system.cpu.icache.demand_mshr_misses::cpu.inst 203657 # number of demand (read+write) MSHR misses
787 system.cpu.icache.demand_mshr_misses::total 203657 # number of demand (read+write) MSHR misses
788 system.cpu.icache.overall_mshr_misses::cpu.inst 203657 # number of overall MSHR misses
789 system.cpu.icache.overall_mshr_misses::total 203657 # number of overall MSHR misses
790 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 915942000 # number of ReadReq MSHR miss cycles
791 system.cpu.icache.ReadReq_mshr_miss_latency::total 915942000 # number of ReadReq MSHR miss cycles
792 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 915942000 # number of demand (read+write) MSHR miss cycles
793 system.cpu.icache.demand_mshr_miss_latency::total 915942000 # number of demand (read+write) MSHR miss cycles
794 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 915942000 # number of overall MSHR miss cycles
795 system.cpu.icache.overall_mshr_miss_latency::total 915942000 # number of overall MSHR miss cycles
796 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001193 # mshr miss rate for ReadReq accesses
797 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001193 # mshr miss rate for ReadReq accesses
798 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001193 # mshr miss rate for demand accesses
799 system.cpu.icache.demand_mshr_miss_rate::total 0.001193 # mshr miss rate for demand accesses
800 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001193 # mshr miss rate for overall accesses
801 system.cpu.icache.overall_mshr_miss_rate::total 0.001193 # mshr miss rate for overall accesses
802 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 4497.473694 # average ReadReq mshr miss latency
803 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 4497.473694 # average ReadReq mshr miss latency
804 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 4497.473694 # average overall mshr miss latency
805 system.cpu.icache.demand_avg_mshr_miss_latency::total 4497.473694 # average overall mshr miss latency
806 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4497.473694 # average overall mshr miss latency
807 system.cpu.icache.overall_avg_mshr_miss_latency::total 4497.473694 # average overall mshr miss latency
808 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
809 system.cpu.l2cache.tags.replacements 355353 # number of replacements
810 system.cpu.l2cache.tags.tagsinuse 29622.360261 # Cycle average of tags in use
811 system.cpu.l2cache.tags.total_refs 3892845 # Total number of references to valid blocks.
812 system.cpu.l2cache.tags.sampled_refs 387686 # Sample count of references to valid blocks.
813 system.cpu.l2cache.tags.avg_refs 10.041232 # Average number of references to valid blocks.
814 system.cpu.l2cache.tags.warmup_cycle 189329679500 # Cycle when the warmup percentage was hit.
815 system.cpu.l2cache.tags.occ_blocks::writebacks 21025.083247 # Average occupied blocks per requestor
816 system.cpu.l2cache.tags.occ_blocks::cpu.inst 186.619745 # Average occupied blocks per requestor
817 system.cpu.l2cache.tags.occ_blocks::cpu.data 8410.657269 # Average occupied blocks per requestor
818 system.cpu.l2cache.tags.occ_percent::writebacks 0.641635 # Average percentage of cache occupancy
819 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005695 # Average percentage of cache occupancy
820 system.cpu.l2cache.tags.occ_percent::cpu.data 0.256673 # Average percentage of cache occupancy
821 system.cpu.l2cache.tags.occ_percent::total 0.904003 # Average percentage of cache occupancy
822 system.cpu.l2cache.tags.occ_task_id_blocks::1024 32333 # Occupied blocks per task id
823 system.cpu.l2cache.tags.age_task_id_blocks_1024::0 88 # Occupied blocks per task id
824 system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id
825 system.cpu.l2cache.tags.age_task_id_blocks_1024::2 228 # Occupied blocks per task id
826 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 13404 # Occupied blocks per task id
827 system.cpu.l2cache.tags.age_task_id_blocks_1024::4 18612 # Occupied blocks per task id
828 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.986725 # Percentage of cache occupancy per task id
829 system.cpu.l2cache.tags.tag_accesses 43282239 # Number of tag accesses
830 system.cpu.l2cache.tags.data_accesses 43282239 # Number of data accesses
831 system.cpu.l2cache.WritebackDirty_hits::writebacks 2330580 # number of WritebackDirty hits
832 system.cpu.l2cache.WritebackDirty_hits::total 2330580 # number of WritebackDirty hits
833 system.cpu.l2cache.WritebackClean_hits::writebacks 6244 # number of WritebackClean hits
834 system.cpu.l2cache.WritebackClean_hits::total 6244 # number of WritebackClean hits
835 system.cpu.l2cache.UpgradeReq_hits::cpu.data 1851 # number of UpgradeReq hits
836 system.cpu.l2cache.UpgradeReq_hits::total 1851 # number of UpgradeReq hits
837 system.cpu.l2cache.ReadExReq_hits::cpu.data 563583 # number of ReadExReq hits
838 system.cpu.l2cache.ReadExReq_hits::total 563583 # number of ReadExReq hits
839 system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 5681 # number of ReadCleanReq hits
840 system.cpu.l2cache.ReadCleanReq_hits::total 5681 # number of ReadCleanReq hits
841 system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1587941 # number of ReadSharedReq hits
842 system.cpu.l2cache.ReadSharedReq_hits::total 1587941 # number of ReadSharedReq hits
843 system.cpu.l2cache.demand_hits::cpu.inst 5681 # number of demand (read+write) hits
844 system.cpu.l2cache.demand_hits::cpu.data 2151524 # number of demand (read+write) hits
845 system.cpu.l2cache.demand_hits::total 2157205 # number of demand (read+write) hits
846 system.cpu.l2cache.overall_hits::cpu.inst 5681 # number of overall hits
847 system.cpu.l2cache.overall_hits::cpu.data 2151524 # number of overall hits
848 system.cpu.l2cache.overall_hits::total 2157205 # number of overall hits
849 system.cpu.l2cache.UpgradeReq_misses::cpu.data 193439 # number of UpgradeReq misses
850 system.cpu.l2cache.UpgradeReq_misses::total 193439 # number of UpgradeReq misses
851 system.cpu.l2cache.ReadExReq_misses::cpu.data 206924 # number of ReadExReq misses
852 system.cpu.l2cache.ReadExReq_misses::total 206924 # number of ReadExReq misses
853 system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2558 # number of ReadCleanReq misses
854 system.cpu.l2cache.ReadCleanReq_misses::total 2558 # number of ReadCleanReq misses
855 system.cpu.l2cache.ReadSharedReq_misses::cpu.data 176660 # number of ReadSharedReq misses
856 system.cpu.l2cache.ReadSharedReq_misses::total 176660 # number of ReadSharedReq misses
857 system.cpu.l2cache.demand_misses::cpu.inst 2558 # number of demand (read+write) misses
858 system.cpu.l2cache.demand_misses::cpu.data 383584 # number of demand (read+write) misses
859 system.cpu.l2cache.demand_misses::total 386142 # number of demand (read+write) misses
860 system.cpu.l2cache.overall_misses::cpu.inst 2558 # number of overall misses
861 system.cpu.l2cache.overall_misses::cpu.data 383584 # number of overall misses
862 system.cpu.l2cache.overall_misses::total 386142 # number of overall misses
863 system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 13992500 # number of UpgradeReq miss cycles
864 system.cpu.l2cache.UpgradeReq_miss_latency::total 13992500 # number of UpgradeReq miss cycles
865 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16415552000 # number of ReadExReq miss cycles
866 system.cpu.l2cache.ReadExReq_miss_latency::total 16415552000 # number of ReadExReq miss cycles
867 system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 208018000 # number of ReadCleanReq miss cycles
868 system.cpu.l2cache.ReadCleanReq_miss_latency::total 208018000 # number of ReadCleanReq miss cycles
869 system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 14197973500 # number of ReadSharedReq miss cycles
870 system.cpu.l2cache.ReadSharedReq_miss_latency::total 14197973500 # number of ReadSharedReq miss cycles
871 system.cpu.l2cache.demand_miss_latency::cpu.inst 208018000 # number of demand (read+write) miss cycles
872 system.cpu.l2cache.demand_miss_latency::cpu.data 30613525500 # number of demand (read+write) miss cycles
873 system.cpu.l2cache.demand_miss_latency::total 30821543500 # number of demand (read+write) miss cycles
874 system.cpu.l2cache.overall_miss_latency::cpu.inst 208018000 # number of overall miss cycles
875 system.cpu.l2cache.overall_miss_latency::cpu.data 30613525500 # number of overall miss cycles
876 system.cpu.l2cache.overall_miss_latency::total 30821543500 # number of overall miss cycles
877 system.cpu.l2cache.WritebackDirty_accesses::writebacks 2330580 # number of WritebackDirty accesses(hits+misses)
878 system.cpu.l2cache.WritebackDirty_accesses::total 2330580 # number of WritebackDirty accesses(hits+misses)
879 system.cpu.l2cache.WritebackClean_accesses::writebacks 6244 # number of WritebackClean accesses(hits+misses)
880 system.cpu.l2cache.WritebackClean_accesses::total 6244 # number of WritebackClean accesses(hits+misses)
881 system.cpu.l2cache.UpgradeReq_accesses::cpu.data 195290 # number of UpgradeReq accesses(hits+misses)
882 system.cpu.l2cache.UpgradeReq_accesses::total 195290 # number of UpgradeReq accesses(hits+misses)
883 system.cpu.l2cache.ReadExReq_accesses::cpu.data 770507 # number of ReadExReq accesses(hits+misses)
884 system.cpu.l2cache.ReadExReq_accesses::total 770507 # number of ReadExReq accesses(hits+misses)
885 system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 8239 # number of ReadCleanReq accesses(hits+misses)
886 system.cpu.l2cache.ReadCleanReq_accesses::total 8239 # number of ReadCleanReq accesses(hits+misses)
887 system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1764601 # number of ReadSharedReq accesses(hits+misses)
888 system.cpu.l2cache.ReadSharedReq_accesses::total 1764601 # number of ReadSharedReq accesses(hits+misses)
889 system.cpu.l2cache.demand_accesses::cpu.inst 8239 # number of demand (read+write) accesses
890 system.cpu.l2cache.demand_accesses::cpu.data 2535108 # number of demand (read+write) accesses
891 system.cpu.l2cache.demand_accesses::total 2543347 # number of demand (read+write) accesses
892 system.cpu.l2cache.overall_accesses::cpu.inst 8239 # number of overall (read+write) accesses
893 system.cpu.l2cache.overall_accesses::cpu.data 2535108 # number of overall (read+write) accesses
894 system.cpu.l2cache.overall_accesses::total 2543347 # number of overall (read+write) accesses
895 system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.990522 # miss rate for UpgradeReq accesses
896 system.cpu.l2cache.UpgradeReq_miss_rate::total 0.990522 # miss rate for UpgradeReq accesses
897 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.268556 # miss rate for ReadExReq accesses
898 system.cpu.l2cache.ReadExReq_miss_rate::total 0.268556 # miss rate for ReadExReq accesses
899 system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.310475 # miss rate for ReadCleanReq accesses
900 system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.310475 # miss rate for ReadCleanReq accesses
901 system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.100113 # miss rate for ReadSharedReq accesses
902 system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.100113 # miss rate for ReadSharedReq accesses
903 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.310475 # miss rate for demand accesses
904 system.cpu.l2cache.demand_miss_rate::cpu.data 0.151309 # miss rate for demand accesses
905 system.cpu.l2cache.demand_miss_rate::total 0.151824 # miss rate for demand accesses
906 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.310475 # miss rate for overall accesses
907 system.cpu.l2cache.overall_miss_rate::cpu.data 0.151309 # miss rate for overall accesses
908 system.cpu.l2cache.overall_miss_rate::total 0.151824 # miss rate for overall accesses
909 system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 72.335465 # average UpgradeReq miss latency
910 system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 72.335465 # average UpgradeReq miss latency
911 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79331.310046 # average ReadExReq miss latency
912 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79331.310046 # average ReadExReq miss latency
913 system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 81320.562940 # average ReadCleanReq miss latency
914 system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 81320.562940 # average ReadCleanReq miss latency
915 system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80368.920525 # average ReadSharedReq miss latency
916 system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80368.920525 # average ReadSharedReq miss latency
917 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81320.562940 # average overall miss latency
918 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79809.182604 # average overall miss latency
919 system.cpu.l2cache.demand_avg_miss_latency::total 79819.194752 # average overall miss latency
920 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81320.562940 # average overall miss latency
921 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79809.182604 # average overall miss latency
922 system.cpu.l2cache.overall_avg_miss_latency::total 79819.194752 # average overall miss latency
923 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
924 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
925 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
926 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
927 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
928 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
929 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
930 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
931 system.cpu.l2cache.writebacks::writebacks 295163 # number of writebacks
932 system.cpu.l2cache.writebacks::total 295163 # number of writebacks
933 system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits
934 system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits
935 system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
936 system.cpu.l2cache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits
937 system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
938 system.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits
939 system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 8 # number of CleanEvict MSHR misses
940 system.cpu.l2cache.CleanEvict_mshr_misses::total 8 # number of CleanEvict MSHR misses
941 system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 193439 # number of UpgradeReq MSHR misses
942 system.cpu.l2cache.UpgradeReq_mshr_misses::total 193439 # number of UpgradeReq MSHR misses
943 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206924 # number of ReadExReq MSHR misses
944 system.cpu.l2cache.ReadExReq_mshr_misses::total 206924 # number of ReadExReq MSHR misses
945 system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2557 # number of ReadCleanReq MSHR misses
946 system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2557 # number of ReadCleanReq MSHR misses
947 system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 176660 # number of ReadSharedReq MSHR misses
948 system.cpu.l2cache.ReadSharedReq_mshr_misses::total 176660 # number of ReadSharedReq MSHR misses
949 system.cpu.l2cache.demand_mshr_misses::cpu.inst 2557 # number of demand (read+write) MSHR misses
950 system.cpu.l2cache.demand_mshr_misses::cpu.data 383584 # number of demand (read+write) MSHR misses
951 system.cpu.l2cache.demand_mshr_misses::total 386141 # number of demand (read+write) MSHR misses
952 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2557 # number of overall MSHR misses
953 system.cpu.l2cache.overall_mshr_misses::cpu.data 383584 # number of overall MSHR misses
954 system.cpu.l2cache.overall_mshr_misses::total 386141 # number of overall MSHR misses
955 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 4268097007 # number of UpgradeReq MSHR miss cycles
956 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 4268097007 # number of UpgradeReq MSHR miss cycles
957 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 14346312000 # number of ReadExReq MSHR miss cycles
958 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 14346312000 # number of ReadExReq MSHR miss cycles
959 system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 182391500 # number of ReadCleanReq MSHR miss cycles
960 system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 182391500 # number of ReadCleanReq MSHR miss cycles
961 system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 12431373500 # number of ReadSharedReq MSHR miss cycles
962 system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 12431373500 # number of ReadSharedReq MSHR miss cycles
963 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 182391500 # number of demand (read+write) MSHR miss cycles
964 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 26777685500 # number of demand (read+write) MSHR miss cycles
965 system.cpu.l2cache.demand_mshr_miss_latency::total 26960077000 # number of demand (read+write) MSHR miss cycles
966 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 182391500 # number of overall MSHR miss cycles
967 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 26777685500 # number of overall MSHR miss cycles
968 system.cpu.l2cache.overall_mshr_miss_latency::total 26960077000 # number of overall MSHR miss cycles
969 system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
970 system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
971 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.990522 # mshr miss rate for UpgradeReq accesses
972 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.990522 # mshr miss rate for UpgradeReq accesses
973 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.268556 # mshr miss rate for ReadExReq accesses
974 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.268556 # mshr miss rate for ReadExReq accesses
975 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.310353 # mshr miss rate for ReadCleanReq accesses
976 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.310353 # mshr miss rate for ReadCleanReq accesses
977 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.100113 # mshr miss rate for ReadSharedReq accesses
978 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.100113 # mshr miss rate for ReadSharedReq accesses
979 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.310353 # mshr miss rate for demand accesses
980 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.151309 # mshr miss rate for demand accesses
981 system.cpu.l2cache.demand_mshr_miss_rate::total 0.151824 # mshr miss rate for demand accesses
982 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.310353 # mshr miss rate for overall accesses
983 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.151309 # mshr miss rate for overall accesses
984 system.cpu.l2cache.overall_mshr_miss_rate::total 0.151824 # mshr miss rate for overall accesses
985 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 22064.304546 # average UpgradeReq mshr miss latency
986 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 22064.304546 # average UpgradeReq mshr miss latency
987 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69331.310046 # average ReadExReq mshr miss latency
988 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69331.310046 # average ReadExReq mshr miss latency
989 system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71330.269847 # average ReadCleanReq mshr miss latency
990 system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71330.269847 # average ReadCleanReq mshr miss latency
991 system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70368.920525 # average ReadSharedReq mshr miss latency
992 system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70368.920525 # average ReadSharedReq mshr miss latency
993 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71330.269847 # average overall mshr miss latency
994 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69809.182604 # average overall mshr miss latency
995 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69819.255143 # average overall mshr miss latency
996 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71330.269847 # average overall mshr miss latency
997 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69809.182604 # average overall mshr miss latency
998 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69819.255143 # average overall mshr miss latency
999 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
1000 system.cpu.toL2Bus.snoop_filter.tot_requests 5471713 # Total number of requests made to the snoop filter.
1001 system.cpu.toL2Bus.snoop_filter.hit_single_requests 2729811 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1002 system.cpu.toL2Bus.snoop_filter.hit_multi_requests 210473 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1003 system.cpu.toL2Bus.snoop_filter.tot_snoops 3600 # Total number of snoops made to the snoop filter.
1004 system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3600 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1005 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
1006 system.cpu.toL2Bus.trans_dist::ReadResp 1968256 # Transaction distribution
1007 system.cpu.toL2Bus.trans_dist::WritebackDirty 2625743 # Transaction distribution
1008 system.cpu.toL2Bus.trans_dist::WritebackClean 6244 # Transaction distribution
1009 system.cpu.toL2Bus.trans_dist::CleanEvict 249948 # Transaction distribution
1010 system.cpu.toL2Bus.trans_dist::UpgradeReq 195290 # Transaction distribution
1011 system.cpu.toL2Bus.trans_dist::UpgradeResp 195290 # Transaction distribution
1012 system.cpu.toL2Bus.trans_dist::ReadExReq 770507 # Transaction distribution
1013 system.cpu.toL2Bus.trans_dist::ReadExResp 770507 # Transaction distribution
1014 system.cpu.toL2Bus.trans_dist::ReadCleanReq 203657 # Transaction distribution
1015 system.cpu.toL2Bus.trans_dist::ReadSharedReq 1764601 # Transaction distribution
1016 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 218138 # Packet count per connected master and slave (bytes)
1017 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7981134 # Packet count per connected master and slave (bytes)
1018 system.cpu.toL2Bus.pkt_count::total 8199272 # Packet count per connected master and slave (bytes)
1019 system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 926784 # Cumulative packet size per connected master and slave (bytes)
1020 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311404032 # Cumulative packet size per connected master and slave (bytes)
1021 system.cpu.toL2Bus.pkt_size::total 312330816 # Cumulative packet size per connected master and slave (bytes)
1022 system.cpu.toL2Bus.snoops 550771 # Total snoops (count)
1023 system.cpu.toL2Bus.snoop_fanout::samples 3289408 # Request fanout histogram
1024 system.cpu.toL2Bus.snoop_fanout::mean 0.123462 # Request fanout histogram
1025 system.cpu.toL2Bus.snoop_fanout::stdev 0.328967 # Request fanout histogram
1026 system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1027 system.cpu.toL2Bus.snoop_fanout::0 2883292 87.65% 87.65% # Request fanout histogram
1028 system.cpu.toL2Bus.snoop_fanout::1 406116 12.35% 100.00% # Request fanout histogram
1029 system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
1030 system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1031 system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
1032 system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
1033 system.cpu.toL2Bus.snoop_fanout::total 3289408 # Request fanout histogram
1034 system.cpu.toL2Bus.reqLayer0.occupancy 5101560430 # Layer occupancy (ticks)
1035 system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%)
1036 system.cpu.toL2Bus.respLayer0.occupancy 305490983 # Layer occupancy (ticks)
1037 system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
1038 system.cpu.toL2Bus.respLayer1.occupancy 3900309572 # Layer occupancy (ticks)
1039 system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%)
1040 system.membus.trans_dist::ReadResp 179215 # Transaction distribution
1041 system.membus.trans_dist::WritebackDirty 295163 # Transaction distribution
1042 system.membus.trans_dist::CleanEvict 56660 # Transaction distribution
1043 system.membus.trans_dist::UpgradeReq 193490 # Transaction distribution
1044 system.membus.trans_dist::UpgradeResp 193490 # Transaction distribution
1045 system.membus.trans_dist::ReadExReq 206873 # Transaction distribution
1046 system.membus.trans_dist::ReadExResp 206873 # Transaction distribution
1047 system.membus.trans_dist::ReadSharedReq 179216 # Transaction distribution
1048 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1510980 # Packet count per connected master and slave (bytes)
1049 system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1510980 # Packet count per connected master and slave (bytes)
1050 system.membus.pkt_count::total 1510980 # Packet count per connected master and slave (bytes)
1051 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43600064 # Cumulative packet size per connected master and slave (bytes)
1052 system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43600064 # Cumulative packet size per connected master and slave (bytes)
1053 system.membus.pkt_size::total 43600064 # Cumulative packet size per connected master and slave (bytes)
1054 system.membus.snoops 0 # Total snoops (count)
1055 system.membus.snoop_fanout::samples 931402 # Request fanout histogram
1056 system.membus.snoop_fanout::mean 0 # Request fanout histogram
1057 system.membus.snoop_fanout::stdev 0 # Request fanout histogram
1058 system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1059 system.membus.snoop_fanout::0 931402 100.00% 100.00% # Request fanout histogram
1060 system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
1061 system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1062 system.membus.snoop_fanout::min_value 0 # Request fanout histogram
1063 system.membus.snoop_fanout::max_value 0 # Request fanout histogram
1064 system.membus.snoop_fanout::total 931402 # Request fanout histogram
1065 system.membus.reqLayer0.occupancy 2242581485 # Layer occupancy (ticks)
1066 system.membus.reqLayer0.utilization 0.6 # Layer utilization (%)
1067 system.membus.respLayer1.occupancy 2429056686 # Layer occupancy (ticks)
1068 system.membus.respLayer1.utilization 0.6 # Layer utilization (%)
1070 ---------- End Simulation Statistics ----------
projects / gem5.git / blob