2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.417785 # Number of seconds simulated
4 sim_ticks 417784645500 # Number of ticks simulated
5 final_tick 417784645500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 77548 # Simulator instruction rate (inst/s)
8 host_op_rate 143396 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 39181823 # Simulator tick rate (ticks/s)
10 host_mem_usage 423644 # Number of bytes of host memory used
11 host_seconds 10662.72 # Real time elapsed on the host
12 sim_insts 826877109 # Number of instructions simulated
13 sim_ops 1528988701 # Number of ops (including micro ops) simulated
14 system.voltage_domain.voltage 1 # Voltage in Volts
15 system.clk_domain.clock 1000 # Clock period in ticks
16 system.physmem.bytes_read::cpu.inst 225536 # Number of bytes read from this memory
17 system.physmem.bytes_read::cpu.data 24536320 # Number of bytes read from this memory
18 system.physmem.bytes_read::total 24761856 # Number of bytes read from this memory
19 system.physmem.bytes_inst_read::cpu.inst 225536 # Number of instructions bytes read from this memory
20 system.physmem.bytes_inst_read::total 225536 # Number of instructions bytes read from this memory
21 system.physmem.bytes_written::writebacks 18818176 # Number of bytes written to this memory
22 system.physmem.bytes_written::total 18818176 # Number of bytes written to this memory
23 system.physmem.num_reads::cpu.inst 3524 # Number of read requests responded to by this memory
24 system.physmem.num_reads::cpu.data 383380 # Number of read requests responded to by this memory
25 system.physmem.num_reads::total 386904 # Number of read requests responded to by this memory
26 system.physmem.num_writes::writebacks 294034 # Number of write requests responded to by this memory
27 system.physmem.num_writes::total 294034 # Number of write requests responded to by this memory
28 system.physmem.bw_read::cpu.inst 539838 # Total read bandwidth from this memory (bytes/s)
29 system.physmem.bw_read::cpu.data 58729588 # Total read bandwidth from this memory (bytes/s)
30 system.physmem.bw_read::total 59269426 # Total read bandwidth from this memory (bytes/s)
31 system.physmem.bw_inst_read::cpu.inst 539838 # Instruction read bandwidth from this memory (bytes/s)
32 system.physmem.bw_inst_read::total 539838 # Instruction read bandwidth from this memory (bytes/s)
33 system.physmem.bw_write::writebacks 45042766 # Write bandwidth from this memory (bytes/s)
34 system.physmem.bw_write::total 45042766 # Write bandwidth from this memory (bytes/s)
35 system.physmem.bw_total::writebacks 45042766 # Total bandwidth to/from this memory (bytes/s)
36 system.physmem.bw_total::cpu.inst 539838 # Total bandwidth to/from this memory (bytes/s)
37 system.physmem.bw_total::cpu.data 58729588 # Total bandwidth to/from this memory (bytes/s)
38 system.physmem.bw_total::total 104312192 # Total bandwidth to/from this memory (bytes/s)
39 system.physmem.readReqs 386904 # Number of read requests accepted
40 system.physmem.writeReqs 294034 # Number of write requests accepted
41 system.physmem.readBursts 386904 # Number of DRAM read bursts, including those serviced by the write queue
42 system.physmem.writeBursts 294034 # Number of DRAM write bursts, including those merged in the write queue
43 system.physmem.bytesReadDRAM 24739840 # Total number of bytes read from DRAM
44 system.physmem.bytesReadWrQ 22016 # Total number of bytes read from write queue
45 system.physmem.bytesWritten 18816320 # Total number of bytes written to DRAM
46 system.physmem.bytesReadSys 24761856 # Total read bytes from the system interface side
47 system.physmem.bytesWrittenSys 18818176 # Total written bytes from the system interface side
48 system.physmem.servicedByWrQ 344 # Number of DRAM read bursts serviced by the write queue
49 system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
50 system.physmem.neitherReadNorWriteReqs 194832 # Number of requests that are neither read nor write
51 system.physmem.perBankRdBursts::0 24113 # Per bank write bursts
52 system.physmem.perBankRdBursts::1 26506 # Per bank write bursts
53 system.physmem.perBankRdBursts::2 24704 # Per bank write bursts
54 system.physmem.perBankRdBursts::3 24585 # Per bank write bursts
55 system.physmem.perBankRdBursts::4 23284 # Per bank write bursts
56 system.physmem.perBankRdBursts::5 23758 # Per bank write bursts
57 system.physmem.perBankRdBursts::6 24455 # Per bank write bursts
58 system.physmem.perBankRdBursts::7 24304 # Per bank write bursts
59 system.physmem.perBankRdBursts::8 23622 # Per bank write bursts
60 system.physmem.perBankRdBursts::9 23951 # Per bank write bursts
61 system.physmem.perBankRdBursts::10 24786 # Per bank write bursts
62 system.physmem.perBankRdBursts::11 24077 # Per bank write bursts
63 system.physmem.perBankRdBursts::12 23364 # Per bank write bursts
64 system.physmem.perBankRdBursts::13 22990 # Per bank write bursts
65 system.physmem.perBankRdBursts::14 24090 # Per bank write bursts
66 system.physmem.perBankRdBursts::15 23971 # Per bank write bursts
67 system.physmem.perBankWrBursts::0 18545 # Per bank write bursts
68 system.physmem.perBankWrBursts::1 19845 # Per bank write bursts
69 system.physmem.perBankWrBursts::2 18943 # Per bank write bursts
70 system.physmem.perBankWrBursts::3 18938 # Per bank write bursts
71 system.physmem.perBankWrBursts::4 18040 # Per bank write bursts
72 system.physmem.perBankWrBursts::5 18456 # Per bank write bursts
73 system.physmem.perBankWrBursts::6 18996 # Per bank write bursts
74 system.physmem.perBankWrBursts::7 18987 # Per bank write bursts
75 system.physmem.perBankWrBursts::8 18549 # Per bank write bursts
76 system.physmem.perBankWrBursts::9 18172 # Per bank write bursts
77 system.physmem.perBankWrBursts::10 18834 # Per bank write bursts
78 system.physmem.perBankWrBursts::11 17732 # Per bank write bursts
79 system.physmem.perBankWrBursts::12 17374 # Per bank write bursts
80 system.physmem.perBankWrBursts::13 16972 # Per bank write bursts
81 system.physmem.perBankWrBursts::14 17820 # Per bank write bursts
82 system.physmem.perBankWrBursts::15 17802 # Per bank write bursts
83 system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
84 system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
85 system.physmem.totGap 417784619000 # Total gap between requests
86 system.physmem.readPktSize::0 0 # Read request sizes (log2)
87 system.physmem.readPktSize::1 0 # Read request sizes (log2)
88 system.physmem.readPktSize::2 0 # Read request sizes (log2)
89 system.physmem.readPktSize::3 0 # Read request sizes (log2)
90 system.physmem.readPktSize::4 0 # Read request sizes (log2)
91 system.physmem.readPktSize::5 0 # Read request sizes (log2)
92 system.physmem.readPktSize::6 386904 # Read request sizes (log2)
93 system.physmem.writePktSize::0 0 # Write request sizes (log2)
94 system.physmem.writePktSize::1 0 # Write request sizes (log2)
95 system.physmem.writePktSize::2 0 # Write request sizes (log2)
96 system.physmem.writePktSize::3 0 # Write request sizes (log2)
97 system.physmem.writePktSize::4 0 # Write request sizes (log2)
98 system.physmem.writePktSize::5 0 # Write request sizes (log2)
99 system.physmem.writePktSize::6 294034 # Write request sizes (log2)
100 system.physmem.rdQLenPdf::0 381510 # What read queue length does an incoming req see
101 system.physmem.rdQLenPdf::1 4656 # What read queue length does an incoming req see
102 system.physmem.rdQLenPdf::2 343 # What read queue length does an incoming req see
103 system.physmem.rdQLenPdf::3 42 # What read queue length does an incoming req see
104 system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see
105 system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
106 system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
107 system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
108 system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
109 system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
110 system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
111 system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
112 system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
113 system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
114 system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
115 system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
116 system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
117 system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
118 system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
119 system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
120 system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
121 system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
122 system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
123 system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
124 system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
125 system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
126 system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
127 system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
128 system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
129 system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
130 system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
131 system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
132 system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
133 system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
134 system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
135 system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
136 system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
137 system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
138 system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
139 system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
140 system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
141 system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
142 system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
143 system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
144 system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
145 system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
146 system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
147 system.physmem.wrQLenPdf::15 6151 # What write queue length does an incoming req see
148 system.physmem.wrQLenPdf::16 6574 # What write queue length does an incoming req see
149 system.physmem.wrQLenPdf::17 16911 # What write queue length does an incoming req see
150 system.physmem.wrQLenPdf::18 17474 # What write queue length does an incoming req see
151 system.physmem.wrQLenPdf::19 17558 # What write queue length does an incoming req see
152 system.physmem.wrQLenPdf::20 17562 # What write queue length does an incoming req see
153 system.physmem.wrQLenPdf::21 17584 # What write queue length does an incoming req see
154 system.physmem.wrQLenPdf::22 17583 # What write queue length does an incoming req see
155 system.physmem.wrQLenPdf::23 17630 # What write queue length does an incoming req see
156 system.physmem.wrQLenPdf::24 17652 # What write queue length does an incoming req see
157 system.physmem.wrQLenPdf::25 17624 # What write queue length does an incoming req see
158 system.physmem.wrQLenPdf::26 17632 # What write queue length does an incoming req see
159 system.physmem.wrQLenPdf::27 17742 # What write queue length does an incoming req see
160 system.physmem.wrQLenPdf::28 17647 # What write queue length does an incoming req see
161 system.physmem.wrQLenPdf::29 17645 # What write queue length does an incoming req see
162 system.physmem.wrQLenPdf::30 17830 # What write queue length does an incoming req see
163 system.physmem.wrQLenPdf::31 17528 # What write queue length does an incoming req see
164 system.physmem.wrQLenPdf::32 17474 # What write queue length does an incoming req see
165 system.physmem.wrQLenPdf::33 39 # What write queue length does an incoming req see
166 system.physmem.wrQLenPdf::34 27 # What write queue length does an incoming req see
167 system.physmem.wrQLenPdf::35 20 # What write queue length does an incoming req see
168 system.physmem.wrQLenPdf::36 21 # What write queue length does an incoming req see
169 system.physmem.wrQLenPdf::37 15 # What write queue length does an incoming req see
170 system.physmem.wrQLenPdf::38 10 # What write queue length does an incoming req see
171 system.physmem.wrQLenPdf::39 6 # What write queue length does an incoming req see
172 system.physmem.wrQLenPdf::40 7 # What write queue length does an incoming req see
173 system.physmem.wrQLenPdf::41 5 # What write queue length does an incoming req see
174 system.physmem.wrQLenPdf::42 6 # What write queue length does an incoming req see
175 system.physmem.wrQLenPdf::43 5 # What write queue length does an incoming req see
176 system.physmem.wrQLenPdf::44 6 # What write queue length does an incoming req see
177 system.physmem.wrQLenPdf::45 5 # What write queue length does an incoming req see
178 system.physmem.wrQLenPdf::46 4 # What write queue length does an incoming req see
179 system.physmem.wrQLenPdf::47 6 # What write queue length does an incoming req see
180 system.physmem.wrQLenPdf::48 2 # What write queue length does an incoming req see
181 system.physmem.wrQLenPdf::49 4 # What write queue length does an incoming req see
182 system.physmem.wrQLenPdf::50 4 # What write queue length does an incoming req see
183 system.physmem.wrQLenPdf::51 7 # What write queue length does an incoming req see
184 system.physmem.wrQLenPdf::52 5 # What write queue length does an incoming req see
185 system.physmem.wrQLenPdf::53 7 # What write queue length does an incoming req see
186 system.physmem.wrQLenPdf::54 4 # What write queue length does an incoming req see
187 system.physmem.wrQLenPdf::55 2 # What write queue length does an incoming req see
188 system.physmem.wrQLenPdf::56 1 # What write queue length does an incoming req see
189 system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
190 system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
191 system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
192 system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
193 system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
194 system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
195 system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
196 system.physmem.bytesPerActivate::samples 147384 # Bytes accessed per row activation
197 system.physmem.bytesPerActivate::mean 295.518428 # Bytes accessed per row activation
198 system.physmem.bytesPerActivate::gmean 174.412890 # Bytes accessed per row activation
199 system.physmem.bytesPerActivate::stdev 322.590500 # Bytes accessed per row activation
200 system.physmem.bytesPerActivate::0-127 54886 37.24% 37.24% # Bytes accessed per row activation
201 system.physmem.bytesPerActivate::128-255 39792 27.00% 64.24% # Bytes accessed per row activation
202 system.physmem.bytesPerActivate::256-383 13719 9.31% 73.55% # Bytes accessed per row activation
203 system.physmem.bytesPerActivate::384-511 7560 5.13% 78.68% # Bytes accessed per row activation
204 system.physmem.bytesPerActivate::512-639 5573 3.78% 82.46% # Bytes accessed per row activation
205 system.physmem.bytesPerActivate::640-767 3862 2.62% 85.08% # Bytes accessed per row activation
206 system.physmem.bytesPerActivate::768-895 3103 2.11% 87.18% # Bytes accessed per row activation
207 system.physmem.bytesPerActivate::896-1023 2674 1.81% 89.00% # Bytes accessed per row activation
208 system.physmem.bytesPerActivate::1024-1151 16215 11.00% 100.00% # Bytes accessed per row activation
209 system.physmem.bytesPerActivate::total 147384 # Bytes accessed per row activation
210 system.physmem.rdPerTurnAround::samples 17444 # Reads before turning the bus around for writes
211 system.physmem.rdPerTurnAround::mean 22.159252 # Reads before turning the bus around for writes
212 system.physmem.rdPerTurnAround::stdev 209.918601 # Reads before turning the bus around for writes
213 system.physmem.rdPerTurnAround::0-1023 17431 99.93% 99.93% # Reads before turning the bus around for writes
214 system.physmem.rdPerTurnAround::1024-2047 8 0.05% 99.97% # Reads before turning the bus around for writes
215 system.physmem.rdPerTurnAround::2048-3071 3 0.02% 99.99% # Reads before turning the bus around for writes
216 system.physmem.rdPerTurnAround::3072-4095 1 0.01% 99.99% # Reads before turning the bus around for writes
217 system.physmem.rdPerTurnAround::26624-27647 1 0.01% 100.00% # Reads before turning the bus around for writes
218 system.physmem.rdPerTurnAround::total 17444 # Reads before turning the bus around for writes
219 system.physmem.wrPerTurnAround::samples 17444 # Writes before turning the bus around for reads
220 system.physmem.wrPerTurnAround::mean 16.854219 # Writes before turning the bus around for reads
221 system.physmem.wrPerTurnAround::gmean 16.780353 # Writes before turning the bus around for reads
222 system.physmem.wrPerTurnAround::stdev 2.660093 # Writes before turning the bus around for reads
223 system.physmem.wrPerTurnAround::16-19 17244 98.85% 98.85% # Writes before turning the bus around for reads
224 system.physmem.wrPerTurnAround::20-23 141 0.81% 99.66% # Writes before turning the bus around for reads
225 system.physmem.wrPerTurnAround::24-27 26 0.15% 99.81% # Writes before turning the bus around for reads
226 system.physmem.wrPerTurnAround::28-31 11 0.06% 99.87% # Writes before turning the bus around for reads
227 system.physmem.wrPerTurnAround::32-35 5 0.03% 99.90% # Writes before turning the bus around for reads
228 system.physmem.wrPerTurnAround::40-43 3 0.02% 99.92% # Writes before turning the bus around for reads
229 system.physmem.wrPerTurnAround::44-47 3 0.02% 99.94% # Writes before turning the bus around for reads
230 system.physmem.wrPerTurnAround::48-51 1 0.01% 99.94% # Writes before turning the bus around for reads
231 system.physmem.wrPerTurnAround::64-67 1 0.01% 99.95% # Writes before turning the bus around for reads
232 system.physmem.wrPerTurnAround::68-71 1 0.01% 99.95% # Writes before turning the bus around for reads
233 system.physmem.wrPerTurnAround::72-75 1 0.01% 99.96% # Writes before turning the bus around for reads
234 system.physmem.wrPerTurnAround::76-79 1 0.01% 99.97% # Writes before turning the bus around for reads
235 system.physmem.wrPerTurnAround::80-83 2 0.01% 99.98% # Writes before turning the bus around for reads
236 system.physmem.wrPerTurnAround::88-91 1 0.01% 99.98% # Writes before turning the bus around for reads
237 system.physmem.wrPerTurnAround::104-107 1 0.01% 99.99% # Writes before turning the bus around for reads
238 system.physmem.wrPerTurnAround::128-131 1 0.01% 99.99% # Writes before turning the bus around for reads
239 system.physmem.wrPerTurnAround::236-239 1 0.01% 100.00% # Writes before turning the bus around for reads
240 system.physmem.wrPerTurnAround::total 17444 # Writes before turning the bus around for reads
241 system.physmem.totQLat 4274781750 # Total ticks spent queuing
242 system.physmem.totMemAccLat 11522781750 # Total ticks spent from burst creation until serviced by the DRAM
243 system.physmem.totBusLat 1932800000 # Total ticks spent in databus transfers
244 system.physmem.avgQLat 11058.52 # Average queueing delay per DRAM burst
245 system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
246 system.physmem.avgMemAccLat 29808.52 # Average memory access latency per DRAM burst
247 system.physmem.avgRdBW 59.22 # Average DRAM read bandwidth in MiByte/s
248 system.physmem.avgWrBW 45.04 # Average achieved write bandwidth in MiByte/s
249 system.physmem.avgRdBWSys 59.27 # Average system read bandwidth in MiByte/s
250 system.physmem.avgWrBWSys 45.04 # Average system write bandwidth in MiByte/s
251 system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
252 system.physmem.busUtil 0.81 # Data bus utilization in percentage
253 system.physmem.busUtilRead 0.46 # Data bus utilization in percentage for reads
254 system.physmem.busUtilWrite 0.35 # Data bus utilization in percentage for writes
255 system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing
256 system.physmem.avgWrQLen 21.29 # Average write queue length when enqueuing
257 system.physmem.readRowHits 318043 # Number of row buffer hits during reads
258 system.physmem.writeRowHits 215127 # Number of row buffer hits during writes
259 system.physmem.readRowHitRate 82.28 # Row buffer hit rate for reads
260 system.physmem.writeRowHitRate 73.16 # Row buffer hit rate for writes
261 system.physmem.avgGap 613542.82 # Average gap between requests
262 system.physmem.pageHitRate 78.34 # Row buffer hit rate, read and write combined
263 system.physmem_0.actEnergy 567476280 # Energy for activate commands per rank (pJ)
264 system.physmem_0.preEnergy 309634875 # Energy for precharge commands per rank (pJ)
265 system.physmem_0.readEnergy 1526389800 # Energy for read commands per rank (pJ)
266 system.physmem_0.writeEnergy 976691520 # Energy for write commands per rank (pJ)
267 system.physmem_0.refreshEnergy 27287295360 # Energy for refresh commands per rank (pJ)
268 system.physmem_0.actBackEnergy 63728995635 # Energy for active background per rank (pJ)
269 system.physmem_0.preBackEnergy 194764938000 # Energy for precharge background per rank (pJ)
270 system.physmem_0.totalEnergy 289161421470 # Total energy per rank (pJ)
271 system.physmem_0.averagePower 692.139218 # Core power per rank (mW)
272 system.physmem_0.memoryStateTime::IDLE 323446024000 # Time in different power states
273 system.physmem_0.memoryStateTime::REF 13950560000 # Time in different power states
274 system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
275 system.physmem_0.memoryStateTime::ACT 80384174500 # Time in different power states
276 system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
277 system.physmem_1.actEnergy 546399000 # Energy for activate commands per rank (pJ)
278 system.physmem_1.preEnergy 298134375 # Energy for precharge commands per rank (pJ)
279 system.physmem_1.readEnergy 1488177600 # Energy for read commands per rank (pJ)
280 system.physmem_1.writeEnergy 928104480 # Energy for write commands per rank (pJ)
281 system.physmem_1.refreshEnergy 27287295360 # Energy for refresh commands per rank (pJ)
282 system.physmem_1.actBackEnergy 61807042845 # Energy for active background per rank (pJ)
283 system.physmem_1.preBackEnergy 196450861500 # Energy for precharge background per rank (pJ)
284 system.physmem_1.totalEnergy 288806015160 # Total energy per rank (pJ)
285 system.physmem_1.averagePower 691.288514 # Core power per rank (mW)
286 system.physmem_1.memoryStateTime::IDLE 326265955250 # Time in different power states
287 system.physmem_1.memoryStateTime::REF 13950560000 # Time in different power states
288 system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
289 system.physmem_1.memoryStateTime::ACT 77563900250 # Time in different power states
290 system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
291 system.cpu.branchPred.lookups 230228501 # Number of BP lookups
292 system.cpu.branchPred.condPredicted 230228501 # Number of conditional branches predicted
293 system.cpu.branchPred.condIncorrect 9739021 # Number of conditional branches incorrect
294 system.cpu.branchPred.BTBLookups 131459692 # Number of BTB lookups
295 system.cpu.branchPred.BTBHits 128773186 # Number of BTB hits
296 system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
297 system.cpu.branchPred.BTBHitPct 97.956403 # BTB Hit Percentage
298 system.cpu.branchPred.usedRAS 27739164 # Number of times the RAS was used to get a target.
299 system.cpu.branchPred.RASInCorrect 1472550 # Number of incorrect RAS predictions.
300 system.cpu_clk_domain.clock 500 # Clock period in ticks
301 system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
302 system.cpu.workload.num_syscalls 551 # Number of system calls
303 system.cpu.numCycles 835569292 # number of cpu cycles simulated
304 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
305 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
306 system.cpu.fetch.icacheStallCycles 185184379 # Number of cycles fetch is stalled on an Icache miss
307 system.cpu.fetch.Insts 1269166320 # Number of instructions fetch has processed
308 system.cpu.fetch.Branches 230228501 # Number of branches that fetch encountered
309 system.cpu.fetch.predictedBranches 156512350 # Number of branches that fetch has predicted taken
310 system.cpu.fetch.Cycles 639147953 # Number of cycles fetch has run and was not squashing or blocked
311 system.cpu.fetch.SquashCycles 20213743 # Number of cycles fetch has spent squashing
312 system.cpu.fetch.TlbCycles 511 # Number of cycles fetch has spent waiting for tlb
313 system.cpu.fetch.MiscStallCycles 99253 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
314 system.cpu.fetch.PendingTrapStallCycles 822297 # Number of stall cycles due to pending traps
315 system.cpu.fetch.PendingQuiesceStallCycles 1772 # Number of stall cycles due to pending quiesce instructions
316 system.cpu.fetch.IcacheWaitRetryStallCycles 30 # Number of stall cycles due to full MSHR
317 system.cpu.fetch.CacheLines 179484418 # Number of cache lines fetched
318 system.cpu.fetch.IcacheSquashes 2740851 # Number of outstanding Icache misses that were squashed
319 system.cpu.fetch.ItlbSquashes 7 # Number of outstanding ITLB misses that were squashed
320 system.cpu.fetch.rateDist::samples 835363066 # Number of instructions fetched each cycle (Total)
321 system.cpu.fetch.rateDist::mean 2.826562 # Number of instructions fetched each cycle (Total)
322 system.cpu.fetch.rateDist::stdev 3.382493 # Number of instructions fetched each cycle (Total)
323 system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
324 system.cpu.fetch.rateDist::0 427868247 51.22% 51.22% # Number of instructions fetched each cycle (Total)
325 system.cpu.fetch.rateDist::1 33702021 4.03% 55.25% # Number of instructions fetched each cycle (Total)
326 system.cpu.fetch.rateDist::2 32929710 3.94% 59.20% # Number of instructions fetched each cycle (Total)
327 system.cpu.fetch.rateDist::3 33265996 3.98% 63.18% # Number of instructions fetched each cycle (Total)
328 system.cpu.fetch.rateDist::4 27012416 3.23% 66.41% # Number of instructions fetched each cycle (Total)
329 system.cpu.fetch.rateDist::5 27748723 3.32% 69.73% # Number of instructions fetched each cycle (Total)
330 system.cpu.fetch.rateDist::6 36992796 4.43% 74.16% # Number of instructions fetched each cycle (Total)
331 system.cpu.fetch.rateDist::7 33648824 4.03% 78.19% # Number of instructions fetched each cycle (Total)
332 system.cpu.fetch.rateDist::8 182194333 21.81% 100.00% # Number of instructions fetched each cycle (Total)
333 system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
334 system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
335 system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
336 system.cpu.fetch.rateDist::total 835363066 # Number of instructions fetched each cycle (Total)
337 system.cpu.fetch.branchRate 0.275535 # Number of branch fetches per cycle
338 system.cpu.fetch.rate 1.518924 # Number of inst fetches per cycle
339 system.cpu.decode.IdleCycles 127510375 # Number of cycles decode is idle
340 system.cpu.decode.BlockedCycles 375947418 # Number of cycles decode is blocked
341 system.cpu.decode.RunCycles 240571925 # Number of cycles decode is running
342 system.cpu.decode.UnblockCycles 81226477 # Number of cycles decode is unblocking
343 system.cpu.decode.SquashCycles 10106871 # Number of cycles decode is squashing
344 system.cpu.decode.DecodedInsts 2225382694 # Number of instructions handled by decode
345 system.cpu.rename.SquashCycles 10106871 # Number of cycles rename is squashing
346 system.cpu.rename.IdleCycles 159640008 # Number of cycles rename is idle
347 system.cpu.rename.BlockCycles 160513488 # Number of cycles rename is blocking
348 system.cpu.rename.serializeStallCycles 42854 # count of cycles rename stalled for serializing inst
349 system.cpu.rename.RunCycles 285557624 # Number of cycles rename is running
350 system.cpu.rename.UnblockCycles 219502221 # Number of cycles rename is unblocking
351 system.cpu.rename.RenamedInsts 2175351414 # Number of instructions processed by rename
352 system.cpu.rename.ROBFullEvents 185986 # Number of times rename has blocked due to ROB full
353 system.cpu.rename.IQFullEvents 136028392 # Number of times rename has blocked due to IQ full
354 system.cpu.rename.LQFullEvents 24255750 # Number of times rename has blocked due to LQ full
355 system.cpu.rename.SQFullEvents 49096014 # Number of times rename has blocked due to SQ full
356 system.cpu.rename.RenamedOperands 2279465980 # Number of destination operands rename has renamed
357 system.cpu.rename.RenameLookups 5501874168 # Number of register rename lookups that rename has made
358 system.cpu.rename.int_rename_lookups 3499442561 # Number of integer rename lookups
359 system.cpu.rename.fp_rename_lookups 66867 # Number of floating rename lookups
360 system.cpu.rename.CommittedMaps 1614040854 # Number of HB maps that are committed
361 system.cpu.rename.UndoneMaps 665425126 # Number of HB maps that are undone due to squashing
362 system.cpu.rename.serializingInsts 3167 # count of serializing insts renamed
363 system.cpu.rename.tempSerializingInsts 2999 # count of temporary serializing insts renamed
364 system.cpu.rename.skidInsts 415602419 # count of insts added to the skid buffer
365 system.cpu.memDep0.insertedLoads 528341229 # Number of loads inserted to the mem dependence unit.
366 system.cpu.memDep0.insertedStores 209838821 # Number of stores inserted to the mem dependence unit.
367 system.cpu.memDep0.conflictingLoads 239501304 # Number of conflicting loads.
368 system.cpu.memDep0.conflictingStores 72157646 # Number of conflicting stores.
369 system.cpu.iq.iqInstsAdded 2101036293 # Number of instructions added to the IQ (excludes non-spec)
370 system.cpu.iq.iqNonSpecInstsAdded 25395 # Number of non-speculative instructions added to the IQ
371 system.cpu.iq.iqInstsIssued 1826926557 # Number of instructions issued
372 system.cpu.iq.iqSquashedInstsIssued 429463 # Number of squashed instructions issued
373 system.cpu.iq.iqSquashedInstsExamined 572072987 # Number of squashed instructions iterated over during squash; mainly for profiling
374 system.cpu.iq.iqSquashedOperandsExamined 974001425 # Number of squashed operands that are examined and possibly removed from graph
375 system.cpu.iq.iqSquashedNonSpecRemoved 24843 # Number of squashed non-spec instructions that were removed
376 system.cpu.iq.issued_per_cycle::samples 835363066 # Number of insts issued each cycle
377 system.cpu.iq.issued_per_cycle::mean 2.186985 # Number of insts issued each cycle
378 system.cpu.iq.issued_per_cycle::stdev 2.073368 # Number of insts issued each cycle
379 system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
380 system.cpu.iq.issued_per_cycle::0 255962202 30.64% 30.64% # Number of insts issued each cycle
381 system.cpu.iq.issued_per_cycle::1 125607638 15.04% 45.68% # Number of insts issued each cycle
382 system.cpu.iq.issued_per_cycle::2 118770145 14.22% 59.89% # Number of insts issued each cycle
383 system.cpu.iq.issued_per_cycle::3 111086257 13.30% 73.19% # Number of insts issued each cycle
384 system.cpu.iq.issued_per_cycle::4 92824001 11.11% 84.30% # Number of insts issued each cycle
385 system.cpu.iq.issued_per_cycle::5 61460839 7.36% 91.66% # Number of insts issued each cycle
386 system.cpu.iq.issued_per_cycle::6 43056890 5.15% 96.82% # Number of insts issued each cycle
387 system.cpu.iq.issued_per_cycle::7 19182433 2.30% 99.11% # Number of insts issued each cycle
388 system.cpu.iq.issued_per_cycle::8 7412661 0.89% 100.00% # Number of insts issued each cycle
389 system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
390 system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
391 system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
392 system.cpu.iq.issued_per_cycle::total 835363066 # Number of insts issued each cycle
393 system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
394 system.cpu.iq.fu_full::IntAlu 11317596 42.46% 42.46% # attempts to use FU when none available
395 system.cpu.iq.fu_full::IntMult 0 0.00% 42.46% # attempts to use FU when none available
396 system.cpu.iq.fu_full::IntDiv 0 0.00% 42.46% # attempts to use FU when none available
397 system.cpu.iq.fu_full::FloatAdd 0 0.00% 42.46% # attempts to use FU when none available
398 system.cpu.iq.fu_full::FloatCmp 0 0.00% 42.46% # attempts to use FU when none available
399 system.cpu.iq.fu_full::FloatCvt 0 0.00% 42.46% # attempts to use FU when none available
400 system.cpu.iq.fu_full::FloatMult 0 0.00% 42.46% # attempts to use FU when none available
401 system.cpu.iq.fu_full::FloatDiv 0 0.00% 42.46% # attempts to use FU when none available
402 system.cpu.iq.fu_full::FloatSqrt 0 0.00% 42.46% # attempts to use FU when none available
403 system.cpu.iq.fu_full::SimdAdd 0 0.00% 42.46% # attempts to use FU when none available
404 system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 42.46% # attempts to use FU when none available
405 system.cpu.iq.fu_full::SimdAlu 0 0.00% 42.46% # attempts to use FU when none available
406 system.cpu.iq.fu_full::SimdCmp 0 0.00% 42.46% # attempts to use FU when none available
407 system.cpu.iq.fu_full::SimdCvt 0 0.00% 42.46% # attempts to use FU when none available
408 system.cpu.iq.fu_full::SimdMisc 0 0.00% 42.46% # attempts to use FU when none available
409 system.cpu.iq.fu_full::SimdMult 0 0.00% 42.46% # attempts to use FU when none available
410 system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 42.46% # attempts to use FU when none available
411 system.cpu.iq.fu_full::SimdShift 0 0.00% 42.46% # attempts to use FU when none available
412 system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 42.46% # attempts to use FU when none available
413 system.cpu.iq.fu_full::SimdSqrt 0 0.00% 42.46% # attempts to use FU when none available
414 system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 42.46% # attempts to use FU when none available
415 system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 42.46% # attempts to use FU when none available
416 system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 42.46% # attempts to use FU when none available
417 system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 42.46% # attempts to use FU when none available
418 system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 42.46% # attempts to use FU when none available
419 system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 42.46% # attempts to use FU when none available
420 system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 42.46% # attempts to use FU when none available
421 system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 42.46% # attempts to use FU when none available
422 system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 42.46% # attempts to use FU when none available
423 system.cpu.iq.fu_full::MemRead 12272214 46.05% 88.51% # attempts to use FU when none available
424 system.cpu.iq.fu_full::MemWrite 3062486 11.49% 100.00% # attempts to use FU when none available
425 system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
426 system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
427 system.cpu.iq.FU_type_0::No_OpClass 2719434 0.15% 0.15% # Type of FU issued
428 system.cpu.iq.FU_type_0::IntAlu 1211207278 66.30% 66.45% # Type of FU issued
429 system.cpu.iq.FU_type_0::IntMult 389699 0.02% 66.47% # Type of FU issued
430 system.cpu.iq.FU_type_0::IntDiv 3880989 0.21% 66.68% # Type of FU issued
431 system.cpu.iq.FU_type_0::FloatAdd 135 0.00% 66.68% # Type of FU issued
432 system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.68% # Type of FU issued
433 system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.68% # Type of FU issued
434 system.cpu.iq.FU_type_0::FloatMult 39 0.00% 66.68% # Type of FU issued
435 system.cpu.iq.FU_type_0::FloatDiv 410 0.00% 66.68% # Type of FU issued
436 system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.68% # Type of FU issued
437 system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.68% # Type of FU issued
438 system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.68% # Type of FU issued
439 system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.68% # Type of FU issued
440 system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.68% # Type of FU issued
441 system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.68% # Type of FU issued
442 system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.68% # Type of FU issued
443 system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.68% # Type of FU issued
444 system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.68% # Type of FU issued
445 system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.68% # Type of FU issued
446 system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.68% # Type of FU issued
447 system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.68% # Type of FU issued
448 system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.68% # Type of FU issued
449 system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.68% # Type of FU issued
450 system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.68% # Type of FU issued
451 system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.68% # Type of FU issued
452 system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.68% # Type of FU issued
453 system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.68% # Type of FU issued
454 system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.68% # Type of FU issued
455 system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.68% # Type of FU issued
456 system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.68% # Type of FU issued
457 system.cpu.iq.FU_type_0::MemRead 435021653 23.81% 90.49% # Type of FU issued
458 system.cpu.iq.FU_type_0::MemWrite 173706920 9.51% 100.00% # Type of FU issued
459 system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
460 system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
461 system.cpu.iq.FU_type_0::total 1826926557 # Type of FU issued
462 system.cpu.iq.rate 2.186445 # Inst issue rate
463 system.cpu.iq.fu_busy_cnt 26652296 # FU busy when requested
464 system.cpu.iq.fu_busy_rate 0.014589 # FU busy rate (busy events/executed inst)
465 system.cpu.iq.int_inst_queue_reads 4516265766 # Number of integer instruction queue reads
466 system.cpu.iq.int_inst_queue_writes 2673396604 # Number of integer instruction queue writes
467 system.cpu.iq.int_inst_queue_wakeup_accesses 1796798251 # Number of integer instruction queue wakeup accesses
468 system.cpu.iq.fp_inst_queue_reads 32173 # Number of floating instruction queue reads
469 system.cpu.iq.fp_inst_queue_writes 70520 # Number of floating instruction queue writes
470 system.cpu.iq.fp_inst_queue_wakeup_accesses 7153 # Number of floating instruction queue wakeup accesses
471 system.cpu.iq.int_alu_accesses 1850844448 # Number of integer alu accesses
472 system.cpu.iq.fp_alu_accesses 14971 # Number of floating point alu accesses
473 system.cpu.iew.lsq.thread0.forwLoads 185549711 # Number of loads that had data forwarded from stores
474 system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
475 system.cpu.iew.lsq.thread0.squashedLoads 144242393 # Number of loads squashed
476 system.cpu.iew.lsq.thread0.ignoredResponses 210251 # Number of memory responses ignored because the instruction is squashed
477 system.cpu.iew.lsq.thread0.memOrderViolation 386532 # Number of memory ordering violations
478 system.cpu.iew.lsq.thread0.squashedStores 60678635 # Number of stores squashed
479 system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
480 system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
481 system.cpu.iew.lsq.thread0.rescheduledLoads 19153 # Number of loads that were rescheduled
482 system.cpu.iew.lsq.thread0.cacheBlocked 1029 # Number of times an access to memory failed due to the cache being blocked
483 system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
484 system.cpu.iew.iewSquashCycles 10106871 # Number of cycles IEW is squashing
485 system.cpu.iew.iewBlockCycles 107291908 # Number of cycles IEW is blocking
486 system.cpu.iew.iewUnblockCycles 6438859 # Number of cycles IEW is unblocking
487 system.cpu.iew.iewDispatchedInsts 2101061688 # Number of instructions dispatched to IQ
488 system.cpu.iew.iewDispSquashedInsts 392799 # Number of squashed instructions skipped by dispatch
489 system.cpu.iew.iewDispLoadInsts 528344550 # Number of dispatched load instructions
490 system.cpu.iew.iewDispStoreInsts 209838821 # Number of dispatched store instructions
491 system.cpu.iew.iewDispNonSpecInsts 7385 # Number of dispatched non-speculative instructions
492 system.cpu.iew.iewIQFullEvents 1906737 # Number of times the IQ has become full, causing a stall
493 system.cpu.iew.iewLSQFullEvents 3653179 # Number of times the LSQ has become full, causing a stall
494 system.cpu.iew.memOrderViolationEvents 386532 # Number of memory order violations
495 system.cpu.iew.predictedTakenIncorrect 5738958 # Number of branches that were predicted taken incorrectly
496 system.cpu.iew.predictedNotTakenIncorrect 4581595 # Number of branches that were predicted not taken incorrectly
497 system.cpu.iew.branchMispredicts 10320553 # Number of branch mispredicts detected at execute
498 system.cpu.iew.iewExecutedInsts 1805492449 # Number of executed instructions
499 system.cpu.iew.iewExecLoadInsts 428838978 # Number of load instructions executed
500 system.cpu.iew.iewExecSquashedInsts 21434108 # Number of squashed instructions skipped in execute
501 system.cpu.iew.exec_swp 0 # number of swp insts executed
502 system.cpu.iew.exec_nop 0 # number of nop insts executed
503 system.cpu.iew.exec_refs 598981338 # number of memory reference insts executed
504 system.cpu.iew.exec_branches 171787473 # Number of branches executed
505 system.cpu.iew.exec_stores 170142360 # Number of stores executed
506 system.cpu.iew.exec_rate 2.160793 # Inst execution rate
507 system.cpu.iew.wb_sent 1802094257 # cumulative count of insts sent to commit
508 system.cpu.iew.wb_count 1796805404 # cumulative count of insts written-back
509 system.cpu.iew.wb_producers 1368063103 # num instructions producing a value
510 system.cpu.iew.wb_consumers 2090238527 # num instructions consuming a value
511 system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
512 system.cpu.iew.wb_rate 2.150397 # insts written-back per cycle
513 system.cpu.iew.wb_fanout 0.654501 # average fanout of values written-back
514 system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
515 system.cpu.commit.commitSquashedInsts 572152437 # The number of squashed insts skipped by commit
516 system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards
517 system.cpu.commit.branchMispredicts 9826757 # The number of times a branch was mispredicted
518 system.cpu.commit.committed_per_cycle::samples 757699482 # Number of insts commited each cycle
519 system.cpu.commit.committed_per_cycle::mean 2.017936 # Number of insts commited each cycle
520 system.cpu.commit.committed_per_cycle::stdev 2.547497 # Number of insts commited each cycle
521 system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
522 system.cpu.commit.committed_per_cycle::0 289066041 38.15% 38.15% # Number of insts commited each cycle
523 system.cpu.commit.committed_per_cycle::1 175144894 23.12% 61.27% # Number of insts commited each cycle
524 system.cpu.commit.committed_per_cycle::2 57411271 7.58% 68.84% # Number of insts commited each cycle
525 system.cpu.commit.committed_per_cycle::3 86235215 11.38% 80.22% # Number of insts commited each cycle
526 system.cpu.commit.committed_per_cycle::4 27150149 3.58% 83.81% # Number of insts commited each cycle
527 system.cpu.commit.committed_per_cycle::5 27136057 3.58% 87.39% # Number of insts commited each cycle
528 system.cpu.commit.committed_per_cycle::6 9784065 1.29% 88.68% # Number of insts commited each cycle
529 system.cpu.commit.committed_per_cycle::7 8843971 1.17% 89.85% # Number of insts commited each cycle
530 system.cpu.commit.committed_per_cycle::8 76927819 10.15% 100.00% # Number of insts commited each cycle
531 system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
532 system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
533 system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
534 system.cpu.commit.committed_per_cycle::total 757699482 # Number of insts commited each cycle
535 system.cpu.commit.committedInsts 826877109 # Number of instructions committed
536 system.cpu.commit.committedOps 1528988701 # Number of ops (including micro ops) committed
537 system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
538 system.cpu.commit.refs 533262343 # Number of memory references committed
539 system.cpu.commit.loads 384102157 # Number of loads committed
540 system.cpu.commit.membars 0 # Number of memory barriers committed
541 system.cpu.commit.branches 149758583 # Number of branches committed
542 system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
543 system.cpu.commit.int_insts 1526605509 # Number of committed integer instructions.
544 system.cpu.commit.function_calls 17673145 # Number of function calls committed.
545 system.cpu.commit.op_class_0::No_OpClass 1819099 0.12% 0.12% # Class of committed instruction
546 system.cpu.commit.op_class_0::IntAlu 989721889 64.73% 64.85% # Class of committed instruction
547 system.cpu.commit.op_class_0::IntMult 306834 0.02% 64.87% # Class of committed instruction
548 system.cpu.commit.op_class_0::IntDiv 3878536 0.25% 65.12% # Class of committed instruction
549 system.cpu.commit.op_class_0::FloatAdd 0 0.00% 65.12% # Class of committed instruction
550 system.cpu.commit.op_class_0::FloatCmp 0 0.00% 65.12% # Class of committed instruction
551 system.cpu.commit.op_class_0::FloatCvt 0 0.00% 65.12% # Class of committed instruction
552 system.cpu.commit.op_class_0::FloatMult 0 0.00% 65.12% # Class of committed instruction
553 system.cpu.commit.op_class_0::FloatDiv 0 0.00% 65.12% # Class of committed instruction
554 system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 65.12% # Class of committed instruction
555 system.cpu.commit.op_class_0::SimdAdd 0 0.00% 65.12% # Class of committed instruction
556 system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 65.12% # Class of committed instruction
557 system.cpu.commit.op_class_0::SimdAlu 0 0.00% 65.12% # Class of committed instruction
558 system.cpu.commit.op_class_0::SimdCmp 0 0.00% 65.12% # Class of committed instruction
559 system.cpu.commit.op_class_0::SimdCvt 0 0.00% 65.12% # Class of committed instruction
560 system.cpu.commit.op_class_0::SimdMisc 0 0.00% 65.12% # Class of committed instruction
561 system.cpu.commit.op_class_0::SimdMult 0 0.00% 65.12% # Class of committed instruction
562 system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 65.12% # Class of committed instruction
563 system.cpu.commit.op_class_0::SimdShift 0 0.00% 65.12% # Class of committed instruction
564 system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 65.12% # Class of committed instruction
565 system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 65.12% # Class of committed instruction
566 system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 65.12% # Class of committed instruction
567 system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 65.12% # Class of committed instruction
568 system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 65.12% # Class of committed instruction
569 system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 65.12% # Class of committed instruction
570 system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 65.12% # Class of committed instruction
571 system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 65.12% # Class of committed instruction
572 system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 65.12% # Class of committed instruction
573 system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.12% # Class of committed instruction
574 system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.12% # Class of committed instruction
575 system.cpu.commit.op_class_0::MemRead 384102157 25.12% 90.24% # Class of committed instruction
576 system.cpu.commit.op_class_0::MemWrite 149160186 9.76% 100.00% # Class of committed instruction
577 system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
578 system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
579 system.cpu.commit.op_class_0::total 1528988701 # Class of committed instruction
580 system.cpu.commit.bw_lim_events 76927819 # number cycles where commit BW limit reached
581 system.cpu.rob.rob_reads 2781912801 # The number of ROB reads
582 system.cpu.rob.rob_writes 4280130406 # The number of ROB writes
583 system.cpu.timesIdled 2299 # Number of times that the entire CPU went into an idle state and unscheduled itself
584 system.cpu.idleCycles 206226 # Total number of cycles that the CPU has spent unscheduled due to idling
585 system.cpu.committedInsts 826877109 # Number of Instructions Simulated
586 system.cpu.committedOps 1528988701 # Number of Ops (including micro ops) Simulated
587 system.cpu.cpi 1.010512 # CPI: Cycles Per Instruction
588 system.cpu.cpi_total 1.010512 # CPI: Total CPI of All Threads
589 system.cpu.ipc 0.989597 # IPC: Instructions Per Cycle
590 system.cpu.ipc_total 0.989597 # IPC: Total IPC of All Threads
591 system.cpu.int_regfile_reads 2761971319 # number of integer regfile reads
592 system.cpu.int_regfile_writes 1465030124 # number of integer regfile writes
593 system.cpu.fp_regfile_reads 7481 # number of floating regfile reads
594 system.cpu.fp_regfile_writes 493 # number of floating regfile writes
595 system.cpu.cc_regfile_reads 600902917 # number of cc regfile reads
596 system.cpu.cc_regfile_writes 409659635 # number of cc regfile writes
597 system.cpu.misc_regfile_reads 990136590 # number of misc regfile reads
598 system.cpu.misc_regfile_writes 1 # number of misc regfile writes
599 system.cpu.dcache.tags.replacements 2534249 # number of replacements
600 system.cpu.dcache.tags.tagsinuse 4087.994933 # Cycle average of tags in use
601 system.cpu.dcache.tags.total_refs 387820460 # Total number of references to valid blocks.
602 system.cpu.dcache.tags.sampled_refs 2538345 # Sample count of references to valid blocks.
603 system.cpu.dcache.tags.avg_refs 152.784771 # Average number of references to valid blocks.
604 system.cpu.dcache.tags.warmup_cycle 1688557250 # Cycle when the warmup percentage was hit.
605 system.cpu.dcache.tags.occ_blocks::cpu.data 4087.994933 # Average occupied blocks per requestor
606 system.cpu.dcache.tags.occ_percent::cpu.data 0.998046 # Average percentage of cache occupancy
607 system.cpu.dcache.tags.occ_percent::total 0.998046 # Average percentage of cache occupancy
608 system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
609 system.cpu.dcache.tags.age_task_id_blocks_1024::0 28 # Occupied blocks per task id
610 system.cpu.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id
611 system.cpu.dcache.tags.age_task_id_blocks_1024::2 869 # Occupied blocks per task id
612 system.cpu.dcache.tags.age_task_id_blocks_1024::3 3173 # Occupied blocks per task id
613 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
614 system.cpu.dcache.tags.tag_accesses 784768509 # Number of tag accesses
615 system.cpu.dcache.tags.data_accesses 784768509 # Number of data accesses
616 system.cpu.dcache.ReadReq_hits::cpu.data 239165062 # number of ReadReq hits
617 system.cpu.dcache.ReadReq_hits::total 239165062 # number of ReadReq hits
618 system.cpu.dcache.WriteReq_hits::cpu.data 148173846 # number of WriteReq hits
619 system.cpu.dcache.WriteReq_hits::total 148173846 # number of WriteReq hits
620 system.cpu.dcache.demand_hits::cpu.data 387338908 # number of demand (read+write) hits
621 system.cpu.dcache.demand_hits::total 387338908 # number of demand (read+write) hits
622 system.cpu.dcache.overall_hits::cpu.data 387338908 # number of overall hits
623 system.cpu.dcache.overall_hits::total 387338908 # number of overall hits
624 system.cpu.dcache.ReadReq_misses::cpu.data 2789818 # number of ReadReq misses
625 system.cpu.dcache.ReadReq_misses::total 2789818 # number of ReadReq misses
626 system.cpu.dcache.WriteReq_misses::cpu.data 986356 # number of WriteReq misses
627 system.cpu.dcache.WriteReq_misses::total 986356 # number of WriteReq misses
628 system.cpu.dcache.demand_misses::cpu.data 3776174 # number of demand (read+write) misses
629 system.cpu.dcache.demand_misses::total 3776174 # number of demand (read+write) misses
630 system.cpu.dcache.overall_misses::cpu.data 3776174 # number of overall misses
631 system.cpu.dcache.overall_misses::total 3776174 # number of overall misses
632 system.cpu.dcache.ReadReq_miss_latency::cpu.data 60126724251 # number of ReadReq miss cycles
633 system.cpu.dcache.ReadReq_miss_latency::total 60126724251 # number of ReadReq miss cycles
634 system.cpu.dcache.WriteReq_miss_latency::cpu.data 31294703774 # number of WriteReq miss cycles
635 system.cpu.dcache.WriteReq_miss_latency::total 31294703774 # number of WriteReq miss cycles
636 system.cpu.dcache.demand_miss_latency::cpu.data 91421428025 # number of demand (read+write) miss cycles
637 system.cpu.dcache.demand_miss_latency::total 91421428025 # number of demand (read+write) miss cycles
638 system.cpu.dcache.overall_miss_latency::cpu.data 91421428025 # number of overall miss cycles
639 system.cpu.dcache.overall_miss_latency::total 91421428025 # number of overall miss cycles
640 system.cpu.dcache.ReadReq_accesses::cpu.data 241954880 # number of ReadReq accesses(hits+misses)
641 system.cpu.dcache.ReadReq_accesses::total 241954880 # number of ReadReq accesses(hits+misses)
642 system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses)
643 system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses)
644 system.cpu.dcache.demand_accesses::cpu.data 391115082 # number of demand (read+write) accesses
645 system.cpu.dcache.demand_accesses::total 391115082 # number of demand (read+write) accesses
646 system.cpu.dcache.overall_accesses::cpu.data 391115082 # number of overall (read+write) accesses
647 system.cpu.dcache.overall_accesses::total 391115082 # number of overall (read+write) accesses
648 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011530 # miss rate for ReadReq accesses
649 system.cpu.dcache.ReadReq_miss_rate::total 0.011530 # miss rate for ReadReq accesses
650 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006613 # miss rate for WriteReq accesses
651 system.cpu.dcache.WriteReq_miss_rate::total 0.006613 # miss rate for WriteReq accesses
652 system.cpu.dcache.demand_miss_rate::cpu.data 0.009655 # miss rate for demand accesses
653 system.cpu.dcache.demand_miss_rate::total 0.009655 # miss rate for demand accesses
654 system.cpu.dcache.overall_miss_rate::cpu.data 0.009655 # miss rate for overall accesses
655 system.cpu.dcache.overall_miss_rate::total 0.009655 # miss rate for overall accesses
656 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21552.203137 # average ReadReq miss latency
657 system.cpu.dcache.ReadReq_avg_miss_latency::total 21552.203137 # average ReadReq miss latency
658 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31727.595081 # average WriteReq miss latency
659 system.cpu.dcache.WriteReq_avg_miss_latency::total 31727.595081 # average WriteReq miss latency
660 system.cpu.dcache.demand_avg_miss_latency::cpu.data 24210.067657 # average overall miss latency
661 system.cpu.dcache.demand_avg_miss_latency::total 24210.067657 # average overall miss latency
662 system.cpu.dcache.overall_avg_miss_latency::cpu.data 24210.067657 # average overall miss latency
663 system.cpu.dcache.overall_avg_miss_latency::total 24210.067657 # average overall miss latency
664 system.cpu.dcache.blocked_cycles::no_mshrs 10621 # number of cycles access was blocked
665 system.cpu.dcache.blocked_cycles::no_targets 71 # number of cycles access was blocked
666 system.cpu.dcache.blocked::no_mshrs 1078 # number of cycles access was blocked
667 system.cpu.dcache.blocked::no_targets 5 # number of cycles access was blocked
668 system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.852505 # average number of cycles each access was blocked
669 system.cpu.dcache.avg_blocked_cycles::no_targets 14.200000 # average number of cycles each access was blocked
670 system.cpu.dcache.fast_writes 0 # number of fast writes performed
671 system.cpu.dcache.cache_copies 0 # number of cache copies performed
672 system.cpu.dcache.writebacks::writebacks 2332976 # number of writebacks
673 system.cpu.dcache.writebacks::total 2332976 # number of writebacks
674 system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1022764 # number of ReadReq MSHR hits
675 system.cpu.dcache.ReadReq_mshr_hits::total 1022764 # number of ReadReq MSHR hits
676 system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18373 # number of WriteReq MSHR hits
677 system.cpu.dcache.WriteReq_mshr_hits::total 18373 # number of WriteReq MSHR hits
678 system.cpu.dcache.demand_mshr_hits::cpu.data 1041137 # number of demand (read+write) MSHR hits
679 system.cpu.dcache.demand_mshr_hits::total 1041137 # number of demand (read+write) MSHR hits
680 system.cpu.dcache.overall_mshr_hits::cpu.data 1041137 # number of overall MSHR hits
681 system.cpu.dcache.overall_mshr_hits::total 1041137 # number of overall MSHR hits
682 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1767054 # number of ReadReq MSHR misses
683 system.cpu.dcache.ReadReq_mshr_misses::total 1767054 # number of ReadReq MSHR misses
684 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 967983 # number of WriteReq MSHR misses
685 system.cpu.dcache.WriteReq_mshr_misses::total 967983 # number of WriteReq MSHR misses
686 system.cpu.dcache.demand_mshr_misses::cpu.data 2735037 # number of demand (read+write) MSHR misses
687 system.cpu.dcache.demand_mshr_misses::total 2735037 # number of demand (read+write) MSHR misses
688 system.cpu.dcache.overall_mshr_misses::cpu.data 2735037 # number of overall MSHR misses
689 system.cpu.dcache.overall_mshr_misses::total 2735037 # number of overall MSHR misses
690 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 32779636252 # number of ReadReq MSHR miss cycles
691 system.cpu.dcache.ReadReq_mshr_miss_latency::total 32779636252 # number of ReadReq MSHR miss cycles
692 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 29507402723 # number of WriteReq MSHR miss cycles
693 system.cpu.dcache.WriteReq_mshr_miss_latency::total 29507402723 # number of WriteReq MSHR miss cycles
694 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 62287038975 # number of demand (read+write) MSHR miss cycles
695 system.cpu.dcache.demand_mshr_miss_latency::total 62287038975 # number of demand (read+write) MSHR miss cycles
696 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 62287038975 # number of overall MSHR miss cycles
697 system.cpu.dcache.overall_mshr_miss_latency::total 62287038975 # number of overall MSHR miss cycles
698 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007303 # mshr miss rate for ReadReq accesses
699 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007303 # mshr miss rate for ReadReq accesses
700 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006490 # mshr miss rate for WriteReq accesses
701 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006490 # mshr miss rate for WriteReq accesses
702 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006993 # mshr miss rate for demand accesses
703 system.cpu.dcache.demand_mshr_miss_rate::total 0.006993 # mshr miss rate for demand accesses
704 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006993 # mshr miss rate for overall accesses
705 system.cpu.dcache.overall_mshr_miss_rate::total 0.006993 # mshr miss rate for overall accesses
706 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18550.443989 # average ReadReq mshr miss latency
707 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18550.443989 # average ReadReq mshr miss latency
708 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30483.389401 # average WriteReq mshr miss latency
709 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30483.389401 # average WriteReq mshr miss latency
710 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22773.746379 # average overall mshr miss latency
711 system.cpu.dcache.demand_avg_mshr_miss_latency::total 22773.746379 # average overall mshr miss latency
712 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22773.746379 # average overall mshr miss latency
713 system.cpu.dcache.overall_avg_mshr_miss_latency::total 22773.746379 # average overall mshr miss latency
714 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
715 system.cpu.icache.tags.replacements 7023 # number of replacements
716 system.cpu.icache.tags.tagsinuse 1053.963479 # Cycle average of tags in use
717 system.cpu.icache.tags.total_refs 179273130 # Total number of references to valid blocks.
718 system.cpu.icache.tags.sampled_refs 8620 # Sample count of references to valid blocks.
719 system.cpu.icache.tags.avg_refs 20797.346868 # Average number of references to valid blocks.
720 system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
721 system.cpu.icache.tags.occ_blocks::cpu.inst 1053.963479 # Average occupied blocks per requestor
722 system.cpu.icache.tags.occ_percent::cpu.inst 0.514631 # Average percentage of cache occupancy
723 system.cpu.icache.tags.occ_percent::total 0.514631 # Average percentage of cache occupancy
724 system.cpu.icache.tags.occ_task_id_blocks::1024 1597 # Occupied blocks per task id
725 system.cpu.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id
726 system.cpu.icache.tags.age_task_id_blocks_1024::1 16 # Occupied blocks per task id
727 system.cpu.icache.tags.age_task_id_blocks_1024::2 44 # Occupied blocks per task id
728 system.cpu.icache.tags.age_task_id_blocks_1024::3 319 # Occupied blocks per task id
729 system.cpu.icache.tags.age_task_id_blocks_1024::4 1155 # Occupied blocks per task id
730 system.cpu.icache.tags.occ_task_id_percent::1024 0.779785 # Percentage of cache occupancy per task id
731 system.cpu.icache.tags.tag_accesses 359174294 # Number of tag accesses
732 system.cpu.icache.tags.data_accesses 359174294 # Number of data accesses
733 system.cpu.icache.ReadReq_hits::cpu.inst 179276307 # number of ReadReq hits
734 system.cpu.icache.ReadReq_hits::total 179276307 # number of ReadReq hits
735 system.cpu.icache.demand_hits::cpu.inst 179276307 # number of demand (read+write) hits
736 system.cpu.icache.demand_hits::total 179276307 # number of demand (read+write) hits
737 system.cpu.icache.overall_hits::cpu.inst 179276307 # number of overall hits
738 system.cpu.icache.overall_hits::total 179276307 # number of overall hits
739 system.cpu.icache.ReadReq_misses::cpu.inst 208110 # number of ReadReq misses
740 system.cpu.icache.ReadReq_misses::total 208110 # number of ReadReq misses
741 system.cpu.icache.demand_misses::cpu.inst 208110 # number of demand (read+write) misses
742 system.cpu.icache.demand_misses::total 208110 # number of demand (read+write) misses
743 system.cpu.icache.overall_misses::cpu.inst 208110 # number of overall misses
744 system.cpu.icache.overall_misses::total 208110 # number of overall misses
745 system.cpu.icache.ReadReq_miss_latency::cpu.inst 1327923993 # number of ReadReq miss cycles
746 system.cpu.icache.ReadReq_miss_latency::total 1327923993 # number of ReadReq miss cycles
747 system.cpu.icache.demand_miss_latency::cpu.inst 1327923993 # number of demand (read+write) miss cycles
748 system.cpu.icache.demand_miss_latency::total 1327923993 # number of demand (read+write) miss cycles
749 system.cpu.icache.overall_miss_latency::cpu.inst 1327923993 # number of overall miss cycles
750 system.cpu.icache.overall_miss_latency::total 1327923993 # number of overall miss cycles
751 system.cpu.icache.ReadReq_accesses::cpu.inst 179484417 # number of ReadReq accesses(hits+misses)
752 system.cpu.icache.ReadReq_accesses::total 179484417 # number of ReadReq accesses(hits+misses)
753 system.cpu.icache.demand_accesses::cpu.inst 179484417 # number of demand (read+write) accesses
754 system.cpu.icache.demand_accesses::total 179484417 # number of demand (read+write) accesses
755 system.cpu.icache.overall_accesses::cpu.inst 179484417 # number of overall (read+write) accesses
756 system.cpu.icache.overall_accesses::total 179484417 # number of overall (read+write) accesses
757 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001159 # miss rate for ReadReq accesses
758 system.cpu.icache.ReadReq_miss_rate::total 0.001159 # miss rate for ReadReq accesses
759 system.cpu.icache.demand_miss_rate::cpu.inst 0.001159 # miss rate for demand accesses
760 system.cpu.icache.demand_miss_rate::total 0.001159 # miss rate for demand accesses
761 system.cpu.icache.overall_miss_rate::cpu.inst 0.001159 # miss rate for overall accesses
762 system.cpu.icache.overall_miss_rate::total 0.001159 # miss rate for overall accesses
763 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6380.875465 # average ReadReq miss latency
764 system.cpu.icache.ReadReq_avg_miss_latency::total 6380.875465 # average ReadReq miss latency
765 system.cpu.icache.demand_avg_miss_latency::cpu.inst 6380.875465 # average overall miss latency
766 system.cpu.icache.demand_avg_miss_latency::total 6380.875465 # average overall miss latency
767 system.cpu.icache.overall_avg_miss_latency::cpu.inst 6380.875465 # average overall miss latency
768 system.cpu.icache.overall_avg_miss_latency::total 6380.875465 # average overall miss latency
769 system.cpu.icache.blocked_cycles::no_mshrs 695 # number of cycles access was blocked
770 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
771 system.cpu.icache.blocked::no_mshrs 12 # number of cycles access was blocked
772 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
773 system.cpu.icache.avg_blocked_cycles::no_mshrs 57.916667 # average number of cycles each access was blocked
774 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
775 system.cpu.icache.fast_writes 0 # number of fast writes performed
776 system.cpu.icache.cache_copies 0 # number of cache copies performed
777 system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2649 # number of ReadReq MSHR hits
778 system.cpu.icache.ReadReq_mshr_hits::total 2649 # number of ReadReq MSHR hits
779 system.cpu.icache.demand_mshr_hits::cpu.inst 2649 # number of demand (read+write) MSHR hits
780 system.cpu.icache.demand_mshr_hits::total 2649 # number of demand (read+write) MSHR hits
781 system.cpu.icache.overall_mshr_hits::cpu.inst 2649 # number of overall MSHR hits
782 system.cpu.icache.overall_mshr_hits::total 2649 # number of overall MSHR hits
783 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 205461 # number of ReadReq MSHR misses
784 system.cpu.icache.ReadReq_mshr_misses::total 205461 # number of ReadReq MSHR misses
785 system.cpu.icache.demand_mshr_misses::cpu.inst 205461 # number of demand (read+write) MSHR misses
786 system.cpu.icache.demand_mshr_misses::total 205461 # number of demand (read+write) MSHR misses
787 system.cpu.icache.overall_mshr_misses::cpu.inst 205461 # number of overall MSHR misses
788 system.cpu.icache.overall_mshr_misses::total 205461 # number of overall MSHR misses
789 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 892683754 # number of ReadReq MSHR miss cycles
790 system.cpu.icache.ReadReq_mshr_miss_latency::total 892683754 # number of ReadReq MSHR miss cycles
791 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 892683754 # number of demand (read+write) MSHR miss cycles
792 system.cpu.icache.demand_mshr_miss_latency::total 892683754 # number of demand (read+write) MSHR miss cycles
793 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 892683754 # number of overall MSHR miss cycles
794 system.cpu.icache.overall_mshr_miss_latency::total 892683754 # number of overall MSHR miss cycles
795 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001145 # mshr miss rate for ReadReq accesses
796 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001145 # mshr miss rate for ReadReq accesses
797 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001145 # mshr miss rate for demand accesses
798 system.cpu.icache.demand_mshr_miss_rate::total 0.001145 # mshr miss rate for demand accesses
799 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001145 # mshr miss rate for overall accesses
800 system.cpu.icache.overall_mshr_miss_rate::total 0.001145 # mshr miss rate for overall accesses
801 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 4344.784431 # average ReadReq mshr miss latency
802 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 4344.784431 # average ReadReq mshr miss latency
803 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 4344.784431 # average overall mshr miss latency
804 system.cpu.icache.demand_avg_mshr_miss_latency::total 4344.784431 # average overall mshr miss latency
805 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4344.784431 # average overall mshr miss latency
806 system.cpu.icache.overall_avg_mshr_miss_latency::total 4344.784431 # average overall mshr miss latency
807 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
808 system.cpu.l2cache.tags.replacements 354223 # number of replacements
809 system.cpu.l2cache.tags.tagsinuse 29619.061304 # Cycle average of tags in use
810 system.cpu.l2cache.tags.total_refs 3704244 # Total number of references to valid blocks.
811 system.cpu.l2cache.tags.sampled_refs 386583 # Sample count of references to valid blocks.
812 system.cpu.l2cache.tags.avg_refs 9.582015 # Average number of references to valid blocks.
813 system.cpu.l2cache.tags.warmup_cycle 197893481000 # Cycle when the warmup percentage was hit.
814 system.cpu.l2cache.tags.occ_blocks::writebacks 21085.370146 # Average occupied blocks per requestor
815 system.cpu.l2cache.tags.occ_blocks::cpu.inst 251.812049 # Average occupied blocks per requestor
816 system.cpu.l2cache.tags.occ_blocks::cpu.data 8281.879109 # Average occupied blocks per requestor
817 system.cpu.l2cache.tags.occ_percent::writebacks 0.643474 # Average percentage of cache occupancy
818 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.007685 # Average percentage of cache occupancy
819 system.cpu.l2cache.tags.occ_percent::cpu.data 0.252743 # Average percentage of cache occupancy
820 system.cpu.l2cache.tags.occ_percent::total 0.903902 # Average percentage of cache occupancy
821 system.cpu.l2cache.tags.occ_task_id_blocks::1024 32360 # Occupied blocks per task id
822 system.cpu.l2cache.tags.age_task_id_blocks_1024::0 80 # Occupied blocks per task id
823 system.cpu.l2cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id
824 system.cpu.l2cache.tags.age_task_id_blocks_1024::2 242 # Occupied blocks per task id
825 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 13363 # Occupied blocks per task id
826 system.cpu.l2cache.tags.age_task_id_blocks_1024::4 18671 # Occupied blocks per task id
827 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987549 # Percentage of cache occupancy per task id
828 system.cpu.l2cache.tags.tag_accesses 41773644 # Number of tag accesses
829 system.cpu.l2cache.tags.data_accesses 41773644 # Number of data accesses
830 system.cpu.l2cache.ReadReq_hits::cpu.inst 5119 # number of ReadReq hits
831 system.cpu.l2cache.ReadReq_hits::cpu.data 1590451 # number of ReadReq hits
832 system.cpu.l2cache.ReadReq_hits::total 1595570 # number of ReadReq hits
833 system.cpu.l2cache.Writeback_hits::writebacks 2332976 # number of Writeback hits
834 system.cpu.l2cache.Writeback_hits::total 2332976 # number of Writeback hits
835 system.cpu.l2cache.UpgradeReq_hits::cpu.data 1900 # number of UpgradeReq hits
836 system.cpu.l2cache.UpgradeReq_hits::total 1900 # number of UpgradeReq hits
837 system.cpu.l2cache.ReadExReq_hits::cpu.data 564474 # number of ReadExReq hits
838 system.cpu.l2cache.ReadExReq_hits::total 564474 # number of ReadExReq hits
839 system.cpu.l2cache.demand_hits::cpu.inst 5119 # number of demand (read+write) hits
840 system.cpu.l2cache.demand_hits::cpu.data 2154925 # number of demand (read+write) hits
841 system.cpu.l2cache.demand_hits::total 2160044 # number of demand (read+write) hits
842 system.cpu.l2cache.overall_hits::cpu.inst 5119 # number of overall hits
843 system.cpu.l2cache.overall_hits::cpu.data 2154925 # number of overall hits
844 system.cpu.l2cache.overall_hits::total 2160044 # number of overall hits
845 system.cpu.l2cache.ReadReq_misses::cpu.inst 3526 # number of ReadReq misses
846 system.cpu.l2cache.ReadReq_misses::cpu.data 176410 # number of ReadReq misses
847 system.cpu.l2cache.ReadReq_misses::total 179936 # number of ReadReq misses
848 system.cpu.l2cache.UpgradeReq_misses::cpu.data 194792 # number of UpgradeReq misses
849 system.cpu.l2cache.UpgradeReq_misses::total 194792 # number of UpgradeReq misses
850 system.cpu.l2cache.ReadExReq_misses::cpu.data 207010 # number of ReadExReq misses
851 system.cpu.l2cache.ReadExReq_misses::total 207010 # number of ReadExReq misses
852 system.cpu.l2cache.demand_misses::cpu.inst 3526 # number of demand (read+write) misses
853 system.cpu.l2cache.demand_misses::cpu.data 383420 # number of demand (read+write) misses
854 system.cpu.l2cache.demand_misses::total 386946 # number of demand (read+write) misses
855 system.cpu.l2cache.overall_misses::cpu.inst 3526 # number of overall misses
856 system.cpu.l2cache.overall_misses::cpu.data 383420 # number of overall misses
857 system.cpu.l2cache.overall_misses::total 386946 # number of overall misses
858 system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 288437750 # number of ReadReq miss cycles
859 system.cpu.l2cache.ReadReq_miss_latency::cpu.data 14275708250 # number of ReadReq miss cycles
860 system.cpu.l2cache.ReadReq_miss_latency::total 14564146000 # number of ReadReq miss cycles
861 system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 12898587 # number of UpgradeReq miss cycles
862 system.cpu.l2cache.UpgradeReq_miss_latency::total 12898587 # number of UpgradeReq miss cycles
863 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16427155710 # number of ReadExReq miss cycles
864 system.cpu.l2cache.ReadExReq_miss_latency::total 16427155710 # number of ReadExReq miss cycles
865 system.cpu.l2cache.demand_miss_latency::cpu.inst 288437750 # number of demand (read+write) miss cycles
866 system.cpu.l2cache.demand_miss_latency::cpu.data 30702863960 # number of demand (read+write) miss cycles
867 system.cpu.l2cache.demand_miss_latency::total 30991301710 # number of demand (read+write) miss cycles
868 system.cpu.l2cache.overall_miss_latency::cpu.inst 288437750 # number of overall miss cycles
869 system.cpu.l2cache.overall_miss_latency::cpu.data 30702863960 # number of overall miss cycles
870 system.cpu.l2cache.overall_miss_latency::total 30991301710 # number of overall miss cycles
871 system.cpu.l2cache.ReadReq_accesses::cpu.inst 8645 # number of ReadReq accesses(hits+misses)
872 system.cpu.l2cache.ReadReq_accesses::cpu.data 1766861 # number of ReadReq accesses(hits+misses)
873 system.cpu.l2cache.ReadReq_accesses::total 1775506 # number of ReadReq accesses(hits+misses)
874 system.cpu.l2cache.Writeback_accesses::writebacks 2332976 # number of Writeback accesses(hits+misses)
875 system.cpu.l2cache.Writeback_accesses::total 2332976 # number of Writeback accesses(hits+misses)
876 system.cpu.l2cache.UpgradeReq_accesses::cpu.data 196692 # number of UpgradeReq accesses(hits+misses)
877 system.cpu.l2cache.UpgradeReq_accesses::total 196692 # number of UpgradeReq accesses(hits+misses)
878 system.cpu.l2cache.ReadExReq_accesses::cpu.data 771484 # number of ReadExReq accesses(hits+misses)
879 system.cpu.l2cache.ReadExReq_accesses::total 771484 # number of ReadExReq accesses(hits+misses)
880 system.cpu.l2cache.demand_accesses::cpu.inst 8645 # number of demand (read+write) accesses
881 system.cpu.l2cache.demand_accesses::cpu.data 2538345 # number of demand (read+write) accesses
882 system.cpu.l2cache.demand_accesses::total 2546990 # number of demand (read+write) accesses
883 system.cpu.l2cache.overall_accesses::cpu.inst 8645 # number of overall (read+write) accesses
884 system.cpu.l2cache.overall_accesses::cpu.data 2538345 # number of overall (read+write) accesses
885 system.cpu.l2cache.overall_accesses::total 2546990 # number of overall (read+write) accesses
886 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.407866 # miss rate for ReadReq accesses
887 system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.099844 # miss rate for ReadReq accesses
888 system.cpu.l2cache.ReadReq_miss_rate::total 0.101344 # miss rate for ReadReq accesses
889 system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.990340 # miss rate for UpgradeReq accesses
890 system.cpu.l2cache.UpgradeReq_miss_rate::total 0.990340 # miss rate for UpgradeReq accesses
891 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.268327 # miss rate for ReadExReq accesses
892 system.cpu.l2cache.ReadExReq_miss_rate::total 0.268327 # miss rate for ReadExReq accesses
893 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.407866 # miss rate for demand accesses
894 system.cpu.l2cache.demand_miss_rate::cpu.data 0.151051 # miss rate for demand accesses
895 system.cpu.l2cache.demand_miss_rate::total 0.151923 # miss rate for demand accesses
896 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.407866 # miss rate for overall accesses
897 system.cpu.l2cache.overall_miss_rate::cpu.data 0.151051 # miss rate for overall accesses
898 system.cpu.l2cache.overall_miss_rate::total 0.151923 # miss rate for overall accesses
899 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 81803.105502 # average ReadReq miss latency
900 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 80923.463806 # average ReadReq miss latency
901 system.cpu.l2cache.ReadReq_avg_miss_latency::total 80940.701138 # average ReadReq miss latency
902 system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 66.217232 # average UpgradeReq miss latency
903 system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 66.217232 # average UpgradeReq miss latency
904 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79354.406599 # average ReadExReq miss latency
905 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79354.406599 # average ReadExReq miss latency
906 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81803.105502 # average overall miss latency
907 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80076.323509 # average overall miss latency
908 system.cpu.l2cache.demand_avg_miss_latency::total 80092.058608 # average overall miss latency
909 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81803.105502 # average overall miss latency
910 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80076.323509 # average overall miss latency
911 system.cpu.l2cache.overall_avg_miss_latency::total 80092.058608 # average overall miss latency
912 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
913 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
914 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
915 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
916 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
917 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
918 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
919 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
920 system.cpu.l2cache.writebacks::writebacks 294034 # number of writebacks
921 system.cpu.l2cache.writebacks::total 294034 # number of writebacks
922 system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits
923 system.cpu.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits
924 system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
925 system.cpu.l2cache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits
926 system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
927 system.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits
928 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3525 # number of ReadReq MSHR misses
929 system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 176410 # number of ReadReq MSHR misses
930 system.cpu.l2cache.ReadReq_mshr_misses::total 179935 # number of ReadReq MSHR misses
931 system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 194792 # number of UpgradeReq MSHR misses
932 system.cpu.l2cache.UpgradeReq_mshr_misses::total 194792 # number of UpgradeReq MSHR misses
933 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 207010 # number of ReadExReq MSHR misses
934 system.cpu.l2cache.ReadExReq_mshr_misses::total 207010 # number of ReadExReq MSHR misses
935 system.cpu.l2cache.demand_mshr_misses::cpu.inst 3525 # number of demand (read+write) MSHR misses
936 system.cpu.l2cache.demand_mshr_misses::cpu.data 383420 # number of demand (read+write) MSHR misses
937 system.cpu.l2cache.demand_mshr_misses::total 386945 # number of demand (read+write) MSHR misses
938 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3525 # number of overall MSHR misses
939 system.cpu.l2cache.overall_mshr_misses::cpu.data 383420 # number of overall MSHR misses
940 system.cpu.l2cache.overall_mshr_misses::total 386945 # number of overall MSHR misses
941 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 244319250 # number of ReadReq MSHR miss cycles
942 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 12068297250 # number of ReadReq MSHR miss cycles
943 system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12312616500 # number of ReadReq MSHR miss cycles
944 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 3517284221 # number of UpgradeReq MSHR miss cycles
945 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 3517284221 # number of UpgradeReq MSHR miss cycles
946 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13838517790 # number of ReadExReq MSHR miss cycles
947 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13838517790 # number of ReadExReq MSHR miss cycles
948 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 244319250 # number of demand (read+write) MSHR miss cycles
949 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 25906815040 # number of demand (read+write) MSHR miss cycles
950 system.cpu.l2cache.demand_mshr_miss_latency::total 26151134290 # number of demand (read+write) MSHR miss cycles
951 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 244319250 # number of overall MSHR miss cycles
952 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 25906815040 # number of overall MSHR miss cycles
953 system.cpu.l2cache.overall_mshr_miss_latency::total 26151134290 # number of overall MSHR miss cycles
954 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.407750 # mshr miss rate for ReadReq accesses
955 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.099844 # mshr miss rate for ReadReq accesses
956 system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.101343 # mshr miss rate for ReadReq accesses
957 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.990340 # mshr miss rate for UpgradeReq accesses
958 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.990340 # mshr miss rate for UpgradeReq accesses
959 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.268327 # mshr miss rate for ReadExReq accesses
960 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.268327 # mshr miss rate for ReadExReq accesses
961 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.407750 # mshr miss rate for demand accesses
962 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.151051 # mshr miss rate for demand accesses
963 system.cpu.l2cache.demand_mshr_miss_rate::total 0.151922 # mshr miss rate for demand accesses
964 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.407750 # mshr miss rate for overall accesses
965 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.151051 # mshr miss rate for overall accesses
966 system.cpu.l2cache.overall_mshr_miss_rate::total 0.151922 # mshr miss rate for overall accesses
967 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 69310.425532 # average ReadReq mshr miss latency
968 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 68410.505357 # average ReadReq mshr miss latency
969 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 68428.135160 # average ReadReq mshr miss latency
970 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 18056.615369 # average UpgradeReq mshr miss latency
971 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18056.615369 # average UpgradeReq mshr miss latency
972 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66849.513502 # average ReadExReq mshr miss latency
973 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66849.513502 # average ReadExReq mshr miss latency
974 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69310.425532 # average overall mshr miss latency
975 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67567.719576 # average overall mshr miss latency
976 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67583.595317 # average overall mshr miss latency
977 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69310.425532 # average overall mshr miss latency
978 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67567.719576 # average overall mshr miss latency
979 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67583.595317 # average overall mshr miss latency
980 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
981 system.cpu.toL2Bus.trans_dist::ReadReq 1972322 # Transaction distribution
982 system.cpu.toL2Bus.trans_dist::ReadResp 1972321 # Transaction distribution
983 system.cpu.toL2Bus.trans_dist::Writeback 2332976 # Transaction distribution
984 system.cpu.toL2Bus.trans_dist::UpgradeReq 196692 # Transaction distribution
985 system.cpu.toL2Bus.trans_dist::UpgradeResp 196692 # Transaction distribution
986 system.cpu.toL2Bus.trans_dist::ReadExReq 771484 # Transaction distribution
987 system.cpu.toL2Bus.trans_dist::ReadExResp 771484 # Transaction distribution
988 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 214105 # Packet count per connected master and slave (bytes)
989 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7803050 # Packet count per connected master and slave (bytes)
990 system.cpu.toL2Bus.pkt_count::total 8017155 # Packet count per connected master and slave (bytes)
991 system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 553216 # Cumulative packet size per connected master and slave (bytes)
992 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311764544 # Cumulative packet size per connected master and slave (bytes)
993 system.cpu.toL2Bus.pkt_size::total 312317760 # Cumulative packet size per connected master and slave (bytes)
994 system.cpu.toL2Bus.snoops 196816 # Total snoops (count)
995 system.cpu.toL2Bus.snoop_fanout::samples 5273474 # Request fanout histogram
996 system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
997 system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
998 system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
999 system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
1000 system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
1001 system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
1002 system.cpu.toL2Bus.snoop_fanout::3 5273474 100.00% 100.00% # Request fanout histogram
1003 system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
1004 system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1005 system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
1006 system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
1007 system.cpu.toL2Bus.snoop_fanout::total 5273474 # Request fanout histogram
1008 system.cpu.toL2Bus.reqLayer0.occupancy 4998709391 # Layer occupancy (ticks)
1009 system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%)
1010 system.cpu.toL2Bus.respLayer0.occupancy 308726995 # Layer occupancy (ticks)
1011 system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
1012 system.cpu.toL2Bus.respLayer1.occupancy 3988953025 # Layer occupancy (ticks)
1013 system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%)
1014 system.membus.trans_dist::ReadReq 179934 # Transaction distribution
1015 system.membus.trans_dist::ReadResp 179934 # Transaction distribution
1016 system.membus.trans_dist::Writeback 294034 # Transaction distribution
1017 system.membus.trans_dist::UpgradeReq 194832 # Transaction distribution
1018 system.membus.trans_dist::UpgradeResp 194832 # Transaction distribution
1019 system.membus.trans_dist::ReadExReq 206970 # Transaction distribution
1020 system.membus.trans_dist::ReadExResp 206970 # Transaction distribution
1021 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1457506 # Packet count per connected master and slave (bytes)
1022 system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1457506 # Packet count per connected master and slave (bytes)
1023 system.membus.pkt_count::total 1457506 # Packet count per connected master and slave (bytes)
1024 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43580032 # Cumulative packet size per connected master and slave (bytes)
1025 system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43580032 # Cumulative packet size per connected master and slave (bytes)
1026 system.membus.pkt_size::total 43580032 # Cumulative packet size per connected master and slave (bytes)
1027 system.membus.snoops 0 # Total snoops (count)
1028 system.membus.snoop_fanout::samples 875770 # Request fanout histogram
1029 system.membus.snoop_fanout::mean 0 # Request fanout histogram
1030 system.membus.snoop_fanout::stdev 0 # Request fanout histogram
1031 system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1032 system.membus.snoop_fanout::0 875770 100.00% 100.00% # Request fanout histogram
1033 system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
1034 system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1035 system.membus.snoop_fanout::min_value 0 # Request fanout histogram
1036 system.membus.snoop_fanout::max_value 0 # Request fanout histogram
1037 system.membus.snoop_fanout::total 875770 # Request fanout histogram
1038 system.membus.reqLayer0.occupancy 2246779030 # Layer occupancy (ticks)
1039 system.membus.reqLayer0.utilization 0.5 # Layer utilization (%)
1040 system.membus.respLayer1.occupancy 2437213959 # Layer occupancy (ticks)
1041 system.membus.respLayer1.utilization 0.6 # Layer utilization (%)
1043 ---------- End Simulation Statistics ----------
projects / gem5.git / blob