2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.403931 # Number of seconds simulated
4 sim_ticks 403931323500 # Number of ticks simulated
5 final_tick 403931323500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 95186 # Simulator instruction rate (inst/s)
8 host_op_rate 176009 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 46498470 # Simulator tick rate (ticks/s)
10 host_mem_usage 433064 # Number of bytes of host memory used
11 host_seconds 8686.98 # Real time elapsed on the host
12 sim_insts 826877109 # Number of instructions simulated
13 sim_ops 1528988701 # Number of ops (including micro ops) simulated
14 system.voltage_domain.voltage 1 # Voltage in Volts
15 system.clk_domain.clock 1000 # Clock period in ticks
16 system.physmem.bytes_read::cpu.inst 217984 # Number of bytes read from this memory
17 system.physmem.bytes_read::cpu.data 24500544 # Number of bytes read from this memory
18 system.physmem.bytes_read::total 24718528 # Number of bytes read from this memory
19 system.physmem.bytes_inst_read::cpu.inst 217984 # Number of instructions bytes read from this memory
20 system.physmem.bytes_inst_read::total 217984 # Number of instructions bytes read from this memory
21 system.physmem.bytes_written::writebacks 18869632 # Number of bytes written to this memory
22 system.physmem.bytes_written::total 18869632 # Number of bytes written to this memory
23 system.physmem.num_reads::cpu.inst 3406 # Number of read requests responded to by this memory
24 system.physmem.num_reads::cpu.data 382821 # Number of read requests responded to by this memory
25 system.physmem.num_reads::total 386227 # Number of read requests responded to by this memory
26 system.physmem.num_writes::writebacks 294838 # Number of write requests responded to by this memory
27 system.physmem.num_writes::total 294838 # Number of write requests responded to by this memory
28 system.physmem.bw_read::cpu.inst 539656 # Total read bandwidth from this memory (bytes/s)
29 system.physmem.bw_read::cpu.data 60655222 # Total read bandwidth from this memory (bytes/s)
30 system.physmem.bw_read::total 61194878 # Total read bandwidth from this memory (bytes/s)
31 system.physmem.bw_inst_read::cpu.inst 539656 # Instruction read bandwidth from this memory (bytes/s)
32 system.physmem.bw_inst_read::total 539656 # Instruction read bandwidth from this memory (bytes/s)
33 system.physmem.bw_write::writebacks 46714951 # Write bandwidth from this memory (bytes/s)
34 system.physmem.bw_write::total 46714951 # Write bandwidth from this memory (bytes/s)
35 system.physmem.bw_total::writebacks 46714951 # Total bandwidth to/from this memory (bytes/s)
36 system.physmem.bw_total::cpu.inst 539656 # Total bandwidth to/from this memory (bytes/s)
37 system.physmem.bw_total::cpu.data 60655222 # Total bandwidth to/from this memory (bytes/s)
38 system.physmem.bw_total::total 107909829 # Total bandwidth to/from this memory (bytes/s)
39 system.physmem.readReqs 386228 # Number of read requests accepted
40 system.physmem.writeReqs 294838 # Number of write requests accepted
41 system.physmem.readBursts 386228 # Number of DRAM read bursts, including those serviced by the write queue
42 system.physmem.writeBursts 294838 # Number of DRAM write bursts, including those merged in the write queue
43 system.physmem.bytesReadDRAM 24699456 # Total number of bytes read from DRAM
44 system.physmem.bytesReadWrQ 19136 # Total number of bytes read from write queue
45 system.physmem.bytesWritten 18868032 # Total number of bytes written to DRAM
46 system.physmem.bytesReadSys 24718592 # Total read bytes from the system interface side
47 system.physmem.bytesWrittenSys 18869632 # Total written bytes from the system interface side
48 system.physmem.servicedByWrQ 299 # Number of DRAM read bursts serviced by the write queue
49 system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
50 system.physmem.neitherReadNorWriteReqs 196128 # Number of requests that are neither read nor write
51 system.physmem.perBankRdBursts::0 24062 # Per bank write bursts
52 system.physmem.perBankRdBursts::1 26430 # Per bank write bursts
53 system.physmem.perBankRdBursts::2 24903 # Per bank write bursts
54 system.physmem.perBankRdBursts::3 24577 # Per bank write bursts
55 system.physmem.perBankRdBursts::4 23181 # Per bank write bursts
56 system.physmem.perBankRdBursts::5 23704 # Per bank write bursts
57 system.physmem.perBankRdBursts::6 24550 # Per bank write bursts
58 system.physmem.perBankRdBursts::7 24303 # Per bank write bursts
59 system.physmem.perBankRdBursts::8 23663 # Per bank write bursts
60 system.physmem.perBankRdBursts::9 23568 # Per bank write bursts
61 system.physmem.perBankRdBursts::10 24789 # Per bank write bursts
62 system.physmem.perBankRdBursts::11 23975 # Per bank write bursts
63 system.physmem.perBankRdBursts::12 23330 # Per bank write bursts
64 system.physmem.perBankRdBursts::13 22932 # Per bank write bursts
65 system.physmem.perBankRdBursts::14 24089 # Per bank write bursts
66 system.physmem.perBankRdBursts::15 23873 # Per bank write bursts
67 system.physmem.perBankWrBursts::0 18604 # Per bank write bursts
68 system.physmem.perBankWrBursts::1 19922 # Per bank write bursts
69 system.physmem.perBankWrBursts::2 19191 # Per bank write bursts
70 system.physmem.perBankWrBursts::3 18985 # Per bank write bursts
71 system.physmem.perBankWrBursts::4 18090 # Per bank write bursts
72 system.physmem.perBankWrBursts::5 18485 # Per bank write bursts
73 system.physmem.perBankWrBursts::6 19138 # Per bank write bursts
74 system.physmem.perBankWrBursts::7 19082 # Per bank write bursts
75 system.physmem.perBankWrBursts::8 18642 # Per bank write bursts
76 system.physmem.perBankWrBursts::9 17946 # Per bank write bursts
77 system.physmem.perBankWrBursts::10 18887 # Per bank write bursts
78 system.physmem.perBankWrBursts::11 17737 # Per bank write bursts
79 system.physmem.perBankWrBursts::12 17398 # Per bank write bursts
80 system.physmem.perBankWrBursts::13 16988 # Per bank write bursts
81 system.physmem.perBankWrBursts::14 17875 # Per bank write bursts
82 system.physmem.perBankWrBursts::15 17843 # Per bank write bursts
83 system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
84 system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
85 system.physmem.totGap 403931308500 # Total gap between requests
86 system.physmem.readPktSize::0 0 # Read request sizes (log2)
87 system.physmem.readPktSize::1 0 # Read request sizes (log2)
88 system.physmem.readPktSize::2 0 # Read request sizes (log2)
89 system.physmem.readPktSize::3 0 # Read request sizes (log2)
90 system.physmem.readPktSize::4 0 # Read request sizes (log2)
91 system.physmem.readPktSize::5 0 # Read request sizes (log2)
92 system.physmem.readPktSize::6 386228 # Read request sizes (log2)
93 system.physmem.writePktSize::0 0 # Write request sizes (log2)
94 system.physmem.writePktSize::1 0 # Write request sizes (log2)
95 system.physmem.writePktSize::2 0 # Write request sizes (log2)
96 system.physmem.writePktSize::3 0 # Write request sizes (log2)
97 system.physmem.writePktSize::4 0 # Write request sizes (log2)
98 system.physmem.writePktSize::5 0 # Write request sizes (log2)
99 system.physmem.writePktSize::6 294838 # Write request sizes (log2)
100 system.physmem.rdQLenPdf::0 380968 # What read queue length does an incoming req see
101 system.physmem.rdQLenPdf::1 4611 # What read queue length does an incoming req see
102 system.physmem.rdQLenPdf::2 308 # What read queue length does an incoming req see
103 system.physmem.rdQLenPdf::3 33 # What read queue length does an incoming req see
104 system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see
105 system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see
106 system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
107 system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
108 system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
109 system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
110 system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
111 system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
112 system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
113 system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
114 system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
115 system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
116 system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
117 system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
118 system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
119 system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
120 system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
121 system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
122 system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
123 system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
124 system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
125 system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
126 system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
127 system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
128 system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
129 system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
130 system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
131 system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
132 system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
133 system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
134 system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
135 system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
136 system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
137 system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
138 system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
139 system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
140 system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
141 system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
142 system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
143 system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
144 system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
145 system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
146 system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
147 system.physmem.wrQLenPdf::15 6145 # What write queue length does an incoming req see
148 system.physmem.wrQLenPdf::16 6562 # What write queue length does an incoming req see
149 system.physmem.wrQLenPdf::17 16953 # What write queue length does an incoming req see
150 system.physmem.wrQLenPdf::18 17544 # What write queue length does an incoming req see
151 system.physmem.wrQLenPdf::19 17606 # What write queue length does an incoming req see
152 system.physmem.wrQLenPdf::20 17653 # What write queue length does an incoming req see
153 system.physmem.wrQLenPdf::21 17643 # What write queue length does an incoming req see
154 system.physmem.wrQLenPdf::22 17627 # What write queue length does an incoming req see
155 system.physmem.wrQLenPdf::23 17674 # What write queue length does an incoming req see
156 system.physmem.wrQLenPdf::24 17646 # What write queue length does an incoming req see
157 system.physmem.wrQLenPdf::25 17722 # What write queue length does an incoming req see
158 system.physmem.wrQLenPdf::26 17675 # What write queue length does an incoming req see
159 system.physmem.wrQLenPdf::27 17751 # What write queue length does an incoming req see
160 system.physmem.wrQLenPdf::28 17740 # What write queue length does an incoming req see
161 system.physmem.wrQLenPdf::29 17710 # What write queue length does an incoming req see
162 system.physmem.wrQLenPdf::30 17865 # What write queue length does an incoming req see
163 system.physmem.wrQLenPdf::31 17590 # What write queue length does an incoming req see
164 system.physmem.wrQLenPdf::32 17529 # What write queue length does an incoming req see
165 system.physmem.wrQLenPdf::33 45 # What write queue length does an incoming req see
166 system.physmem.wrQLenPdf::34 27 # What write queue length does an incoming req see
167 system.physmem.wrQLenPdf::35 25 # What write queue length does an incoming req see
168 system.physmem.wrQLenPdf::36 21 # What write queue length does an incoming req see
169 system.physmem.wrQLenPdf::37 15 # What write queue length does an incoming req see
170 system.physmem.wrQLenPdf::38 14 # What write queue length does an incoming req see
171 system.physmem.wrQLenPdf::39 6 # What write queue length does an incoming req see
172 system.physmem.wrQLenPdf::40 6 # What write queue length does an incoming req see
173 system.physmem.wrQLenPdf::41 7 # What write queue length does an incoming req see
174 system.physmem.wrQLenPdf::42 9 # What write queue length does an incoming req see
175 system.physmem.wrQLenPdf::43 6 # What write queue length does an incoming req see
176 system.physmem.wrQLenPdf::44 5 # What write queue length does an incoming req see
177 system.physmem.wrQLenPdf::45 2 # What write queue length does an incoming req see
178 system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
179 system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
180 system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
181 system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
182 system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
183 system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
184 system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
185 system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
186 system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
187 system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
188 system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
189 system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
190 system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
191 system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
192 system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
193 system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
194 system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
195 system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
196 system.physmem.bytesPerActivate::samples 146866 # Bytes accessed per row activation
197 system.physmem.bytesPerActivate::mean 296.637860 # Bytes accessed per row activation
198 system.physmem.bytesPerActivate::gmean 175.325639 # Bytes accessed per row activation
199 system.physmem.bytesPerActivate::stdev 323.046473 # Bytes accessed per row activation
200 system.physmem.bytesPerActivate::0-127 54140 36.86% 36.86% # Bytes accessed per row activation
201 system.physmem.bytesPerActivate::128-255 39981 27.22% 64.09% # Bytes accessed per row activation
202 system.physmem.bytesPerActivate::256-383 13765 9.37% 73.46% # Bytes accessed per row activation
203 system.physmem.bytesPerActivate::384-511 7667 5.22% 78.68% # Bytes accessed per row activation
204 system.physmem.bytesPerActivate::512-639 5371 3.66% 82.34% # Bytes accessed per row activation
205 system.physmem.bytesPerActivate::640-767 3914 2.67% 85.00% # Bytes accessed per row activation
206 system.physmem.bytesPerActivate::768-895 3025 2.06% 87.06% # Bytes accessed per row activation
207 system.physmem.bytesPerActivate::896-1023 2731 1.86% 88.92% # Bytes accessed per row activation
208 system.physmem.bytesPerActivate::1024-1151 16272 11.08% 100.00% # Bytes accessed per row activation
209 system.physmem.bytesPerActivate::total 146866 # Bytes accessed per row activation
210 system.physmem.rdPerTurnAround::samples 17494 # Reads before turning the bus around for writes
211 system.physmem.rdPerTurnAround::mean 22.060078 # Reads before turning the bus around for writes
212 system.physmem.rdPerTurnAround::stdev 218.173610 # Reads before turning the bus around for writes
213 system.physmem.rdPerTurnAround::0-1023 17485 99.95% 99.95% # Reads before turning the bus around for writes
214 system.physmem.rdPerTurnAround::1024-2047 4 0.02% 99.97% # Reads before turning the bus around for writes
215 system.physmem.rdPerTurnAround::3072-4095 3 0.02% 99.99% # Reads before turning the bus around for writes
216 system.physmem.rdPerTurnAround::8192-9215 1 0.01% 99.99% # Reads before turning the bus around for writes
217 system.physmem.rdPerTurnAround::26624-27647 1 0.01% 100.00% # Reads before turning the bus around for writes
218 system.physmem.rdPerTurnAround::total 17494 # Reads before turning the bus around for writes
219 system.physmem.wrPerTurnAround::samples 17494 # Writes before turning the bus around for reads
220 system.physmem.wrPerTurnAround::mean 16.852235 # Writes before turning the bus around for reads
221 system.physmem.wrPerTurnAround::gmean 16.776145 # Writes before turning the bus around for reads
222 system.physmem.wrPerTurnAround::stdev 2.682764 # Writes before turning the bus around for reads
223 system.physmem.wrPerTurnAround::16-19 17296 98.87% 98.87% # Writes before turning the bus around for reads
224 system.physmem.wrPerTurnAround::20-23 143 0.82% 99.69% # Writes before turning the bus around for reads
225 system.physmem.wrPerTurnAround::24-27 28 0.16% 99.85% # Writes before turning the bus around for reads
226 system.physmem.wrPerTurnAround::28-31 5 0.03% 99.87% # Writes before turning the bus around for reads
227 system.physmem.wrPerTurnAround::32-35 3 0.02% 99.89% # Writes before turning the bus around for reads
228 system.physmem.wrPerTurnAround::36-39 3 0.02% 99.91% # Writes before turning the bus around for reads
229 system.physmem.wrPerTurnAround::40-43 1 0.01% 99.91% # Writes before turning the bus around for reads
230 system.physmem.wrPerTurnAround::44-47 1 0.01% 99.92% # Writes before turning the bus around for reads
231 system.physmem.wrPerTurnAround::52-55 1 0.01% 99.93% # Writes before turning the bus around for reads
232 system.physmem.wrPerTurnAround::56-59 1 0.01% 99.93% # Writes before turning the bus around for reads
233 system.physmem.wrPerTurnAround::60-63 2 0.01% 99.94% # Writes before turning the bus around for reads
234 system.physmem.wrPerTurnAround::64-67 3 0.02% 99.96% # Writes before turning the bus around for reads
235 system.physmem.wrPerTurnAround::84-87 1 0.01% 99.97% # Writes before turning the bus around for reads
236 system.physmem.wrPerTurnAround::88-91 1 0.01% 99.97% # Writes before turning the bus around for reads
237 system.physmem.wrPerTurnAround::92-95 1 0.01% 99.98% # Writes before turning the bus around for reads
238 system.physmem.wrPerTurnAround::108-111 1 0.01% 99.98% # Writes before turning the bus around for reads
239 system.physmem.wrPerTurnAround::116-119 1 0.01% 99.99% # Writes before turning the bus around for reads
240 system.physmem.wrPerTurnAround::120-123 1 0.01% 99.99% # Writes before turning the bus around for reads
241 system.physmem.wrPerTurnAround::216-219 1 0.01% 100.00% # Writes before turning the bus around for reads
242 system.physmem.wrPerTurnAround::total 17494 # Writes before turning the bus around for reads
243 system.physmem.totQLat 4291077750 # Total ticks spent queuing
244 system.physmem.totMemAccLat 11527246500 # Total ticks spent from burst creation until serviced by the DRAM
245 system.physmem.totBusLat 1929645000 # Total ticks spent in databus transfers
246 system.physmem.avgQLat 11118.83 # Average queueing delay per DRAM burst
247 system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
248 system.physmem.avgMemAccLat 29868.83 # Average memory access latency per DRAM burst
249 system.physmem.avgRdBW 61.15 # Average DRAM read bandwidth in MiByte/s
250 system.physmem.avgWrBW 46.71 # Average achieved write bandwidth in MiByte/s
251 system.physmem.avgRdBWSys 61.20 # Average system read bandwidth in MiByte/s
252 system.physmem.avgWrBWSys 46.71 # Average system write bandwidth in MiByte/s
253 system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
254 system.physmem.busUtil 0.84 # Data bus utilization in percentage
255 system.physmem.busUtilRead 0.48 # Data bus utilization in percentage for reads
256 system.physmem.busUtilWrite 0.36 # Data bus utilization in percentage for writes
257 system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing
258 system.physmem.avgWrQLen 21.35 # Average write queue length when enqueuing
259 system.physmem.readRowHits 317989 # Number of row buffer hits during reads
260 system.physmem.writeRowHits 215873 # Number of row buffer hits during writes
261 system.physmem.readRowHitRate 82.40 # Row buffer hit rate for reads
262 system.physmem.writeRowHitRate 73.22 # Row buffer hit rate for writes
263 system.physmem.avgGap 593086.88 # Average gap between requests
264 system.physmem.pageHitRate 78.42 # Row buffer hit rate, read and write combined
265 system.physmem_0.actEnergy 567438480 # Energy for activate commands per rank (pJ)
266 system.physmem_0.preEnergy 309614250 # Energy for precharge commands per rank (pJ)
267 system.physmem_0.readEnergy 1526405400 # Energy for read commands per rank (pJ)
268 system.physmem_0.writeEnergy 981499680 # Energy for write commands per rank (pJ)
269 system.physmem_0.refreshEnergy 26382567120 # Energy for refresh commands per rank (pJ)
270 system.physmem_0.actBackEnergy 62258546970 # Energy for active background per rank (pJ)
271 system.physmem_0.preBackEnergy 187743770250 # Energy for precharge background per rank (pJ)
272 system.physmem_0.totalEnergy 279769842150 # Total energy per rank (pJ)
273 system.physmem_0.averagePower 692.623817 # Core power per rank (mW)
274 system.physmem_0.memoryStateTime::IDLE 311776883750 # Time in different power states
275 system.physmem_0.memoryStateTime::REF 13488020000 # Time in different power states
276 system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
277 system.physmem_0.memoryStateTime::ACT 78662661250 # Time in different power states
278 system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
279 system.physmem_1.actEnergy 542467800 # Energy for activate commands per rank (pJ)
280 system.physmem_1.preEnergy 295989375 # Energy for precharge commands per rank (pJ)
281 system.physmem_1.readEnergy 1483341600 # Energy for read commands per rank (pJ)
282 system.physmem_1.writeEnergy 928473840 # Energy for write commands per rank (pJ)
283 system.physmem_1.refreshEnergy 26382567120 # Energy for refresh commands per rank (pJ)
284 system.physmem_1.actBackEnergy 60448758210 # Energy for active background per rank (pJ)
285 system.physmem_1.preBackEnergy 189331310250 # Energy for precharge background per rank (pJ)
286 system.physmem_1.totalEnergy 279412908195 # Total energy per rank (pJ)
287 system.physmem_1.averagePower 691.740141 # Core power per rank (mW)
288 system.physmem_1.memoryStateTime::IDLE 314432491250 # Time in different power states
289 system.physmem_1.memoryStateTime::REF 13488020000 # Time in different power states
290 system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
291 system.physmem_1.memoryStateTime::ACT 76007072500 # Time in different power states
292 system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
293 system.cpu.branchPred.lookups 219314839 # Number of BP lookups
294 system.cpu.branchPred.condPredicted 219314839 # Number of conditional branches predicted
295 system.cpu.branchPred.condIncorrect 8530231 # Number of conditional branches incorrect
296 system.cpu.branchPred.BTBLookups 123981217 # Number of BTB lookups
297 system.cpu.branchPred.BTBHits 121825604 # Number of BTB hits
298 system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
299 system.cpu.branchPred.BTBHitPct 98.261339 # BTB Hit Percentage
300 system.cpu.branchPred.usedRAS 27068206 # Number of times the RAS was used to get a target.
301 system.cpu.branchPred.RASInCorrect 1407908 # Number of incorrect RAS predictions.
302 system.cpu_clk_domain.clock 500 # Clock period in ticks
303 system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
304 system.cpu.workload.num_syscalls 551 # Number of system calls
305 system.cpu.numCycles 807862648 # number of cpu cycles simulated
306 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
307 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
308 system.cpu.fetch.icacheStallCycles 175941692 # Number of cycles fetch is stalled on an Icache miss
309 system.cpu.fetch.Insts 1208657835 # Number of instructions fetch has processed
310 system.cpu.fetch.Branches 219314839 # Number of branches that fetch encountered
311 system.cpu.fetch.predictedBranches 148893810 # Number of branches that fetch has predicted taken
312 system.cpu.fetch.Cycles 622000001 # Number of cycles fetch has run and was not squashing or blocked
313 system.cpu.fetch.SquashCycles 17769177 # Number of cycles fetch has spent squashing
314 system.cpu.fetch.TlbCycles 227 # Number of cycles fetch has spent waiting for tlb
315 system.cpu.fetch.MiscStallCycles 92380 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
316 system.cpu.fetch.PendingTrapStallCycles 735169 # Number of stall cycles due to pending traps
317 system.cpu.fetch.PendingQuiesceStallCycles 1433 # Number of stall cycles due to pending quiesce instructions
318 system.cpu.fetch.IcacheWaitRetryStallCycles 29 # Number of stall cycles due to full MSHR
319 system.cpu.fetch.CacheLines 170789403 # Number of cache lines fetched
320 system.cpu.fetch.IcacheSquashes 2323822 # Number of outstanding Icache misses that were squashed
321 system.cpu.fetch.ItlbSquashes 4 # Number of outstanding ITLB misses that were squashed
322 system.cpu.fetch.rateDist::samples 807655519 # Number of instructions fetched each cycle (Total)
323 system.cpu.fetch.rateDist::mean 2.784658 # Number of instructions fetched each cycle (Total)
324 system.cpu.fetch.rateDist::stdev 3.367182 # Number of instructions fetched each cycle (Total)
325 system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
326 system.cpu.fetch.rateDist::0 417598750 51.71% 51.71% # Number of instructions fetched each cycle (Total)
327 system.cpu.fetch.rateDist::1 32531773 4.03% 55.73% # Number of instructions fetched each cycle (Total)
328 system.cpu.fetch.rateDist::2 31857083 3.94% 59.68% # Number of instructions fetched each cycle (Total)
329 system.cpu.fetch.rateDist::3 32716073 4.05% 63.73% # Number of instructions fetched each cycle (Total)
330 system.cpu.fetch.rateDist::4 26594170 3.29% 67.02% # Number of instructions fetched each cycle (Total)
331 system.cpu.fetch.rateDist::5 26933309 3.33% 70.36% # Number of instructions fetched each cycle (Total)
332 system.cpu.fetch.rateDist::6 35181908 4.36% 74.71% # Number of instructions fetched each cycle (Total)
333 system.cpu.fetch.rateDist::7 31423846 3.89% 78.60% # Number of instructions fetched each cycle (Total)
334 system.cpu.fetch.rateDist::8 172818607 21.40% 100.00% # Number of instructions fetched each cycle (Total)
335 system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
336 system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
337 system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
338 system.cpu.fetch.rateDist::total 807655519 # Number of instructions fetched each cycle (Total)
339 system.cpu.fetch.branchRate 0.271475 # Number of branch fetches per cycle
340 system.cpu.fetch.rate 1.496118 # Number of inst fetches per cycle
341 system.cpu.decode.IdleCycles 120412218 # Number of cycles decode is idle
342 system.cpu.decode.BlockedCycles 371076736 # Number of cycles decode is blocked
343 system.cpu.decode.RunCycles 225209960 # Number of cycles decode is running
344 system.cpu.decode.UnblockCycles 82072017 # Number of cycles decode is unblocking
345 system.cpu.decode.SquashCycles 8884588 # Number of cycles decode is squashing
346 system.cpu.decode.DecodedInsts 2132095724 # Number of instructions handled by decode
347 system.cpu.rename.SquashCycles 8884588 # Number of cycles rename is squashing
348 system.cpu.rename.IdleCycles 152556291 # Number of cycles rename is idle
349 system.cpu.rename.BlockCycles 150817488 # Number of cycles rename is blocking
350 system.cpu.rename.serializeStallCycles 41958 # count of cycles rename stalled for serializing inst
351 system.cpu.rename.RunCycles 271423783 # Number of cycles rename is running
352 system.cpu.rename.UnblockCycles 223931411 # Number of cycles rename is unblocking
353 system.cpu.rename.RenamedInsts 2088526658 # Number of instructions processed by rename
354 system.cpu.rename.ROBFullEvents 137354 # Number of times rename has blocked due to ROB full
355 system.cpu.rename.IQFullEvents 138380994 # Number of times rename has blocked due to IQ full
356 system.cpu.rename.LQFullEvents 24891978 # Number of times rename has blocked due to LQ full
357 system.cpu.rename.SQFullEvents 50561951 # Number of times rename has blocked due to SQ full
358 system.cpu.rename.RenamedOperands 2190720490 # Number of destination operands rename has renamed
359 system.cpu.rename.RenameLookups 5278322969 # Number of register rename lookups that rename has made
360 system.cpu.rename.int_rename_lookups 3357144423 # Number of integer rename lookups
361 system.cpu.rename.fp_rename_lookups 60320 # Number of floating rename lookups
362 system.cpu.rename.CommittedMaps 1614040854 # Number of HB maps that are committed
363 system.cpu.rename.UndoneMaps 576679636 # Number of HB maps that are undone due to squashing
364 system.cpu.rename.serializingInsts 3187 # count of serializing insts renamed
365 system.cpu.rename.tempSerializingInsts 2956 # count of temporary serializing insts renamed
366 system.cpu.rename.skidInsts 423114583 # count of insts added to the skid buffer
367 system.cpu.memDep0.insertedLoads 507122992 # Number of loads inserted to the mem dependence unit.
368 system.cpu.memDep0.insertedStores 200812983 # Number of stores inserted to the mem dependence unit.
369 system.cpu.memDep0.conflictingLoads 229080264 # Number of conflicting loads.
370 system.cpu.memDep0.conflictingStores 68423458 # Number of conflicting stores.
371 system.cpu.iq.iqInstsAdded 2023133283 # Number of instructions added to the IQ (excludes non-spec)
372 system.cpu.iq.iqNonSpecInstsAdded 22942 # Number of non-speculative instructions added to the IQ
373 system.cpu.iq.iqInstsIssued 1788928106 # Number of instructions issued
374 system.cpu.iq.iqSquashedInstsIssued 421261 # Number of squashed instructions issued
375 system.cpu.iq.iqSquashedInstsExamined 494167524 # Number of squashed instructions iterated over during squash; mainly for profiling
376 system.cpu.iq.iqSquashedOperandsExamined 833180412 # Number of squashed operands that are examined and possibly removed from graph
377 system.cpu.iq.iqSquashedNonSpecRemoved 22390 # Number of squashed non-spec instructions that were removed
378 system.cpu.iq.issued_per_cycle::samples 807655519 # Number of insts issued each cycle
379 system.cpu.iq.issued_per_cycle::mean 2.214964 # Number of insts issued each cycle
380 system.cpu.iq.issued_per_cycle::stdev 2.070282 # Number of insts issued each cycle
381 system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
382 system.cpu.iq.issued_per_cycle::0 238829466 29.57% 29.57% # Number of insts issued each cycle
383 system.cpu.iq.issued_per_cycle::1 123732265 15.32% 44.89% # Number of insts issued each cycle
384 system.cpu.iq.issued_per_cycle::2 119115162 14.75% 59.64% # Number of insts issued each cycle
385 system.cpu.iq.issued_per_cycle::3 107661207 13.33% 72.97% # Number of insts issued each cycle
386 system.cpu.iq.issued_per_cycle::4 89581047 11.09% 84.06% # Number of insts issued each cycle
387 system.cpu.iq.issued_per_cycle::5 60232277 7.46% 91.52% # Number of insts issued each cycle
388 system.cpu.iq.issued_per_cycle::6 42307619 5.24% 96.76% # Number of insts issued each cycle
389 system.cpu.iq.issued_per_cycle::7 18921199 2.34% 99.10% # Number of insts issued each cycle
390 system.cpu.iq.issued_per_cycle::8 7275277 0.90% 100.00% # Number of insts issued each cycle
391 system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
392 system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
393 system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
394 system.cpu.iq.issued_per_cycle::total 807655519 # Number of insts issued each cycle
395 system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
396 system.cpu.iq.fu_full::IntAlu 11512552 42.68% 42.68% # attempts to use FU when none available
397 system.cpu.iq.fu_full::IntMult 0 0.00% 42.68% # attempts to use FU when none available
398 system.cpu.iq.fu_full::IntDiv 0 0.00% 42.68% # attempts to use FU when none available
399 system.cpu.iq.fu_full::FloatAdd 0 0.00% 42.68% # attempts to use FU when none available
400 system.cpu.iq.fu_full::FloatCmp 0 0.00% 42.68% # attempts to use FU when none available
401 system.cpu.iq.fu_full::FloatCvt 0 0.00% 42.68% # attempts to use FU when none available
402 system.cpu.iq.fu_full::FloatMult 0 0.00% 42.68% # attempts to use FU when none available
403 system.cpu.iq.fu_full::FloatDiv 0 0.00% 42.68% # attempts to use FU when none available
404 system.cpu.iq.fu_full::FloatSqrt 0 0.00% 42.68% # attempts to use FU when none available
405 system.cpu.iq.fu_full::SimdAdd 0 0.00% 42.68% # attempts to use FU when none available
406 system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 42.68% # attempts to use FU when none available
407 system.cpu.iq.fu_full::SimdAlu 0 0.00% 42.68% # attempts to use FU when none available
408 system.cpu.iq.fu_full::SimdCmp 0 0.00% 42.68% # attempts to use FU when none available
409 system.cpu.iq.fu_full::SimdCvt 0 0.00% 42.68% # attempts to use FU when none available
410 system.cpu.iq.fu_full::SimdMisc 0 0.00% 42.68% # attempts to use FU when none available
411 system.cpu.iq.fu_full::SimdMult 0 0.00% 42.68% # attempts to use FU when none available
412 system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 42.68% # attempts to use FU when none available
413 system.cpu.iq.fu_full::SimdShift 0 0.00% 42.68% # attempts to use FU when none available
414 system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 42.68% # attempts to use FU when none available
415 system.cpu.iq.fu_full::SimdSqrt 0 0.00% 42.68% # attempts to use FU when none available
416 system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 42.68% # attempts to use FU when none available
417 system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 42.68% # attempts to use FU when none available
418 system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 42.68% # attempts to use FU when none available
419 system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 42.68% # attempts to use FU when none available
420 system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 42.68% # attempts to use FU when none available
421 system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 42.68% # attempts to use FU when none available
422 system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 42.68% # attempts to use FU when none available
423 system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 42.68% # attempts to use FU when none available
424 system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 42.68% # attempts to use FU when none available
425 system.cpu.iq.fu_full::MemRead 12355843 45.81% 88.49% # attempts to use FU when none available
426 system.cpu.iq.fu_full::MemWrite 3105832 11.51% 100.00% # attempts to use FU when none available
427 system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
428 system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
429 system.cpu.iq.FU_type_0::No_OpClass 2718297 0.15% 0.15% # Type of FU issued
430 system.cpu.iq.FU_type_0::IntAlu 1183078959 66.13% 66.29% # Type of FU issued
431 system.cpu.iq.FU_type_0::IntMult 370517 0.02% 66.31% # Type of FU issued
432 system.cpu.iq.FU_type_0::IntDiv 3881151 0.22% 66.52% # Type of FU issued
433 system.cpu.iq.FU_type_0::FloatAdd 134 0.00% 66.52% # Type of FU issued
434 system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.52% # Type of FU issued
435 system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.52% # Type of FU issued
436 system.cpu.iq.FU_type_0::FloatMult 67 0.00% 66.52% # Type of FU issued
437 system.cpu.iq.FU_type_0::FloatDiv 365 0.00% 66.52% # Type of FU issued
438 system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.52% # Type of FU issued
439 system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.52% # Type of FU issued
440 system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.52% # Type of FU issued
441 system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.52% # Type of FU issued
442 system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.52% # Type of FU issued
443 system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.52% # Type of FU issued
444 system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.52% # Type of FU issued
445 system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.52% # Type of FU issued
446 system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.52% # Type of FU issued
447 system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.52% # Type of FU issued
448 system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.52% # Type of FU issued
449 system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.52% # Type of FU issued
450 system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.52% # Type of FU issued
451 system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.52% # Type of FU issued
452 system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.52% # Type of FU issued
453 system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.52% # Type of FU issued
454 system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.52% # Type of FU issued
455 system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.52% # Type of FU issued
456 system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.52% # Type of FU issued
457 system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.52% # Type of FU issued
458 system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.52% # Type of FU issued
459 system.cpu.iq.FU_type_0::MemRead 428492741 23.95% 90.48% # Type of FU issued
460 system.cpu.iq.FU_type_0::MemWrite 170385875 9.52% 100.00% # Type of FU issued
461 system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
462 system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
463 system.cpu.iq.FU_type_0::total 1788928106 # Type of FU issued
464 system.cpu.iq.rate 2.214396 # Inst issue rate
465 system.cpu.iq.fu_busy_cnt 26974227 # FU busy when requested
466 system.cpu.iq.fu_busy_rate 0.015078 # FU busy rate (busy events/executed inst)
467 system.cpu.iq.int_inst_queue_reads 4412876800 # Number of integer instruction queue reads
468 system.cpu.iq.int_inst_queue_writes 2517572556 # Number of integer instruction queue writes
469 system.cpu.iq.int_inst_queue_wakeup_accesses 1762303286 # Number of integer instruction queue wakeup accesses
470 system.cpu.iq.fp_inst_queue_reads 30419 # Number of floating instruction queue reads
471 system.cpu.iq.fp_inst_queue_writes 69720 # Number of floating instruction queue writes
472 system.cpu.iq.fp_inst_queue_wakeup_accesses 5693 # Number of floating instruction queue wakeup accesses
473 system.cpu.iq.int_alu_accesses 1813170766 # Number of integer alu accesses
474 system.cpu.iq.fp_alu_accesses 13270 # Number of floating point alu accesses
475 system.cpu.iew.lsq.thread0.forwLoads 186079397 # Number of loads that had data forwarded from stores
476 system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
477 system.cpu.iew.lsq.thread0.squashedLoads 123023075 # Number of loads squashed
478 system.cpu.iew.lsq.thread0.ignoredResponses 212257 # Number of memory responses ignored because the instruction is squashed
479 system.cpu.iew.lsq.thread0.memOrderViolation 371984 # Number of memory ordering violations
480 system.cpu.iew.lsq.thread0.squashedStores 51652797 # Number of stores squashed
481 system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
482 system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
483 system.cpu.iew.lsq.thread0.rescheduledLoads 22860 # Number of loads that were rescheduled
484 system.cpu.iew.lsq.thread0.cacheBlocked 1101 # Number of times an access to memory failed due to the cache being blocked
485 system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
486 system.cpu.iew.iewSquashCycles 8884588 # Number of cycles IEW is squashing
487 system.cpu.iew.iewBlockCycles 97906785 # Number of cycles IEW is blocking
488 system.cpu.iew.iewUnblockCycles 6199562 # Number of cycles IEW is unblocking
489 system.cpu.iew.iewDispatchedInsts 2023156225 # Number of instructions dispatched to IQ
490 system.cpu.iew.iewDispSquashedInsts 370486 # Number of squashed instructions skipped by dispatch
491 system.cpu.iew.iewDispLoadInsts 507125232 # Number of dispatched load instructions
492 system.cpu.iew.iewDispStoreInsts 200812983 # Number of dispatched store instructions
493 system.cpu.iew.iewDispNonSpecInsts 7241 # Number of dispatched non-speculative instructions
494 system.cpu.iew.iewIQFullEvents 1822287 # Number of times the IQ has become full, causing a stall
495 system.cpu.iew.iewLSQFullEvents 3474512 # Number of times the LSQ has become full, causing a stall
496 system.cpu.iew.memOrderViolationEvents 371984 # Number of memory order violations
497 system.cpu.iew.predictedTakenIncorrect 4845065 # Number of branches that were predicted taken incorrectly
498 system.cpu.iew.predictedNotTakenIncorrect 4137242 # Number of branches that were predicted not taken incorrectly
499 system.cpu.iew.branchMispredicts 8982307 # Number of branch mispredicts detected at execute
500 system.cpu.iew.iewExecutedInsts 1769932780 # Number of executed instructions
501 system.cpu.iew.iewExecLoadInsts 423113153 # Number of load instructions executed
502 system.cpu.iew.iewExecSquashedInsts 18995326 # Number of squashed instructions skipped in execute
503 system.cpu.iew.exec_swp 0 # number of swp insts executed
504 system.cpu.iew.exec_nop 0 # number of nop insts executed
505 system.cpu.iew.exec_refs 590301691 # number of memory reference insts executed
506 system.cpu.iew.exec_branches 168980249 # Number of branches executed
507 system.cpu.iew.exec_stores 167188538 # Number of stores executed
508 system.cpu.iew.exec_rate 2.190883 # Inst execution rate
509 system.cpu.iew.wb_sent 1766804374 # cumulative count of insts sent to commit
510 system.cpu.iew.wb_count 1762308979 # cumulative count of insts written-back
511 system.cpu.iew.wb_producers 1339663552 # num instructions producing a value
512 system.cpu.iew.wb_consumers 2049989844 # num instructions consuming a value
513 system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
514 system.cpu.iew.wb_rate 2.181446 # insts written-back per cycle
515 system.cpu.iew.wb_fanout 0.653498 # average fanout of values written-back
516 system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
517 system.cpu.commit.commitSquashedInsts 494228972 # The number of squashed insts skipped by commit
518 system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards
519 system.cpu.commit.branchMispredicts 8612841 # The number of times a branch was mispredicted
520 system.cpu.commit.committed_per_cycle::samples 740434686 # Number of insts commited each cycle
521 system.cpu.commit.committed_per_cycle::mean 2.064988 # Number of insts commited each cycle
522 system.cpu.commit.committed_per_cycle::stdev 2.575030 # Number of insts commited each cycle
523 system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
524 system.cpu.commit.committed_per_cycle::0 276267324 37.31% 37.31% # Number of insts commited each cycle
525 system.cpu.commit.committed_per_cycle::1 172135150 23.25% 60.56% # Number of insts commited each cycle
526 system.cpu.commit.committed_per_cycle::2 56000087 7.56% 68.12% # Number of insts commited each cycle
527 system.cpu.commit.committed_per_cycle::3 86333753 11.66% 79.78% # Number of insts commited each cycle
528 system.cpu.commit.committed_per_cycle::4 25859703 3.49% 83.27% # Number of insts commited each cycle
529 system.cpu.commit.committed_per_cycle::5 26527369 3.58% 86.86% # Number of insts commited each cycle
530 system.cpu.commit.committed_per_cycle::6 9854605 1.33% 88.19% # Number of insts commited each cycle
531 system.cpu.commit.committed_per_cycle::7 9004729 1.22% 89.40% # Number of insts commited each cycle
532 system.cpu.commit.committed_per_cycle::8 78451966 10.60% 100.00% # Number of insts commited each cycle
533 system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
534 system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
535 system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
536 system.cpu.commit.committed_per_cycle::total 740434686 # Number of insts commited each cycle
537 system.cpu.commit.committedInsts 826877109 # Number of instructions committed
538 system.cpu.commit.committedOps 1528988701 # Number of ops (including micro ops) committed
539 system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
540 system.cpu.commit.refs 533262343 # Number of memory references committed
541 system.cpu.commit.loads 384102157 # Number of loads committed
542 system.cpu.commit.membars 0 # Number of memory barriers committed
543 system.cpu.commit.branches 149758583 # Number of branches committed
544 system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
545 system.cpu.commit.int_insts 1526605509 # Number of committed integer instructions.
546 system.cpu.commit.function_calls 17673145 # Number of function calls committed.
547 system.cpu.commit.op_class_0::No_OpClass 1819099 0.12% 0.12% # Class of committed instruction
548 system.cpu.commit.op_class_0::IntAlu 989721889 64.73% 64.85% # Class of committed instruction
549 system.cpu.commit.op_class_0::IntMult 306834 0.02% 64.87% # Class of committed instruction
550 system.cpu.commit.op_class_0::IntDiv 3878536 0.25% 65.12% # Class of committed instruction
551 system.cpu.commit.op_class_0::FloatAdd 0 0.00% 65.12% # Class of committed instruction
552 system.cpu.commit.op_class_0::FloatCmp 0 0.00% 65.12% # Class of committed instruction
553 system.cpu.commit.op_class_0::FloatCvt 0 0.00% 65.12% # Class of committed instruction
554 system.cpu.commit.op_class_0::FloatMult 0 0.00% 65.12% # Class of committed instruction
555 system.cpu.commit.op_class_0::FloatDiv 0 0.00% 65.12% # Class of committed instruction
556 system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 65.12% # Class of committed instruction
557 system.cpu.commit.op_class_0::SimdAdd 0 0.00% 65.12% # Class of committed instruction
558 system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 65.12% # Class of committed instruction
559 system.cpu.commit.op_class_0::SimdAlu 0 0.00% 65.12% # Class of committed instruction
560 system.cpu.commit.op_class_0::SimdCmp 0 0.00% 65.12% # Class of committed instruction
561 system.cpu.commit.op_class_0::SimdCvt 0 0.00% 65.12% # Class of committed instruction
562 system.cpu.commit.op_class_0::SimdMisc 0 0.00% 65.12% # Class of committed instruction
563 system.cpu.commit.op_class_0::SimdMult 0 0.00% 65.12% # Class of committed instruction
564 system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 65.12% # Class of committed instruction
565 system.cpu.commit.op_class_0::SimdShift 0 0.00% 65.12% # Class of committed instruction
566 system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 65.12% # Class of committed instruction
567 system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 65.12% # Class of committed instruction
568 system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 65.12% # Class of committed instruction
569 system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 65.12% # Class of committed instruction
570 system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 65.12% # Class of committed instruction
571 system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 65.12% # Class of committed instruction
572 system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 65.12% # Class of committed instruction
573 system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 65.12% # Class of committed instruction
574 system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 65.12% # Class of committed instruction
575 system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.12% # Class of committed instruction
576 system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.12% # Class of committed instruction
577 system.cpu.commit.op_class_0::MemRead 384102157 25.12% 90.24% # Class of committed instruction
578 system.cpu.commit.op_class_0::MemWrite 149160186 9.76% 100.00% # Class of committed instruction
579 system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
580 system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
581 system.cpu.commit.op_class_0::total 1528988701 # Class of committed instruction
582 system.cpu.commit.bw_lim_events 78451966 # number cycles where commit BW limit reached
583 system.cpu.rob.rob_reads 2685200393 # The number of ROB reads
584 system.cpu.rob.rob_writes 4113829657 # The number of ROB writes
585 system.cpu.timesIdled 2326 # Number of times that the entire CPU went into an idle state and unscheduled itself
586 system.cpu.idleCycles 207129 # Total number of cycles that the CPU has spent unscheduled due to idling
587 system.cpu.committedInsts 826877109 # Number of Instructions Simulated
588 system.cpu.committedOps 1528988701 # Number of Ops (including micro ops) Simulated
589 system.cpu.cpi 0.977004 # CPI: Cycles Per Instruction
590 system.cpu.cpi_total 0.977004 # CPI: Total CPI of All Threads
591 system.cpu.ipc 1.023537 # IPC: Instructions Per Cycle
592 system.cpu.ipc_total 1.023537 # IPC: Total IPC of All Threads
593 system.cpu.int_regfile_reads 2722489562 # number of integer regfile reads
594 system.cpu.int_regfile_writes 1435790744 # number of integer regfile writes
595 system.cpu.fp_regfile_reads 5969 # number of floating regfile reads
596 system.cpu.fp_regfile_writes 521 # number of floating regfile writes
597 system.cpu.cc_regfile_reads 596647275 # number of cc regfile reads
598 system.cpu.cc_regfile_writes 405463698 # number of cc regfile writes
599 system.cpu.misc_regfile_reads 971582048 # number of misc regfile reads
600 system.cpu.misc_regfile_writes 1 # number of misc regfile writes
601 system.cpu.dcache.tags.replacements 2530897 # number of replacements
602 system.cpu.dcache.tags.tagsinuse 4087.817920 # Cycle average of tags in use
603 system.cpu.dcache.tags.total_refs 381840179 # Total number of references to valid blocks.
604 system.cpu.dcache.tags.sampled_refs 2534993 # Sample count of references to valid blocks.
605 system.cpu.dcache.tags.avg_refs 150.627705 # Average number of references to valid blocks.
606 system.cpu.dcache.tags.warmup_cycle 1673396500 # Cycle when the warmup percentage was hit.
607 system.cpu.dcache.tags.occ_blocks::cpu.data 4087.817920 # Average occupied blocks per requestor
608 system.cpu.dcache.tags.occ_percent::cpu.data 0.998002 # Average percentage of cache occupancy
609 system.cpu.dcache.tags.occ_percent::total 0.998002 # Average percentage of cache occupancy
610 system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
611 system.cpu.dcache.tags.age_task_id_blocks_1024::0 29 # Occupied blocks per task id
612 system.cpu.dcache.tags.age_task_id_blocks_1024::1 29 # Occupied blocks per task id
613 system.cpu.dcache.tags.age_task_id_blocks_1024::2 865 # Occupied blocks per task id
614 system.cpu.dcache.tags.age_task_id_blocks_1024::3 3173 # Occupied blocks per task id
615 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
616 system.cpu.dcache.tags.tag_accesses 772772413 # Number of tag accesses
617 system.cpu.dcache.tags.data_accesses 772772413 # Number of data accesses
618 system.cpu.dcache.ReadReq_hits::cpu.data 233184165 # number of ReadReq hits
619 system.cpu.dcache.ReadReq_hits::total 233184165 # number of ReadReq hits
620 system.cpu.dcache.WriteReq_hits::cpu.data 148172813 # number of WriteReq hits
621 system.cpu.dcache.WriteReq_hits::total 148172813 # number of WriteReq hits
622 system.cpu.dcache.demand_hits::cpu.data 381356978 # number of demand (read+write) hits
623 system.cpu.dcache.demand_hits::total 381356978 # number of demand (read+write) hits
624 system.cpu.dcache.overall_hits::cpu.data 381356978 # number of overall hits
625 system.cpu.dcache.overall_hits::total 381356978 # number of overall hits
626 system.cpu.dcache.ReadReq_misses::cpu.data 2774343 # number of ReadReq misses
627 system.cpu.dcache.ReadReq_misses::total 2774343 # number of ReadReq misses
628 system.cpu.dcache.WriteReq_misses::cpu.data 987389 # number of WriteReq misses
629 system.cpu.dcache.WriteReq_misses::total 987389 # number of WriteReq misses
630 system.cpu.dcache.demand_misses::cpu.data 3761732 # number of demand (read+write) misses
631 system.cpu.dcache.demand_misses::total 3761732 # number of demand (read+write) misses
632 system.cpu.dcache.overall_misses::cpu.data 3761732 # number of overall misses
633 system.cpu.dcache.overall_misses::total 3761732 # number of overall misses
634 system.cpu.dcache.ReadReq_miss_latency::cpu.data 59119368500 # number of ReadReq miss cycles
635 system.cpu.dcache.ReadReq_miss_latency::total 59119368500 # number of ReadReq miss cycles
636 system.cpu.dcache.WriteReq_miss_latency::cpu.data 31296279995 # number of WriteReq miss cycles
637 system.cpu.dcache.WriteReq_miss_latency::total 31296279995 # number of WriteReq miss cycles
638 system.cpu.dcache.demand_miss_latency::cpu.data 90415648495 # number of demand (read+write) miss cycles
639 system.cpu.dcache.demand_miss_latency::total 90415648495 # number of demand (read+write) miss cycles
640 system.cpu.dcache.overall_miss_latency::cpu.data 90415648495 # number of overall miss cycles
641 system.cpu.dcache.overall_miss_latency::total 90415648495 # number of overall miss cycles
642 system.cpu.dcache.ReadReq_accesses::cpu.data 235958508 # number of ReadReq accesses(hits+misses)
643 system.cpu.dcache.ReadReq_accesses::total 235958508 # number of ReadReq accesses(hits+misses)
644 system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses)
645 system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses)
646 system.cpu.dcache.demand_accesses::cpu.data 385118710 # number of demand (read+write) accesses
647 system.cpu.dcache.demand_accesses::total 385118710 # number of demand (read+write) accesses
648 system.cpu.dcache.overall_accesses::cpu.data 385118710 # number of overall (read+write) accesses
649 system.cpu.dcache.overall_accesses::total 385118710 # number of overall (read+write) accesses
650 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011758 # miss rate for ReadReq accesses
651 system.cpu.dcache.ReadReq_miss_rate::total 0.011758 # miss rate for ReadReq accesses
652 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006620 # miss rate for WriteReq accesses
653 system.cpu.dcache.WriteReq_miss_rate::total 0.006620 # miss rate for WriteReq accesses
654 system.cpu.dcache.demand_miss_rate::cpu.data 0.009768 # miss rate for demand accesses
655 system.cpu.dcache.demand_miss_rate::total 0.009768 # miss rate for demand accesses
656 system.cpu.dcache.overall_miss_rate::cpu.data 0.009768 # miss rate for overall accesses
657 system.cpu.dcache.overall_miss_rate::total 0.009768 # miss rate for overall accesses
658 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21309.322063 # average ReadReq miss latency
659 system.cpu.dcache.ReadReq_avg_miss_latency::total 21309.322063 # average ReadReq miss latency
660 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31695.998229 # average WriteReq miss latency
661 system.cpu.dcache.WriteReq_avg_miss_latency::total 31695.998229 # average WriteReq miss latency
662 system.cpu.dcache.demand_avg_miss_latency::cpu.data 24035.643287 # average overall miss latency
663 system.cpu.dcache.demand_avg_miss_latency::total 24035.643287 # average overall miss latency
664 system.cpu.dcache.overall_avg_miss_latency::cpu.data 24035.643287 # average overall miss latency
665 system.cpu.dcache.overall_avg_miss_latency::total 24035.643287 # average overall miss latency
666 system.cpu.dcache.blocked_cycles::no_mshrs 10106 # number of cycles access was blocked
667 system.cpu.dcache.blocked_cycles::no_targets 15 # number of cycles access was blocked
668 system.cpu.dcache.blocked::no_mshrs 1086 # number of cycles access was blocked
669 system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked
670 system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.305709 # average number of cycles each access was blocked
671 system.cpu.dcache.avg_blocked_cycles::no_targets 7.500000 # average number of cycles each access was blocked
672 system.cpu.dcache.fast_writes 0 # number of fast writes performed
673 system.cpu.dcache.cache_copies 0 # number of cache copies performed
674 system.cpu.dcache.writebacks::writebacks 2330787 # number of writebacks
675 system.cpu.dcache.writebacks::total 2330787 # number of writebacks
676 system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1009448 # number of ReadReq MSHR hits
677 system.cpu.dcache.ReadReq_mshr_hits::total 1009448 # number of ReadReq MSHR hits
678 system.cpu.dcache.WriteReq_mshr_hits::cpu.data 19379 # number of WriteReq MSHR hits
679 system.cpu.dcache.WriteReq_mshr_hits::total 19379 # number of WriteReq MSHR hits
680 system.cpu.dcache.demand_mshr_hits::cpu.data 1028827 # number of demand (read+write) MSHR hits
681 system.cpu.dcache.demand_mshr_hits::total 1028827 # number of demand (read+write) MSHR hits
682 system.cpu.dcache.overall_mshr_hits::cpu.data 1028827 # number of overall MSHR hits
683 system.cpu.dcache.overall_mshr_hits::total 1028827 # number of overall MSHR hits
684 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1764895 # number of ReadReq MSHR misses
685 system.cpu.dcache.ReadReq_mshr_misses::total 1764895 # number of ReadReq MSHR misses
686 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 968010 # number of WriteReq MSHR misses
687 system.cpu.dcache.WriteReq_mshr_misses::total 968010 # number of WriteReq MSHR misses
688 system.cpu.dcache.demand_mshr_misses::cpu.data 2732905 # number of demand (read+write) MSHR misses
689 system.cpu.dcache.demand_mshr_misses::total 2732905 # number of demand (read+write) MSHR misses
690 system.cpu.dcache.overall_mshr_misses::cpu.data 2732905 # number of overall MSHR misses
691 system.cpu.dcache.overall_mshr_misses::total 2732905 # number of overall MSHR misses
692 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33550858500 # number of ReadReq MSHR miss cycles
693 system.cpu.dcache.ReadReq_mshr_miss_latency::total 33550858500 # number of ReadReq MSHR miss cycles
694 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 30073647496 # number of WriteReq MSHR miss cycles
695 system.cpu.dcache.WriteReq_mshr_miss_latency::total 30073647496 # number of WriteReq MSHR miss cycles
696 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 63624505996 # number of demand (read+write) MSHR miss cycles
697 system.cpu.dcache.demand_mshr_miss_latency::total 63624505996 # number of demand (read+write) MSHR miss cycles
698 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 63624505996 # number of overall MSHR miss cycles
699 system.cpu.dcache.overall_mshr_miss_latency::total 63624505996 # number of overall MSHR miss cycles
700 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007480 # mshr miss rate for ReadReq accesses
701 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007480 # mshr miss rate for ReadReq accesses
702 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006490 # mshr miss rate for WriteReq accesses
703 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006490 # mshr miss rate for WriteReq accesses
704 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.007096 # mshr miss rate for demand accesses
705 system.cpu.dcache.demand_mshr_miss_rate::total 0.007096 # mshr miss rate for demand accesses
706 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.007096 # mshr miss rate for overall accesses
707 system.cpu.dcache.overall_mshr_miss_rate::total 0.007096 # mshr miss rate for overall accesses
708 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19010.115899 # average ReadReq mshr miss latency
709 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19010.115899 # average ReadReq mshr miss latency
710 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31067.496716 # average WriteReq mshr miss latency
711 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31067.496716 # average WriteReq mshr miss latency
712 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23280.906580 # average overall mshr miss latency
713 system.cpu.dcache.demand_avg_mshr_miss_latency::total 23280.906580 # average overall mshr miss latency
714 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23280.906580 # average overall mshr miss latency
715 system.cpu.dcache.overall_avg_mshr_miss_latency::total 23280.906580 # average overall mshr miss latency
716 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
717 system.cpu.icache.tags.replacements 6655 # number of replacements
718 system.cpu.icache.tags.tagsinuse 1037.678215 # Cycle average of tags in use
719 system.cpu.icache.tags.total_refs 170577740 # Total number of references to valid blocks.
720 system.cpu.icache.tags.sampled_refs 8265 # Sample count of references to valid blocks.
721 system.cpu.icache.tags.avg_refs 20638.565033 # Average number of references to valid blocks.
722 system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
723 system.cpu.icache.tags.occ_blocks::cpu.inst 1037.678215 # Average occupied blocks per requestor
724 system.cpu.icache.tags.occ_percent::cpu.inst 0.506679 # Average percentage of cache occupancy
725 system.cpu.icache.tags.occ_percent::total 0.506679 # Average percentage of cache occupancy
726 system.cpu.icache.tags.occ_task_id_blocks::1024 1610 # Occupied blocks per task id
727 system.cpu.icache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id
728 system.cpu.icache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id
729 system.cpu.icache.tags.age_task_id_blocks_1024::2 50 # Occupied blocks per task id
730 system.cpu.icache.tags.age_task_id_blocks_1024::3 326 # Occupied blocks per task id
731 system.cpu.icache.tags.age_task_id_blocks_1024::4 1153 # Occupied blocks per task id
732 system.cpu.icache.tags.occ_task_id_percent::1024 0.786133 # Percentage of cache occupancy per task id
733 system.cpu.icache.tags.tag_accesses 341785100 # Number of tag accesses
734 system.cpu.icache.tags.data_accesses 341785100 # Number of data accesses
735 system.cpu.icache.ReadReq_hits::cpu.inst 170580521 # number of ReadReq hits
736 system.cpu.icache.ReadReq_hits::total 170580521 # number of ReadReq hits
737 system.cpu.icache.demand_hits::cpu.inst 170580521 # number of demand (read+write) hits
738 system.cpu.icache.demand_hits::total 170580521 # number of demand (read+write) hits
739 system.cpu.icache.overall_hits::cpu.inst 170580521 # number of overall hits
740 system.cpu.icache.overall_hits::total 170580521 # number of overall hits
741 system.cpu.icache.ReadReq_misses::cpu.inst 208882 # number of ReadReq misses
742 system.cpu.icache.ReadReq_misses::total 208882 # number of ReadReq misses
743 system.cpu.icache.demand_misses::cpu.inst 208882 # number of demand (read+write) misses
744 system.cpu.icache.demand_misses::total 208882 # number of demand (read+write) misses
745 system.cpu.icache.overall_misses::cpu.inst 208882 # number of overall misses
746 system.cpu.icache.overall_misses::total 208882 # number of overall misses
747 system.cpu.icache.ReadReq_miss_latency::cpu.inst 1312211500 # number of ReadReq miss cycles
748 system.cpu.icache.ReadReq_miss_latency::total 1312211500 # number of ReadReq miss cycles
749 system.cpu.icache.demand_miss_latency::cpu.inst 1312211500 # number of demand (read+write) miss cycles
750 system.cpu.icache.demand_miss_latency::total 1312211500 # number of demand (read+write) miss cycles
751 system.cpu.icache.overall_miss_latency::cpu.inst 1312211500 # number of overall miss cycles
752 system.cpu.icache.overall_miss_latency::total 1312211500 # number of overall miss cycles
753 system.cpu.icache.ReadReq_accesses::cpu.inst 170789403 # number of ReadReq accesses(hits+misses)
754 system.cpu.icache.ReadReq_accesses::total 170789403 # number of ReadReq accesses(hits+misses)
755 system.cpu.icache.demand_accesses::cpu.inst 170789403 # number of demand (read+write) accesses
756 system.cpu.icache.demand_accesses::total 170789403 # number of demand (read+write) accesses
757 system.cpu.icache.overall_accesses::cpu.inst 170789403 # number of overall (read+write) accesses
758 system.cpu.icache.overall_accesses::total 170789403 # number of overall (read+write) accesses
759 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001223 # miss rate for ReadReq accesses
760 system.cpu.icache.ReadReq_miss_rate::total 0.001223 # miss rate for ReadReq accesses
761 system.cpu.icache.demand_miss_rate::cpu.inst 0.001223 # miss rate for demand accesses
762 system.cpu.icache.demand_miss_rate::total 0.001223 # miss rate for demand accesses
763 system.cpu.icache.overall_miss_rate::cpu.inst 0.001223 # miss rate for overall accesses
764 system.cpu.icache.overall_miss_rate::total 0.001223 # miss rate for overall accesses
765 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6282.070739 # average ReadReq miss latency
766 system.cpu.icache.ReadReq_avg_miss_latency::total 6282.070739 # average ReadReq miss latency
767 system.cpu.icache.demand_avg_miss_latency::cpu.inst 6282.070739 # average overall miss latency
768 system.cpu.icache.demand_avg_miss_latency::total 6282.070739 # average overall miss latency
769 system.cpu.icache.overall_avg_miss_latency::cpu.inst 6282.070739 # average overall miss latency
770 system.cpu.icache.overall_avg_miss_latency::total 6282.070739 # average overall miss latency
771 system.cpu.icache.blocked_cycles::no_mshrs 889 # number of cycles access was blocked
772 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
773 system.cpu.icache.blocked::no_mshrs 12 # number of cycles access was blocked
774 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
775 system.cpu.icache.avg_blocked_cycles::no_mshrs 74.083333 # average number of cycles each access was blocked
776 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
777 system.cpu.icache.fast_writes 0 # number of fast writes performed
778 system.cpu.icache.cache_copies 0 # number of cache copies performed
779 system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2585 # number of ReadReq MSHR hits
780 system.cpu.icache.ReadReq_mshr_hits::total 2585 # number of ReadReq MSHR hits
781 system.cpu.icache.demand_mshr_hits::cpu.inst 2585 # number of demand (read+write) MSHR hits
782 system.cpu.icache.demand_mshr_hits::total 2585 # number of demand (read+write) MSHR hits
783 system.cpu.icache.overall_mshr_hits::cpu.inst 2585 # number of overall MSHR hits
784 system.cpu.icache.overall_mshr_hits::total 2585 # number of overall MSHR hits
785 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 206297 # number of ReadReq MSHR misses
786 system.cpu.icache.ReadReq_mshr_misses::total 206297 # number of ReadReq MSHR misses
787 system.cpu.icache.demand_mshr_misses::cpu.inst 206297 # number of demand (read+write) MSHR misses
788 system.cpu.icache.demand_mshr_misses::total 206297 # number of demand (read+write) MSHR misses
789 system.cpu.icache.overall_mshr_misses::cpu.inst 206297 # number of overall MSHR misses
790 system.cpu.icache.overall_mshr_misses::total 206297 # number of overall MSHR misses
791 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 989635000 # number of ReadReq MSHR miss cycles
792 system.cpu.icache.ReadReq_mshr_miss_latency::total 989635000 # number of ReadReq MSHR miss cycles
793 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 989635000 # number of demand (read+write) MSHR miss cycles
794 system.cpu.icache.demand_mshr_miss_latency::total 989635000 # number of demand (read+write) MSHR miss cycles
795 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 989635000 # number of overall MSHR miss cycles
796 system.cpu.icache.overall_mshr_miss_latency::total 989635000 # number of overall MSHR miss cycles
797 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001208 # mshr miss rate for ReadReq accesses
798 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001208 # mshr miss rate for ReadReq accesses
799 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001208 # mshr miss rate for demand accesses
800 system.cpu.icache.demand_mshr_miss_rate::total 0.001208 # mshr miss rate for demand accesses
801 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001208 # mshr miss rate for overall accesses
802 system.cpu.icache.overall_mshr_miss_rate::total 0.001208 # mshr miss rate for overall accesses
803 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 4797.137137 # average ReadReq mshr miss latency
804 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 4797.137137 # average ReadReq mshr miss latency
805 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 4797.137137 # average overall mshr miss latency
806 system.cpu.icache.demand_avg_mshr_miss_latency::total 4797.137137 # average overall mshr miss latency
807 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4797.137137 # average overall mshr miss latency
808 system.cpu.icache.overall_avg_mshr_miss_latency::total 4797.137137 # average overall mshr miss latency
809 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
810 system.cpu.l2cache.tags.replacements 353544 # number of replacements
811 system.cpu.l2cache.tags.tagsinuse 29619.458392 # Cycle average of tags in use
812 system.cpu.l2cache.tags.total_refs 3891749 # Total number of references to valid blocks.
813 system.cpu.l2cache.tags.sampled_refs 385874 # Sample count of references to valid blocks.
814 system.cpu.l2cache.tags.avg_refs 10.085543 # Average number of references to valid blocks.
815 system.cpu.l2cache.tags.warmup_cycle 189343942500 # Cycle when the warmup percentage was hit.
816 system.cpu.l2cache.tags.occ_blocks::writebacks 20941.541383 # Average occupied blocks per requestor
817 system.cpu.l2cache.tags.occ_blocks::cpu.inst 242.518808 # Average occupied blocks per requestor
818 system.cpu.l2cache.tags.occ_blocks::cpu.data 8435.398201 # Average occupied blocks per requestor
819 system.cpu.l2cache.tags.occ_percent::writebacks 0.639085 # Average percentage of cache occupancy
820 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.007401 # Average percentage of cache occupancy
821 system.cpu.l2cache.tags.occ_percent::cpu.data 0.257428 # Average percentage of cache occupancy
822 system.cpu.l2cache.tags.occ_percent::total 0.903914 # Average percentage of cache occupancy
823 system.cpu.l2cache.tags.occ_task_id_blocks::1024 32330 # Occupied blocks per task id
824 system.cpu.l2cache.tags.age_task_id_blocks_1024::0 84 # Occupied blocks per task id
825 system.cpu.l2cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id
826 system.cpu.l2cache.tags.age_task_id_blocks_1024::2 215 # Occupied blocks per task id
827 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 13379 # Occupied blocks per task id
828 system.cpu.l2cache.tags.age_task_id_blocks_1024::4 18648 # Occupied blocks per task id
829 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.986633 # Percentage of cache occupancy per task id
830 system.cpu.l2cache.tags.tag_accesses 43295860 # Number of tag accesses
831 system.cpu.l2cache.tags.data_accesses 43295860 # Number of data accesses
832 system.cpu.l2cache.Writeback_hits::writebacks 2330787 # number of Writeback hits
833 system.cpu.l2cache.Writeback_hits::total 2330787 # number of Writeback hits
834 system.cpu.l2cache.UpgradeReq_hits::cpu.data 1834 # number of UpgradeReq hits
835 system.cpu.l2cache.UpgradeReq_hits::total 1834 # number of UpgradeReq hits
836 system.cpu.l2cache.ReadExReq_hits::cpu.data 563915 # number of ReadExReq hits
837 system.cpu.l2cache.ReadExReq_hits::total 563915 # number of ReadExReq hits
838 system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 4843 # number of ReadCleanReq hits
839 system.cpu.l2cache.ReadCleanReq_hits::total 4843 # number of ReadCleanReq hits
840 system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1588207 # number of ReadSharedReq hits
841 system.cpu.l2cache.ReadSharedReq_hits::total 1588207 # number of ReadSharedReq hits
842 system.cpu.l2cache.demand_hits::cpu.inst 4843 # number of demand (read+write) hits
843 system.cpu.l2cache.demand_hits::cpu.data 2152122 # number of demand (read+write) hits
844 system.cpu.l2cache.demand_hits::total 2156965 # number of demand (read+write) hits
845 system.cpu.l2cache.overall_hits::cpu.inst 4843 # number of overall hits
846 system.cpu.l2cache.overall_hits::cpu.data 2152122 # number of overall hits
847 system.cpu.l2cache.overall_hits::total 2156965 # number of overall hits
848 system.cpu.l2cache.UpgradeReq_misses::cpu.data 196078 # number of UpgradeReq misses
849 system.cpu.l2cache.UpgradeReq_misses::total 196078 # number of UpgradeReq misses
850 system.cpu.l2cache.ReadExReq_misses::cpu.data 206573 # number of ReadExReq misses
851 system.cpu.l2cache.ReadExReq_misses::total 206573 # number of ReadExReq misses
852 system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3410 # number of ReadCleanReq misses
853 system.cpu.l2cache.ReadCleanReq_misses::total 3410 # number of ReadCleanReq misses
854 system.cpu.l2cache.ReadSharedReq_misses::cpu.data 176298 # number of ReadSharedReq misses
855 system.cpu.l2cache.ReadSharedReq_misses::total 176298 # number of ReadSharedReq misses
856 system.cpu.l2cache.demand_misses::cpu.inst 3410 # number of demand (read+write) misses
857 system.cpu.l2cache.demand_misses::cpu.data 382871 # number of demand (read+write) misses
858 system.cpu.l2cache.demand_misses::total 386281 # number of demand (read+write) misses
859 system.cpu.l2cache.overall_misses::cpu.inst 3410 # number of overall misses
860 system.cpu.l2cache.overall_misses::cpu.data 382871 # number of overall misses
861 system.cpu.l2cache.overall_misses::total 386281 # number of overall misses
862 system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 13890000 # number of UpgradeReq miss cycles
863 system.cpu.l2cache.UpgradeReq_miss_latency::total 13890000 # number of UpgradeReq miss cycles
864 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16378927500 # number of ReadExReq miss cycles
865 system.cpu.l2cache.ReadExReq_miss_latency::total 16378927500 # number of ReadExReq miss cycles
866 system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 280136500 # number of ReadCleanReq miss cycles
867 system.cpu.l2cache.ReadCleanReq_miss_latency::total 280136500 # number of ReadCleanReq miss cycles
868 system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 14178823000 # number of ReadSharedReq miss cycles
869 system.cpu.l2cache.ReadSharedReq_miss_latency::total 14178823000 # number of ReadSharedReq miss cycles
870 system.cpu.l2cache.demand_miss_latency::cpu.inst 280136500 # number of demand (read+write) miss cycles
871 system.cpu.l2cache.demand_miss_latency::cpu.data 30557750500 # number of demand (read+write) miss cycles
872 system.cpu.l2cache.demand_miss_latency::total 30837887000 # number of demand (read+write) miss cycles
873 system.cpu.l2cache.overall_miss_latency::cpu.inst 280136500 # number of overall miss cycles
874 system.cpu.l2cache.overall_miss_latency::cpu.data 30557750500 # number of overall miss cycles
875 system.cpu.l2cache.overall_miss_latency::total 30837887000 # number of overall miss cycles
876 system.cpu.l2cache.Writeback_accesses::writebacks 2330787 # number of Writeback accesses(hits+misses)
877 system.cpu.l2cache.Writeback_accesses::total 2330787 # number of Writeback accesses(hits+misses)
878 system.cpu.l2cache.UpgradeReq_accesses::cpu.data 197912 # number of UpgradeReq accesses(hits+misses)
879 system.cpu.l2cache.UpgradeReq_accesses::total 197912 # number of UpgradeReq accesses(hits+misses)
880 system.cpu.l2cache.ReadExReq_accesses::cpu.data 770488 # number of ReadExReq accesses(hits+misses)
881 system.cpu.l2cache.ReadExReq_accesses::total 770488 # number of ReadExReq accesses(hits+misses)
882 system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 8253 # number of ReadCleanReq accesses(hits+misses)
883 system.cpu.l2cache.ReadCleanReq_accesses::total 8253 # number of ReadCleanReq accesses(hits+misses)
884 system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1764505 # number of ReadSharedReq accesses(hits+misses)
885 system.cpu.l2cache.ReadSharedReq_accesses::total 1764505 # number of ReadSharedReq accesses(hits+misses)
886 system.cpu.l2cache.demand_accesses::cpu.inst 8253 # number of demand (read+write) accesses
887 system.cpu.l2cache.demand_accesses::cpu.data 2534993 # number of demand (read+write) accesses
888 system.cpu.l2cache.demand_accesses::total 2543246 # number of demand (read+write) accesses
889 system.cpu.l2cache.overall_accesses::cpu.inst 8253 # number of overall (read+write) accesses
890 system.cpu.l2cache.overall_accesses::cpu.data 2534993 # number of overall (read+write) accesses
891 system.cpu.l2cache.overall_accesses::total 2543246 # number of overall (read+write) accesses
892 system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.990733 # miss rate for UpgradeReq accesses
893 system.cpu.l2cache.UpgradeReq_miss_rate::total 0.990733 # miss rate for UpgradeReq accesses
894 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.268107 # miss rate for ReadExReq accesses
895 system.cpu.l2cache.ReadExReq_miss_rate::total 0.268107 # miss rate for ReadExReq accesses
896 system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.413183 # miss rate for ReadCleanReq accesses
897 system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.413183 # miss rate for ReadCleanReq accesses
898 system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.099914 # miss rate for ReadSharedReq accesses
899 system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.099914 # miss rate for ReadSharedReq accesses
900 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.413183 # miss rate for demand accesses
901 system.cpu.l2cache.demand_miss_rate::cpu.data 0.151034 # miss rate for demand accesses
902 system.cpu.l2cache.demand_miss_rate::total 0.151885 # miss rate for demand accesses
903 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.413183 # miss rate for overall accesses
904 system.cpu.l2cache.overall_miss_rate::cpu.data 0.151034 # miss rate for overall accesses
905 system.cpu.l2cache.overall_miss_rate::total 0.151885 # miss rate for overall accesses
906 system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 70.839156 # average UpgradeReq miss latency
907 system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 70.839156 # average UpgradeReq miss latency
908 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79288.810735 # average ReadExReq miss latency
909 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79288.810735 # average ReadExReq miss latency
910 system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82151.466276 # average ReadCleanReq miss latency
911 system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82151.466276 # average ReadCleanReq miss latency
912 system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80425.319629 # average ReadSharedReq miss latency
913 system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80425.319629 # average ReadSharedReq miss latency
914 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82151.466276 # average overall miss latency
915 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79812.131240 # average overall miss latency
916 system.cpu.l2cache.demand_avg_miss_latency::total 79832.782353 # average overall miss latency
917 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82151.466276 # average overall miss latency
918 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79812.131240 # average overall miss latency
919 system.cpu.l2cache.overall_avg_miss_latency::total 79832.782353 # average overall miss latency
920 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
921 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
922 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
923 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
924 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
925 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
926 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
927 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
928 system.cpu.l2cache.writebacks::writebacks 294838 # number of writebacks
929 system.cpu.l2cache.writebacks::total 294838 # number of writebacks
930 system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 2 # number of ReadCleanReq MSHR hits
931 system.cpu.l2cache.ReadCleanReq_mshr_hits::total 2 # number of ReadCleanReq MSHR hits
932 system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits
933 system.cpu.l2cache.demand_mshr_hits::total 2 # number of demand (read+write) MSHR hits
934 system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits
935 system.cpu.l2cache.overall_mshr_hits::total 2 # number of overall MSHR hits
936 system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 1958 # number of CleanEvict MSHR misses
937 system.cpu.l2cache.CleanEvict_mshr_misses::total 1958 # number of CleanEvict MSHR misses
938 system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 196078 # number of UpgradeReq MSHR misses
939 system.cpu.l2cache.UpgradeReq_mshr_misses::total 196078 # number of UpgradeReq MSHR misses
940 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206573 # number of ReadExReq MSHR misses
941 system.cpu.l2cache.ReadExReq_mshr_misses::total 206573 # number of ReadExReq MSHR misses
942 system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3408 # number of ReadCleanReq MSHR misses
943 system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3408 # number of ReadCleanReq MSHR misses
944 system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 176298 # number of ReadSharedReq MSHR misses
945 system.cpu.l2cache.ReadSharedReq_mshr_misses::total 176298 # number of ReadSharedReq MSHR misses
946 system.cpu.l2cache.demand_mshr_misses::cpu.inst 3408 # number of demand (read+write) MSHR misses
947 system.cpu.l2cache.demand_mshr_misses::cpu.data 382871 # number of demand (read+write) MSHR misses
948 system.cpu.l2cache.demand_mshr_misses::total 386279 # number of demand (read+write) MSHR misses
949 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3408 # number of overall MSHR misses
950 system.cpu.l2cache.overall_mshr_misses::cpu.data 382871 # number of overall MSHR misses
951 system.cpu.l2cache.overall_mshr_misses::total 386279 # number of overall MSHR misses
952 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 4323708271 # number of UpgradeReq MSHR miss cycles
953 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 4323708271 # number of UpgradeReq MSHR miss cycles
954 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 14313197500 # number of ReadExReq MSHR miss cycles
955 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 14313197500 # number of ReadExReq MSHR miss cycles
956 system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 245909500 # number of ReadCleanReq MSHR miss cycles
957 system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 245909500 # number of ReadCleanReq MSHR miss cycles
958 system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 12415843000 # number of ReadSharedReq MSHR miss cycles
959 system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 12415843000 # number of ReadSharedReq MSHR miss cycles
960 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 245909500 # number of demand (read+write) MSHR miss cycles
961 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 26729040500 # number of demand (read+write) MSHR miss cycles
962 system.cpu.l2cache.demand_mshr_miss_latency::total 26974950000 # number of demand (read+write) MSHR miss cycles
963 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 245909500 # number of overall MSHR miss cycles
964 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 26729040500 # number of overall MSHR miss cycles
965 system.cpu.l2cache.overall_mshr_miss_latency::total 26974950000 # number of overall MSHR miss cycles
966 system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
967 system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
968 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.990733 # mshr miss rate for UpgradeReq accesses
969 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.990733 # mshr miss rate for UpgradeReq accesses
970 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.268107 # mshr miss rate for ReadExReq accesses
971 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.268107 # mshr miss rate for ReadExReq accesses
972 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.412941 # mshr miss rate for ReadCleanReq accesses
973 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.412941 # mshr miss rate for ReadCleanReq accesses
974 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.099914 # mshr miss rate for ReadSharedReq accesses
975 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.099914 # mshr miss rate for ReadSharedReq accesses
976 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.412941 # mshr miss rate for demand accesses
977 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.151034 # mshr miss rate for demand accesses
978 system.cpu.l2cache.demand_mshr_miss_rate::total 0.151884 # mshr miss rate for demand accesses
979 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.412941 # mshr miss rate for overall accesses
980 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.151034 # mshr miss rate for overall accesses
981 system.cpu.l2cache.overall_mshr_miss_rate::total 0.151884 # mshr miss rate for overall accesses
982 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 22050.960694 # average UpgradeReq mshr miss latency
983 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 22050.960694 # average UpgradeReq mshr miss latency
984 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69288.810735 # average ReadExReq mshr miss latency
985 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69288.810735 # average ReadExReq mshr miss latency
986 system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72156.543427 # average ReadCleanReq mshr miss latency
987 system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72156.543427 # average ReadCleanReq mshr miss latency
988 system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70425.319629 # average ReadSharedReq mshr miss latency
989 system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70425.319629 # average ReadSharedReq mshr miss latency
990 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72156.543427 # average overall mshr miss latency
991 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69812.131240 # average overall mshr miss latency
992 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69832.815141 # average overall mshr miss latency
993 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72156.543427 # average overall mshr miss latency
994 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69812.131240 # average overall mshr miss latency
995 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69832.815141 # average overall mshr miss latency
996 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
997 system.cpu.toL2Bus.snoop_filter.tot_requests 5476754 # Total number of requests made to the snoop filter.
998 system.cpu.toL2Bus.snoop_filter.hit_single_requests 2732107 # Number of requests hitting in the snoop filter with a single holder of the requested data.
999 system.cpu.toL2Bus.snoop_filter.hit_multi_requests 213805 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1000 system.cpu.toL2Bus.snoop_filter.tot_snoops 3607 # Total number of snoops made to the snoop filter.
1001 system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3607 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1002 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
1003 system.cpu.toL2Bus.trans_dist::ReadResp 1970799 # Transaction distribution
1004 system.cpu.toL2Bus.trans_dist::Writeback 2625625 # Transaction distribution
1005 system.cpu.toL2Bus.trans_dist::CleanEvict 253914 # Transaction distribution
1006 system.cpu.toL2Bus.trans_dist::UpgradeReq 197912 # Transaction distribution
1007 system.cpu.toL2Bus.trans_dist::UpgradeResp 197912 # Transaction distribution
1008 system.cpu.toL2Bus.trans_dist::ReadExReq 770488 # Transaction distribution
1009 system.cpu.toL2Bus.trans_dist::ReadExResp 770488 # Transaction distribution
1010 system.cpu.toL2Bus.trans_dist::ReadCleanReq 206297 # Transaction distribution
1011 system.cpu.toL2Bus.trans_dist::ReadSharedReq 1764505 # Transaction distribution
1012 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 220789 # Packet count per connected master and slave (bytes)
1013 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7985563 # Packet count per connected master and slave (bytes)
1014 system.cpu.toL2Bus.pkt_count::total 8206352 # Packet count per connected master and slave (bytes)
1015 system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 528000 # Cumulative packet size per connected master and slave (bytes)
1016 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311409920 # Cumulative packet size per connected master and slave (bytes)
1017 system.cpu.toL2Bus.pkt_size::total 311937920 # Cumulative packet size per connected master and slave (bytes)
1018 system.cpu.toL2Bus.snoops 551588 # Total snoops (count)
1019 system.cpu.toL2Bus.snoop_fanout::samples 5830298 # Request fanout histogram
1020 system.cpu.toL2Bus.snoop_fanout::mean 0.072755 # Request fanout histogram
1021 system.cpu.toL2Bus.snoop_fanout::stdev 0.259734 # Request fanout histogram
1022 system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1023 system.cpu.toL2Bus.snoop_fanout::0 5406114 92.72% 92.72% # Request fanout histogram
1024 system.cpu.toL2Bus.snoop_fanout::1 424184 7.28% 100.00% # Request fanout histogram
1025 system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
1026 system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1027 system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
1028 system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
1029 system.cpu.toL2Bus.snoop_fanout::total 5830298 # Request fanout histogram
1030 system.cpu.toL2Bus.reqLayer0.occupancy 5097760193 # Layer occupancy (ticks)
1031 system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%)
1032 system.cpu.toL2Bus.respLayer0.occupancy 309447487 # Layer occupancy (ticks)
1033 system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
1034 system.cpu.toL2Bus.respLayer1.occupancy 3901446077 # Layer occupancy (ticks)
1035 system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%)
1036 system.membus.trans_dist::ReadResp 179703 # Transaction distribution
1037 system.membus.trans_dist::Writeback 294838 # Transaction distribution
1038 system.membus.trans_dist::CleanEvict 57117 # Transaction distribution
1039 system.membus.trans_dist::UpgradeReq 196128 # Transaction distribution
1040 system.membus.trans_dist::UpgradeResp 196128 # Transaction distribution
1041 system.membus.trans_dist::ReadExReq 206523 # Transaction distribution
1042 system.membus.trans_dist::ReadExResp 206523 # Transaction distribution
1043 system.membus.trans_dist::ReadSharedReq 179705 # Transaction distribution
1044 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1516665 # Packet count per connected master and slave (bytes)
1045 system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1516665 # Packet count per connected master and slave (bytes)
1046 system.membus.pkt_count::total 1516665 # Packet count per connected master and slave (bytes)
1047 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43588096 # Cumulative packet size per connected master and slave (bytes)
1048 system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43588096 # Cumulative packet size per connected master and slave (bytes)
1049 system.membus.pkt_size::total 43588096 # Cumulative packet size per connected master and slave (bytes)
1050 system.membus.snoops 0 # Total snoops (count)
1051 system.membus.snoop_fanout::samples 934311 # Request fanout histogram
1052 system.membus.snoop_fanout::mean 0 # Request fanout histogram
1053 system.membus.snoop_fanout::stdev 0 # Request fanout histogram
1054 system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1055 system.membus.snoop_fanout::0 934311 100.00% 100.00% # Request fanout histogram
1056 system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
1057 system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1058 system.membus.snoop_fanout::min_value 0 # Request fanout histogram
1059 system.membus.snoop_fanout::max_value 0 # Request fanout histogram
1060 system.membus.snoop_fanout::total 934311 # Request fanout histogram
1061 system.membus.reqLayer0.occupancy 2245481708 # Layer occupancy (ticks)
1062 system.membus.reqLayer0.utilization 0.6 # Layer utilization (%)
1063 system.membus.respLayer1.occupancy 2435298904 # Layer occupancy (ticks)
1064 system.membus.respLayer1.utilization 0.6 # Layer utilization (%)
1066 ---------- End Simulation Statistics ----------
projects / gem5.git / blob