2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.417996 # Number of seconds simulated
4 sim_ticks 417996021500 # Number of ticks simulated
5 final_tick 417996021500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 98610 # Simulator instruction rate (inst/s)
8 host_op_rate 182341 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 49848381 # Simulator tick rate (ticks/s)
10 host_mem_usage 430328 # Number of bytes of host memory used
11 host_seconds 8385.35 # Real time elapsed on the host
12 sim_insts 826877109 # Number of instructions simulated
13 sim_ops 1528988701 # Number of ops (including micro ops) simulated
14 system.voltage_domain.voltage 1 # Voltage in Volts
15 system.clk_domain.clock 1000 # Clock period in ticks
16 system.physmem.bytes_read::cpu.inst 227200 # Number of bytes read from this memory
17 system.physmem.bytes_read::cpu.data 24536320 # Number of bytes read from this memory
18 system.physmem.bytes_read::total 24763520 # Number of bytes read from this memory
19 system.physmem.bytes_inst_read::cpu.inst 227200 # Number of instructions bytes read from this memory
20 system.physmem.bytes_inst_read::total 227200 # Number of instructions bytes read from this memory
21 system.physmem.bytes_written::writebacks 18818240 # Number of bytes written to this memory
22 system.physmem.bytes_written::total 18818240 # Number of bytes written to this memory
23 system.physmem.num_reads::cpu.inst 3550 # Number of read requests responded to by this memory
24 system.physmem.num_reads::cpu.data 383380 # Number of read requests responded to by this memory
25 system.physmem.num_reads::total 386930 # Number of read requests responded to by this memory
26 system.physmem.num_writes::writebacks 294035 # Number of write requests responded to by this memory
27 system.physmem.num_writes::total 294035 # Number of write requests responded to by this memory
28 system.physmem.bw_read::cpu.inst 543546 # Total read bandwidth from this memory (bytes/s)
29 system.physmem.bw_read::cpu.data 58699889 # Total read bandwidth from this memory (bytes/s)
30 system.physmem.bw_read::total 59243435 # Total read bandwidth from this memory (bytes/s)
31 system.physmem.bw_inst_read::cpu.inst 543546 # Instruction read bandwidth from this memory (bytes/s)
32 system.physmem.bw_inst_read::total 543546 # Instruction read bandwidth from this memory (bytes/s)
33 system.physmem.bw_write::writebacks 45020141 # Write bandwidth from this memory (bytes/s)
34 system.physmem.bw_write::total 45020141 # Write bandwidth from this memory (bytes/s)
35 system.physmem.bw_total::writebacks 45020141 # Total bandwidth to/from this memory (bytes/s)
36 system.physmem.bw_total::cpu.inst 543546 # Total bandwidth to/from this memory (bytes/s)
37 system.physmem.bw_total::cpu.data 58699889 # Total bandwidth to/from this memory (bytes/s)
38 system.physmem.bw_total::total 104263576 # Total bandwidth to/from this memory (bytes/s)
39 system.physmem.readReqs 386930 # Number of read requests accepted
40 system.physmem.writeReqs 294035 # Number of write requests accepted
41 system.physmem.readBursts 386930 # Number of DRAM read bursts, including those serviced by the write queue
42 system.physmem.writeBursts 294035 # Number of DRAM write bursts, including those merged in the write queue
43 system.physmem.bytesReadDRAM 24740928 # Total number of bytes read from DRAM
44 system.physmem.bytesReadWrQ 22592 # Total number of bytes read from write queue
45 system.physmem.bytesWritten 18817024 # Total number of bytes written to DRAM
46 system.physmem.bytesReadSys 24763520 # Total read bytes from the system interface side
47 system.physmem.bytesWrittenSys 18818240 # Total written bytes from the system interface side
48 system.physmem.servicedByWrQ 353 # Number of DRAM read bursts serviced by the write queue
49 system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
50 system.physmem.neitherReadNorWriteReqs 195133 # Number of requests that are neither read nor write
51 system.physmem.perBankRdBursts::0 24110 # Per bank write bursts
52 system.physmem.perBankRdBursts::1 26511 # Per bank write bursts
53 system.physmem.perBankRdBursts::2 24689 # Per bank write bursts
54 system.physmem.perBankRdBursts::3 24586 # Per bank write bursts
55 system.physmem.perBankRdBursts::4 23301 # Per bank write bursts
56 system.physmem.perBankRdBursts::5 23773 # Per bank write bursts
57 system.physmem.perBankRdBursts::6 24463 # Per bank write bursts
58 system.physmem.perBankRdBursts::7 24300 # Per bank write bursts
59 system.physmem.perBankRdBursts::8 23625 # Per bank write bursts
60 system.physmem.perBankRdBursts::9 23952 # Per bank write bursts
61 system.physmem.perBankRdBursts::10 24787 # Per bank write bursts
62 system.physmem.perBankRdBursts::11 24070 # Per bank write bursts
63 system.physmem.perBankRdBursts::12 23353 # Per bank write bursts
64 system.physmem.perBankRdBursts::13 22981 # Per bank write bursts
65 system.physmem.perBankRdBursts::14 24097 # Per bank write bursts
66 system.physmem.perBankRdBursts::15 23979 # Per bank write bursts
67 system.physmem.perBankWrBursts::0 18543 # Per bank write bursts
68 system.physmem.perBankWrBursts::1 19847 # Per bank write bursts
69 system.physmem.perBankWrBursts::2 18947 # Per bank write bursts
70 system.physmem.perBankWrBursts::3 18939 # Per bank write bursts
71 system.physmem.perBankWrBursts::4 18047 # Per bank write bursts
72 system.physmem.perBankWrBursts::5 18457 # Per bank write bursts
73 system.physmem.perBankWrBursts::6 18996 # Per bank write bursts
74 system.physmem.perBankWrBursts::7 18981 # Per bank write bursts
75 system.physmem.perBankWrBursts::8 18548 # Per bank write bursts
76 system.physmem.perBankWrBursts::9 18168 # Per bank write bursts
77 system.physmem.perBankWrBursts::10 18839 # Per bank write bursts
78 system.physmem.perBankWrBursts::11 17728 # Per bank write bursts
79 system.physmem.perBankWrBursts::12 17372 # Per bank write bursts
80 system.physmem.perBankWrBursts::13 16973 # Per bank write bursts
81 system.physmem.perBankWrBursts::14 17820 # Per bank write bursts
82 system.physmem.perBankWrBursts::15 17811 # Per bank write bursts
83 system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
84 system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
85 system.physmem.totGap 417995980500 # Total gap between requests
86 system.physmem.readPktSize::0 0 # Read request sizes (log2)
87 system.physmem.readPktSize::1 0 # Read request sizes (log2)
88 system.physmem.readPktSize::2 0 # Read request sizes (log2)
89 system.physmem.readPktSize::3 0 # Read request sizes (log2)
90 system.physmem.readPktSize::4 0 # Read request sizes (log2)
91 system.physmem.readPktSize::5 0 # Read request sizes (log2)
92 system.physmem.readPktSize::6 386930 # Read request sizes (log2)
93 system.physmem.writePktSize::0 0 # Write request sizes (log2)
94 system.physmem.writePktSize::1 0 # Write request sizes (log2)
95 system.physmem.writePktSize::2 0 # Write request sizes (log2)
96 system.physmem.writePktSize::3 0 # Write request sizes (log2)
97 system.physmem.writePktSize::4 0 # Write request sizes (log2)
98 system.physmem.writePktSize::5 0 # Write request sizes (log2)
99 system.physmem.writePktSize::6 294035 # Write request sizes (log2)
100 system.physmem.rdQLenPdf::0 381501 # What read queue length does an incoming req see
101 system.physmem.rdQLenPdf::1 4668 # What read queue length does an incoming req see
102 system.physmem.rdQLenPdf::2 352 # What read queue length does an incoming req see
103 system.physmem.rdQLenPdf::3 43 # What read queue length does an incoming req see
104 system.physmem.rdQLenPdf::4 10 # What read queue length does an incoming req see
105 system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see
106 system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
107 system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
108 system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
109 system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
110 system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
111 system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
112 system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
113 system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
114 system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
115 system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
116 system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
117 system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
118 system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
119 system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
120 system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
121 system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
122 system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
123 system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
124 system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
125 system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
126 system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
127 system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
128 system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
129 system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
130 system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
131 system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
132 system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
133 system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
134 system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
135 system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
136 system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
137 system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
138 system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
139 system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
140 system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
141 system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
142 system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
143 system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
144 system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
145 system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
146 system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
147 system.physmem.wrQLenPdf::15 6148 # What write queue length does an incoming req see
148 system.physmem.wrQLenPdf::16 6568 # What write queue length does an incoming req see
149 system.physmem.wrQLenPdf::17 16924 # What write queue length does an incoming req see
150 system.physmem.wrQLenPdf::18 17484 # What write queue length does an incoming req see
151 system.physmem.wrQLenPdf::19 17568 # What write queue length does an incoming req see
152 system.physmem.wrQLenPdf::20 17557 # What write queue length does an incoming req see
153 system.physmem.wrQLenPdf::21 17592 # What write queue length does an incoming req see
154 system.physmem.wrQLenPdf::22 17589 # What write queue length does an incoming req see
155 system.physmem.wrQLenPdf::23 17636 # What write queue length does an incoming req see
156 system.physmem.wrQLenPdf::24 17648 # What write queue length does an incoming req see
157 system.physmem.wrQLenPdf::25 17630 # What write queue length does an incoming req see
158 system.physmem.wrQLenPdf::26 17636 # What write queue length does an incoming req see
159 system.physmem.wrQLenPdf::27 17729 # What write queue length does an incoming req see
160 system.physmem.wrQLenPdf::28 17645 # What write queue length does an incoming req see
161 system.physmem.wrQLenPdf::29 17645 # What write queue length does an incoming req see
162 system.physmem.wrQLenPdf::30 17825 # What write queue length does an incoming req see
163 system.physmem.wrQLenPdf::31 17527 # What write queue length does an incoming req see
164 system.physmem.wrQLenPdf::32 17476 # What write queue length does an incoming req see
165 system.physmem.wrQLenPdf::33 34 # What write queue length does an incoming req see
166 system.physmem.wrQLenPdf::34 22 # What write queue length does an incoming req see
167 system.physmem.wrQLenPdf::35 16 # What write queue length does an incoming req see
168 system.physmem.wrQLenPdf::36 17 # What write queue length does an incoming req see
169 system.physmem.wrQLenPdf::37 13 # What write queue length does an incoming req see
170 system.physmem.wrQLenPdf::38 8 # What write queue length does an incoming req see
171 system.physmem.wrQLenPdf::39 5 # What write queue length does an incoming req see
172 system.physmem.wrQLenPdf::40 6 # What write queue length does an incoming req see
173 system.physmem.wrQLenPdf::41 4 # What write queue length does an incoming req see
174 system.physmem.wrQLenPdf::42 6 # What write queue length does an incoming req see
175 system.physmem.wrQLenPdf::43 5 # What write queue length does an incoming req see
176 system.physmem.wrQLenPdf::44 6 # What write queue length does an incoming req see
177 system.physmem.wrQLenPdf::45 5 # What write queue length does an incoming req see
178 system.physmem.wrQLenPdf::46 4 # What write queue length does an incoming req see
179 system.physmem.wrQLenPdf::47 6 # What write queue length does an incoming req see
180 system.physmem.wrQLenPdf::48 2 # What write queue length does an incoming req see
181 system.physmem.wrQLenPdf::49 4 # What write queue length does an incoming req see
182 system.physmem.wrQLenPdf::50 4 # What write queue length does an incoming req see
183 system.physmem.wrQLenPdf::51 7 # What write queue length does an incoming req see
184 system.physmem.wrQLenPdf::52 5 # What write queue length does an incoming req see
185 system.physmem.wrQLenPdf::53 7 # What write queue length does an incoming req see
186 system.physmem.wrQLenPdf::54 4 # What write queue length does an incoming req see
187 system.physmem.wrQLenPdf::55 2 # What write queue length does an incoming req see
188 system.physmem.wrQLenPdf::56 1 # What write queue length does an incoming req see
189 system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
190 system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
191 system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
192 system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
193 system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
194 system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
195 system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
196 system.physmem.bytesPerActivate::samples 147449 # Bytes accessed per row activation
197 system.physmem.bytesPerActivate::mean 295.402912 # Bytes accessed per row activation
198 system.physmem.bytesPerActivate::gmean 174.387317 # Bytes accessed per row activation
199 system.physmem.bytesPerActivate::stdev 322.474139 # Bytes accessed per row activation
200 system.physmem.bytesPerActivate::0-127 54872 37.21% 37.21% # Bytes accessed per row activation
201 system.physmem.bytesPerActivate::128-255 39881 27.05% 64.26% # Bytes accessed per row activation
202 system.physmem.bytesPerActivate::256-383 13729 9.31% 73.57% # Bytes accessed per row activation
203 system.physmem.bytesPerActivate::384-511 7544 5.12% 78.69% # Bytes accessed per row activation
204 system.physmem.bytesPerActivate::512-639 5538 3.76% 82.44% # Bytes accessed per row activation
205 system.physmem.bytesPerActivate::640-767 3897 2.64% 85.09% # Bytes accessed per row activation
206 system.physmem.bytesPerActivate::768-895 3110 2.11% 87.20% # Bytes accessed per row activation
207 system.physmem.bytesPerActivate::896-1023 2694 1.83% 89.02% # Bytes accessed per row activation
208 system.physmem.bytesPerActivate::1024-1151 16184 10.98% 100.00% # Bytes accessed per row activation
209 system.physmem.bytesPerActivate::total 147449 # Bytes accessed per row activation
210 system.physmem.rdPerTurnAround::samples 17448 # Reads before turning the bus around for writes
211 system.physmem.rdPerTurnAround::mean 22.155834 # Reads before turning the bus around for writes
212 system.physmem.rdPerTurnAround::stdev 209.387263 # Reads before turning the bus around for writes
213 system.physmem.rdPerTurnAround::0-1023 17435 99.93% 99.93% # Reads before turning the bus around for writes
214 system.physmem.rdPerTurnAround::1024-2047 8 0.05% 99.97% # Reads before turning the bus around for writes
215 system.physmem.rdPerTurnAround::2048-3071 3 0.02% 99.99% # Reads before turning the bus around for writes
216 system.physmem.rdPerTurnAround::3072-4095 1 0.01% 99.99% # Reads before turning the bus around for writes
217 system.physmem.rdPerTurnAround::26624-27647 1 0.01% 100.00% # Reads before turning the bus around for writes
218 system.physmem.rdPerTurnAround::total 17448 # Reads before turning the bus around for writes
219 system.physmem.wrPerTurnAround::samples 17448 # Writes before turning the bus around for reads
220 system.physmem.wrPerTurnAround::mean 16.850986 # Writes before turning the bus around for reads
221 system.physmem.wrPerTurnAround::gmean 16.777295 # Writes before turning the bus around for reads
222 system.physmem.wrPerTurnAround::stdev 2.658929 # Writes before turning the bus around for reads
223 system.physmem.wrPerTurnAround::16-19 17245 98.84% 98.84% # Writes before turning the bus around for reads
224 system.physmem.wrPerTurnAround::20-23 147 0.84% 99.68% # Writes before turning the bus around for reads
225 system.physmem.wrPerTurnAround::24-27 24 0.14% 99.82% # Writes before turning the bus around for reads
226 system.physmem.wrPerTurnAround::28-31 10 0.06% 99.87% # Writes before turning the bus around for reads
227 system.physmem.wrPerTurnAround::32-35 5 0.03% 99.90% # Writes before turning the bus around for reads
228 system.physmem.wrPerTurnAround::40-43 3 0.02% 99.92% # Writes before turning the bus around for reads
229 system.physmem.wrPerTurnAround::44-47 3 0.02% 99.94% # Writes before turning the bus around for reads
230 system.physmem.wrPerTurnAround::48-51 1 0.01% 99.94% # Writes before turning the bus around for reads
231 system.physmem.wrPerTurnAround::64-67 1 0.01% 99.95% # Writes before turning the bus around for reads
232 system.physmem.wrPerTurnAround::68-71 1 0.01% 99.95% # Writes before turning the bus around for reads
233 system.physmem.wrPerTurnAround::72-75 1 0.01% 99.96% # Writes before turning the bus around for reads
234 system.physmem.wrPerTurnAround::76-79 1 0.01% 99.97% # Writes before turning the bus around for reads
235 system.physmem.wrPerTurnAround::80-83 2 0.01% 99.98% # Writes before turning the bus around for reads
236 system.physmem.wrPerTurnAround::88-91 1 0.01% 99.98% # Writes before turning the bus around for reads
237 system.physmem.wrPerTurnAround::104-107 1 0.01% 99.99% # Writes before turning the bus around for reads
238 system.physmem.wrPerTurnAround::128-131 1 0.01% 99.99% # Writes before turning the bus around for reads
239 system.physmem.wrPerTurnAround::236-239 1 0.01% 100.00% # Writes before turning the bus around for reads
240 system.physmem.wrPerTurnAround::total 17448 # Writes before turning the bus around for reads
241 system.physmem.totQLat 4282714250 # Total ticks spent queuing
242 system.physmem.totMemAccLat 11531033000 # Total ticks spent from burst creation until serviced by the DRAM
243 system.physmem.totBusLat 1932885000 # Total ticks spent in databus transfers
244 system.physmem.avgQLat 11078.55 # Average queueing delay per DRAM burst
245 system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
246 system.physmem.avgMemAccLat 29828.55 # Average memory access latency per DRAM burst
247 system.physmem.avgRdBW 59.19 # Average DRAM read bandwidth in MiByte/s
248 system.physmem.avgWrBW 45.02 # Average achieved write bandwidth in MiByte/s
249 system.physmem.avgRdBWSys 59.24 # Average system read bandwidth in MiByte/s
250 system.physmem.avgWrBWSys 45.02 # Average system write bandwidth in MiByte/s
251 system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
252 system.physmem.busUtil 0.81 # Data bus utilization in percentage
253 system.physmem.busUtilRead 0.46 # Data bus utilization in percentage for reads
254 system.physmem.busUtilWrite 0.35 # Data bus utilization in percentage for writes
255 system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing
256 system.physmem.avgWrQLen 21.74 # Average write queue length when enqueuing
257 system.physmem.readRowHits 318033 # Number of row buffer hits during reads
258 system.physmem.writeRowHits 215097 # Number of row buffer hits during writes
259 system.physmem.readRowHitRate 82.27 # Row buffer hit rate for reads
260 system.physmem.writeRowHitRate 73.15 # Row buffer hit rate for writes
261 system.physmem.avgGap 613828.88 # Average gap between requests
262 system.physmem.pageHitRate 78.33 # Row buffer hit rate, read and write combined
263 system.physmem_0.actEnergy 567967680 # Energy for activate commands per rank (pJ)
264 system.physmem_0.preEnergy 309903000 # Energy for precharge commands per rank (pJ)
265 system.physmem_0.readEnergy 1526584800 # Energy for read commands per rank (pJ)
266 system.physmem_0.writeEnergy 976607280 # Energy for write commands per rank (pJ)
267 system.physmem_0.refreshEnergy 27301026480 # Energy for refresh commands per rank (pJ)
268 system.physmem_0.actBackEnergy 63862686000 # Energy for active background per rank (pJ)
269 system.physmem_0.preBackEnergy 194773803000 # Energy for precharge background per rank (pJ)
270 system.physmem_0.totalEnergy 289318578240 # Total energy per rank (pJ)
271 system.physmem_0.averagePower 692.167087 # Core power per rank (mW)
272 system.physmem_0.memoryStateTime::IDLE 323459791500 # Time in different power states
273 system.physmem_0.memoryStateTime::REF 13957580000 # Time in different power states
274 system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
275 system.physmem_0.memoryStateTime::ACT 80574068000 # Time in different power states
276 system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
277 system.physmem_1.actEnergy 546278040 # Energy for activate commands per rank (pJ)
278 system.physmem_1.preEnergy 298068375 # Energy for precharge commands per rank (pJ)
279 system.physmem_1.readEnergy 1488138600 # Energy for read commands per rank (pJ)
280 system.physmem_1.writeEnergy 928098000 # Energy for write commands per rank (pJ)
281 system.physmem_1.refreshEnergy 27301026480 # Energy for refresh commands per rank (pJ)
282 system.physmem_1.actBackEnergy 61813739205 # Energy for active background per rank (pJ)
283 system.physmem_1.preBackEnergy 196571124750 # Energy for precharge background per rank (pJ)
284 system.physmem_1.totalEnergy 288946473450 # Total energy per rank (pJ)
285 system.physmem_1.averagePower 691.276862 # Core power per rank (mW)
286 system.physmem_1.memoryStateTime::IDLE 326467583000 # Time in different power states
287 system.physmem_1.memoryStateTime::REF 13957580000 # Time in different power states
288 system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
289 system.physmem_1.memoryStateTime::ACT 77566206500 # Time in different power states
290 system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
291 system.cpu.branchPred.lookups 230262495 # Number of BP lookups
292 system.cpu.branchPred.condPredicted 230262495 # Number of conditional branches predicted
293 system.cpu.branchPred.condIncorrect 9742888 # Number of conditional branches incorrect
294 system.cpu.branchPred.BTBLookups 131521089 # Number of BTB lookups
295 system.cpu.branchPred.BTBHits 128797905 # Number of BTB hits
296 system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
297 system.cpu.branchPred.BTBHitPct 97.929470 # BTB Hit Percentage
298 system.cpu.branchPred.usedRAS 27751403 # Number of times the RAS was used to get a target.
299 system.cpu.branchPred.RASInCorrect 1472504 # Number of incorrect RAS predictions.
300 system.cpu_clk_domain.clock 500 # Clock period in ticks
301 system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
302 system.cpu.workload.num_syscalls 551 # Number of system calls
303 system.cpu.numCycles 835992044 # number of cpu cycles simulated
304 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
305 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
306 system.cpu.fetch.icacheStallCycles 185232757 # Number of cycles fetch is stalled on an Icache miss
307 system.cpu.fetch.Insts 1269385486 # Number of instructions fetch has processed
308 system.cpu.fetch.Branches 230262495 # Number of branches that fetch encountered
309 system.cpu.fetch.predictedBranches 156549308 # Number of branches that fetch has predicted taken
310 system.cpu.fetch.Cycles 639500926 # Number of cycles fetch has run and was not squashing or blocked
311 system.cpu.fetch.SquashCycles 20224879 # Number of cycles fetch has spent squashing
312 system.cpu.fetch.TlbCycles 485 # Number of cycles fetch has spent waiting for tlb
313 system.cpu.fetch.MiscStallCycles 100878 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
314 system.cpu.fetch.PendingTrapStallCycles 834249 # Number of stall cycles due to pending traps
315 system.cpu.fetch.PendingQuiesceStallCycles 1640 # Number of stall cycles due to pending quiesce instructions
316 system.cpu.fetch.IcacheWaitRetryStallCycles 42 # Number of stall cycles due to full MSHR
317 system.cpu.fetch.CacheLines 179526470 # Number of cache lines fetched
318 system.cpu.fetch.IcacheSquashes 2741098 # Number of outstanding Icache misses that were squashed
319 system.cpu.fetch.ItlbSquashes 7 # Number of outstanding ITLB misses that were squashed
320 system.cpu.fetch.rateDist::samples 835783416 # Number of instructions fetched each cycle (Total)
321 system.cpu.fetch.rateDist::mean 2.825648 # Number of instructions fetched each cycle (Total)
322 system.cpu.fetch.rateDist::stdev 3.381813 # Number of instructions fetched each cycle (Total)
323 system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
324 system.cpu.fetch.rateDist::0 428043161 51.21% 51.21% # Number of instructions fetched each cycle (Total)
325 system.cpu.fetch.rateDist::1 33828750 4.05% 55.26% # Number of instructions fetched each cycle (Total)
326 system.cpu.fetch.rateDist::2 32944896 3.94% 59.20% # Number of instructions fetched each cycle (Total)
327 system.cpu.fetch.rateDist::3 33232373 3.98% 63.18% # Number of instructions fetched each cycle (Total)
328 system.cpu.fetch.rateDist::4 27262474 3.26% 66.44% # Number of instructions fetched each cycle (Total)
329 system.cpu.fetch.rateDist::5 27644327 3.31% 69.75% # Number of instructions fetched each cycle (Total)
330 system.cpu.fetch.rateDist::6 36950250 4.42% 74.17% # Number of instructions fetched each cycle (Total)
331 system.cpu.fetch.rateDist::7 33776724 4.04% 78.21% # Number of instructions fetched each cycle (Total)
332 system.cpu.fetch.rateDist::8 182100461 21.79% 100.00% # Number of instructions fetched each cycle (Total)
333 system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
334 system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
335 system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
336 system.cpu.fetch.rateDist::total 835783416 # Number of instructions fetched each cycle (Total)
337 system.cpu.fetch.branchRate 0.275436 # Number of branch fetches per cycle
338 system.cpu.fetch.rate 1.518418 # Number of inst fetches per cycle
339 system.cpu.decode.IdleCycles 127710765 # Number of cycles decode is idle
340 system.cpu.decode.BlockedCycles 376117098 # Number of cycles decode is blocked
341 system.cpu.decode.RunCycles 240273770 # Number of cycles decode is running
342 system.cpu.decode.UnblockCycles 81569344 # Number of cycles decode is unblocking
343 system.cpu.decode.SquashCycles 10112439 # Number of cycles decode is squashing
344 system.cpu.decode.DecodedInsts 2225700133 # Number of instructions handled by decode
345 system.cpu.rename.SquashCycles 10112439 # Number of cycles rename is squashing
346 system.cpu.rename.IdleCycles 159685424 # Number of cycles rename is idle
347 system.cpu.rename.BlockCycles 160601450 # Number of cycles rename is blocking
348 system.cpu.rename.serializeStallCycles 42674 # count of cycles rename stalled for serializing inst
349 system.cpu.rename.RunCycles 285796855 # Number of cycles rename is running
350 system.cpu.rename.UnblockCycles 219544574 # Number of cycles rename is unblocking
351 system.cpu.rename.RenamedInsts 2175664077 # Number of instructions processed by rename
352 system.cpu.rename.ROBFullEvents 185857 # Number of times rename has blocked due to ROB full
353 system.cpu.rename.IQFullEvents 136149821 # Number of times rename has blocked due to IQ full
354 system.cpu.rename.LQFullEvents 24262583 # Number of times rename has blocked due to LQ full
355 system.cpu.rename.SQFullEvents 49140413 # Number of times rename has blocked due to SQ full
356 system.cpu.rename.RenamedOperands 2279803570 # Number of destination operands rename has renamed
357 system.cpu.rename.RenameLookups 5502723498 # Number of register rename lookups that rename has made
358 system.cpu.rename.int_rename_lookups 3499975195 # Number of integer rename lookups
359 system.cpu.rename.fp_rename_lookups 67752 # Number of floating rename lookups
360 system.cpu.rename.CommittedMaps 1614040854 # Number of HB maps that are committed
361 system.cpu.rename.UndoneMaps 665762716 # Number of HB maps that are undone due to squashing
362 system.cpu.rename.serializingInsts 3202 # count of serializing insts renamed
363 system.cpu.rename.tempSerializingInsts 3008 # count of temporary serializing insts renamed
364 system.cpu.rename.skidInsts 414696821 # count of insts added to the skid buffer
365 system.cpu.memDep0.insertedLoads 528426075 # Number of loads inserted to the mem dependence unit.
366 system.cpu.memDep0.insertedStores 209872279 # Number of stores inserted to the mem dependence unit.
367 system.cpu.memDep0.conflictingLoads 239265917 # Number of conflicting loads.
368 system.cpu.memDep0.conflictingStores 72168406 # Number of conflicting stores.
369 system.cpu.iq.iqInstsAdded 2101339198 # Number of instructions added to the IQ (excludes non-spec)
370 system.cpu.iq.iqNonSpecInstsAdded 25266 # Number of non-speculative instructions added to the IQ
371 system.cpu.iq.iqInstsIssued 1827025844 # Number of instructions issued
372 system.cpu.iq.iqSquashedInstsIssued 429417 # Number of squashed instructions issued
373 system.cpu.iq.iqSquashedInstsExamined 572375763 # Number of squashed instructions iterated over during squash; mainly for profiling
374 system.cpu.iq.iqSquashedOperandsExamined 974716036 # Number of squashed operands that are examined and possibly removed from graph
375 system.cpu.iq.iqSquashedNonSpecRemoved 24714 # Number of squashed non-spec instructions that were removed
376 system.cpu.iq.issued_per_cycle::samples 835783416 # Number of insts issued each cycle
377 system.cpu.iq.issued_per_cycle::mean 2.186004 # Number of insts issued each cycle
378 system.cpu.iq.issued_per_cycle::stdev 2.072692 # Number of insts issued each cycle
379 system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
380 system.cpu.iq.issued_per_cycle::0 256113706 30.64% 30.64% # Number of insts issued each cycle
381 system.cpu.iq.issued_per_cycle::1 125601677 15.03% 45.67% # Number of insts issued each cycle
382 system.cpu.iq.issued_per_cycle::2 119268677 14.27% 59.94% # Number of insts issued each cycle
383 system.cpu.iq.issued_per_cycle::3 111065913 13.29% 73.23% # Number of insts issued each cycle
384 system.cpu.iq.issued_per_cycle::4 92467369 11.06% 84.29% # Number of insts issued each cycle
385 system.cpu.iq.issued_per_cycle::5 61706105 7.38% 91.68% # Number of insts issued each cycle
386 system.cpu.iq.issued_per_cycle::6 43038473 5.15% 96.83% # Number of insts issued each cycle
387 system.cpu.iq.issued_per_cycle::7 19113733 2.29% 99.11% # Number of insts issued each cycle
388 system.cpu.iq.issued_per_cycle::8 7407763 0.89% 100.00% # Number of insts issued each cycle
389 system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
390 system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
391 system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
392 system.cpu.iq.issued_per_cycle::total 835783416 # Number of insts issued each cycle
393 system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
394 system.cpu.iq.fu_full::IntAlu 11312018 42.37% 42.37% # attempts to use FU when none available
395 system.cpu.iq.fu_full::IntMult 0 0.00% 42.37% # attempts to use FU when none available
396 system.cpu.iq.fu_full::IntDiv 0 0.00% 42.37% # attempts to use FU when none available
397 system.cpu.iq.fu_full::FloatAdd 0 0.00% 42.37% # attempts to use FU when none available
398 system.cpu.iq.fu_full::FloatCmp 0 0.00% 42.37% # attempts to use FU when none available
399 system.cpu.iq.fu_full::FloatCvt 0 0.00% 42.37% # attempts to use FU when none available
400 system.cpu.iq.fu_full::FloatMult 0 0.00% 42.37% # attempts to use FU when none available
401 system.cpu.iq.fu_full::FloatDiv 0 0.00% 42.37% # attempts to use FU when none available
402 system.cpu.iq.fu_full::FloatSqrt 0 0.00% 42.37% # attempts to use FU when none available
403 system.cpu.iq.fu_full::SimdAdd 0 0.00% 42.37% # attempts to use FU when none available
404 system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 42.37% # attempts to use FU when none available
405 system.cpu.iq.fu_full::SimdAlu 0 0.00% 42.37% # attempts to use FU when none available
406 system.cpu.iq.fu_full::SimdCmp 0 0.00% 42.37% # attempts to use FU when none available
407 system.cpu.iq.fu_full::SimdCvt 0 0.00% 42.37% # attempts to use FU when none available
408 system.cpu.iq.fu_full::SimdMisc 0 0.00% 42.37% # attempts to use FU when none available
409 system.cpu.iq.fu_full::SimdMult 0 0.00% 42.37% # attempts to use FU when none available
410 system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 42.37% # attempts to use FU when none available
411 system.cpu.iq.fu_full::SimdShift 0 0.00% 42.37% # attempts to use FU when none available
412 system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 42.37% # attempts to use FU when none available
413 system.cpu.iq.fu_full::SimdSqrt 0 0.00% 42.37% # attempts to use FU when none available
414 system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 42.37% # attempts to use FU when none available
415 system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 42.37% # attempts to use FU when none available
416 system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 42.37% # attempts to use FU when none available
417 system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 42.37% # attempts to use FU when none available
418 system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 42.37% # attempts to use FU when none available
419 system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 42.37% # attempts to use FU when none available
420 system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 42.37% # attempts to use FU when none available
421 system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 42.37% # attempts to use FU when none available
422 system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 42.37% # attempts to use FU when none available
423 system.cpu.iq.fu_full::MemRead 12328079 46.18% 88.55% # attempts to use FU when none available
424 system.cpu.iq.fu_full::MemWrite 3055344 11.45% 100.00% # attempts to use FU when none available
425 system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
426 system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
427 system.cpu.iq.FU_type_0::No_OpClass 2717945 0.15% 0.15% # Type of FU issued
428 system.cpu.iq.FU_type_0::IntAlu 1211291441 66.30% 66.45% # Type of FU issued
429 system.cpu.iq.FU_type_0::IntMult 390219 0.02% 66.47% # Type of FU issued
430 system.cpu.iq.FU_type_0::IntDiv 3881058 0.21% 66.68% # Type of FU issued
431 system.cpu.iq.FU_type_0::FloatAdd 119 0.00% 66.68% # Type of FU issued
432 system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.68% # Type of FU issued
433 system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.68% # Type of FU issued
434 system.cpu.iq.FU_type_0::FloatMult 36 0.00% 66.68% # Type of FU issued
435 system.cpu.iq.FU_type_0::FloatDiv 409 0.00% 66.68% # Type of FU issued
436 system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.68% # Type of FU issued
437 system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.68% # Type of FU issued
438 system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.68% # Type of FU issued
439 system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.68% # Type of FU issued
440 system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.68% # Type of FU issued
441 system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.68% # Type of FU issued
442 system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.68% # Type of FU issued
443 system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.68% # Type of FU issued
444 system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.68% # Type of FU issued
445 system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.68% # Type of FU issued
446 system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.68% # Type of FU issued
447 system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.68% # Type of FU issued
448 system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.68% # Type of FU issued
449 system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.68% # Type of FU issued
450 system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.68% # Type of FU issued
451 system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.68% # Type of FU issued
452 system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.68% # Type of FU issued
453 system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.68% # Type of FU issued
454 system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.68% # Type of FU issued
455 system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.68% # Type of FU issued
456 system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.68% # Type of FU issued
457 system.cpu.iq.FU_type_0::MemRead 435052343 23.81% 90.49% # Type of FU issued
458 system.cpu.iq.FU_type_0::MemWrite 173692274 9.51% 100.00% # Type of FU issued
459 system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
460 system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
461 system.cpu.iq.FU_type_0::total 1827025844 # Type of FU issued
462 system.cpu.iq.rate 2.185458 # Inst issue rate
463 system.cpu.iq.fu_busy_cnt 26695441 # FU busy when requested
464 system.cpu.iq.fu_busy_rate 0.014611 # FU busy rate (busy events/executed inst)
465 system.cpu.iq.int_inst_queue_reads 4516927324 # Number of integer instruction queue reads
466 system.cpu.iq.int_inst_queue_writes 2674001021 # Number of integer instruction queue writes
467 system.cpu.iq.int_inst_queue_wakeup_accesses 1796885315 # Number of integer instruction queue wakeup accesses
468 system.cpu.iq.fp_inst_queue_reads 32638 # Number of floating instruction queue reads
469 system.cpu.iq.fp_inst_queue_writes 71794 # Number of floating instruction queue writes
470 system.cpu.iq.fp_inst_queue_wakeup_accesses 7253 # Number of floating instruction queue wakeup accesses
471 system.cpu.iq.int_alu_accesses 1850988135 # Number of integer alu accesses
472 system.cpu.iq.fp_alu_accesses 15205 # Number of floating point alu accesses
473 system.cpu.iew.lsq.thread0.forwLoads 185719617 # Number of loads that had data forwarded from stores
474 system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
475 system.cpu.iew.lsq.thread0.squashedLoads 144326663 # Number of loads squashed
476 system.cpu.iew.lsq.thread0.ignoredResponses 210089 # Number of memory responses ignored because the instruction is squashed
477 system.cpu.iew.lsq.thread0.memOrderViolation 386690 # Number of memory ordering violations
478 system.cpu.iew.lsq.thread0.squashedStores 60712093 # Number of stores squashed
479 system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
480 system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
481 system.cpu.iew.lsq.thread0.rescheduledLoads 19150 # Number of loads that were rescheduled
482 system.cpu.iew.lsq.thread0.cacheBlocked 1058 # Number of times an access to memory failed due to the cache being blocked
483 system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
484 system.cpu.iew.iewSquashCycles 10112439 # Number of cycles IEW is squashing
485 system.cpu.iew.iewBlockCycles 107482997 # Number of cycles IEW is blocking
486 system.cpu.iew.iewUnblockCycles 6407343 # Number of cycles IEW is unblocking
487 system.cpu.iew.iewDispatchedInsts 2101364464 # Number of instructions dispatched to IQ
488 system.cpu.iew.iewDispSquashedInsts 396756 # Number of squashed instructions skipped by dispatch
489 system.cpu.iew.iewDispLoadInsts 528428820 # Number of dispatched load instructions
490 system.cpu.iew.iewDispStoreInsts 209872279 # Number of dispatched store instructions
491 system.cpu.iew.iewDispNonSpecInsts 7401 # Number of dispatched non-speculative instructions
492 system.cpu.iew.iewIQFullEvents 1872023 # Number of times the IQ has become full, causing a stall
493 system.cpu.iew.iewLSQFullEvents 3639843 # Number of times the LSQ has become full, causing a stall
494 system.cpu.iew.memOrderViolationEvents 386690 # Number of memory order violations
495 system.cpu.iew.predictedTakenIncorrect 5742846 # Number of branches that were predicted taken incorrectly
496 system.cpu.iew.predictedNotTakenIncorrect 4583278 # Number of branches that were predicted not taken incorrectly
497 system.cpu.iew.branchMispredicts 10326124 # Number of branch mispredicts detected at execute
498 system.cpu.iew.iewExecutedInsts 1805593119 # Number of executed instructions
499 system.cpu.iew.iewExecLoadInsts 428868135 # Number of load instructions executed
500 system.cpu.iew.iewExecSquashedInsts 21432725 # Number of squashed instructions skipped in execute
501 system.cpu.iew.exec_swp 0 # number of swp insts executed
502 system.cpu.iew.exec_nop 0 # number of nop insts executed
503 system.cpu.iew.exec_refs 598999412 # number of memory reference insts executed
504 system.cpu.iew.exec_branches 171793179 # Number of branches executed
505 system.cpu.iew.exec_stores 170131277 # Number of stores executed
506 system.cpu.iew.exec_rate 2.159821 # Inst execution rate
507 system.cpu.iew.wb_sent 1802187162 # cumulative count of insts sent to commit
508 system.cpu.iew.wb_count 1796892568 # cumulative count of insts written-back
509 system.cpu.iew.wb_producers 1367992688 # num instructions producing a value
510 system.cpu.iew.wb_consumers 2090178306 # num instructions consuming a value
511 system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
512 system.cpu.iew.wb_rate 2.149413 # insts written-back per cycle
513 system.cpu.iew.wb_fanout 0.654486 # average fanout of values written-back
514 system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
515 system.cpu.commit.commitSquashedInsts 572454923 # The number of squashed insts skipped by commit
516 system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards
517 system.cpu.commit.branchMispredicts 9832210 # The number of times a branch was mispredicted
518 system.cpu.commit.committed_per_cycle::samples 758082487 # Number of insts commited each cycle
519 system.cpu.commit.committed_per_cycle::mean 2.016916 # Number of insts commited each cycle
520 system.cpu.commit.committed_per_cycle::stdev 2.546878 # Number of insts commited each cycle
521 system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
522 system.cpu.commit.committed_per_cycle::0 289327383 38.17% 38.17% # Number of insts commited each cycle
523 system.cpu.commit.committed_per_cycle::1 175257093 23.12% 61.28% # Number of insts commited each cycle
524 system.cpu.commit.committed_per_cycle::2 57420140 7.57% 68.86% # Number of insts commited each cycle
525 system.cpu.commit.committed_per_cycle::3 86252758 11.38% 80.24% # Number of insts commited each cycle
526 system.cpu.commit.committed_per_cycle::4 27155131 3.58% 83.82% # Number of insts commited each cycle
527 system.cpu.commit.committed_per_cycle::5 27117110 3.58% 87.40% # Number of insts commited each cycle
528 system.cpu.commit.committed_per_cycle::6 9822533 1.30% 88.69% # Number of insts commited each cycle
529 system.cpu.commit.committed_per_cycle::7 8850930 1.17% 89.86% # Number of insts commited each cycle
530 system.cpu.commit.committed_per_cycle::8 76879409 10.14% 100.00% # Number of insts commited each cycle
531 system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
532 system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
533 system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
534 system.cpu.commit.committed_per_cycle::total 758082487 # Number of insts commited each cycle
535 system.cpu.commit.committedInsts 826877109 # Number of instructions committed
536 system.cpu.commit.committedOps 1528988701 # Number of ops (including micro ops) committed
537 system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
538 system.cpu.commit.refs 533262343 # Number of memory references committed
539 system.cpu.commit.loads 384102157 # Number of loads committed
540 system.cpu.commit.membars 0 # Number of memory barriers committed
541 system.cpu.commit.branches 149758583 # Number of branches committed
542 system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
543 system.cpu.commit.int_insts 1526605509 # Number of committed integer instructions.
544 system.cpu.commit.function_calls 17673145 # Number of function calls committed.
545 system.cpu.commit.op_class_0::No_OpClass 1819099 0.12% 0.12% # Class of committed instruction
546 system.cpu.commit.op_class_0::IntAlu 989721889 64.73% 64.85% # Class of committed instruction
547 system.cpu.commit.op_class_0::IntMult 306834 0.02% 64.87% # Class of committed instruction
548 system.cpu.commit.op_class_0::IntDiv 3878536 0.25% 65.12% # Class of committed instruction
549 system.cpu.commit.op_class_0::FloatAdd 0 0.00% 65.12% # Class of committed instruction
550 system.cpu.commit.op_class_0::FloatCmp 0 0.00% 65.12% # Class of committed instruction
551 system.cpu.commit.op_class_0::FloatCvt 0 0.00% 65.12% # Class of committed instruction
552 system.cpu.commit.op_class_0::FloatMult 0 0.00% 65.12% # Class of committed instruction
553 system.cpu.commit.op_class_0::FloatDiv 0 0.00% 65.12% # Class of committed instruction
554 system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 65.12% # Class of committed instruction
555 system.cpu.commit.op_class_0::SimdAdd 0 0.00% 65.12% # Class of committed instruction
556 system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 65.12% # Class of committed instruction
557 system.cpu.commit.op_class_0::SimdAlu 0 0.00% 65.12% # Class of committed instruction
558 system.cpu.commit.op_class_0::SimdCmp 0 0.00% 65.12% # Class of committed instruction
559 system.cpu.commit.op_class_0::SimdCvt 0 0.00% 65.12% # Class of committed instruction
560 system.cpu.commit.op_class_0::SimdMisc 0 0.00% 65.12% # Class of committed instruction
561 system.cpu.commit.op_class_0::SimdMult 0 0.00% 65.12% # Class of committed instruction
562 system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 65.12% # Class of committed instruction
563 system.cpu.commit.op_class_0::SimdShift 0 0.00% 65.12% # Class of committed instruction
564 system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 65.12% # Class of committed instruction
565 system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 65.12% # Class of committed instruction
566 system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 65.12% # Class of committed instruction
567 system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 65.12% # Class of committed instruction
568 system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 65.12% # Class of committed instruction
569 system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 65.12% # Class of committed instruction
570 system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 65.12% # Class of committed instruction
571 system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 65.12% # Class of committed instruction
572 system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 65.12% # Class of committed instruction
573 system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.12% # Class of committed instruction
574 system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.12% # Class of committed instruction
575 system.cpu.commit.op_class_0::MemRead 384102157 25.12% 90.24% # Class of committed instruction
576 system.cpu.commit.op_class_0::MemWrite 149160186 9.76% 100.00% # Class of committed instruction
577 system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
578 system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
579 system.cpu.commit.op_class_0::total 1528988701 # Class of committed instruction
580 system.cpu.commit.bw_lim_events 76879409 # number cycles where commit BW limit reached
581 system.cpu.rob.rob_reads 2782646702 # The number of ROB reads
582 system.cpu.rob.rob_writes 4280772798 # The number of ROB writes
583 system.cpu.timesIdled 2318 # Number of times that the entire CPU went into an idle state and unscheduled itself
584 system.cpu.idleCycles 208628 # Total number of cycles that the CPU has spent unscheduled due to idling
585 system.cpu.committedInsts 826877109 # Number of Instructions Simulated
586 system.cpu.committedOps 1528988701 # Number of Ops (including micro ops) Simulated
587 system.cpu.cpi 1.011023 # CPI: Cycles Per Instruction
588 system.cpu.cpi_total 1.011023 # CPI: Total CPI of All Threads
589 system.cpu.ipc 0.989097 # IPC: Instructions Per Cycle
590 system.cpu.ipc_total 0.989097 # IPC: Total IPC of All Threads
591 system.cpu.int_regfile_reads 2762036439 # number of integer regfile reads
592 system.cpu.int_regfile_writes 1465125360 # number of integer regfile writes
593 system.cpu.fp_regfile_reads 7563 # number of floating regfile reads
594 system.cpu.fp_regfile_writes 476 # number of floating regfile writes
595 system.cpu.cc_regfile_reads 600921582 # number of cc regfile reads
596 system.cpu.cc_regfile_writes 409666959 # number of cc regfile writes
597 system.cpu.misc_regfile_reads 990189445 # number of misc regfile reads
598 system.cpu.misc_regfile_writes 1 # number of misc regfile writes
599 system.cpu.dcache.tags.replacements 2534281 # number of replacements
600 system.cpu.dcache.tags.tagsinuse 4087.998981 # Cycle average of tags in use
601 system.cpu.dcache.tags.total_refs 387677401 # Total number of references to valid blocks.
602 system.cpu.dcache.tags.sampled_refs 2538377 # Sample count of references to valid blocks.
603 system.cpu.dcache.tags.avg_refs 152.726487 # Average number of references to valid blocks.
604 system.cpu.dcache.tags.warmup_cycle 1688557250 # Cycle when the warmup percentage was hit.
605 system.cpu.dcache.tags.occ_blocks::cpu.data 4087.998981 # Average occupied blocks per requestor
606 system.cpu.dcache.tags.occ_percent::cpu.data 0.998047 # Average percentage of cache occupancy
607 system.cpu.dcache.tags.occ_percent::total 0.998047 # Average percentage of cache occupancy
608 system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
609 system.cpu.dcache.tags.age_task_id_blocks_1024::0 28 # Occupied blocks per task id
610 system.cpu.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id
611 system.cpu.dcache.tags.age_task_id_blocks_1024::2 873 # Occupied blocks per task id
612 system.cpu.dcache.tags.age_task_id_blocks_1024::3 3167 # Occupied blocks per task id
613 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
614 system.cpu.dcache.tags.tag_accesses 784481905 # Number of tag accesses
615 system.cpu.dcache.tags.data_accesses 784481905 # Number of data accesses
616 system.cpu.dcache.ReadReq_hits::cpu.data 239023256 # number of ReadReq hits
617 system.cpu.dcache.ReadReq_hits::total 239023256 # number of ReadReq hits
618 system.cpu.dcache.WriteReq_hits::cpu.data 148173502 # number of WriteReq hits
619 system.cpu.dcache.WriteReq_hits::total 148173502 # number of WriteReq hits
620 system.cpu.dcache.demand_hits::cpu.data 387196758 # number of demand (read+write) hits
621 system.cpu.dcache.demand_hits::total 387196758 # number of demand (read+write) hits
622 system.cpu.dcache.overall_hits::cpu.data 387196758 # number of overall hits
623 system.cpu.dcache.overall_hits::total 387196758 # number of overall hits
624 system.cpu.dcache.ReadReq_misses::cpu.data 2788306 # number of ReadReq misses
625 system.cpu.dcache.ReadReq_misses::total 2788306 # number of ReadReq misses
626 system.cpu.dcache.WriteReq_misses::cpu.data 986700 # number of WriteReq misses
627 system.cpu.dcache.WriteReq_misses::total 986700 # number of WriteReq misses
628 system.cpu.dcache.demand_misses::cpu.data 3775006 # number of demand (read+write) misses
629 system.cpu.dcache.demand_misses::total 3775006 # number of demand (read+write) misses
630 system.cpu.dcache.overall_misses::cpu.data 3775006 # number of overall misses
631 system.cpu.dcache.overall_misses::total 3775006 # number of overall misses
632 system.cpu.dcache.ReadReq_miss_latency::cpu.data 60089695608 # number of ReadReq miss cycles
633 system.cpu.dcache.ReadReq_miss_latency::total 60089695608 # number of ReadReq miss cycles
634 system.cpu.dcache.WriteReq_miss_latency::cpu.data 31307364104 # number of WriteReq miss cycles
635 system.cpu.dcache.WriteReq_miss_latency::total 31307364104 # number of WriteReq miss cycles
636 system.cpu.dcache.demand_miss_latency::cpu.data 91397059712 # number of demand (read+write) miss cycles
637 system.cpu.dcache.demand_miss_latency::total 91397059712 # number of demand (read+write) miss cycles
638 system.cpu.dcache.overall_miss_latency::cpu.data 91397059712 # number of overall miss cycles
639 system.cpu.dcache.overall_miss_latency::total 91397059712 # number of overall miss cycles
640 system.cpu.dcache.ReadReq_accesses::cpu.data 241811562 # number of ReadReq accesses(hits+misses)
641 system.cpu.dcache.ReadReq_accesses::total 241811562 # number of ReadReq accesses(hits+misses)
642 system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses)
643 system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses)
644 system.cpu.dcache.demand_accesses::cpu.data 390971764 # number of demand (read+write) accesses
645 system.cpu.dcache.demand_accesses::total 390971764 # number of demand (read+write) accesses
646 system.cpu.dcache.overall_accesses::cpu.data 390971764 # number of overall (read+write) accesses
647 system.cpu.dcache.overall_accesses::total 390971764 # number of overall (read+write) accesses
648 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011531 # miss rate for ReadReq accesses
649 system.cpu.dcache.ReadReq_miss_rate::total 0.011531 # miss rate for ReadReq accesses
650 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006615 # miss rate for WriteReq accesses
651 system.cpu.dcache.WriteReq_miss_rate::total 0.006615 # miss rate for WriteReq accesses
652 system.cpu.dcache.demand_miss_rate::cpu.data 0.009655 # miss rate for demand accesses
653 system.cpu.dcache.demand_miss_rate::total 0.009655 # miss rate for demand accesses
654 system.cpu.dcache.overall_miss_rate::cpu.data 0.009655 # miss rate for overall accesses
655 system.cpu.dcache.overall_miss_rate::total 0.009655 # miss rate for overall accesses
656 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21550.610158 # average ReadReq miss latency
657 system.cpu.dcache.ReadReq_avg_miss_latency::total 21550.610158 # average ReadReq miss latency
658 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31729.364654 # average WriteReq miss latency
659 system.cpu.dcache.WriteReq_avg_miss_latency::total 31729.364654 # average WriteReq miss latency
660 system.cpu.dcache.demand_avg_miss_latency::cpu.data 24211.103164 # average overall miss latency
661 system.cpu.dcache.demand_avg_miss_latency::total 24211.103164 # average overall miss latency
662 system.cpu.dcache.overall_avg_miss_latency::cpu.data 24211.103164 # average overall miss latency
663 system.cpu.dcache.overall_avg_miss_latency::total 24211.103164 # average overall miss latency
664 system.cpu.dcache.blocked_cycles::no_mshrs 10735 # number of cycles access was blocked
665 system.cpu.dcache.blocked_cycles::no_targets 46 # number of cycles access was blocked
666 system.cpu.dcache.blocked::no_mshrs 1081 # number of cycles access was blocked
667 system.cpu.dcache.blocked::no_targets 5 # number of cycles access was blocked
668 system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.930620 # average number of cycles each access was blocked
669 system.cpu.dcache.avg_blocked_cycles::no_targets 9.200000 # average number of cycles each access was blocked
670 system.cpu.dcache.fast_writes 0 # number of fast writes performed
671 system.cpu.dcache.cache_copies 0 # number of cache copies performed
672 system.cpu.dcache.writebacks::writebacks 2332980 # number of writebacks
673 system.cpu.dcache.writebacks::total 2332980 # number of writebacks
674 system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1021252 # number of ReadReq MSHR hits
675 system.cpu.dcache.ReadReq_mshr_hits::total 1021252 # number of ReadReq MSHR hits
676 system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18400 # number of WriteReq MSHR hits
677 system.cpu.dcache.WriteReq_mshr_hits::total 18400 # number of WriteReq MSHR hits
678 system.cpu.dcache.demand_mshr_hits::cpu.data 1039652 # number of demand (read+write) MSHR hits
679 system.cpu.dcache.demand_mshr_hits::total 1039652 # number of demand (read+write) MSHR hits
680 system.cpu.dcache.overall_mshr_hits::cpu.data 1039652 # number of overall MSHR hits
681 system.cpu.dcache.overall_mshr_hits::total 1039652 # number of overall MSHR hits
682 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1767054 # number of ReadReq MSHR misses
683 system.cpu.dcache.ReadReq_mshr_misses::total 1767054 # number of ReadReq MSHR misses
684 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 968300 # number of WriteReq MSHR misses
685 system.cpu.dcache.WriteReq_mshr_misses::total 968300 # number of WriteReq MSHR misses
686 system.cpu.dcache.demand_mshr_misses::cpu.data 2735354 # number of demand (read+write) MSHR misses
687 system.cpu.dcache.demand_mshr_misses::total 2735354 # number of demand (read+write) MSHR misses
688 system.cpu.dcache.overall_mshr_misses::cpu.data 2735354 # number of overall MSHR misses
689 system.cpu.dcache.overall_mshr_misses::total 2735354 # number of overall MSHR misses
690 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 32779677502 # number of ReadReq MSHR miss cycles
691 system.cpu.dcache.ReadReq_mshr_miss_latency::total 32779677502 # number of ReadReq MSHR miss cycles
692 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 29519299643 # number of WriteReq MSHR miss cycles
693 system.cpu.dcache.WriteReq_mshr_miss_latency::total 29519299643 # number of WriteReq MSHR miss cycles
694 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 62298977145 # number of demand (read+write) MSHR miss cycles
695 system.cpu.dcache.demand_mshr_miss_latency::total 62298977145 # number of demand (read+write) MSHR miss cycles
696 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 62298977145 # number of overall MSHR miss cycles
697 system.cpu.dcache.overall_mshr_miss_latency::total 62298977145 # number of overall MSHR miss cycles
698 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007308 # mshr miss rate for ReadReq accesses
699 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007308 # mshr miss rate for ReadReq accesses
700 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006492 # mshr miss rate for WriteReq accesses
701 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006492 # mshr miss rate for WriteReq accesses
702 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006996 # mshr miss rate for demand accesses
703 system.cpu.dcache.demand_mshr_miss_rate::total 0.006996 # mshr miss rate for demand accesses
704 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006996 # mshr miss rate for overall accesses
705 system.cpu.dcache.overall_mshr_miss_rate::total 0.006996 # mshr miss rate for overall accesses
706 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18550.467333 # average ReadReq mshr miss latency
707 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18550.467333 # average ReadReq mshr miss latency
708 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30485.696213 # average WriteReq mshr miss latency
709 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30485.696213 # average WriteReq mshr miss latency
710 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22775.471528 # average overall mshr miss latency
711 system.cpu.dcache.demand_avg_mshr_miss_latency::total 22775.471528 # average overall mshr miss latency
712 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22775.471528 # average overall mshr miss latency
713 system.cpu.dcache.overall_avg_mshr_miss_latency::total 22775.471528 # average overall mshr miss latency
714 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
715 system.cpu.icache.tags.replacements 7107 # number of replacements
716 system.cpu.icache.tags.tagsinuse 1054.726418 # Cycle average of tags in use
717 system.cpu.icache.tags.total_refs 179314504 # Total number of references to valid blocks.
718 system.cpu.icache.tags.sampled_refs 8709 # Sample count of references to valid blocks.
719 system.cpu.icache.tags.avg_refs 20589.562981 # Average number of references to valid blocks.
720 system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
721 system.cpu.icache.tags.occ_blocks::cpu.inst 1054.726418 # Average occupied blocks per requestor
722 system.cpu.icache.tags.occ_percent::cpu.inst 0.515003 # Average percentage of cache occupancy
723 system.cpu.icache.tags.occ_percent::total 0.515003 # Average percentage of cache occupancy
724 system.cpu.icache.tags.occ_task_id_blocks::1024 1602 # Occupied blocks per task id
725 system.cpu.icache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id
726 system.cpu.icache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id
727 system.cpu.icache.tags.age_task_id_blocks_1024::2 46 # Occupied blocks per task id
728 system.cpu.icache.tags.age_task_id_blocks_1024::3 330 # Occupied blocks per task id
729 system.cpu.icache.tags.age_task_id_blocks_1024::4 1149 # Occupied blocks per task id
730 system.cpu.icache.tags.occ_task_id_percent::1024 0.782227 # Percentage of cache occupancy per task id
731 system.cpu.icache.tags.tag_accesses 359258778 # Number of tag accesses
732 system.cpu.icache.tags.data_accesses 359258778 # Number of data accesses
733 system.cpu.icache.ReadReq_hits::cpu.inst 179317997 # number of ReadReq hits
734 system.cpu.icache.ReadReq_hits::total 179317997 # number of ReadReq hits
735 system.cpu.icache.demand_hits::cpu.inst 179317997 # number of demand (read+write) hits
736 system.cpu.icache.demand_hits::total 179317997 # number of demand (read+write) hits
737 system.cpu.icache.overall_hits::cpu.inst 179317997 # number of overall hits
738 system.cpu.icache.overall_hits::total 179317997 # number of overall hits
739 system.cpu.icache.ReadReq_misses::cpu.inst 208472 # number of ReadReq misses
740 system.cpu.icache.ReadReq_misses::total 208472 # number of ReadReq misses
741 system.cpu.icache.demand_misses::cpu.inst 208472 # number of demand (read+write) misses
742 system.cpu.icache.demand_misses::total 208472 # number of demand (read+write) misses
743 system.cpu.icache.overall_misses::cpu.inst 208472 # number of overall misses
744 system.cpu.icache.overall_misses::total 208472 # number of overall misses
745 system.cpu.icache.ReadReq_miss_latency::cpu.inst 1336227738 # number of ReadReq miss cycles
746 system.cpu.icache.ReadReq_miss_latency::total 1336227738 # number of ReadReq miss cycles
747 system.cpu.icache.demand_miss_latency::cpu.inst 1336227738 # number of demand (read+write) miss cycles
748 system.cpu.icache.demand_miss_latency::total 1336227738 # number of demand (read+write) miss cycles
749 system.cpu.icache.overall_miss_latency::cpu.inst 1336227738 # number of overall miss cycles
750 system.cpu.icache.overall_miss_latency::total 1336227738 # number of overall miss cycles
751 system.cpu.icache.ReadReq_accesses::cpu.inst 179526469 # number of ReadReq accesses(hits+misses)
752 system.cpu.icache.ReadReq_accesses::total 179526469 # number of ReadReq accesses(hits+misses)
753 system.cpu.icache.demand_accesses::cpu.inst 179526469 # number of demand (read+write) accesses
754 system.cpu.icache.demand_accesses::total 179526469 # number of demand (read+write) accesses
755 system.cpu.icache.overall_accesses::cpu.inst 179526469 # number of overall (read+write) accesses
756 system.cpu.icache.overall_accesses::total 179526469 # number of overall (read+write) accesses
757 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001161 # miss rate for ReadReq accesses
758 system.cpu.icache.ReadReq_miss_rate::total 0.001161 # miss rate for ReadReq accesses
759 system.cpu.icache.demand_miss_rate::cpu.inst 0.001161 # miss rate for demand accesses
760 system.cpu.icache.demand_miss_rate::total 0.001161 # miss rate for demand accesses
761 system.cpu.icache.overall_miss_rate::cpu.inst 0.001161 # miss rate for overall accesses
762 system.cpu.icache.overall_miss_rate::total 0.001161 # miss rate for overall accesses
763 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6409.626895 # average ReadReq miss latency
764 system.cpu.icache.ReadReq_avg_miss_latency::total 6409.626895 # average ReadReq miss latency
765 system.cpu.icache.demand_avg_miss_latency::cpu.inst 6409.626895 # average overall miss latency
766 system.cpu.icache.demand_avg_miss_latency::total 6409.626895 # average overall miss latency
767 system.cpu.icache.overall_avg_miss_latency::cpu.inst 6409.626895 # average overall miss latency
768 system.cpu.icache.overall_avg_miss_latency::total 6409.626895 # average overall miss latency
769 system.cpu.icache.blocked_cycles::no_mshrs 1217 # number of cycles access was blocked
770 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
771 system.cpu.icache.blocked::no_mshrs 15 # number of cycles access was blocked
772 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
773 system.cpu.icache.avg_blocked_cycles::no_mshrs 81.133333 # average number of cycles each access was blocked
774 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
775 system.cpu.icache.fast_writes 0 # number of fast writes performed
776 system.cpu.icache.cache_copies 0 # number of cache copies performed
777 system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2630 # number of ReadReq MSHR hits
778 system.cpu.icache.ReadReq_mshr_hits::total 2630 # number of ReadReq MSHR hits
779 system.cpu.icache.demand_mshr_hits::cpu.inst 2630 # number of demand (read+write) MSHR hits
780 system.cpu.icache.demand_mshr_hits::total 2630 # number of demand (read+write) MSHR hits
781 system.cpu.icache.overall_mshr_hits::cpu.inst 2630 # number of overall MSHR hits
782 system.cpu.icache.overall_mshr_hits::total 2630 # number of overall MSHR hits
783 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 205842 # number of ReadReq MSHR misses
784 system.cpu.icache.ReadReq_mshr_misses::total 205842 # number of ReadReq MSHR misses
785 system.cpu.icache.demand_mshr_misses::cpu.inst 205842 # number of demand (read+write) MSHR misses
786 system.cpu.icache.demand_mshr_misses::total 205842 # number of demand (read+write) MSHR misses
787 system.cpu.icache.overall_mshr_misses::cpu.inst 205842 # number of overall MSHR misses
788 system.cpu.icache.overall_mshr_misses::total 205842 # number of overall MSHR misses
789 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 900667759 # number of ReadReq MSHR miss cycles
790 system.cpu.icache.ReadReq_mshr_miss_latency::total 900667759 # number of ReadReq MSHR miss cycles
791 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 900667759 # number of demand (read+write) MSHR miss cycles
792 system.cpu.icache.demand_mshr_miss_latency::total 900667759 # number of demand (read+write) MSHR miss cycles
793 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 900667759 # number of overall MSHR miss cycles
794 system.cpu.icache.overall_mshr_miss_latency::total 900667759 # number of overall MSHR miss cycles
795 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001147 # mshr miss rate for ReadReq accesses
796 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001147 # mshr miss rate for ReadReq accesses
797 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001147 # mshr miss rate for demand accesses
798 system.cpu.icache.demand_mshr_miss_rate::total 0.001147 # mshr miss rate for demand accesses
799 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001147 # mshr miss rate for overall accesses
800 system.cpu.icache.overall_mshr_miss_rate::total 0.001147 # mshr miss rate for overall accesses
801 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 4375.529576 # average ReadReq mshr miss latency
802 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 4375.529576 # average ReadReq mshr miss latency
803 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 4375.529576 # average overall mshr miss latency
804 system.cpu.icache.demand_avg_mshr_miss_latency::total 4375.529576 # average overall mshr miss latency
805 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4375.529576 # average overall mshr miss latency
806 system.cpu.icache.overall_avg_mshr_miss_latency::total 4375.529576 # average overall mshr miss latency
807 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
808 system.cpu.l2cache.tags.replacements 354249 # number of replacements
809 system.cpu.l2cache.tags.tagsinuse 29619.496841 # Cycle average of tags in use
810 system.cpu.l2cache.tags.total_refs 3704141 # Total number of references to valid blocks.
811 system.cpu.l2cache.tags.sampled_refs 386604 # Sample count of references to valid blocks.
812 system.cpu.l2cache.tags.avg_refs 9.581228 # Average number of references to valid blocks.
813 system.cpu.l2cache.tags.warmup_cycle 197893481000 # Cycle when the warmup percentage was hit.
814 system.cpu.l2cache.tags.occ_blocks::writebacks 21082.499774 # Average occupied blocks per requestor
815 system.cpu.l2cache.tags.occ_blocks::cpu.inst 254.372713 # Average occupied blocks per requestor
816 system.cpu.l2cache.tags.occ_blocks::cpu.data 8282.624354 # Average occupied blocks per requestor
817 system.cpu.l2cache.tags.occ_percent::writebacks 0.643387 # Average percentage of cache occupancy
818 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.007763 # Average percentage of cache occupancy
819 system.cpu.l2cache.tags.occ_percent::cpu.data 0.252766 # Average percentage of cache occupancy
820 system.cpu.l2cache.tags.occ_percent::total 0.903915 # Average percentage of cache occupancy
821 system.cpu.l2cache.tags.occ_task_id_blocks::1024 32355 # Occupied blocks per task id
822 system.cpu.l2cache.tags.age_task_id_blocks_1024::0 76 # Occupied blocks per task id
823 system.cpu.l2cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id
824 system.cpu.l2cache.tags.age_task_id_blocks_1024::2 245 # Occupied blocks per task id
825 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 13370 # Occupied blocks per task id
826 system.cpu.l2cache.tags.age_task_id_blocks_1024::4 18660 # Occupied blocks per task id
827 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987396 # Percentage of cache occupancy per task id
828 system.cpu.l2cache.tags.tag_accesses 41777056 # Number of tag accesses
829 system.cpu.l2cache.tags.data_accesses 41777056 # Number of data accesses
830 system.cpu.l2cache.ReadReq_hits::cpu.inst 5192 # number of ReadReq hits
831 system.cpu.l2cache.ReadReq_hits::cpu.data 1590453 # number of ReadReq hits
832 system.cpu.l2cache.ReadReq_hits::total 1595645 # number of ReadReq hits
833 system.cpu.l2cache.Writeback_hits::writebacks 2332980 # number of Writeback hits
834 system.cpu.l2cache.Writeback_hits::total 2332980 # number of Writeback hits
835 system.cpu.l2cache.UpgradeReq_hits::cpu.data 1881 # number of UpgradeReq hits
836 system.cpu.l2cache.UpgradeReq_hits::total 1881 # number of UpgradeReq hits
837 system.cpu.l2cache.ReadExReq_hits::cpu.data 564507 # number of ReadExReq hits
838 system.cpu.l2cache.ReadExReq_hits::total 564507 # number of ReadExReq hits
839 system.cpu.l2cache.demand_hits::cpu.inst 5192 # number of demand (read+write) hits
840 system.cpu.l2cache.demand_hits::cpu.data 2154960 # number of demand (read+write) hits
841 system.cpu.l2cache.demand_hits::total 2160152 # number of demand (read+write) hits
842 system.cpu.l2cache.overall_hits::cpu.inst 5192 # number of overall hits
843 system.cpu.l2cache.overall_hits::cpu.data 2154960 # number of overall hits
844 system.cpu.l2cache.overall_hits::total 2160152 # number of overall hits
845 system.cpu.l2cache.ReadReq_misses::cpu.inst 3552 # number of ReadReq misses
846 system.cpu.l2cache.ReadReq_misses::cpu.data 176400 # number of ReadReq misses
847 system.cpu.l2cache.ReadReq_misses::total 179952 # number of ReadReq misses
848 system.cpu.l2cache.UpgradeReq_misses::cpu.data 195096 # number of UpgradeReq misses
849 system.cpu.l2cache.UpgradeReq_misses::total 195096 # number of UpgradeReq misses
850 system.cpu.l2cache.ReadExReq_misses::cpu.data 207017 # number of ReadExReq misses
851 system.cpu.l2cache.ReadExReq_misses::total 207017 # number of ReadExReq misses
852 system.cpu.l2cache.demand_misses::cpu.inst 3552 # number of demand (read+write) misses
853 system.cpu.l2cache.demand_misses::cpu.data 383417 # number of demand (read+write) misses
854 system.cpu.l2cache.demand_misses::total 386969 # number of demand (read+write) misses
855 system.cpu.l2cache.overall_misses::cpu.inst 3552 # number of overall misses
856 system.cpu.l2cache.overall_misses::cpu.data 383417 # number of overall misses
857 system.cpu.l2cache.overall_misses::total 386969 # number of overall misses
858 system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 294540500 # number of ReadReq miss cycles
859 system.cpu.l2cache.ReadReq_miss_latency::cpu.data 14275679000 # number of ReadReq miss cycles
860 system.cpu.l2cache.ReadReq_miss_latency::total 14570219500 # number of ReadReq miss cycles
861 system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 13220077 # number of UpgradeReq miss cycles
862 system.cpu.l2cache.UpgradeReq_miss_latency::total 13220077 # number of UpgradeReq miss cycles
863 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16430030463 # number of ReadExReq miss cycles
864 system.cpu.l2cache.ReadExReq_miss_latency::total 16430030463 # number of ReadExReq miss cycles
865 system.cpu.l2cache.demand_miss_latency::cpu.inst 294540500 # number of demand (read+write) miss cycles
866 system.cpu.l2cache.demand_miss_latency::cpu.data 30705709463 # number of demand (read+write) miss cycles
867 system.cpu.l2cache.demand_miss_latency::total 31000249963 # number of demand (read+write) miss cycles
868 system.cpu.l2cache.overall_miss_latency::cpu.inst 294540500 # number of overall miss cycles
869 system.cpu.l2cache.overall_miss_latency::cpu.data 30705709463 # number of overall miss cycles
870 system.cpu.l2cache.overall_miss_latency::total 31000249963 # number of overall miss cycles
871 system.cpu.l2cache.ReadReq_accesses::cpu.inst 8744 # number of ReadReq accesses(hits+misses)
872 system.cpu.l2cache.ReadReq_accesses::cpu.data 1766853 # number of ReadReq accesses(hits+misses)
873 system.cpu.l2cache.ReadReq_accesses::total 1775597 # number of ReadReq accesses(hits+misses)
874 system.cpu.l2cache.Writeback_accesses::writebacks 2332980 # number of Writeback accesses(hits+misses)
875 system.cpu.l2cache.Writeback_accesses::total 2332980 # number of Writeback accesses(hits+misses)
876 system.cpu.l2cache.UpgradeReq_accesses::cpu.data 196977 # number of UpgradeReq accesses(hits+misses)
877 system.cpu.l2cache.UpgradeReq_accesses::total 196977 # number of UpgradeReq accesses(hits+misses)
878 system.cpu.l2cache.ReadExReq_accesses::cpu.data 771524 # number of ReadExReq accesses(hits+misses)
879 system.cpu.l2cache.ReadExReq_accesses::total 771524 # number of ReadExReq accesses(hits+misses)
880 system.cpu.l2cache.demand_accesses::cpu.inst 8744 # number of demand (read+write) accesses
881 system.cpu.l2cache.demand_accesses::cpu.data 2538377 # number of demand (read+write) accesses
882 system.cpu.l2cache.demand_accesses::total 2547121 # number of demand (read+write) accesses
883 system.cpu.l2cache.overall_accesses::cpu.inst 8744 # number of overall (read+write) accesses
884 system.cpu.l2cache.overall_accesses::cpu.data 2538377 # number of overall (read+write) accesses
885 system.cpu.l2cache.overall_accesses::total 2547121 # number of overall (read+write) accesses
886 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.406221 # miss rate for ReadReq accesses
887 system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.099839 # miss rate for ReadReq accesses
888 system.cpu.l2cache.ReadReq_miss_rate::total 0.101347 # miss rate for ReadReq accesses
889 system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.990451 # miss rate for UpgradeReq accesses
890 system.cpu.l2cache.UpgradeReq_miss_rate::total 0.990451 # miss rate for UpgradeReq accesses
891 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.268322 # miss rate for ReadExReq accesses
892 system.cpu.l2cache.ReadExReq_miss_rate::total 0.268322 # miss rate for ReadExReq accesses
893 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.406221 # miss rate for demand accesses
894 system.cpu.l2cache.demand_miss_rate::cpu.data 0.151048 # miss rate for demand accesses
895 system.cpu.l2cache.demand_miss_rate::total 0.151924 # miss rate for demand accesses
896 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.406221 # miss rate for overall accesses
897 system.cpu.l2cache.overall_miss_rate::cpu.data 0.151048 # miss rate for overall accesses
898 system.cpu.l2cache.overall_miss_rate::total 0.151924 # miss rate for overall accesses
899 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 82922.438063 # average ReadReq miss latency
900 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 80927.885488 # average ReadReq miss latency
901 system.cpu.l2cache.ReadReq_avg_miss_latency::total 80967.255157 # average ReadReq miss latency
902 system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 67.761907 # average UpgradeReq miss latency
903 system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 67.761907 # average UpgradeReq miss latency
904 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79365.609892 # average ReadExReq miss latency
905 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79365.609892 # average ReadExReq miss latency
906 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82922.438063 # average overall miss latency
907 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80084.371488 # average overall miss latency
908 system.cpu.l2cache.demand_avg_miss_latency::total 80110.422186 # average overall miss latency
909 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82922.438063 # average overall miss latency
910 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80084.371488 # average overall miss latency
911 system.cpu.l2cache.overall_avg_miss_latency::total 80110.422186 # average overall miss latency
912 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
913 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
914 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
915 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
916 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
917 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
918 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
919 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
920 system.cpu.l2cache.writebacks::writebacks 294035 # number of writebacks
921 system.cpu.l2cache.writebacks::total 294035 # number of writebacks
922 system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits
923 system.cpu.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits
924 system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
925 system.cpu.l2cache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits
926 system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
927 system.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits
928 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3551 # number of ReadReq MSHR misses
929 system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 176400 # number of ReadReq MSHR misses
930 system.cpu.l2cache.ReadReq_mshr_misses::total 179951 # number of ReadReq MSHR misses
931 system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 195096 # number of UpgradeReq MSHR misses
932 system.cpu.l2cache.UpgradeReq_mshr_misses::total 195096 # number of UpgradeReq MSHR misses
933 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 207017 # number of ReadExReq MSHR misses
934 system.cpu.l2cache.ReadExReq_mshr_misses::total 207017 # number of ReadExReq MSHR misses
935 system.cpu.l2cache.demand_mshr_misses::cpu.inst 3551 # number of demand (read+write) MSHR misses
936 system.cpu.l2cache.demand_mshr_misses::cpu.data 383417 # number of demand (read+write) MSHR misses
937 system.cpu.l2cache.demand_mshr_misses::total 386968 # number of demand (read+write) MSHR misses
938 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3551 # number of overall MSHR misses
939 system.cpu.l2cache.overall_mshr_misses::cpu.data 383417 # number of overall MSHR misses
940 system.cpu.l2cache.overall_mshr_misses::total 386968 # number of overall MSHR misses
941 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 250130000 # number of ReadReq MSHR miss cycles
942 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 12068381000 # number of ReadReq MSHR miss cycles
943 system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12318511000 # number of ReadReq MSHR miss cycles
944 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 3521803787 # number of UpgradeReq MSHR miss cycles
945 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 3521803787 # number of UpgradeReq MSHR miss cycles
946 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13841306537 # number of ReadExReq MSHR miss cycles
947 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13841306537 # number of ReadExReq MSHR miss cycles
948 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 250130000 # number of demand (read+write) MSHR miss cycles
949 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 25909687537 # number of demand (read+write) MSHR miss cycles
950 system.cpu.l2cache.demand_mshr_miss_latency::total 26159817537 # number of demand (read+write) MSHR miss cycles
951 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 250130000 # number of overall MSHR miss cycles
952 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 25909687537 # number of overall MSHR miss cycles
953 system.cpu.l2cache.overall_mshr_miss_latency::total 26159817537 # number of overall MSHR miss cycles
954 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.406107 # mshr miss rate for ReadReq accesses
955 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.099839 # mshr miss rate for ReadReq accesses
956 system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.101347 # mshr miss rate for ReadReq accesses
957 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.990451 # mshr miss rate for UpgradeReq accesses
958 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.990451 # mshr miss rate for UpgradeReq accesses
959 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.268322 # mshr miss rate for ReadExReq accesses
960 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.268322 # mshr miss rate for ReadExReq accesses
961 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.406107 # mshr miss rate for demand accesses
962 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.151048 # mshr miss rate for demand accesses
963 system.cpu.l2cache.demand_mshr_miss_rate::total 0.151924 # mshr miss rate for demand accesses
964 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.406107 # mshr miss rate for overall accesses
965 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.151048 # mshr miss rate for overall accesses
966 system.cpu.l2cache.overall_mshr_miss_rate::total 0.151924 # mshr miss rate for overall accesses
967 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 70439.312870 # average ReadReq mshr miss latency
968 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 68414.858277 # average ReadReq mshr miss latency
969 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 68454.807142 # average ReadReq mshr miss latency
970 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 18051.645277 # average UpgradeReq mshr miss latency
971 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18051.645277 # average UpgradeReq mshr miss latency
972 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66860.724177 # average ReadExReq mshr miss latency
973 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66860.724177 # average ReadExReq mshr miss latency
974 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70439.312870 # average overall mshr miss latency
975 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67575.740087 # average overall mshr miss latency
976 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67602.017575 # average overall mshr miss latency
977 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70439.312870 # average overall mshr miss latency
978 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67575.740087 # average overall mshr miss latency
979 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67602.017575 # average overall mshr miss latency
980 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
981 system.cpu.toL2Bus.trans_dist::ReadReq 1972695 # Transaction distribution
982 system.cpu.toL2Bus.trans_dist::ReadResp 1972693 # Transaction distribution
983 system.cpu.toL2Bus.trans_dist::Writeback 2332980 # Transaction distribution
984 system.cpu.toL2Bus.trans_dist::UpgradeReq 196977 # Transaction distribution
985 system.cpu.toL2Bus.trans_dist::UpgradeResp 196977 # Transaction distribution
986 system.cpu.toL2Bus.trans_dist::ReadExReq 771524 # Transaction distribution
987 system.cpu.toL2Bus.trans_dist::ReadExResp 771524 # Transaction distribution
988 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 214584 # Packet count per connected master and slave (bytes)
989 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7803688 # Packet count per connected master and slave (bytes)
990 system.cpu.toL2Bus.pkt_count::total 8018272 # Packet count per connected master and slave (bytes)
991 system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 559488 # Cumulative packet size per connected master and slave (bytes)
992 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311766848 # Cumulative packet size per connected master and slave (bytes)
993 system.cpu.toL2Bus.pkt_size::total 312326336 # Cumulative packet size per connected master and slave (bytes)
994 system.cpu.toL2Bus.snoops 197098 # Total snoops (count)
995 system.cpu.toL2Bus.snoop_fanout::samples 5274176 # Request fanout histogram
996 system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
997 system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
998 system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
999 system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
1000 system.cpu.toL2Bus.snoop_fanout::1 5274176 100.00% 100.00% # Request fanout histogram
1001 system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
1002 system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1003 system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
1004 system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
1005 system.cpu.toL2Bus.snoop_fanout::total 5274176 # Request fanout histogram
1006 system.cpu.toL2Bus.reqLayer0.occupancy 4998685151 # Layer occupancy (ticks)
1007 system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%)
1008 system.cpu.toL2Bus.respLayer0.occupancy 309293990 # Layer occupancy (ticks)
1009 system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
1010 system.cpu.toL2Bus.respLayer1.occupancy 3989146355 # Layer occupancy (ticks)
1011 system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%)
1012 system.membus.trans_dist::ReadReq 179950 # Transaction distribution
1013 system.membus.trans_dist::ReadResp 179949 # Transaction distribution
1014 system.membus.trans_dist::Writeback 294035 # Transaction distribution
1015 system.membus.trans_dist::UpgradeReq 195133 # Transaction distribution
1016 system.membus.trans_dist::UpgradeResp 195133 # Transaction distribution
1017 system.membus.trans_dist::ReadExReq 206980 # Transaction distribution
1018 system.membus.trans_dist::ReadExResp 206980 # Transaction distribution
1019 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1458160 # Packet count per connected master and slave (bytes)
1020 system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1458160 # Packet count per connected master and slave (bytes)
1021 system.membus.pkt_count::total 1458160 # Packet count per connected master and slave (bytes)
1022 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43581696 # Cumulative packet size per connected master and slave (bytes)
1023 system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43581696 # Cumulative packet size per connected master and slave (bytes)
1024 system.membus.pkt_size::total 43581696 # Cumulative packet size per connected master and slave (bytes)
1025 system.membus.snoops 0 # Total snoops (count)
1026 system.membus.snoop_fanout::samples 876098 # Request fanout histogram
1027 system.membus.snoop_fanout::mean 0 # Request fanout histogram
1028 system.membus.snoop_fanout::stdev 0 # Request fanout histogram
1029 system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1030 system.membus.snoop_fanout::0 876098 100.00% 100.00% # Request fanout histogram
1031 system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
1032 system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1033 system.membus.snoop_fanout::min_value 0 # Request fanout histogram
1034 system.membus.snoop_fanout::max_value 0 # Request fanout histogram
1035 system.membus.snoop_fanout::total 876098 # Request fanout histogram
1036 system.membus.reqLayer0.occupancy 2246796268 # Layer occupancy (ticks)
1037 system.membus.reqLayer0.utilization 0.5 # Layer utilization (%)
1038 system.membus.respLayer1.occupancy 2437948408 # Layer occupancy (ticks)
1039 system.membus.respLayer1.utilization 0.6 # Layer utilization (%)
1041 ---------- End Simulation Statistics ----------
projects / gem5.git / blob