2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.456433 # Number of seconds simulated
4 sim_ticks 456433328000 # Number of ticks simulated
5 final_tick 456433328000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 81383 # Simulator instruction rate (inst/s)
8 host_op_rate 150486 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 44923021 # Simulator tick rate (ticks/s)
10 host_mem_usage 402504 # Number of bytes of host memory used
11 host_seconds 10160.34 # Real time elapsed on the host
12 sim_insts 826877109 # Number of instructions simulated
13 sim_ops 1528988701 # Number of ops (including micro ops) simulated
14 system.voltage_domain.voltage 1 # Voltage in Volts
15 system.clk_domain.clock 1000 # Clock period in ticks
16 system.physmem.bytes_read::cpu.inst 210304 # Number of bytes read from this memory
17 system.physmem.bytes_read::cpu.data 24488448 # Number of bytes read from this memory
18 system.physmem.bytes_read::total 24698752 # Number of bytes read from this memory
19 system.physmem.bytes_inst_read::cpu.inst 210304 # Number of instructions bytes read from this memory
20 system.physmem.bytes_inst_read::total 210304 # Number of instructions bytes read from this memory
21 system.physmem.bytes_written::writebacks 18796480 # Number of bytes written to this memory
22 system.physmem.bytes_written::total 18796480 # Number of bytes written to this memory
23 system.physmem.num_reads::cpu.inst 3286 # Number of read requests responded to by this memory
24 system.physmem.num_reads::cpu.data 382632 # Number of read requests responded to by this memory
25 system.physmem.num_reads::total 385918 # Number of read requests responded to by this memory
26 system.physmem.num_writes::writebacks 293695 # Number of write requests responded to by this memory
27 system.physmem.num_writes::total 293695 # Number of write requests responded to by this memory
28 system.physmem.bw_read::cpu.inst 460755 # Total read bandwidth from this memory (bytes/s)
29 system.physmem.bw_read::cpu.data 53651753 # Total read bandwidth from this memory (bytes/s)
30 system.physmem.bw_read::total 54112508 # Total read bandwidth from this memory (bytes/s)
31 system.physmem.bw_inst_read::cpu.inst 460755 # Instruction read bandwidth from this memory (bytes/s)
32 system.physmem.bw_inst_read::total 460755 # Instruction read bandwidth from this memory (bytes/s)
33 system.physmem.bw_write::writebacks 41181217 # Write bandwidth from this memory (bytes/s)
34 system.physmem.bw_write::total 41181217 # Write bandwidth from this memory (bytes/s)
35 system.physmem.bw_total::writebacks 41181217 # Total bandwidth to/from this memory (bytes/s)
36 system.physmem.bw_total::cpu.inst 460755 # Total bandwidth to/from this memory (bytes/s)
37 system.physmem.bw_total::cpu.data 53651753 # Total bandwidth to/from this memory (bytes/s)
38 system.physmem.bw_total::total 95293725 # Total bandwidth to/from this memory (bytes/s)
39 system.physmem.readReqs 385918 # Number of read requests accepted
40 system.physmem.writeReqs 293695 # Number of write requests accepted
41 system.physmem.readBursts 385918 # Number of DRAM read bursts, including those serviced by the write queue
42 system.physmem.writeBursts 293695 # Number of DRAM write bursts, including those merged in the write queue
43 system.physmem.bytesReadDRAM 24677440 # Total number of bytes read from DRAM
44 system.physmem.bytesReadWrQ 21312 # Total number of bytes read from write queue
45 system.physmem.bytesWritten 18795136 # Total number of bytes written to DRAM
46 system.physmem.bytesReadSys 24698752 # Total read bytes from the system interface side
47 system.physmem.bytesWrittenSys 18796480 # Total written bytes from the system interface side
48 system.physmem.servicedByWrQ 333 # Number of DRAM read bursts serviced by the write queue
49 system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
50 system.physmem.neitherReadNorWriteReqs 143951 # Number of requests that are neither read nor write
51 system.physmem.perBankRdBursts::0 24030 # Per bank write bursts
52 system.physmem.perBankRdBursts::1 26462 # Per bank write bursts
53 system.physmem.perBankRdBursts::2 24796 # Per bank write bursts
54 system.physmem.perBankRdBursts::3 24548 # Per bank write bursts
55 system.physmem.perBankRdBursts::4 23428 # Per bank write bursts
56 system.physmem.perBankRdBursts::5 23679 # Per bank write bursts
57 system.physmem.perBankRdBursts::6 24455 # Per bank write bursts
58 system.physmem.perBankRdBursts::7 24282 # Per bank write bursts
59 system.physmem.perBankRdBursts::8 23646 # Per bank write bursts
60 system.physmem.perBankRdBursts::9 23871 # Per bank write bursts
61 system.physmem.perBankRdBursts::10 24701 # Per bank write bursts
62 system.physmem.perBankRdBursts::11 23965 # Per bank write bursts
63 system.physmem.perBankRdBursts::12 23120 # Per bank write bursts
64 system.physmem.perBankRdBursts::13 22899 # Per bank write bursts
65 system.physmem.perBankRdBursts::14 23768 # Per bank write bursts
66 system.physmem.perBankRdBursts::15 23935 # Per bank write bursts
67 system.physmem.perBankWrBursts::0 18533 # Per bank write bursts
68 system.physmem.perBankWrBursts::1 19857 # Per bank write bursts
69 system.physmem.perBankWrBursts::2 18944 # Per bank write bursts
70 system.physmem.perBankWrBursts::3 18929 # Per bank write bursts
71 system.physmem.perBankWrBursts::4 18079 # Per bank write bursts
72 system.physmem.perBankWrBursts::5 18409 # Per bank write bursts
73 system.physmem.perBankWrBursts::6 18979 # Per bank write bursts
74 system.physmem.perBankWrBursts::7 18957 # Per bank write bursts
75 system.physmem.perBankWrBursts::8 18565 # Per bank write bursts
76 system.physmem.perBankWrBursts::9 18141 # Per bank write bursts
77 system.physmem.perBankWrBursts::10 18792 # Per bank write bursts
78 system.physmem.perBankWrBursts::11 17687 # Per bank write bursts
79 system.physmem.perBankWrBursts::12 17335 # Per bank write bursts
80 system.physmem.perBankWrBursts::13 16957 # Per bank write bursts
81 system.physmem.perBankWrBursts::14 17714 # Per bank write bursts
82 system.physmem.perBankWrBursts::15 17796 # Per bank write bursts
83 system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
84 system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
85 system.physmem.totGap 456433277000 # Total gap between requests
86 system.physmem.readPktSize::0 0 # Read request sizes (log2)
87 system.physmem.readPktSize::1 0 # Read request sizes (log2)
88 system.physmem.readPktSize::2 0 # Read request sizes (log2)
89 system.physmem.readPktSize::3 0 # Read request sizes (log2)
90 system.physmem.readPktSize::4 0 # Read request sizes (log2)
91 system.physmem.readPktSize::5 0 # Read request sizes (log2)
92 system.physmem.readPktSize::6 385918 # Read request sizes (log2)
93 system.physmem.writePktSize::0 0 # Write request sizes (log2)
94 system.physmem.writePktSize::1 0 # Write request sizes (log2)
95 system.physmem.writePktSize::2 0 # Write request sizes (log2)
96 system.physmem.writePktSize::3 0 # Write request sizes (log2)
97 system.physmem.writePktSize::4 0 # Write request sizes (log2)
98 system.physmem.writePktSize::5 0 # Write request sizes (log2)
99 system.physmem.writePktSize::6 293695 # Write request sizes (log2)
100 system.physmem.rdQLenPdf::0 380841 # What read queue length does an incoming req see
101 system.physmem.rdQLenPdf::1 4378 # What read queue length does an incoming req see
102 system.physmem.rdQLenPdf::2 326 # What read queue length does an incoming req see
103 system.physmem.rdQLenPdf::3 33 # What read queue length does an incoming req see
104 system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see
105 system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
106 system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
107 system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
108 system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
109 system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
110 system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
111 system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
112 system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
113 system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
114 system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
115 system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
116 system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
117 system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
118 system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
119 system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
120 system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
121 system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
122 system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
123 system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
124 system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
125 system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
126 system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
127 system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
128 system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
129 system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
130 system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
131 system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
132 system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
133 system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
134 system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
135 system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
136 system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
137 system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
138 system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
139 system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
140 system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
141 system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
142 system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
143 system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
144 system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
145 system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
146 system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
147 system.physmem.wrQLenPdf::15 6284 # What write queue length does an incoming req see
148 system.physmem.wrQLenPdf::16 6678 # What write queue length does an incoming req see
149 system.physmem.wrQLenPdf::17 16870 # What write queue length does an incoming req see
150 system.physmem.wrQLenPdf::18 17435 # What write queue length does an incoming req see
151 system.physmem.wrQLenPdf::19 17552 # What write queue length does an incoming req see
152 system.physmem.wrQLenPdf::20 17522 # What write queue length does an incoming req see
153 system.physmem.wrQLenPdf::21 17553 # What write queue length does an incoming req see
154 system.physmem.wrQLenPdf::22 17543 # What write queue length does an incoming req see
155 system.physmem.wrQLenPdf::23 17585 # What write queue length does an incoming req see
156 system.physmem.wrQLenPdf::24 17598 # What write queue length does an incoming req see
157 system.physmem.wrQLenPdf::25 17605 # What write queue length does an incoming req see
158 system.physmem.wrQLenPdf::26 17592 # What write queue length does an incoming req see
159 system.physmem.wrQLenPdf::27 17759 # What write queue length does an incoming req see
160 system.physmem.wrQLenPdf::28 17628 # What write queue length does an incoming req see
161 system.physmem.wrQLenPdf::29 17575 # What write queue length does an incoming req see
162 system.physmem.wrQLenPdf::30 17808 # What write queue length does an incoming req see
163 system.physmem.wrQLenPdf::31 17489 # What write queue length does an incoming req see
164 system.physmem.wrQLenPdf::32 17442 # What write queue length does an incoming req see
165 system.physmem.wrQLenPdf::33 37 # What write queue length does an incoming req see
166 system.physmem.wrQLenPdf::34 20 # What write queue length does an incoming req see
167 system.physmem.wrQLenPdf::35 15 # What write queue length does an incoming req see
168 system.physmem.wrQLenPdf::36 14 # What write queue length does an incoming req see
169 system.physmem.wrQLenPdf::37 15 # What write queue length does an incoming req see
170 system.physmem.wrQLenPdf::38 12 # What write queue length does an incoming req see
171 system.physmem.wrQLenPdf::39 12 # What write queue length does an incoming req see
172 system.physmem.wrQLenPdf::40 9 # What write queue length does an incoming req see
173 system.physmem.wrQLenPdf::41 9 # What write queue length does an incoming req see
174 system.physmem.wrQLenPdf::42 5 # What write queue length does an incoming req see
175 system.physmem.wrQLenPdf::43 4 # What write queue length does an incoming req see
176 system.physmem.wrQLenPdf::44 5 # What write queue length does an incoming req see
177 system.physmem.wrQLenPdf::45 2 # What write queue length does an incoming req see
178 system.physmem.wrQLenPdf::46 2 # What write queue length does an incoming req see
179 system.physmem.wrQLenPdf::47 1 # What write queue length does an incoming req see
180 system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
181 system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
182 system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
183 system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
184 system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
185 system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
186 system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
187 system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
188 system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
189 system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
190 system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
191 system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
192 system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
193 system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
194 system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
195 system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
196 system.physmem.bytesPerActivate::samples 146599 # Bytes accessed per row activation
197 system.physmem.bytesPerActivate::mean 296.532446 # Bytes accessed per row activation
198 system.physmem.bytesPerActivate::gmean 174.978677 # Bytes accessed per row activation
199 system.physmem.bytesPerActivate::stdev 323.931077 # Bytes accessed per row activation
200 system.physmem.bytesPerActivate::0-127 54105 36.91% 36.91% # Bytes accessed per row activation
201 system.physmem.bytesPerActivate::128-255 40284 27.48% 64.39% # Bytes accessed per row activation
202 system.physmem.bytesPerActivate::256-383 13640 9.30% 73.69% # Bytes accessed per row activation
203 system.physmem.bytesPerActivate::384-511 7345 5.01% 78.70% # Bytes accessed per row activation
204 system.physmem.bytesPerActivate::512-639 5124 3.50% 82.20% # Bytes accessed per row activation
205 system.physmem.bytesPerActivate::640-767 3885 2.65% 84.85% # Bytes accessed per row activation
206 system.physmem.bytesPerActivate::768-895 3054 2.08% 86.93% # Bytes accessed per row activation
207 system.physmem.bytesPerActivate::896-1023 2802 1.91% 88.84% # Bytes accessed per row activation
208 system.physmem.bytesPerActivate::1024-1151 16360 11.16% 100.00% # Bytes accessed per row activation
209 system.physmem.bytesPerActivate::total 146599 # Bytes accessed per row activation
210 system.physmem.rdPerTurnAround::samples 17413 # Reads before turning the bus around for writes
211 system.physmem.rdPerTurnAround::mean 22.143169 # Reads before turning the bus around for writes
212 system.physmem.rdPerTurnAround::stdev 209.002812 # Reads before turning the bus around for writes
213 system.physmem.rdPerTurnAround::0-1023 17400 99.93% 99.93% # Reads before turning the bus around for writes
214 system.physmem.rdPerTurnAround::1024-2047 9 0.05% 99.98% # Reads before turning the bus around for writes
215 system.physmem.rdPerTurnAround::2048-3071 2 0.01% 99.99% # Reads before turning the bus around for writes
216 system.physmem.rdPerTurnAround::3072-4095 1 0.01% 99.99% # Reads before turning the bus around for writes
217 system.physmem.rdPerTurnAround::26624-27647 1 0.01% 100.00% # Reads before turning the bus around for writes
218 system.physmem.rdPerTurnAround::total 17413 # Reads before turning the bus around for writes
219 system.physmem.wrPerTurnAround::samples 17413 # Writes before turning the bus around for reads
220 system.physmem.wrPerTurnAround::mean 16.865216 # Writes before turning the bus around for reads
221 system.physmem.wrPerTurnAround::gmean 16.791721 # Writes before turning the bus around for reads
222 system.physmem.wrPerTurnAround::stdev 2.763276 # Writes before turning the bus around for reads
223 system.physmem.wrPerTurnAround::16-19 17216 98.87% 98.87% # Writes before turning the bus around for reads
224 system.physmem.wrPerTurnAround::20-23 134 0.77% 99.64% # Writes before turning the bus around for reads
225 system.physmem.wrPerTurnAround::24-27 42 0.24% 99.88% # Writes before turning the bus around for reads
226 system.physmem.wrPerTurnAround::28-31 4 0.02% 99.90% # Writes before turning the bus around for reads
227 system.physmem.wrPerTurnAround::32-35 3 0.02% 99.92% # Writes before turning the bus around for reads
228 system.physmem.wrPerTurnAround::36-39 2 0.01% 99.93% # Writes before turning the bus around for reads
229 system.physmem.wrPerTurnAround::44-47 1 0.01% 99.94% # Writes before turning the bus around for reads
230 system.physmem.wrPerTurnAround::48-51 2 0.01% 99.95% # Writes before turning the bus around for reads
231 system.physmem.wrPerTurnAround::56-59 1 0.01% 99.95% # Writes before turning the bus around for reads
232 system.physmem.wrPerTurnAround::68-71 1 0.01% 99.96% # Writes before turning the bus around for reads
233 system.physmem.wrPerTurnAround::72-75 1 0.01% 99.97% # Writes before turning the bus around for reads
234 system.physmem.wrPerTurnAround::88-91 1 0.01% 99.97% # Writes before turning the bus around for reads
235 system.physmem.wrPerTurnAround::108-111 1 0.01% 99.98% # Writes before turning the bus around for reads
236 system.physmem.wrPerTurnAround::112-115 2 0.01% 99.99% # Writes before turning the bus around for reads
237 system.physmem.wrPerTurnAround::128-131 1 0.01% 99.99% # Writes before turning the bus around for reads
238 system.physmem.wrPerTurnAround::244-247 1 0.01% 100.00% # Writes before turning the bus around for reads
239 system.physmem.wrPerTurnAround::total 17413 # Writes before turning the bus around for reads
240 system.physmem.totQLat 4238739250 # Total ticks spent queuing
241 system.physmem.totMemAccLat 11468458000 # Total ticks spent from burst creation until serviced by the DRAM
242 system.physmem.totBusLat 1927925000 # Total ticks spent in databus transfers
243 system.physmem.avgQLat 10993.01 # Average queueing delay per DRAM burst
244 system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
245 system.physmem.avgMemAccLat 29743.01 # Average memory access latency per DRAM burst
246 system.physmem.avgRdBW 54.07 # Average DRAM read bandwidth in MiByte/s
247 system.physmem.avgWrBW 41.18 # Average achieved write bandwidth in MiByte/s
248 system.physmem.avgRdBWSys 54.11 # Average system read bandwidth in MiByte/s
249 system.physmem.avgWrBWSys 41.18 # Average system write bandwidth in MiByte/s
250 system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
251 system.physmem.busUtil 0.74 # Data bus utilization in percentage
252 system.physmem.busUtilRead 0.42 # Data bus utilization in percentage for reads
253 system.physmem.busUtilWrite 0.32 # Data bus utilization in percentage for writes
254 system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing
255 system.physmem.avgWrQLen 21.44 # Average write queue length when enqueuing
256 system.physmem.readRowHits 317362 # Number of row buffer hits during reads
257 system.physmem.writeRowHits 215286 # Number of row buffer hits during writes
258 system.physmem.readRowHitRate 82.31 # Row buffer hit rate for reads
259 system.physmem.writeRowHitRate 73.30 # Row buffer hit rate for writes
260 system.physmem.avgGap 671607.63 # Average gap between requests
261 system.physmem.pageHitRate 78.41 # Row buffer hit rate, read and write combined
262 system.physmem.memoryStateTime::IDLE 317298172500 # Time in different power states
263 system.physmem.memoryStateTime::REF 15241200000 # Time in different power states
264 system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
265 system.physmem.memoryStateTime::ACT 123890904750 # Time in different power states
266 system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
267 system.membus.throughput 95293725 # Throughput (bytes/s)
268 system.membus.trans_dist::ReadReq 179074 # Transaction distribution
269 system.membus.trans_dist::ReadResp 179074 # Transaction distribution
270 system.membus.trans_dist::Writeback 293695 # Transaction distribution
271 system.membus.trans_dist::UpgradeReq 143951 # Transaction distribution
272 system.membus.trans_dist::UpgradeResp 143951 # Transaction distribution
273 system.membus.trans_dist::ReadExReq 206844 # Transaction distribution
274 system.membus.trans_dist::ReadExResp 206844 # Transaction distribution
275 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1353433 # Packet count per connected master and slave (bytes)
276 system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1353433 # Packet count per connected master and slave (bytes)
277 system.membus.pkt_count::total 1353433 # Packet count per connected master and slave (bytes)
278 system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43495232 # Cumulative packet size per connected master and slave (bytes)
279 system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 43495232 # Cumulative packet size per connected master and slave (bytes)
280 system.membus.tot_pkt_size::total 43495232 # Cumulative packet size per connected master and slave (bytes)
281 system.membus.data_through_bus 43495232 # Total data (bytes)
282 system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
283 system.membus.reqLayer0.occupancy 3409046000 # Layer occupancy (ticks)
284 system.membus.reqLayer0.utilization 0.7 # Layer utilization (%)
285 system.membus.respLayer1.occupancy 3919297073 # Layer occupancy (ticks)
286 system.membus.respLayer1.utilization 0.9 # Layer utilization (%)
287 system.cpu_clk_domain.clock 500 # Clock period in ticks
288 system.cpu.branchPred.lookups 214172576 # Number of BP lookups
289 system.cpu.branchPred.condPredicted 214172576 # Number of conditional branches predicted
290 system.cpu.branchPred.condIncorrect 10017048 # Number of conditional branches incorrect
291 system.cpu.branchPred.BTBLookups 122104582 # Number of BTB lookups
292 system.cpu.branchPred.BTBHits 119561484 # Number of BTB hits
293 system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
294 system.cpu.branchPred.BTBHitPct 97.917279 # BTB Hit Percentage
295 system.cpu.branchPred.usedRAS 25755339 # Number of times the RAS was used to get a target.
296 system.cpu.branchPred.RASInCorrect 1811393 # Number of incorrect RAS predictions.
297 system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
298 system.cpu.workload.num_syscalls 551 # Number of system calls
299 system.cpu.numCycles 913134033 # number of cpu cycles simulated
300 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
301 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
302 system.cpu.fetch.icacheStallCycles 172957677 # Number of cycles fetch is stalled on an Icache miss
303 system.cpu.fetch.Insts 1180093576 # Number of instructions fetch has processed
304 system.cpu.fetch.Branches 214172576 # Number of branches that fetch encountered
305 system.cpu.fetch.predictedBranches 145316823 # Number of branches that fetch has predicted taken
306 system.cpu.fetch.Cycles 366593738 # Number of cycles fetch has run and was not squashing or blocked
307 system.cpu.fetch.SquashCycles 80936667 # Number of cycles fetch has spent squashing
308 system.cpu.fetch.BlockedCycles 266990637 # Number of cycles fetch has spent blocked
309 system.cpu.fetch.MiscStallCycles 56859 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
310 system.cpu.fetch.PendingTrapStallCycles 326654 # Number of stall cycles due to pending traps
311 system.cpu.fetch.CacheLines 167839999 # Number of cache lines fetched
312 system.cpu.fetch.IcacheSquashes 2941367 # Number of outstanding Icache misses that were squashed
313 system.cpu.fetch.rateDist::samples 877562871 # Number of instructions fetched each cycle (Total)
314 system.cpu.fetch.rateDist::mean 2.500418 # Number of instructions fetched each cycle (Total)
315 system.cpu.fetch.rateDist::stdev 3.366055 # Number of instructions fetched each cycle (Total)
316 system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
317 system.cpu.fetch.rateDist::0 515232459 58.71% 58.71% # Number of instructions fetched each cycle (Total)
318 system.cpu.fetch.rateDist::1 24457756 2.79% 61.50% # Number of instructions fetched each cycle (Total)
319 system.cpu.fetch.rateDist::2 25984112 2.96% 64.46% # Number of instructions fetched each cycle (Total)
320 system.cpu.fetch.rateDist::3 28771124 3.28% 67.74% # Number of instructions fetched each cycle (Total)
321 system.cpu.fetch.rateDist::4 18396810 2.10% 69.83% # Number of instructions fetched each cycle (Total)
322 system.cpu.fetch.rateDist::5 23701764 2.70% 72.54% # Number of instructions fetched each cycle (Total)
323 system.cpu.fetch.rateDist::6 30460841 3.47% 76.01% # Number of instructions fetched each cycle (Total)
324 system.cpu.fetch.rateDist::7 27790154 3.17% 79.17% # Number of instructions fetched each cycle (Total)
325 system.cpu.fetch.rateDist::8 182767851 20.83% 100.00% # Number of instructions fetched each cycle (Total)
326 system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
327 system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
328 system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
329 system.cpu.fetch.rateDist::total 877562871 # Number of instructions fetched each cycle (Total)
330 system.cpu.fetch.branchRate 0.234547 # Number of branch fetches per cycle
331 system.cpu.fetch.rate 1.292355 # Number of inst fetches per cycle
332 system.cpu.decode.IdleCycles 214899100 # Number of cycles decode is idle
333 system.cpu.decode.BlockedCycles 235918889 # Number of cycles decode is blocked
334 system.cpu.decode.RunCycles 323832333 # Number of cycles decode is running
335 system.cpu.decode.UnblockCycles 32275243 # Number of cycles decode is unblocking
336 system.cpu.decode.SquashCycles 70637306 # Number of cycles decode is squashing
337 system.cpu.decode.DecodedInsts 2159083489 # Number of instructions handled by decode
338 system.cpu.decode.SquashedInsts 22 # Number of squashed instructions handled by decode
339 system.cpu.rename.SquashCycles 70637306 # Number of cycles rename is squashing
340 system.cpu.rename.IdleCycles 235683125 # Number of cycles rename is idle
341 system.cpu.rename.BlockCycles 99102790 # Number of cycles rename is blocking
342 system.cpu.rename.serializeStallCycles 23033 # count of cycles rename stalled for serializing inst
343 system.cpu.rename.RunCycles 334766565 # Number of cycles rename is running
344 system.cpu.rename.UnblockCycles 137350052 # Number of cycles rename is unblocking
345 system.cpu.rename.RenamedInsts 2116178959 # Number of instructions processed by rename
346 system.cpu.rename.ROBFullEvents 79091 # Number of times rename has blocked due to ROB full
347 system.cpu.rename.IQFullEvents 86333515 # Number of times rename has blocked due to IQ full
348 system.cpu.rename.LQFullEvents 11675978 # Number of times rename has blocked due to LQ full
349 system.cpu.rename.SQFullEvents 34385645 # Number of times rename has blocked due to SQ full
350 system.cpu.rename.RenamedOperands 2221828274 # Number of destination operands rename has renamed
351 system.cpu.rename.RenameLookups 5358350843 # Number of register rename lookups that rename has made
352 system.cpu.rename.int_rename_lookups 3404407883 # Number of integer rename lookups
353 system.cpu.rename.fp_rename_lookups 44462 # Number of floating rename lookups
354 system.cpu.rename.CommittedMaps 1614040854 # Number of HB maps that are committed
355 system.cpu.rename.UndoneMaps 607787420 # Number of HB maps that are undone due to squashing
356 system.cpu.rename.serializingInsts 1530 # count of serializing insts renamed
357 system.cpu.rename.tempSerializingInsts 1409 # count of temporary serializing insts renamed
358 system.cpu.rename.skidInsts 224967788 # count of insts added to the skid buffer
359 system.cpu.memDep0.insertedLoads 514990281 # Number of loads inserted to the mem dependence unit.
360 system.cpu.memDep0.insertedStores 202517058 # Number of stores inserted to the mem dependence unit.
361 system.cpu.memDep0.conflictingLoads 220543258 # Number of conflicting loads.
362 system.cpu.memDep0.conflictingStores 63035338 # Number of conflicting stores.
363 system.cpu.iq.iqInstsAdded 2048951027 # Number of instructions added to the IQ (excludes non-spec)
364 system.cpu.iq.iqNonSpecInstsAdded 18335 # Number of non-speculative instructions added to the IQ
365 system.cpu.iq.iqInstsIssued 1800520380 # Number of instructions issued
366 system.cpu.iq.iqSquashedInstsIssued 873481 # Number of squashed instructions issued
367 system.cpu.iq.iqSquashedInstsExamined 514890445 # Number of squashed instructions iterated over during squash; mainly for profiling
368 system.cpu.iq.iqSquashedOperandsExamined 886881463 # Number of squashed operands that are examined and possibly removed from graph
369 system.cpu.iq.iqSquashedNonSpecRemoved 17783 # Number of squashed non-spec instructions that were removed
370 system.cpu.iq.issued_per_cycle::samples 877562871 # Number of insts issued each cycle
371 system.cpu.iq.issued_per_cycle::mean 2.051728 # Number of insts issued each cycle
372 system.cpu.iq.issued_per_cycle::stdev 1.961101 # Number of insts issued each cycle
373 system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
374 system.cpu.iq.issued_per_cycle::0 278621882 31.75% 31.75% # Number of insts issued each cycle
375 system.cpu.iq.issued_per_cycle::1 139650345 15.91% 47.66% # Number of insts issued each cycle
376 system.cpu.iq.issued_per_cycle::2 122145227 13.92% 61.58% # Number of insts issued each cycle
377 system.cpu.iq.issued_per_cycle::3 121221287 13.81% 75.40% # Number of insts issued each cycle
378 system.cpu.iq.issued_per_cycle::4 101661945 11.58% 86.98% # Number of insts issued each cycle
379 system.cpu.iq.issued_per_cycle::5 58080162 6.62% 93.60% # Number of insts issued each cycle
380 system.cpu.iq.issued_per_cycle::6 39790509 4.53% 98.13% # Number of insts issued each cycle
381 system.cpu.iq.issued_per_cycle::7 14008036 1.60% 99.73% # Number of insts issued each cycle
382 system.cpu.iq.issued_per_cycle::8 2383478 0.27% 100.00% # Number of insts issued each cycle
383 system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
384 system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
385 system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
386 system.cpu.iq.issued_per_cycle::total 877562871 # Number of insts issued each cycle
387 system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
388 system.cpu.iq.fu_full::IntAlu 8996464 42.62% 42.62% # attempts to use FU when none available
389 system.cpu.iq.fu_full::IntMult 0 0.00% 42.62% # attempts to use FU when none available
390 system.cpu.iq.fu_full::IntDiv 0 0.00% 42.62% # attempts to use FU when none available
391 system.cpu.iq.fu_full::FloatAdd 0 0.00% 42.62% # attempts to use FU when none available
392 system.cpu.iq.fu_full::FloatCmp 0 0.00% 42.62% # attempts to use FU when none available
393 system.cpu.iq.fu_full::FloatCvt 0 0.00% 42.62% # attempts to use FU when none available
394 system.cpu.iq.fu_full::FloatMult 0 0.00% 42.62% # attempts to use FU when none available
395 system.cpu.iq.fu_full::FloatDiv 0 0.00% 42.62% # attempts to use FU when none available
396 system.cpu.iq.fu_full::FloatSqrt 0 0.00% 42.62% # attempts to use FU when none available
397 system.cpu.iq.fu_full::SimdAdd 0 0.00% 42.62% # attempts to use FU when none available
398 system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 42.62% # attempts to use FU when none available
399 system.cpu.iq.fu_full::SimdAlu 0 0.00% 42.62% # attempts to use FU when none available
400 system.cpu.iq.fu_full::SimdCmp 0 0.00% 42.62% # attempts to use FU when none available
401 system.cpu.iq.fu_full::SimdCvt 0 0.00% 42.62% # attempts to use FU when none available
402 system.cpu.iq.fu_full::SimdMisc 0 0.00% 42.62% # attempts to use FU when none available
403 system.cpu.iq.fu_full::SimdMult 0 0.00% 42.62% # attempts to use FU when none available
404 system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 42.62% # attempts to use FU when none available
405 system.cpu.iq.fu_full::SimdShift 0 0.00% 42.62% # attempts to use FU when none available
406 system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 42.62% # attempts to use FU when none available
407 system.cpu.iq.fu_full::SimdSqrt 0 0.00% 42.62% # attempts to use FU when none available
408 system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 42.62% # attempts to use FU when none available
409 system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 42.62% # attempts to use FU when none available
410 system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 42.62% # attempts to use FU when none available
411 system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 42.62% # attempts to use FU when none available
412 system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 42.62% # attempts to use FU when none available
413 system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 42.62% # attempts to use FU when none available
414 system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 42.62% # attempts to use FU when none available
415 system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 42.62% # attempts to use FU when none available
416 system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 42.62% # attempts to use FU when none available
417 system.cpu.iq.fu_full::MemRead 9189518 43.53% 86.15% # attempts to use FU when none available
418 system.cpu.iq.fu_full::MemWrite 2923144 13.85% 100.00% # attempts to use FU when none available
419 system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
420 system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
421 system.cpu.iq.FU_type_0::No_OpClass 2650510 0.15% 0.15% # Type of FU issued
422 system.cpu.iq.FU_type_0::IntAlu 1189351125 66.06% 66.20% # Type of FU issued
423 system.cpu.iq.FU_type_0::IntMult 365099 0.02% 66.22% # Type of FU issued
424 system.cpu.iq.FU_type_0::IntDiv 3880777 0.22% 66.44% # Type of FU issued
425 system.cpu.iq.FU_type_0::FloatAdd 57 0.00% 66.44% # Type of FU issued
426 system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.44% # Type of FU issued
427 system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.44% # Type of FU issued
428 system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.44% # Type of FU issued
429 system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.44% # Type of FU issued
430 system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.44% # Type of FU issued
431 system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.44% # Type of FU issued
432 system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.44% # Type of FU issued
433 system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.44% # Type of FU issued
434 system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.44% # Type of FU issued
435 system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.44% # Type of FU issued
436 system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.44% # Type of FU issued
437 system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.44% # Type of FU issued
438 system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.44% # Type of FU issued
439 system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.44% # Type of FU issued
440 system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.44% # Type of FU issued
441 system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.44% # Type of FU issued
442 system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.44% # Type of FU issued
443 system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.44% # Type of FU issued
444 system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.44% # Type of FU issued
445 system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.44% # Type of FU issued
446 system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.44% # Type of FU issued
447 system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.44% # Type of FU issued
448 system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.44% # Type of FU issued
449 system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.44% # Type of FU issued
450 system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.44% # Type of FU issued
451 system.cpu.iq.FU_type_0::MemRead 432328086 24.01% 90.45% # Type of FU issued
452 system.cpu.iq.FU_type_0::MemWrite 171944726 9.55% 100.00% # Type of FU issued
453 system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
454 system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
455 system.cpu.iq.FU_type_0::total 1800520380 # Type of FU issued
456 system.cpu.iq.rate 1.971803 # Inst issue rate
457 system.cpu.iq.fu_busy_cnt 21109126 # FU busy when requested
458 system.cpu.iq.fu_busy_rate 0.011724 # FU busy rate (busy events/executed inst)
459 system.cpu.iq.int_inst_queue_reads 4500567659 # Number of integer instruction queue reads
460 system.cpu.iq.int_inst_queue_writes 2564101057 # Number of integer instruction queue writes
461 system.cpu.iq.int_inst_queue_wakeup_accesses 1771520383 # Number of integer instruction queue wakeup accesses
462 system.cpu.iq.fp_inst_queue_reads 18579 # Number of floating instruction queue reads
463 system.cpu.iq.fp_inst_queue_writes 42290 # Number of floating instruction queue writes
464 system.cpu.iq.fp_inst_queue_wakeup_accesses 4796 # Number of floating instruction queue wakeup accesses
465 system.cpu.iq.int_alu_accesses 1818970082 # Number of integer alu accesses
466 system.cpu.iq.fp_alu_accesses 8914 # Number of floating point alu accesses
467 system.cpu.iew.lsq.thread0.forwLoads 181603573 # Number of loads that had data forwarded from stores
468 system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
469 system.cpu.iew.lsq.thread0.squashedLoads 130889258 # Number of loads squashed
470 system.cpu.iew.lsq.thread0.ignoredResponses 280840 # Number of memory responses ignored because the instruction is squashed
471 system.cpu.iew.lsq.thread0.memOrderViolation 356982 # Number of memory ordering violations
472 system.cpu.iew.lsq.thread0.squashedStores 53356872 # Number of stores squashed
473 system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
474 system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
475 system.cpu.iew.lsq.thread0.rescheduledLoads 17048 # Number of loads that were rescheduled
476 system.cpu.iew.lsq.thread0.cacheBlocked 593 # Number of times an access to memory failed due to the cache being blocked
477 system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
478 system.cpu.iew.iewSquashCycles 70637306 # Number of cycles IEW is squashing
479 system.cpu.iew.iewBlockCycles 60567761 # Number of cycles IEW is blocking
480 system.cpu.iew.iewUnblockCycles 9830463 # Number of cycles IEW is unblocking
481 system.cpu.iew.iewDispatchedInsts 2048969362 # Number of instructions dispatched to IQ
482 system.cpu.iew.iewDispSquashedInsts 565538 # Number of squashed instructions skipped by dispatch
483 system.cpu.iew.iewDispLoadInsts 514991415 # Number of dispatched load instructions
484 system.cpu.iew.iewDispStoreInsts 202517058 # Number of dispatched store instructions
485 system.cpu.iew.iewDispNonSpecInsts 4133 # Number of dispatched non-speculative instructions
486 system.cpu.iew.iewIQFullEvents 4684109 # Number of times the IQ has become full, causing a stall
487 system.cpu.iew.iewLSQFullEvents 2987973 # Number of times the LSQ has become full, causing a stall
488 system.cpu.iew.memOrderViolationEvents 356982 # Number of memory order violations
489 system.cpu.iew.predictedTakenIncorrect 5998592 # Number of branches that were predicted taken incorrectly
490 system.cpu.iew.predictedNotTakenIncorrect 4475905 # Number of branches that were predicted not taken incorrectly
491 system.cpu.iew.branchMispredicts 10474497 # Number of branch mispredicts detected at execute
492 system.cpu.iew.iewExecutedInsts 1780058647 # Number of executed instructions
493 system.cpu.iew.iewExecLoadInsts 427019742 # Number of load instructions executed
494 system.cpu.iew.iewExecSquashedInsts 20461733 # Number of squashed instructions skipped in execute
495 system.cpu.iew.exec_swp 0 # number of swp insts executed
496 system.cpu.iew.exec_nop 0 # number of nop insts executed
497 system.cpu.iew.exec_refs 595482816 # number of memory reference insts executed
498 system.cpu.iew.exec_branches 169731635 # Number of branches executed
499 system.cpu.iew.exec_stores 168463074 # Number of stores executed
500 system.cpu.iew.exec_rate 1.949395 # Inst execution rate
501 system.cpu.iew.wb_sent 1776808975 # cumulative count of insts sent to commit
502 system.cpu.iew.wb_count 1771525179 # cumulative count of insts written-back
503 system.cpu.iew.wb_producers 1358454852 # num instructions producing a value
504 system.cpu.iew.wb_consumers 2034017500 # num instructions consuming a value
505 system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
506 system.cpu.iew.wb_rate 1.940049 # insts written-back per cycle
507 system.cpu.iew.wb_fanout 0.667868 # average fanout of values written-back
508 system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
509 system.cpu.commit.commitSquashedInsts 520066569 # The number of squashed insts skipped by commit
510 system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards
511 system.cpu.commit.branchMispredicts 10054119 # The number of times a branch was mispredicted
512 system.cpu.commit.committed_per_cycle::samples 806925565 # Number of insts commited each cycle
513 system.cpu.commit.committed_per_cycle::mean 1.894832 # Number of insts commited each cycle
514 system.cpu.commit.committed_per_cycle::stdev 2.501115 # Number of insts commited each cycle
515 system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
516 system.cpu.commit.committed_per_cycle::0 332217224 41.17% 41.17% # Number of insts commited each cycle
517 system.cpu.commit.committed_per_cycle::1 181470930 22.49% 63.66% # Number of insts commited each cycle
518 system.cpu.commit.committed_per_cycle::2 58010021 7.19% 70.85% # Number of insts commited each cycle
519 system.cpu.commit.committed_per_cycle::3 87470883 10.84% 81.69% # Number of insts commited each cycle
520 system.cpu.commit.committed_per_cycle::4 24768584 3.07% 84.76% # Number of insts commited each cycle
521 system.cpu.commit.committed_per_cycle::5 27525249 3.41% 88.17% # Number of insts commited each cycle
522 system.cpu.commit.committed_per_cycle::6 9963607 1.23% 89.40% # Number of insts commited each cycle
523 system.cpu.commit.committed_per_cycle::7 11389679 1.41% 90.82% # Number of insts commited each cycle
524 system.cpu.commit.committed_per_cycle::8 74109388 9.18% 100.00% # Number of insts commited each cycle
525 system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
526 system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
527 system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
528 system.cpu.commit.committed_per_cycle::total 806925565 # Number of insts commited each cycle
529 system.cpu.commit.committedInsts 826877109 # Number of instructions committed
530 system.cpu.commit.committedOps 1528988701 # Number of ops (including micro ops) committed
531 system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
532 system.cpu.commit.refs 533262343 # Number of memory references committed
533 system.cpu.commit.loads 384102157 # Number of loads committed
534 system.cpu.commit.membars 0 # Number of memory barriers committed
535 system.cpu.commit.branches 149758583 # Number of branches committed
536 system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
537 system.cpu.commit.int_insts 1526605509 # Number of committed integer instructions.
538 system.cpu.commit.function_calls 17673145 # Number of function calls committed.
539 system.cpu.commit.op_class_0::No_OpClass 1819099 0.12% 0.12% # Class of committed instruction
540 system.cpu.commit.op_class_0::IntAlu 989721889 64.73% 64.85% # Class of committed instruction
541 system.cpu.commit.op_class_0::IntMult 306834 0.02% 64.87% # Class of committed instruction
542 system.cpu.commit.op_class_0::IntDiv 3878536 0.25% 65.12% # Class of committed instruction
543 system.cpu.commit.op_class_0::FloatAdd 0 0.00% 65.12% # Class of committed instruction
544 system.cpu.commit.op_class_0::FloatCmp 0 0.00% 65.12% # Class of committed instruction
545 system.cpu.commit.op_class_0::FloatCvt 0 0.00% 65.12% # Class of committed instruction
546 system.cpu.commit.op_class_0::FloatMult 0 0.00% 65.12% # Class of committed instruction
547 system.cpu.commit.op_class_0::FloatDiv 0 0.00% 65.12% # Class of committed instruction
548 system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 65.12% # Class of committed instruction
549 system.cpu.commit.op_class_0::SimdAdd 0 0.00% 65.12% # Class of committed instruction
550 system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 65.12% # Class of committed instruction
551 system.cpu.commit.op_class_0::SimdAlu 0 0.00% 65.12% # Class of committed instruction
552 system.cpu.commit.op_class_0::SimdCmp 0 0.00% 65.12% # Class of committed instruction
553 system.cpu.commit.op_class_0::SimdCvt 0 0.00% 65.12% # Class of committed instruction
554 system.cpu.commit.op_class_0::SimdMisc 0 0.00% 65.12% # Class of committed instruction
555 system.cpu.commit.op_class_0::SimdMult 0 0.00% 65.12% # Class of committed instruction
556 system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 65.12% # Class of committed instruction
557 system.cpu.commit.op_class_0::SimdShift 0 0.00% 65.12% # Class of committed instruction
558 system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 65.12% # Class of committed instruction
559 system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 65.12% # Class of committed instruction
560 system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 65.12% # Class of committed instruction
561 system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 65.12% # Class of committed instruction
562 system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 65.12% # Class of committed instruction
563 system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 65.12% # Class of committed instruction
564 system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 65.12% # Class of committed instruction
565 system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 65.12% # Class of committed instruction
566 system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 65.12% # Class of committed instruction
567 system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.12% # Class of committed instruction
568 system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.12% # Class of committed instruction
569 system.cpu.commit.op_class_0::MemRead 384102157 25.12% 90.24% # Class of committed instruction
570 system.cpu.commit.op_class_0::MemWrite 149160186 9.76% 100.00% # Class of committed instruction
571 system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
572 system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
573 system.cpu.commit.op_class_0::total 1528988701 # Class of committed instruction
574 system.cpu.commit.bw_lim_events 74109388 # number cycles where commit BW limit reached
575 system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
576 system.cpu.rob.rob_reads 2781871447 # The number of ROB reads
577 system.cpu.rob.rob_writes 4168935238 # The number of ROB writes
578 system.cpu.timesIdled 4004498 # Number of times that the entire CPU went into an idle state and unscheduled itself
579 system.cpu.idleCycles 35571162 # Total number of cycles that the CPU has spent unscheduled due to idling
580 system.cpu.committedInsts 826877109 # Number of Instructions Simulated
581 system.cpu.committedOps 1528988701 # Number of Ops (including micro ops) Simulated
582 system.cpu.cpi 1.104316 # CPI: Cycles Per Instruction
583 system.cpu.cpi_total 1.104316 # CPI: Total CPI of All Threads
584 system.cpu.ipc 0.905537 # IPC: Instructions Per Cycle
585 system.cpu.ipc_total 0.905537 # IPC: Total IPC of All Threads
586 system.cpu.int_regfile_reads 2740022491 # number of integer regfile reads
587 system.cpu.int_regfile_writes 1443498634 # number of integer regfile writes
588 system.cpu.fp_regfile_reads 4829 # number of floating regfile reads
589 system.cpu.fp_regfile_writes 113 # number of floating regfile writes
590 system.cpu.cc_regfile_reads 599382503 # number of cc regfile reads
591 system.cpu.cc_regfile_writes 407768692 # number of cc regfile writes
592 system.cpu.misc_regfile_reads 978269285 # number of misc regfile reads
593 system.cpu.misc_regfile_writes 1 # number of misc regfile writes
594 system.cpu.toL2Bus.throughput 703796459 # Throughput (bytes/s)
595 system.cpu.toL2Bus.trans_dist::ReadReq 1916652 # Transaction distribution
596 system.cpu.toL2Bus.trans_dist::ReadResp 1916650 # Transaction distribution
597 system.cpu.toL2Bus.trans_dist::Writeback 2331152 # Transaction distribution
598 system.cpu.toL2Bus.trans_dist::UpgradeReq 145500 # Transaction distribution
599 system.cpu.toL2Bus.trans_dist::UpgradeResp 145500 # Transaction distribution
600 system.cpu.toL2Bus.trans_dist::ReadExReq 771513 # Transaction distribution
601 system.cpu.toL2Bus.trans_dist::ReadExResp 771513 # Transaction distribution
602 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 160475 # Packet count per connected master and slave (bytes)
603 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7692392 # Packet count per connected master and slave (bytes)
604 system.cpu.toL2Bus.pkt_count::total 7852867 # Packet count per connected master and slave (bytes)
605 system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 475520 # Cumulative packet size per connected master and slave (bytes)
606 system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311441408 # Cumulative packet size per connected master and slave (bytes)
607 system.cpu.toL2Bus.tot_pkt_size::total 311916928 # Cumulative packet size per connected master and slave (bytes)
608 system.cpu.toL2Bus.data_through_bus 311916928 # Total data (bytes)
609 system.cpu.toL2Bus.snoop_data_through_bus 9319232 # Total snoop data (bytes)
610 system.cpu.toL2Bus.reqLayer0.occupancy 4920349397 # Layer occupancy (ticks)
611 system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%)
612 system.cpu.toL2Bus.respLayer0.occupancy 230044243 # Layer occupancy (ticks)
613 system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
614 system.cpu.toL2Bus.respLayer1.occupancy 3958184582 # Layer occupancy (ticks)
615 system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%)
616 system.cpu.icache.tags.replacements 5899 # number of replacements
617 system.cpu.icache.tags.tagsinuse 1053.974853 # Cycle average of tags in use
618 system.cpu.icache.tags.total_refs 167683081 # Total number of references to valid blocks.
619 system.cpu.icache.tags.sampled_refs 7506 # Sample count of references to valid blocks.
620 system.cpu.icache.tags.avg_refs 22339.872236 # Average number of references to valid blocks.
621 system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
622 system.cpu.icache.tags.occ_blocks::cpu.inst 1053.974853 # Average occupied blocks per requestor
623 system.cpu.icache.tags.occ_percent::cpu.inst 0.514636 # Average percentage of cache occupancy
624 system.cpu.icache.tags.occ_percent::total 0.514636 # Average percentage of cache occupancy
625 system.cpu.icache.tags.occ_task_id_blocks::1024 1607 # Occupied blocks per task id
626 system.cpu.icache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id
627 system.cpu.icache.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id
628 system.cpu.icache.tags.age_task_id_blocks_1024::2 63 # Occupied blocks per task id
629 system.cpu.icache.tags.age_task_id_blocks_1024::3 269 # Occupied blocks per task id
630 system.cpu.icache.tags.age_task_id_blocks_1024::4 1203 # Occupied blocks per task id
631 system.cpu.icache.tags.occ_task_id_percent::1024 0.784668 # Percentage of cache occupancy per task id
632 system.cpu.icache.tags.tag_accesses 335833041 # Number of tag accesses
633 system.cpu.icache.tags.data_accesses 335833041 # Number of data accesses
634 system.cpu.icache.ReadReq_hits::cpu.inst 167684909 # number of ReadReq hits
635 system.cpu.icache.ReadReq_hits::total 167684909 # number of ReadReq hits
636 system.cpu.icache.demand_hits::cpu.inst 167684909 # number of demand (read+write) hits
637 system.cpu.icache.demand_hits::total 167684909 # number of demand (read+write) hits
638 system.cpu.icache.overall_hits::cpu.inst 167684909 # number of overall hits
639 system.cpu.icache.overall_hits::total 167684909 # number of overall hits
640 system.cpu.icache.ReadReq_misses::cpu.inst 155090 # number of ReadReq misses
641 system.cpu.icache.ReadReq_misses::total 155090 # number of ReadReq misses
642 system.cpu.icache.demand_misses::cpu.inst 155090 # number of demand (read+write) misses
643 system.cpu.icache.demand_misses::total 155090 # number of demand (read+write) misses
644 system.cpu.icache.overall_misses::cpu.inst 155090 # number of overall misses
645 system.cpu.icache.overall_misses::total 155090 # number of overall misses
646 system.cpu.icache.ReadReq_miss_latency::cpu.inst 984545992 # number of ReadReq miss cycles
647 system.cpu.icache.ReadReq_miss_latency::total 984545992 # number of ReadReq miss cycles
648 system.cpu.icache.demand_miss_latency::cpu.inst 984545992 # number of demand (read+write) miss cycles
649 system.cpu.icache.demand_miss_latency::total 984545992 # number of demand (read+write) miss cycles
650 system.cpu.icache.overall_miss_latency::cpu.inst 984545992 # number of overall miss cycles
651 system.cpu.icache.overall_miss_latency::total 984545992 # number of overall miss cycles
652 system.cpu.icache.ReadReq_accesses::cpu.inst 167839999 # number of ReadReq accesses(hits+misses)
653 system.cpu.icache.ReadReq_accesses::total 167839999 # number of ReadReq accesses(hits+misses)
654 system.cpu.icache.demand_accesses::cpu.inst 167839999 # number of demand (read+write) accesses
655 system.cpu.icache.demand_accesses::total 167839999 # number of demand (read+write) accesses
656 system.cpu.icache.overall_accesses::cpu.inst 167839999 # number of overall (read+write) accesses
657 system.cpu.icache.overall_accesses::total 167839999 # number of overall (read+write) accesses
658 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000924 # miss rate for ReadReq accesses
659 system.cpu.icache.ReadReq_miss_rate::total 0.000924 # miss rate for ReadReq accesses
660 system.cpu.icache.demand_miss_rate::cpu.inst 0.000924 # miss rate for demand accesses
661 system.cpu.icache.demand_miss_rate::total 0.000924 # miss rate for demand accesses
662 system.cpu.icache.overall_miss_rate::cpu.inst 0.000924 # miss rate for overall accesses
663 system.cpu.icache.overall_miss_rate::total 0.000924 # miss rate for overall accesses
664 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6348.223561 # average ReadReq miss latency
665 system.cpu.icache.ReadReq_avg_miss_latency::total 6348.223561 # average ReadReq miss latency
666 system.cpu.icache.demand_avg_miss_latency::cpu.inst 6348.223561 # average overall miss latency
667 system.cpu.icache.demand_avg_miss_latency::total 6348.223561 # average overall miss latency
668 system.cpu.icache.overall_avg_miss_latency::cpu.inst 6348.223561 # average overall miss latency
669 system.cpu.icache.overall_avg_miss_latency::total 6348.223561 # average overall miss latency
670 system.cpu.icache.blocked_cycles::no_mshrs 296 # number of cycles access was blocked
671 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
672 system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked
673 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
674 system.cpu.icache.avg_blocked_cycles::no_mshrs 59.200000 # average number of cycles each access was blocked
675 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
676 system.cpu.icache.fast_writes 0 # number of fast writes performed
677 system.cpu.icache.cache_copies 0 # number of cache copies performed
678 system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2045 # number of ReadReq MSHR hits
679 system.cpu.icache.ReadReq_mshr_hits::total 2045 # number of ReadReq MSHR hits
680 system.cpu.icache.demand_mshr_hits::cpu.inst 2045 # number of demand (read+write) MSHR hits
681 system.cpu.icache.demand_mshr_hits::total 2045 # number of demand (read+write) MSHR hits
682 system.cpu.icache.overall_mshr_hits::cpu.inst 2045 # number of overall MSHR hits
683 system.cpu.icache.overall_mshr_hits::total 2045 # number of overall MSHR hits
684 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 153045 # number of ReadReq MSHR misses
685 system.cpu.icache.ReadReq_mshr_misses::total 153045 # number of ReadReq MSHR misses
686 system.cpu.icache.demand_mshr_misses::cpu.inst 153045 # number of demand (read+write) MSHR misses
687 system.cpu.icache.demand_mshr_misses::total 153045 # number of demand (read+write) MSHR misses
688 system.cpu.icache.overall_mshr_misses::cpu.inst 153045 # number of overall MSHR misses
689 system.cpu.icache.overall_mshr_misses::total 153045 # number of overall MSHR misses
690 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 588350757 # number of ReadReq MSHR miss cycles
691 system.cpu.icache.ReadReq_mshr_miss_latency::total 588350757 # number of ReadReq MSHR miss cycles
692 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 588350757 # number of demand (read+write) MSHR miss cycles
693 system.cpu.icache.demand_mshr_miss_latency::total 588350757 # number of demand (read+write) MSHR miss cycles
694 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 588350757 # number of overall MSHR miss cycles
695 system.cpu.icache.overall_mshr_miss_latency::total 588350757 # number of overall MSHR miss cycles
696 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000912 # mshr miss rate for ReadReq accesses
697 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000912 # mshr miss rate for ReadReq accesses
698 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000912 # mshr miss rate for demand accesses
699 system.cpu.icache.demand_mshr_miss_rate::total 0.000912 # mshr miss rate for demand accesses
700 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000912 # mshr miss rate for overall accesses
701 system.cpu.icache.overall_mshr_miss_rate::total 0.000912 # mshr miss rate for overall accesses
702 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 3844.299108 # average ReadReq mshr miss latency
703 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 3844.299108 # average ReadReq mshr miss latency
704 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 3844.299108 # average overall mshr miss latency
705 system.cpu.icache.demand_avg_mshr_miss_latency::total 3844.299108 # average overall mshr miss latency
706 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 3844.299108 # average overall mshr miss latency
707 system.cpu.icache.overall_avg_mshr_miss_latency::total 3844.299108 # average overall mshr miss latency
708 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
709 system.cpu.l2cache.tags.replacements 353238 # number of replacements
710 system.cpu.l2cache.tags.tagsinuse 29693.365830 # Cycle average of tags in use
711 system.cpu.l2cache.tags.total_refs 3699378 # Total number of references to valid blocks.
712 system.cpu.l2cache.tags.sampled_refs 385610 # Sample count of references to valid blocks.
713 system.cpu.l2cache.tags.avg_refs 9.593574 # Average number of references to valid blocks.
714 system.cpu.l2cache.tags.warmup_cycle 198448245500 # Cycle when the warmup percentage was hit.
715 system.cpu.l2cache.tags.occ_blocks::writebacks 21154.679974 # Average occupied blocks per requestor
716 system.cpu.l2cache.tags.occ_blocks::cpu.inst 231.567464 # Average occupied blocks per requestor
717 system.cpu.l2cache.tags.occ_blocks::cpu.data 8307.118393 # Average occupied blocks per requestor
718 system.cpu.l2cache.tags.occ_percent::writebacks 0.645590 # Average percentage of cache occupancy
719 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.007067 # Average percentage of cache occupancy
720 system.cpu.l2cache.tags.occ_percent::cpu.data 0.253513 # Average percentage of cache occupancy
721 system.cpu.l2cache.tags.occ_percent::total 0.906170 # Average percentage of cache occupancy
722 system.cpu.l2cache.tags.occ_task_id_blocks::1024 32372 # Occupied blocks per task id
723 system.cpu.l2cache.tags.age_task_id_blocks_1024::0 85 # Occupied blocks per task id
724 system.cpu.l2cache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id
725 system.cpu.l2cache.tags.age_task_id_blocks_1024::2 250 # Occupied blocks per task id
726 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 11726 # Occupied blocks per task id
727 system.cpu.l2cache.tags.age_task_id_blocks_1024::4 20309 # Occupied blocks per task id
728 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987915 # Percentage of cache occupancy per task id
729 system.cpu.l2cache.tags.tag_accesses 41312633 # Number of tag accesses
730 system.cpu.l2cache.tags.data_accesses 41312633 # Number of data accesses
731 system.cpu.l2cache.ReadReq_hits::cpu.inst 4144 # number of ReadReq hits
732 system.cpu.l2cache.ReadReq_hits::cpu.data 1587819 # number of ReadReq hits
733 system.cpu.l2cache.ReadReq_hits::total 1591963 # number of ReadReq hits
734 system.cpu.l2cache.Writeback_hits::writebacks 2331152 # number of Writeback hits
735 system.cpu.l2cache.Writeback_hits::total 2331152 # number of Writeback hits
736 system.cpu.l2cache.UpgradeReq_hits::cpu.data 1571 # number of UpgradeReq hits
737 system.cpu.l2cache.UpgradeReq_hits::total 1571 # number of UpgradeReq hits
738 system.cpu.l2cache.ReadExReq_hits::cpu.data 564647 # number of ReadExReq hits
739 system.cpu.l2cache.ReadExReq_hits::total 564647 # number of ReadExReq hits
740 system.cpu.l2cache.demand_hits::cpu.inst 4144 # number of demand (read+write) hits
741 system.cpu.l2cache.demand_hits::cpu.data 2152466 # number of demand (read+write) hits
742 system.cpu.l2cache.demand_hits::total 2156610 # number of demand (read+write) hits
743 system.cpu.l2cache.overall_hits::cpu.inst 4144 # number of overall hits
744 system.cpu.l2cache.overall_hits::cpu.data 2152466 # number of overall hits
745 system.cpu.l2cache.overall_hits::total 2156610 # number of overall hits
746 system.cpu.l2cache.ReadReq_misses::cpu.inst 3288 # number of ReadReq misses
747 system.cpu.l2cache.ReadReq_misses::cpu.data 175788 # number of ReadReq misses
748 system.cpu.l2cache.ReadReq_misses::total 179076 # number of ReadReq misses
749 system.cpu.l2cache.UpgradeReq_misses::cpu.data 143929 # number of UpgradeReq misses
750 system.cpu.l2cache.UpgradeReq_misses::total 143929 # number of UpgradeReq misses
751 system.cpu.l2cache.ReadExReq_misses::cpu.data 206866 # number of ReadExReq misses
752 system.cpu.l2cache.ReadExReq_misses::total 206866 # number of ReadExReq misses
753 system.cpu.l2cache.demand_misses::cpu.inst 3288 # number of demand (read+write) misses
754 system.cpu.l2cache.demand_misses::cpu.data 382654 # number of demand (read+write) misses
755 system.cpu.l2cache.demand_misses::total 385942 # number of demand (read+write) misses
756 system.cpu.l2cache.overall_misses::cpu.inst 3288 # number of overall misses
757 system.cpu.l2cache.overall_misses::cpu.data 382654 # number of overall misses
758 system.cpu.l2cache.overall_misses::total 385942 # number of overall misses
759 system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 243230500 # number of ReadReq miss cycles
760 system.cpu.l2cache.ReadReq_miss_latency::cpu.data 12860278959 # number of ReadReq miss cycles
761 system.cpu.l2cache.ReadReq_miss_latency::total 13103509459 # number of ReadReq miss cycles
762 system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 7140193 # number of UpgradeReq miss cycles
763 system.cpu.l2cache.UpgradeReq_miss_latency::total 7140193 # number of UpgradeReq miss cycles
764 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 14872236978 # number of ReadExReq miss cycles
765 system.cpu.l2cache.ReadExReq_miss_latency::total 14872236978 # number of ReadExReq miss cycles
766 system.cpu.l2cache.demand_miss_latency::cpu.inst 243230500 # number of demand (read+write) miss cycles
767 system.cpu.l2cache.demand_miss_latency::cpu.data 27732515937 # number of demand (read+write) miss cycles
768 system.cpu.l2cache.demand_miss_latency::total 27975746437 # number of demand (read+write) miss cycles
769 system.cpu.l2cache.overall_miss_latency::cpu.inst 243230500 # number of overall miss cycles
770 system.cpu.l2cache.overall_miss_latency::cpu.data 27732515937 # number of overall miss cycles
771 system.cpu.l2cache.overall_miss_latency::total 27975746437 # number of overall miss cycles
772 system.cpu.l2cache.ReadReq_accesses::cpu.inst 7432 # number of ReadReq accesses(hits+misses)
773 system.cpu.l2cache.ReadReq_accesses::cpu.data 1763607 # number of ReadReq accesses(hits+misses)
774 system.cpu.l2cache.ReadReq_accesses::total 1771039 # number of ReadReq accesses(hits+misses)
775 system.cpu.l2cache.Writeback_accesses::writebacks 2331152 # number of Writeback accesses(hits+misses)
776 system.cpu.l2cache.Writeback_accesses::total 2331152 # number of Writeback accesses(hits+misses)
777 system.cpu.l2cache.UpgradeReq_accesses::cpu.data 145500 # number of UpgradeReq accesses(hits+misses)
778 system.cpu.l2cache.UpgradeReq_accesses::total 145500 # number of UpgradeReq accesses(hits+misses)
779 system.cpu.l2cache.ReadExReq_accesses::cpu.data 771513 # number of ReadExReq accesses(hits+misses)
780 system.cpu.l2cache.ReadExReq_accesses::total 771513 # number of ReadExReq accesses(hits+misses)
781 system.cpu.l2cache.demand_accesses::cpu.inst 7432 # number of demand (read+write) accesses
782 system.cpu.l2cache.demand_accesses::cpu.data 2535120 # number of demand (read+write) accesses
783 system.cpu.l2cache.demand_accesses::total 2542552 # number of demand (read+write) accesses
784 system.cpu.l2cache.overall_accesses::cpu.inst 7432 # number of overall (read+write) accesses
785 system.cpu.l2cache.overall_accesses::cpu.data 2535120 # number of overall (read+write) accesses
786 system.cpu.l2cache.overall_accesses::total 2542552 # number of overall (read+write) accesses
787 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.442411 # miss rate for ReadReq accesses
788 system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.099675 # miss rate for ReadReq accesses
789 system.cpu.l2cache.ReadReq_miss_rate::total 0.101114 # miss rate for ReadReq accesses
790 system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.989203 # miss rate for UpgradeReq accesses
791 system.cpu.l2cache.UpgradeReq_miss_rate::total 0.989203 # miss rate for UpgradeReq accesses
792 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.268130 # miss rate for ReadExReq accesses
793 system.cpu.l2cache.ReadExReq_miss_rate::total 0.268130 # miss rate for ReadExReq accesses
794 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.442411 # miss rate for demand accesses
795 system.cpu.l2cache.demand_miss_rate::cpu.data 0.150941 # miss rate for demand accesses
796 system.cpu.l2cache.demand_miss_rate::total 0.151793 # miss rate for demand accesses
797 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.442411 # miss rate for overall accesses
798 system.cpu.l2cache.overall_miss_rate::cpu.data 0.150941 # miss rate for overall accesses
799 system.cpu.l2cache.overall_miss_rate::total 0.151793 # miss rate for overall accesses
800 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73975.212895 # average ReadReq miss latency
801 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73157.888815 # average ReadReq miss latency
802 system.cpu.l2cache.ReadReq_avg_miss_latency::total 73172.895636 # average ReadReq miss latency
803 system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 49.609134 # average UpgradeReq miss latency
804 system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 49.609134 # average UpgradeReq miss latency
805 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71893.094941 # average ReadExReq miss latency
806 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71893.094941 # average ReadExReq miss latency
807 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73975.212895 # average overall miss latency
808 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72474.130512 # average overall miss latency
809 system.cpu.l2cache.demand_avg_miss_latency::total 72486.918856 # average overall miss latency
810 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73975.212895 # average overall miss latency
811 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72474.130512 # average overall miss latency
812 system.cpu.l2cache.overall_avg_miss_latency::total 72486.918856 # average overall miss latency
813 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
814 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
815 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
816 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
817 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
818 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
819 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
820 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
821 system.cpu.l2cache.writebacks::writebacks 293696 # number of writebacks
822 system.cpu.l2cache.writebacks::total 293696 # number of writebacks
823 system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits
824 system.cpu.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits
825 system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
826 system.cpu.l2cache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits
827 system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
828 system.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits
829 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3287 # number of ReadReq MSHR misses
830 system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 175788 # number of ReadReq MSHR misses
831 system.cpu.l2cache.ReadReq_mshr_misses::total 179075 # number of ReadReq MSHR misses
832 system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 143929 # number of UpgradeReq MSHR misses
833 system.cpu.l2cache.UpgradeReq_mshr_misses::total 143929 # number of UpgradeReq MSHR misses
834 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206866 # number of ReadExReq MSHR misses
835 system.cpu.l2cache.ReadExReq_mshr_misses::total 206866 # number of ReadExReq MSHR misses
836 system.cpu.l2cache.demand_mshr_misses::cpu.inst 3287 # number of demand (read+write) MSHR misses
837 system.cpu.l2cache.demand_mshr_misses::cpu.data 382654 # number of demand (read+write) MSHR misses
838 system.cpu.l2cache.demand_mshr_misses::total 385941 # number of demand (read+write) MSHR misses
839 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3287 # number of overall MSHR misses
840 system.cpu.l2cache.overall_mshr_misses::cpu.data 382654 # number of overall MSHR misses
841 system.cpu.l2cache.overall_mshr_misses::total 385941 # number of overall MSHR misses
842 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 202076500 # number of ReadReq MSHR miss cycles
843 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 10620308959 # number of ReadReq MSHR miss cycles
844 system.cpu.l2cache.ReadReq_mshr_miss_latency::total 10822385459 # number of ReadReq MSHR miss cycles
845 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1446267081 # number of UpgradeReq MSHR miss cycles
846 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1446267081 # number of UpgradeReq MSHR miss cycles
847 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 12245262522 # number of ReadExReq MSHR miss cycles
848 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 12245262522 # number of ReadExReq MSHR miss cycles
849 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 202076500 # number of demand (read+write) MSHR miss cycles
850 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 22865571481 # number of demand (read+write) MSHR miss cycles
851 system.cpu.l2cache.demand_mshr_miss_latency::total 23067647981 # number of demand (read+write) MSHR miss cycles
852 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 202076500 # number of overall MSHR miss cycles
853 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 22865571481 # number of overall MSHR miss cycles
854 system.cpu.l2cache.overall_mshr_miss_latency::total 23067647981 # number of overall MSHR miss cycles
855 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.442277 # mshr miss rate for ReadReq accesses
856 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.099675 # mshr miss rate for ReadReq accesses
857 system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.101113 # mshr miss rate for ReadReq accesses
858 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.989203 # mshr miss rate for UpgradeReq accesses
859 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.989203 # mshr miss rate for UpgradeReq accesses
860 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.268130 # mshr miss rate for ReadExReq accesses
861 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.268130 # mshr miss rate for ReadExReq accesses
862 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.442277 # mshr miss rate for demand accesses
863 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150941 # mshr miss rate for demand accesses
864 system.cpu.l2cache.demand_mshr_miss_rate::total 0.151793 # mshr miss rate for demand accesses
865 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.442277 # mshr miss rate for overall accesses
866 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150941 # mshr miss rate for overall accesses
867 system.cpu.l2cache.overall_mshr_miss_rate::total 0.151793 # mshr miss rate for overall accesses
868 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61477.487070 # average ReadReq mshr miss latency
869 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60415.437681 # average ReadReq mshr miss latency
870 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60434.932062 # average ReadReq mshr miss latency
871 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10048.475853 # average UpgradeReq mshr miss latency
872 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10048.475853 # average UpgradeReq mshr miss latency
873 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59194.176530 # average ReadExReq mshr miss latency
874 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59194.176530 # average ReadExReq mshr miss latency
875 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61477.487070 # average overall mshr miss latency
876 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59755.213538 # average overall mshr miss latency
877 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59769.881876 # average overall mshr miss latency
878 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61477.487070 # average overall mshr miss latency
879 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59755.213538 # average overall mshr miss latency
880 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59769.881876 # average overall mshr miss latency
881 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
882 system.cpu.dcache.tags.replacements 2531024 # number of replacements
883 system.cpu.dcache.tags.tagsinuse 4088.627952 # Cycle average of tags in use
884 system.cpu.dcache.tags.total_refs 389841381 # Total number of references to valid blocks.
885 system.cpu.dcache.tags.sampled_refs 2535120 # Sample count of references to valid blocks.
886 system.cpu.dcache.tags.avg_refs 153.776303 # Average number of references to valid blocks.
887 system.cpu.dcache.tags.warmup_cycle 1681469250 # Cycle when the warmup percentage was hit.
888 system.cpu.dcache.tags.occ_blocks::cpu.data 4088.627952 # Average occupied blocks per requestor
889 system.cpu.dcache.tags.occ_percent::cpu.data 0.998200 # Average percentage of cache occupancy
890 system.cpu.dcache.tags.occ_percent::total 0.998200 # Average percentage of cache occupancy
891 system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
892 system.cpu.dcache.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id
893 system.cpu.dcache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id
894 system.cpu.dcache.tags.age_task_id_blocks_1024::2 738 # Occupied blocks per task id
895 system.cpu.dcache.tags.age_task_id_blocks_1024::3 3313 # Occupied blocks per task id
896 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
897 system.cpu.dcache.tags.tag_accesses 788808720 # Number of tag accesses
898 system.cpu.dcache.tags.data_accesses 788808720 # Number of data accesses
899 system.cpu.dcache.ReadReq_hits::cpu.data 241135682 # number of ReadReq hits
900 system.cpu.dcache.ReadReq_hits::total 241135682 # number of ReadReq hits
901 system.cpu.dcache.WriteReq_hits::cpu.data 148226318 # number of WriteReq hits
902 system.cpu.dcache.WriteReq_hits::total 148226318 # number of WriteReq hits
903 system.cpu.dcache.demand_hits::cpu.data 389362000 # number of demand (read+write) hits
904 system.cpu.dcache.demand_hits::total 389362000 # number of demand (read+write) hits
905 system.cpu.dcache.overall_hits::cpu.data 389362000 # number of overall hits
906 system.cpu.dcache.overall_hits::total 389362000 # number of overall hits
907 system.cpu.dcache.ReadReq_misses::cpu.data 2840916 # number of ReadReq misses
908 system.cpu.dcache.ReadReq_misses::total 2840916 # number of ReadReq misses
909 system.cpu.dcache.WriteReq_misses::cpu.data 933884 # number of WriteReq misses
910 system.cpu.dcache.WriteReq_misses::total 933884 # number of WriteReq misses
911 system.cpu.dcache.demand_misses::cpu.data 3774800 # number of demand (read+write) misses
912 system.cpu.dcache.demand_misses::total 3774800 # number of demand (read+write) misses
913 system.cpu.dcache.overall_misses::cpu.data 3774800 # number of overall misses
914 system.cpu.dcache.overall_misses::total 3774800 # number of overall misses
915 system.cpu.dcache.ReadReq_miss_latency::cpu.data 57099614849 # number of ReadReq miss cycles
916 system.cpu.dcache.ReadReq_miss_latency::total 57099614849 # number of ReadReq miss cycles
917 system.cpu.dcache.WriteReq_miss_latency::cpu.data 26803520330 # number of WriteReq miss cycles
918 system.cpu.dcache.WriteReq_miss_latency::total 26803520330 # number of WriteReq miss cycles
919 system.cpu.dcache.demand_miss_latency::cpu.data 83903135179 # number of demand (read+write) miss cycles
920 system.cpu.dcache.demand_miss_latency::total 83903135179 # number of demand (read+write) miss cycles
921 system.cpu.dcache.overall_miss_latency::cpu.data 83903135179 # number of overall miss cycles
922 system.cpu.dcache.overall_miss_latency::total 83903135179 # number of overall miss cycles
923 system.cpu.dcache.ReadReq_accesses::cpu.data 243976598 # number of ReadReq accesses(hits+misses)
924 system.cpu.dcache.ReadReq_accesses::total 243976598 # number of ReadReq accesses(hits+misses)
925 system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses)
926 system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses)
927 system.cpu.dcache.demand_accesses::cpu.data 393136800 # number of demand (read+write) accesses
928 system.cpu.dcache.demand_accesses::total 393136800 # number of demand (read+write) accesses
929 system.cpu.dcache.overall_accesses::cpu.data 393136800 # number of overall (read+write) accesses
930 system.cpu.dcache.overall_accesses::total 393136800 # number of overall (read+write) accesses
931 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011644 # miss rate for ReadReq accesses
932 system.cpu.dcache.ReadReq_miss_rate::total 0.011644 # miss rate for ReadReq accesses
933 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006261 # miss rate for WriteReq accesses
934 system.cpu.dcache.WriteReq_miss_rate::total 0.006261 # miss rate for WriteReq accesses
935 system.cpu.dcache.demand_miss_rate::cpu.data 0.009602 # miss rate for demand accesses
936 system.cpu.dcache.demand_miss_rate::total 0.009602 # miss rate for demand accesses
937 system.cpu.dcache.overall_miss_rate::cpu.data 0.009602 # miss rate for overall accesses
938 system.cpu.dcache.overall_miss_rate::total 0.009602 # miss rate for overall accesses
939 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20099.015546 # average ReadReq miss latency
940 system.cpu.dcache.ReadReq_avg_miss_latency::total 20099.015546 # average ReadReq miss latency
941 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28701.123833 # average WriteReq miss latency
942 system.cpu.dcache.WriteReq_avg_miss_latency::total 28701.123833 # average WriteReq miss latency
943 system.cpu.dcache.demand_avg_miss_latency::cpu.data 22227.173673 # average overall miss latency
944 system.cpu.dcache.demand_avg_miss_latency::total 22227.173673 # average overall miss latency
945 system.cpu.dcache.overall_avg_miss_latency::cpu.data 22227.173673 # average overall miss latency
946 system.cpu.dcache.overall_avg_miss_latency::total 22227.173673 # average overall miss latency
947 system.cpu.dcache.blocked_cycles::no_mshrs 6549 # number of cycles access was blocked
948 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
949 system.cpu.dcache.blocked::no_mshrs 751 # number of cycles access was blocked
950 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
951 system.cpu.dcache.avg_blocked_cycles::no_mshrs 8.720373 # average number of cycles each access was blocked
952 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
953 system.cpu.dcache.fast_writes 0 # number of fast writes performed
954 system.cpu.dcache.cache_copies 0 # number of cache copies performed
955 system.cpu.dcache.writebacks::writebacks 2331152 # number of writebacks
956 system.cpu.dcache.writebacks::total 2331152 # number of writebacks
957 system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1077049 # number of ReadReq MSHR hits
958 system.cpu.dcache.ReadReq_mshr_hits::total 1077049 # number of ReadReq MSHR hits
959 system.cpu.dcache.WriteReq_mshr_hits::cpu.data 17132 # number of WriteReq MSHR hits
960 system.cpu.dcache.WriteReq_mshr_hits::total 17132 # number of WriteReq MSHR hits
961 system.cpu.dcache.demand_mshr_hits::cpu.data 1094181 # number of demand (read+write) MSHR hits
962 system.cpu.dcache.demand_mshr_hits::total 1094181 # number of demand (read+write) MSHR hits
963 system.cpu.dcache.overall_mshr_hits::cpu.data 1094181 # number of overall MSHR hits
964 system.cpu.dcache.overall_mshr_hits::total 1094181 # number of overall MSHR hits
965 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1763867 # number of ReadReq MSHR misses
966 system.cpu.dcache.ReadReq_mshr_misses::total 1763867 # number of ReadReq MSHR misses
967 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 916752 # number of WriteReq MSHR misses
968 system.cpu.dcache.WriteReq_mshr_misses::total 916752 # number of WriteReq MSHR misses
969 system.cpu.dcache.demand_mshr_misses::cpu.data 2680619 # number of demand (read+write) MSHR misses
970 system.cpu.dcache.demand_mshr_misses::total 2680619 # number of demand (read+write) MSHR misses
971 system.cpu.dcache.overall_mshr_misses::cpu.data 2680619 # number of overall MSHR misses
972 system.cpu.dcache.overall_mshr_misses::total 2680619 # number of overall MSHR misses
973 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30539375250 # number of ReadReq MSHR miss cycles
974 system.cpu.dcache.ReadReq_mshr_miss_latency::total 30539375250 # number of ReadReq MSHR miss cycles
975 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 24659789417 # number of WriteReq MSHR miss cycles
976 system.cpu.dcache.WriteReq_mshr_miss_latency::total 24659789417 # number of WriteReq MSHR miss cycles
977 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 55199164667 # number of demand (read+write) MSHR miss cycles
978 system.cpu.dcache.demand_mshr_miss_latency::total 55199164667 # number of demand (read+write) MSHR miss cycles
979 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 55199164667 # number of overall MSHR miss cycles
980 system.cpu.dcache.overall_mshr_miss_latency::total 55199164667 # number of overall MSHR miss cycles
981 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007230 # mshr miss rate for ReadReq accesses
982 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007230 # mshr miss rate for ReadReq accesses
983 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006146 # mshr miss rate for WriteReq accesses
984 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006146 # mshr miss rate for WriteReq accesses
985 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006819 # mshr miss rate for demand accesses
986 system.cpu.dcache.demand_mshr_miss_rate::total 0.006819 # mshr miss rate for demand accesses
987 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006819 # mshr miss rate for overall accesses
988 system.cpu.dcache.overall_mshr_miss_rate::total 0.006819 # mshr miss rate for overall accesses
989 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17313.876415 # average ReadReq mshr miss latency
990 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17313.876415 # average ReadReq mshr miss latency
991 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26899.084395 # average WriteReq mshr miss latency
992 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26899.084395 # average WriteReq mshr miss latency
993 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20591.947109 # average overall mshr miss latency
994 system.cpu.dcache.demand_avg_mshr_miss_latency::total 20591.947109 # average overall mshr miss latency
995 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20591.947109 # average overall mshr miss latency
996 system.cpu.dcache.overall_avg_mshr_miss_latency::total 20591.947109 # average overall mshr miss latency
997 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
999 ---------- End Simulation Statistics ----------
projects / gem5.git / blob