2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.139926 # Number of seconds simulated
4 sim_ticks 139926186500 # Number of ticks simulated
5 final_tick 139926186500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 122800 # Simulator instruction rate (inst/s)
8 host_op_rate 122800 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 43101138 # Simulator tick rate (ticks/s)
10 host_mem_usage 261428 # Number of bytes of host memory used
11 host_seconds 3246.46 # Real time elapsed on the host
12 sim_insts 398664595 # Number of instructions simulated
13 sim_ops 398664595 # Number of ops (including micro ops) simulated
14 system.physmem.bytes_read::cpu.inst 214976 # Number of bytes read from this memory
15 system.physmem.bytes_read::cpu.data 254016 # Number of bytes read from this memory
16 system.physmem.bytes_read::total 468992 # Number of bytes read from this memory
17 system.physmem.bytes_inst_read::cpu.inst 214976 # Number of instructions bytes read from this memory
18 system.physmem.bytes_inst_read::total 214976 # Number of instructions bytes read from this memory
19 system.physmem.num_reads::cpu.inst 3359 # Number of read requests responded to by this memory
20 system.physmem.num_reads::cpu.data 3969 # Number of read requests responded to by this memory
21 system.physmem.num_reads::total 7328 # Number of read requests responded to by this memory
22 system.physmem.bw_read::cpu.inst 1536353 # Total read bandwidth from this memory (bytes/s)
23 system.physmem.bw_read::cpu.data 1815357 # Total read bandwidth from this memory (bytes/s)
24 system.physmem.bw_read::total 3351710 # Total read bandwidth from this memory (bytes/s)
25 system.physmem.bw_inst_read::cpu.inst 1536353 # Instruction read bandwidth from this memory (bytes/s)
26 system.physmem.bw_inst_read::total 1536353 # Instruction read bandwidth from this memory (bytes/s)
27 system.physmem.bw_total::cpu.inst 1536353 # Total bandwidth to/from this memory (bytes/s)
28 system.physmem.bw_total::cpu.data 1815357 # Total bandwidth to/from this memory (bytes/s)
29 system.physmem.bw_total::total 3351710 # Total bandwidth to/from this memory (bytes/s)
30 system.physmem.readReqs 7328 # Number of read requests accepted
31 system.physmem.writeReqs 0 # Number of write requests accepted
32 system.physmem.readBursts 7328 # Number of DRAM read bursts, including those serviced by the write queue
33 system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
34 system.physmem.bytesReadDRAM 468992 # Total number of bytes read from DRAM
35 system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
36 system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
37 system.physmem.bytesReadSys 468992 # Total read bytes from the system interface side
38 system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
39 system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
40 system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
41 system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
42 system.physmem.perBankRdBursts::0 507 # Per bank write bursts
43 system.physmem.perBankRdBursts::1 643 # Per bank write bursts
44 system.physmem.perBankRdBursts::2 444 # Per bank write bursts
45 system.physmem.perBankRdBursts::3 597 # Per bank write bursts
46 system.physmem.perBankRdBursts::4 448 # Per bank write bursts
47 system.physmem.perBankRdBursts::5 451 # Per bank write bursts
48 system.physmem.perBankRdBursts::6 505 # Per bank write bursts
49 system.physmem.perBankRdBursts::7 513 # Per bank write bursts
50 system.physmem.perBankRdBursts::8 423 # Per bank write bursts
51 system.physmem.perBankRdBursts::9 395 # Per bank write bursts
52 system.physmem.perBankRdBursts::10 336 # Per bank write bursts
53 system.physmem.perBankRdBursts::11 304 # Per bank write bursts
54 system.physmem.perBankRdBursts::12 416 # Per bank write bursts
55 system.physmem.perBankRdBursts::13 534 # Per bank write bursts
56 system.physmem.perBankRdBursts::14 441 # Per bank write bursts
57 system.physmem.perBankRdBursts::15 371 # Per bank write bursts
58 system.physmem.perBankWrBursts::0 0 # Per bank write bursts
59 system.physmem.perBankWrBursts::1 0 # Per bank write bursts
60 system.physmem.perBankWrBursts::2 0 # Per bank write bursts
61 system.physmem.perBankWrBursts::3 0 # Per bank write bursts
62 system.physmem.perBankWrBursts::4 0 # Per bank write bursts
63 system.physmem.perBankWrBursts::5 0 # Per bank write bursts
64 system.physmem.perBankWrBursts::6 0 # Per bank write bursts
65 system.physmem.perBankWrBursts::7 0 # Per bank write bursts
66 system.physmem.perBankWrBursts::8 0 # Per bank write bursts
67 system.physmem.perBankWrBursts::9 0 # Per bank write bursts
68 system.physmem.perBankWrBursts::10 0 # Per bank write bursts
69 system.physmem.perBankWrBursts::11 0 # Per bank write bursts
70 system.physmem.perBankWrBursts::12 0 # Per bank write bursts
71 system.physmem.perBankWrBursts::13 0 # Per bank write bursts
72 system.physmem.perBankWrBursts::14 0 # Per bank write bursts
73 system.physmem.perBankWrBursts::15 0 # Per bank write bursts
74 system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
75 system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
76 system.physmem.totGap 139926113000 # Total gap between requests
77 system.physmem.readPktSize::0 0 # Read request sizes (log2)
78 system.physmem.readPktSize::1 0 # Read request sizes (log2)
79 system.physmem.readPktSize::2 0 # Read request sizes (log2)
80 system.physmem.readPktSize::3 0 # Read request sizes (log2)
81 system.physmem.readPktSize::4 0 # Read request sizes (log2)
82 system.physmem.readPktSize::5 0 # Read request sizes (log2)
83 system.physmem.readPktSize::6 7328 # Read request sizes (log2)
84 system.physmem.writePktSize::0 0 # Write request sizes (log2)
85 system.physmem.writePktSize::1 0 # Write request sizes (log2)
86 system.physmem.writePktSize::2 0 # Write request sizes (log2)
87 system.physmem.writePktSize::3 0 # Write request sizes (log2)
88 system.physmem.writePktSize::4 0 # Write request sizes (log2)
89 system.physmem.writePktSize::5 0 # Write request sizes (log2)
90 system.physmem.writePktSize::6 0 # Write request sizes (log2)
91 system.physmem.rdQLenPdf::0 4635 # What read queue length does an incoming req see
92 system.physmem.rdQLenPdf::1 1820 # What read queue length does an incoming req see
93 system.physmem.rdQLenPdf::2 581 # What read queue length does an incoming req see
94 system.physmem.rdQLenPdf::3 229 # What read queue length does an incoming req see
95 system.physmem.rdQLenPdf::4 62 # What read queue length does an incoming req see
96 system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
97 system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
98 system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
99 system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
100 system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
101 system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
102 system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
103 system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
104 system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
105 system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
106 system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
107 system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
108 system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
109 system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
110 system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
111 system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
112 system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
113 system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
114 system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
115 system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
116 system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
117 system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
118 system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
119 system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
120 system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
121 system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
122 system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
123 system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
124 system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
125 system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
126 system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
127 system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
128 system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
129 system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
130 system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
131 system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
132 system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
133 system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
134 system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
135 system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
136 system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
137 system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
138 system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
139 system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
140 system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
141 system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
142 system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
143 system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
144 system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
145 system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
146 system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
147 system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
148 system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
149 system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
150 system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
151 system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
152 system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
153 system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
154 system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
155 system.physmem.bytesPerActivate::samples 1198 # Bytes accessed per row activation
156 system.physmem.bytesPerActivate::mean 387.899833 # Bytes accessed per row activation
157 system.physmem.bytesPerActivate::gmean 185.568922 # Bytes accessed per row activation
158 system.physmem.bytesPerActivate::stdev 772.018563 # Bytes accessed per row activation
159 system.physmem.bytesPerActivate::64-65 419 34.97% 34.97% # Bytes accessed per row activation
160 system.physmem.bytesPerActivate::128-129 201 16.78% 51.75% # Bytes accessed per row activation
161 system.physmem.bytesPerActivate::192-193 128 10.68% 62.44% # Bytes accessed per row activation
162 system.physmem.bytesPerActivate::256-257 91 7.60% 70.03% # Bytes accessed per row activation
163 system.physmem.bytesPerActivate::320-321 61 5.09% 75.13% # Bytes accessed per row activation
164 system.physmem.bytesPerActivate::384-385 40 3.34% 78.46% # Bytes accessed per row activation
165 system.physmem.bytesPerActivate::448-449 30 2.50% 80.97% # Bytes accessed per row activation
166 system.physmem.bytesPerActivate::512-513 22 1.84% 82.80% # Bytes accessed per row activation
167 system.physmem.bytesPerActivate::576-577 25 2.09% 84.89% # Bytes accessed per row activation
168 system.physmem.bytesPerActivate::640-641 18 1.50% 86.39% # Bytes accessed per row activation
169 system.physmem.bytesPerActivate::704-705 20 1.67% 88.06% # Bytes accessed per row activation
170 system.physmem.bytesPerActivate::768-769 8 0.67% 88.73% # Bytes accessed per row activation
171 system.physmem.bytesPerActivate::832-833 17 1.42% 90.15% # Bytes accessed per row activation
172 system.physmem.bytesPerActivate::896-897 10 0.83% 90.98% # Bytes accessed per row activation
173 system.physmem.bytesPerActivate::960-961 8 0.67% 91.65% # Bytes accessed per row activation
174 system.physmem.bytesPerActivate::1024-1025 6 0.50% 92.15% # Bytes accessed per row activation
175 system.physmem.bytesPerActivate::1088-1089 10 0.83% 92.99% # Bytes accessed per row activation
176 system.physmem.bytesPerActivate::1152-1153 7 0.58% 93.57% # Bytes accessed per row activation
177 system.physmem.bytesPerActivate::1216-1217 7 0.58% 94.16% # Bytes accessed per row activation
178 system.physmem.bytesPerActivate::1280-1281 1 0.08% 94.24% # Bytes accessed per row activation
179 system.physmem.bytesPerActivate::1344-1345 4 0.33% 94.57% # Bytes accessed per row activation
180 system.physmem.bytesPerActivate::1408-1409 4 0.33% 94.91% # Bytes accessed per row activation
181 system.physmem.bytesPerActivate::1472-1473 2 0.17% 95.08% # Bytes accessed per row activation
182 system.physmem.bytesPerActivate::1536-1537 5 0.42% 95.49% # Bytes accessed per row activation
183 system.physmem.bytesPerActivate::1600-1601 5 0.42% 95.91% # Bytes accessed per row activation
184 system.physmem.bytesPerActivate::1664-1665 4 0.33% 96.24% # Bytes accessed per row activation
185 system.physmem.bytesPerActivate::1728-1729 1 0.08% 96.33% # Bytes accessed per row activation
186 system.physmem.bytesPerActivate::1792-1793 2 0.17% 96.49% # Bytes accessed per row activation
187 system.physmem.bytesPerActivate::1856-1857 1 0.08% 96.58% # Bytes accessed per row activation
188 system.physmem.bytesPerActivate::1984-1985 2 0.17% 96.74% # Bytes accessed per row activation
189 system.physmem.bytesPerActivate::2048-2049 1 0.08% 96.83% # Bytes accessed per row activation
190 system.physmem.bytesPerActivate::2112-2113 2 0.17% 96.99% # Bytes accessed per row activation
191 system.physmem.bytesPerActivate::2176-2177 1 0.08% 97.08% # Bytes accessed per row activation
192 system.physmem.bytesPerActivate::2240-2241 1 0.08% 97.16% # Bytes accessed per row activation
193 system.physmem.bytesPerActivate::2304-2305 2 0.17% 97.33% # Bytes accessed per row activation
194 system.physmem.bytesPerActivate::2368-2369 1 0.08% 97.41% # Bytes accessed per row activation
195 system.physmem.bytesPerActivate::2432-2433 1 0.08% 97.50% # Bytes accessed per row activation
196 system.physmem.bytesPerActivate::2496-2497 4 0.33% 97.83% # Bytes accessed per row activation
197 system.physmem.bytesPerActivate::2560-2561 2 0.17% 98.00% # Bytes accessed per row activation
198 system.physmem.bytesPerActivate::2624-2625 1 0.08% 98.08% # Bytes accessed per row activation
199 system.physmem.bytesPerActivate::2688-2689 2 0.17% 98.25% # Bytes accessed per row activation
200 system.physmem.bytesPerActivate::2752-2753 1 0.08% 98.33% # Bytes accessed per row activation
201 system.physmem.bytesPerActivate::2816-2817 1 0.08% 98.41% # Bytes accessed per row activation
202 system.physmem.bytesPerActivate::2880-2881 1 0.08% 98.50% # Bytes accessed per row activation
203 system.physmem.bytesPerActivate::3008-3009 2 0.17% 98.66% # Bytes accessed per row activation
204 system.physmem.bytesPerActivate::3136-3137 1 0.08% 98.75% # Bytes accessed per row activation
205 system.physmem.bytesPerActivate::3200-3201 1 0.08% 98.83% # Bytes accessed per row activation
206 system.physmem.bytesPerActivate::3456-3457 1 0.08% 98.91% # Bytes accessed per row activation
207 system.physmem.bytesPerActivate::3584-3585 1 0.08% 99.00% # Bytes accessed per row activation
208 system.physmem.bytesPerActivate::4032-4033 1 0.08% 99.08% # Bytes accessed per row activation
209 system.physmem.bytesPerActivate::4224-4225 1 0.08% 99.17% # Bytes accessed per row activation
210 system.physmem.bytesPerActivate::4544-4545 1 0.08% 99.25% # Bytes accessed per row activation
211 system.physmem.bytesPerActivate::5056-5057 1 0.08% 99.33% # Bytes accessed per row activation
212 system.physmem.bytesPerActivate::5376-5377 1 0.08% 99.42% # Bytes accessed per row activation
213 system.physmem.bytesPerActivate::5440-5441 1 0.08% 99.50% # Bytes accessed per row activation
214 system.physmem.bytesPerActivate::6528-6529 1 0.08% 99.58% # Bytes accessed per row activation
215 system.physmem.bytesPerActivate::7104-7105 1 0.08% 99.67% # Bytes accessed per row activation
216 system.physmem.bytesPerActivate::7616-7617 1 0.08% 99.75% # Bytes accessed per row activation
217 system.physmem.bytesPerActivate::8128-8129 1 0.08% 99.83% # Bytes accessed per row activation
218 system.physmem.bytesPerActivate::8192-8193 2 0.17% 100.00% # Bytes accessed per row activation
219 system.physmem.bytesPerActivate::total 1198 # Bytes accessed per row activation
220 system.physmem.totQLat 59880500 # Total ticks spent queuing
221 system.physmem.totMemAccLat 197624250 # Total ticks spent from burst creation until serviced by the DRAM
222 system.physmem.totBusLat 36640000 # Total ticks spent in databus transfers
223 system.physmem.totBankLat 101103750 # Total ticks spent accessing banks
224 system.physmem.avgQLat 8171.47 # Average queueing delay per DRAM burst
225 system.physmem.avgBankLat 13796.91 # Average bank access latency per DRAM burst
226 system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
227 system.physmem.avgMemAccLat 26968.37 # Average memory access latency per DRAM burst
228 system.physmem.avgRdBW 3.35 # Average DRAM read bandwidth in MiByte/s
229 system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
230 system.physmem.avgRdBWSys 3.35 # Average system read bandwidth in MiByte/s
231 system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
232 system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
233 system.physmem.busUtil 0.03 # Data bus utilization in percentage
234 system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads
235 system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
236 system.physmem.avgRdQLen 0.00 # Average read queue length when enqueuing
237 system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
238 system.physmem.readRowHits 6130 # Number of row buffer hits during reads
239 system.physmem.writeRowHits 0 # Number of row buffer hits during writes
240 system.physmem.readRowHitRate 83.65 # Row buffer hit rate for reads
241 system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
242 system.physmem.avgGap 19094720.66 # Average gap between requests
243 system.physmem.pageHitRate 83.65 # Row buffer hit rate, read and write combined
244 system.physmem.prechargeAllPercent 0.42 # Percentage of time for which DRAM has all the banks in precharge state
245 system.membus.throughput 3351710 # Throughput (bytes/s)
246 system.membus.trans_dist::ReadReq 4183 # Transaction distribution
247 system.membus.trans_dist::ReadResp 4183 # Transaction distribution
248 system.membus.trans_dist::ReadExReq 3145 # Transaction distribution
249 system.membus.trans_dist::ReadExResp 3145 # Transaction distribution
250 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14656 # Packet count per connected master and slave (bytes)
251 system.membus.pkt_count::total 14656 # Packet count per connected master and slave (bytes)
252 system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 468992 # Cumulative packet size per connected master and slave (bytes)
253 system.membus.tot_pkt_size::total 468992 # Cumulative packet size per connected master and slave (bytes)
254 system.membus.data_through_bus 468992 # Total data (bytes)
255 system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
256 system.membus.reqLayer0.occupancy 8743500 # Layer occupancy (ticks)
257 system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
258 system.membus.respLayer1.occupancy 68145750 # Layer occupancy (ticks)
259 system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
260 system.cpu.branchPred.lookups 53489673 # Number of BP lookups
261 system.cpu.branchPred.condPredicted 30685396 # Number of conditional branches predicted
262 system.cpu.branchPred.condIncorrect 15149659 # Number of conditional branches incorrect
263 system.cpu.branchPred.BTBLookups 32882350 # Number of BTB lookups
264 system.cpu.branchPred.BTBHits 15212538 # Number of BTB hits
265 system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
266 system.cpu.branchPred.BTBHitPct 46.263537 # BTB Hit Percentage
267 system.cpu.branchPred.usedRAS 8007516 # Number of times the RAS was used to get a target.
268 system.cpu.branchPred.RASInCorrect 20 # Number of incorrect RAS predictions.
269 system.cpu.dtb.fetch_hits 0 # ITB hits
270 system.cpu.dtb.fetch_misses 0 # ITB misses
271 system.cpu.dtb.fetch_acv 0 # ITB acv
272 system.cpu.dtb.fetch_accesses 0 # ITB accesses
273 system.cpu.dtb.read_hits 94754637 # DTB read hits
274 system.cpu.dtb.read_misses 21 # DTB read misses
275 system.cpu.dtb.read_acv 0 # DTB read access violations
276 system.cpu.dtb.read_accesses 94754658 # DTB read accesses
277 system.cpu.dtb.write_hits 73521124 # DTB write hits
278 system.cpu.dtb.write_misses 35 # DTB write misses
279 system.cpu.dtb.write_acv 0 # DTB write access violations
280 system.cpu.dtb.write_accesses 73521159 # DTB write accesses
281 system.cpu.dtb.data_hits 168275761 # DTB hits
282 system.cpu.dtb.data_misses 56 # DTB misses
283 system.cpu.dtb.data_acv 0 # DTB access violations
284 system.cpu.dtb.data_accesses 168275817 # DTB accesses
285 system.cpu.itb.fetch_hits 48611324 # ITB hits
286 system.cpu.itb.fetch_misses 44520 # ITB misses
287 system.cpu.itb.fetch_acv 0 # ITB acv
288 system.cpu.itb.fetch_accesses 48655844 # ITB accesses
289 system.cpu.itb.read_hits 0 # DTB read hits
290 system.cpu.itb.read_misses 0 # DTB read misses
291 system.cpu.itb.read_acv 0 # DTB read access violations
292 system.cpu.itb.read_accesses 0 # DTB read accesses
293 system.cpu.itb.write_hits 0 # DTB write hits
294 system.cpu.itb.write_misses 0 # DTB write misses
295 system.cpu.itb.write_acv 0 # DTB write access violations
296 system.cpu.itb.write_accesses 0 # DTB write accesses
297 system.cpu.itb.data_hits 0 # DTB hits
298 system.cpu.itb.data_misses 0 # DTB misses
299 system.cpu.itb.data_acv 0 # DTB access violations
300 system.cpu.itb.data_accesses 0 # DTB accesses
301 system.cpu.workload.num_syscalls 215 # Number of system calls
302 system.cpu.numCycles 279852374 # number of cpu cycles simulated
303 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
304 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
305 system.cpu.branch_predictor.predictedTaken 29230505 # Number of Branches Predicted As Taken (True).
306 system.cpu.branch_predictor.predictedNotTaken 24259168 # Number of Branches Predicted As Not Taken (False).
307 system.cpu.regfile_manager.intRegFileReads 280386579 # Number of Reads from Int. Register File
308 system.cpu.regfile_manager.intRegFileWrites 159335859 # Number of Writes to Int. Register File
309 system.cpu.regfile_manager.intRegFileAccesses 439722438 # Total Accesses (Read+Write) to the Int. Register File
310 system.cpu.regfile_manager.floatRegFileReads 119631950 # Number of Reads from FP Register File
311 system.cpu.regfile_manager.floatRegFileWrites 100196481 # Number of Writes to FP Register File
312 system.cpu.regfile_manager.floatRegFileAccesses 219828431 # Total Accesses (Read+Write) to the FP Register File
313 system.cpu.regfile_manager.regForwards 100484574 # Number of Registers Read Through Forwarding Logic
314 system.cpu.agen_unit.agens 168485322 # Number of Address Generations
315 system.cpu.execution_unit.predictedTakenIncorrect 14315634 # Number of Branches Incorrectly Predicted As Taken.
316 system.cpu.execution_unit.predictedNotTakenIncorrect 833366 # Number of Branches Incorrectly Predicted As Not Taken).
317 system.cpu.execution_unit.mispredicted 15149000 # Number of Branches Incorrectly Predicted
318 system.cpu.execution_unit.predicted 29438551 # Number of Branches Incorrectly Predicted
319 system.cpu.execution_unit.mispredictPct 33.975851 # Percentage of Incorrect Branches Predicts
320 system.cpu.execution_unit.executions 205475782 # Number of Instructions Executed.
321 system.cpu.mult_div_unit.multiplies 2124323 # Number of Multipy Operations Executed
322 system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
323 system.cpu.contextSwitches 1 # Number of context switches
324 system.cpu.threadCycles 279400617 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
325 system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
326 system.cpu.timesIdled 7206 # Number of times that the entire CPU went into an idle state and unscheduled itself
327 system.cpu.idleCycles 13545708 # Number of cycles cpu's stages were not processed
328 system.cpu.runCycles 266306666 # Number of cycles cpu stages are processed.
329 system.cpu.activity 95.159695 # Percentage of cycles cpu is active
330 system.cpu.comLoads 94754489 # Number of Load instructions committed
331 system.cpu.comStores 73520729 # Number of Store instructions committed
332 system.cpu.comBranches 44587532 # Number of Branches instructions committed
333 system.cpu.comNops 23089775 # Number of Nop instructions committed
334 system.cpu.comNonSpec 215 # Number of Non-Speculative instructions committed
335 system.cpu.comInts 112239074 # Number of Integer instructions committed
336 system.cpu.comFloats 50439198 # Number of Floating Point instructions committed
337 system.cpu.committedInsts 398664595 # Number of Instructions committed (Per-Thread)
338 system.cpu.committedOps 398664595 # Number of Ops committed (Per-Thread)
339 system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
340 system.cpu.committedInsts_total 398664595 # Number of Instructions committed (Total)
341 system.cpu.cpi 0.701974 # CPI: Cycles Per Instruction (Per-Thread)
342 system.cpu.smt_cpi nan # CPI: Total SMT-CPI
343 system.cpu.cpi_total 0.701974 # CPI: Total CPI of All Threads
344 system.cpu.ipc 1.424553 # IPC: Instructions Per Cycle (Per-Thread)
345 system.cpu.smt_ipc nan # IPC: Total SMT-IPC
346 system.cpu.ipc_total 1.424553 # IPC: Total IPC of All Threads
347 system.cpu.stage0.idleCycles 78104700 # Number of cycles 0 instructions are processed.
348 system.cpu.stage0.runCycles 201747674 # Number of cycles 1+ instructions are processed.
349 system.cpu.stage0.utilization 72.090750 # Percentage of cycles stage was utilized (processing insts).
350 system.cpu.stage1.idleCycles 107200641 # Number of cycles 0 instructions are processed.
351 system.cpu.stage1.runCycles 172651733 # Number of cycles 1+ instructions are processed.
352 system.cpu.stage1.utilization 61.693860 # Percentage of cycles stage was utilized (processing insts).
353 system.cpu.stage2.idleCycles 102637143 # Number of cycles 0 instructions are processed.
354 system.cpu.stage2.runCycles 177215231 # Number of cycles 1+ instructions are processed.
355 system.cpu.stage2.utilization 63.324541 # Percentage of cycles stage was utilized (processing insts).
356 system.cpu.stage3.idleCycles 181107759 # Number of cycles 0 instructions are processed.
357 system.cpu.stage3.runCycles 98744615 # Number of cycles 1+ instructions are processed.
358 system.cpu.stage3.utilization 35.284537 # Percentage of cycles stage was utilized (processing insts).
359 system.cpu.stage4.idleCycles 90384394 # Number of cycles 0 instructions are processed.
360 system.cpu.stage4.runCycles 189467980 # Number of cycles 1+ instructions are processed.
361 system.cpu.stage4.utilization 67.702831 # Percentage of cycles stage was utilized (processing insts).
362 system.cpu.icache.tags.replacements 1975 # number of replacements
363 system.cpu.icache.tags.tagsinuse 1830.939408 # Cycle average of tags in use
364 system.cpu.icache.tags.total_refs 48606790 # Total number of references to valid blocks.
365 system.cpu.icache.tags.sampled_refs 3903 # Sample count of references to valid blocks.
366 system.cpu.icache.tags.avg_refs 12453.699718 # Average number of references to valid blocks.
367 system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
368 system.cpu.icache.tags.occ_blocks::cpu.inst 1830.939408 # Average occupied blocks per requestor
369 system.cpu.icache.tags.occ_percent::cpu.inst 0.894013 # Average percentage of cache occupancy
370 system.cpu.icache.tags.occ_percent::total 0.894013 # Average percentage of cache occupancy
371 system.cpu.icache.ReadReq_hits::cpu.inst 48606790 # number of ReadReq hits
372 system.cpu.icache.ReadReq_hits::total 48606790 # number of ReadReq hits
373 system.cpu.icache.demand_hits::cpu.inst 48606790 # number of demand (read+write) hits
374 system.cpu.icache.demand_hits::total 48606790 # number of demand (read+write) hits
375 system.cpu.icache.overall_hits::cpu.inst 48606790 # number of overall hits
376 system.cpu.icache.overall_hits::total 48606790 # number of overall hits
377 system.cpu.icache.ReadReq_misses::cpu.inst 4534 # number of ReadReq misses
378 system.cpu.icache.ReadReq_misses::total 4534 # number of ReadReq misses
379 system.cpu.icache.demand_misses::cpu.inst 4534 # number of demand (read+write) misses
380 system.cpu.icache.demand_misses::total 4534 # number of demand (read+write) misses
381 system.cpu.icache.overall_misses::cpu.inst 4534 # number of overall misses
382 system.cpu.icache.overall_misses::total 4534 # number of overall misses
383 system.cpu.icache.ReadReq_miss_latency::cpu.inst 280061250 # number of ReadReq miss cycles
384 system.cpu.icache.ReadReq_miss_latency::total 280061250 # number of ReadReq miss cycles
385 system.cpu.icache.demand_miss_latency::cpu.inst 280061250 # number of demand (read+write) miss cycles
386 system.cpu.icache.demand_miss_latency::total 280061250 # number of demand (read+write) miss cycles
387 system.cpu.icache.overall_miss_latency::cpu.inst 280061250 # number of overall miss cycles
388 system.cpu.icache.overall_miss_latency::total 280061250 # number of overall miss cycles
389 system.cpu.icache.ReadReq_accesses::cpu.inst 48611324 # number of ReadReq accesses(hits+misses)
390 system.cpu.icache.ReadReq_accesses::total 48611324 # number of ReadReq accesses(hits+misses)
391 system.cpu.icache.demand_accesses::cpu.inst 48611324 # number of demand (read+write) accesses
392 system.cpu.icache.demand_accesses::total 48611324 # number of demand (read+write) accesses
393 system.cpu.icache.overall_accesses::cpu.inst 48611324 # number of overall (read+write) accesses
394 system.cpu.icache.overall_accesses::total 48611324 # number of overall (read+write) accesses
395 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000093 # miss rate for ReadReq accesses
396 system.cpu.icache.ReadReq_miss_rate::total 0.000093 # miss rate for ReadReq accesses
397 system.cpu.icache.demand_miss_rate::cpu.inst 0.000093 # miss rate for demand accesses
398 system.cpu.icache.demand_miss_rate::total 0.000093 # miss rate for demand accesses
399 system.cpu.icache.overall_miss_rate::cpu.inst 0.000093 # miss rate for overall accesses
400 system.cpu.icache.overall_miss_rate::total 0.000093 # miss rate for overall accesses
401 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61769.133216 # average ReadReq miss latency
402 system.cpu.icache.ReadReq_avg_miss_latency::total 61769.133216 # average ReadReq miss latency
403 system.cpu.icache.demand_avg_miss_latency::cpu.inst 61769.133216 # average overall miss latency
404 system.cpu.icache.demand_avg_miss_latency::total 61769.133216 # average overall miss latency
405 system.cpu.icache.overall_avg_miss_latency::cpu.inst 61769.133216 # average overall miss latency
406 system.cpu.icache.overall_avg_miss_latency::total 61769.133216 # average overall miss latency
407 system.cpu.icache.blocked_cycles::no_mshrs 330 # number of cycles access was blocked
408 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
409 system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked
410 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
411 system.cpu.icache.avg_blocked_cycles::no_mshrs 110 # average number of cycles each access was blocked
412 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
413 system.cpu.icache.fast_writes 0 # number of fast writes performed
414 system.cpu.icache.cache_copies 0 # number of cache copies performed
415 system.cpu.icache.ReadReq_mshr_hits::cpu.inst 631 # number of ReadReq MSHR hits
416 system.cpu.icache.ReadReq_mshr_hits::total 631 # number of ReadReq MSHR hits
417 system.cpu.icache.demand_mshr_hits::cpu.inst 631 # number of demand (read+write) MSHR hits
418 system.cpu.icache.demand_mshr_hits::total 631 # number of demand (read+write) MSHR hits
419 system.cpu.icache.overall_mshr_hits::cpu.inst 631 # number of overall MSHR hits
420 system.cpu.icache.overall_mshr_hits::total 631 # number of overall MSHR hits
421 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 3903 # number of ReadReq MSHR misses
422 system.cpu.icache.ReadReq_mshr_misses::total 3903 # number of ReadReq MSHR misses
423 system.cpu.icache.demand_mshr_misses::cpu.inst 3903 # number of demand (read+write) MSHR misses
424 system.cpu.icache.demand_mshr_misses::total 3903 # number of demand (read+write) MSHR misses
425 system.cpu.icache.overall_mshr_misses::cpu.inst 3903 # number of overall MSHR misses
426 system.cpu.icache.overall_mshr_misses::total 3903 # number of overall MSHR misses
427 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 244179750 # number of ReadReq MSHR miss cycles
428 system.cpu.icache.ReadReq_mshr_miss_latency::total 244179750 # number of ReadReq MSHR miss cycles
429 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 244179750 # number of demand (read+write) MSHR miss cycles
430 system.cpu.icache.demand_mshr_miss_latency::total 244179750 # number of demand (read+write) MSHR miss cycles
431 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 244179750 # number of overall MSHR miss cycles
432 system.cpu.icache.overall_mshr_miss_latency::total 244179750 # number of overall MSHR miss cycles
433 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for ReadReq accesses
434 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000080 # mshr miss rate for ReadReq accesses
435 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for demand accesses
436 system.cpu.icache.demand_mshr_miss_rate::total 0.000080 # mshr miss rate for demand accesses
437 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for overall accesses
438 system.cpu.icache.overall_mshr_miss_rate::total 0.000080 # mshr miss rate for overall accesses
439 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 62562.067640 # average ReadReq mshr miss latency
440 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 62562.067640 # average ReadReq mshr miss latency
441 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 62562.067640 # average overall mshr miss latency
442 system.cpu.icache.demand_avg_mshr_miss_latency::total 62562.067640 # average overall mshr miss latency
443 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 62562.067640 # average overall mshr miss latency
444 system.cpu.icache.overall_avg_mshr_miss_latency::total 62562.067640 # average overall mshr miss latency
445 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
446 system.cpu.toL2Bus.throughput 3981070 # Throughput (bytes/s)
447 system.cpu.toL2Bus.trans_dist::ReadReq 4850 # Transaction distribution
448 system.cpu.toL2Bus.trans_dist::ReadResp 4850 # Transaction distribution
449 system.cpu.toL2Bus.trans_dist::Writeback 649 # Transaction distribution
450 system.cpu.toL2Bus.trans_dist::ReadExReq 3205 # Transaction distribution
451 system.cpu.toL2Bus.trans_dist::ReadExResp 3205 # Transaction distribution
452 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 7806 # Packet count per connected master and slave (bytes)
453 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8953 # Packet count per connected master and slave (bytes)
454 system.cpu.toL2Bus.pkt_count::total 16759 # Packet count per connected master and slave (bytes)
455 system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 249792 # Cumulative packet size per connected master and slave (bytes)
456 system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 307264 # Cumulative packet size per connected master and slave (bytes)
457 system.cpu.toL2Bus.tot_pkt_size::total 557056 # Cumulative packet size per connected master and slave (bytes)
458 system.cpu.toL2Bus.data_through_bus 557056 # Total data (bytes)
459 system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
460 system.cpu.toL2Bus.reqLayer0.occupancy 5001000 # Layer occupancy (ticks)
461 system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
462 system.cpu.toL2Bus.respLayer0.occupancy 6459750 # Layer occupancy (ticks)
463 system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
464 system.cpu.toL2Bus.respLayer1.occupancy 6671999 # Layer occupancy (ticks)
465 system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
466 system.cpu.l2cache.tags.replacements 0 # number of replacements
467 system.cpu.l2cache.tags.tagsinuse 3906.845611 # Cycle average of tags in use
468 system.cpu.l2cache.tags.total_refs 753 # Total number of references to valid blocks.
469 system.cpu.l2cache.tags.sampled_refs 4717 # Sample count of references to valid blocks.
470 system.cpu.l2cache.tags.avg_refs 0.159635 # Average number of references to valid blocks.
471 system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
472 system.cpu.l2cache.tags.occ_blocks::writebacks 370.534640 # Average occupied blocks per requestor
473 system.cpu.l2cache.tags.occ_blocks::cpu.inst 2908.739390 # Average occupied blocks per requestor
474 system.cpu.l2cache.tags.occ_blocks::cpu.data 627.571581 # Average occupied blocks per requestor
475 system.cpu.l2cache.tags.occ_percent::writebacks 0.011308 # Average percentage of cache occupancy
476 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.088768 # Average percentage of cache occupancy
477 system.cpu.l2cache.tags.occ_percent::cpu.data 0.019152 # Average percentage of cache occupancy
478 system.cpu.l2cache.tags.occ_percent::total 0.119227 # Average percentage of cache occupancy
479 system.cpu.l2cache.ReadReq_hits::cpu.inst 544 # number of ReadReq hits
480 system.cpu.l2cache.ReadReq_hits::cpu.data 123 # number of ReadReq hits
481 system.cpu.l2cache.ReadReq_hits::total 667 # number of ReadReq hits
482 system.cpu.l2cache.Writeback_hits::writebacks 649 # number of Writeback hits
483 system.cpu.l2cache.Writeback_hits::total 649 # number of Writeback hits
484 system.cpu.l2cache.ReadExReq_hits::cpu.data 60 # number of ReadExReq hits
485 system.cpu.l2cache.ReadExReq_hits::total 60 # number of ReadExReq hits
486 system.cpu.l2cache.demand_hits::cpu.inst 544 # number of demand (read+write) hits
487 system.cpu.l2cache.demand_hits::cpu.data 183 # number of demand (read+write) hits
488 system.cpu.l2cache.demand_hits::total 727 # number of demand (read+write) hits
489 system.cpu.l2cache.overall_hits::cpu.inst 544 # number of overall hits
490 system.cpu.l2cache.overall_hits::cpu.data 183 # number of overall hits
491 system.cpu.l2cache.overall_hits::total 727 # number of overall hits
492 system.cpu.l2cache.ReadReq_misses::cpu.inst 3359 # number of ReadReq misses
493 system.cpu.l2cache.ReadReq_misses::cpu.data 824 # number of ReadReq misses
494 system.cpu.l2cache.ReadReq_misses::total 4183 # number of ReadReq misses
495 system.cpu.l2cache.ReadExReq_misses::cpu.data 3145 # number of ReadExReq misses
496 system.cpu.l2cache.ReadExReq_misses::total 3145 # number of ReadExReq misses
497 system.cpu.l2cache.demand_misses::cpu.inst 3359 # number of demand (read+write) misses
498 system.cpu.l2cache.demand_misses::cpu.data 3969 # number of demand (read+write) misses
499 system.cpu.l2cache.demand_misses::total 7328 # number of demand (read+write) misses
500 system.cpu.l2cache.overall_misses::cpu.inst 3359 # number of overall misses
501 system.cpu.l2cache.overall_misses::cpu.data 3969 # number of overall misses
502 system.cpu.l2cache.overall_misses::total 7328 # number of overall misses
503 system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 234790750 # number of ReadReq miss cycles
504 system.cpu.l2cache.ReadReq_miss_latency::cpu.data 62080250 # number of ReadReq miss cycles
505 system.cpu.l2cache.ReadReq_miss_latency::total 296871000 # number of ReadReq miss cycles
506 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 227075250 # number of ReadExReq miss cycles
507 system.cpu.l2cache.ReadExReq_miss_latency::total 227075250 # number of ReadExReq miss cycles
508 system.cpu.l2cache.demand_miss_latency::cpu.inst 234790750 # number of demand (read+write) miss cycles
509 system.cpu.l2cache.demand_miss_latency::cpu.data 289155500 # number of demand (read+write) miss cycles
510 system.cpu.l2cache.demand_miss_latency::total 523946250 # number of demand (read+write) miss cycles
511 system.cpu.l2cache.overall_miss_latency::cpu.inst 234790750 # number of overall miss cycles
512 system.cpu.l2cache.overall_miss_latency::cpu.data 289155500 # number of overall miss cycles
513 system.cpu.l2cache.overall_miss_latency::total 523946250 # number of overall miss cycles
514 system.cpu.l2cache.ReadReq_accesses::cpu.inst 3903 # number of ReadReq accesses(hits+misses)
515 system.cpu.l2cache.ReadReq_accesses::cpu.data 947 # number of ReadReq accesses(hits+misses)
516 system.cpu.l2cache.ReadReq_accesses::total 4850 # number of ReadReq accesses(hits+misses)
517 system.cpu.l2cache.Writeback_accesses::writebacks 649 # number of Writeback accesses(hits+misses)
518 system.cpu.l2cache.Writeback_accesses::total 649 # number of Writeback accesses(hits+misses)
519 system.cpu.l2cache.ReadExReq_accesses::cpu.data 3205 # number of ReadExReq accesses(hits+misses)
520 system.cpu.l2cache.ReadExReq_accesses::total 3205 # number of ReadExReq accesses(hits+misses)
521 system.cpu.l2cache.demand_accesses::cpu.inst 3903 # number of demand (read+write) accesses
522 system.cpu.l2cache.demand_accesses::cpu.data 4152 # number of demand (read+write) accesses
523 system.cpu.l2cache.demand_accesses::total 8055 # number of demand (read+write) accesses
524 system.cpu.l2cache.overall_accesses::cpu.inst 3903 # number of overall (read+write) accesses
525 system.cpu.l2cache.overall_accesses::cpu.data 4152 # number of overall (read+write) accesses
526 system.cpu.l2cache.overall_accesses::total 8055 # number of overall (read+write) accesses
527 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.860620 # miss rate for ReadReq accesses
528 system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.870116 # miss rate for ReadReq accesses
529 system.cpu.l2cache.ReadReq_miss_rate::total 0.862474 # miss rate for ReadReq accesses
530 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.981279 # miss rate for ReadExReq accesses
531 system.cpu.l2cache.ReadExReq_miss_rate::total 0.981279 # miss rate for ReadExReq accesses
532 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.860620 # miss rate for demand accesses
533 system.cpu.l2cache.demand_miss_rate::cpu.data 0.955925 # miss rate for demand accesses
534 system.cpu.l2cache.demand_miss_rate::total 0.909745 # miss rate for demand accesses
535 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.860620 # miss rate for overall accesses
536 system.cpu.l2cache.overall_miss_rate::cpu.data 0.955925 # miss rate for overall accesses
537 system.cpu.l2cache.overall_miss_rate::total 0.909745 # miss rate for overall accesses
538 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69899.002679 # average ReadReq miss latency
539 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75340.109223 # average ReadReq miss latency
540 system.cpu.l2cache.ReadReq_avg_miss_latency::total 70970.834329 # average ReadReq miss latency
541 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72201.987281 # average ReadExReq miss latency
542 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72201.987281 # average ReadExReq miss latency
543 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69899.002679 # average overall miss latency
544 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72853.489544 # average overall miss latency
545 system.cpu.l2cache.demand_avg_miss_latency::total 71499.215338 # average overall miss latency
546 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69899.002679 # average overall miss latency
547 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72853.489544 # average overall miss latency
548 system.cpu.l2cache.overall_avg_miss_latency::total 71499.215338 # average overall miss latency
549 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
550 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
551 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
552 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
553 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
554 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
555 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
556 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
557 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3359 # number of ReadReq MSHR misses
558 system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 824 # number of ReadReq MSHR misses
559 system.cpu.l2cache.ReadReq_mshr_misses::total 4183 # number of ReadReq MSHR misses
560 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3145 # number of ReadExReq MSHR misses
561 system.cpu.l2cache.ReadExReq_mshr_misses::total 3145 # number of ReadExReq MSHR misses
562 system.cpu.l2cache.demand_mshr_misses::cpu.inst 3359 # number of demand (read+write) MSHR misses
563 system.cpu.l2cache.demand_mshr_misses::cpu.data 3969 # number of demand (read+write) MSHR misses
564 system.cpu.l2cache.demand_mshr_misses::total 7328 # number of demand (read+write) MSHR misses
565 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3359 # number of overall MSHR misses
566 system.cpu.l2cache.overall_mshr_misses::cpu.data 3969 # number of overall MSHR misses
567 system.cpu.l2cache.overall_mshr_misses::total 7328 # number of overall MSHR misses
568 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 192686250 # number of ReadReq MSHR miss cycles
569 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 51812250 # number of ReadReq MSHR miss cycles
570 system.cpu.l2cache.ReadReq_mshr_miss_latency::total 244498500 # number of ReadReq MSHR miss cycles
571 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 188269250 # number of ReadExReq MSHR miss cycles
572 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 188269250 # number of ReadExReq MSHR miss cycles
573 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 192686250 # number of demand (read+write) MSHR miss cycles
574 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 240081500 # number of demand (read+write) MSHR miss cycles
575 system.cpu.l2cache.demand_mshr_miss_latency::total 432767750 # number of demand (read+write) MSHR miss cycles
576 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 192686250 # number of overall MSHR miss cycles
577 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 240081500 # number of overall MSHR miss cycles
578 system.cpu.l2cache.overall_mshr_miss_latency::total 432767750 # number of overall MSHR miss cycles
579 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.860620 # mshr miss rate for ReadReq accesses
580 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.870116 # mshr miss rate for ReadReq accesses
581 system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.862474 # mshr miss rate for ReadReq accesses
582 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.981279 # mshr miss rate for ReadExReq accesses
583 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.981279 # mshr miss rate for ReadExReq accesses
584 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.860620 # mshr miss rate for demand accesses
585 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.955925 # mshr miss rate for demand accesses
586 system.cpu.l2cache.demand_mshr_miss_rate::total 0.909745 # mshr miss rate for demand accesses
587 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.860620 # mshr miss rate for overall accesses
588 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.955925 # mshr miss rate for overall accesses
589 system.cpu.l2cache.overall_mshr_miss_rate::total 0.909745 # mshr miss rate for overall accesses
590 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57364.170884 # average ReadReq mshr miss latency
591 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62878.944175 # average ReadReq mshr miss latency
592 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58450.513985 # average ReadReq mshr miss latency
593 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59863.036566 # average ReadExReq mshr miss latency
594 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59863.036566 # average ReadExReq mshr miss latency
595 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57364.170884 # average overall mshr miss latency
596 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60489.166037 # average overall mshr miss latency
597 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59056.734443 # average overall mshr miss latency
598 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57364.170884 # average overall mshr miss latency
599 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60489.166037 # average overall mshr miss latency
600 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59056.734443 # average overall mshr miss latency
601 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
602 system.cpu.dcache.tags.replacements 764 # number of replacements
603 system.cpu.dcache.tags.tagsinuse 3284.890275 # Cycle average of tags in use
604 system.cpu.dcache.tags.total_refs 168254255 # Total number of references to valid blocks.
605 system.cpu.dcache.tags.sampled_refs 4152 # Sample count of references to valid blocks.
606 system.cpu.dcache.tags.avg_refs 40523.664499 # Average number of references to valid blocks.
607 system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
608 system.cpu.dcache.tags.occ_blocks::cpu.data 3284.890275 # Average occupied blocks per requestor
609 system.cpu.dcache.tags.occ_percent::cpu.data 0.801975 # Average percentage of cache occupancy
610 system.cpu.dcache.tags.occ_percent::total 0.801975 # Average percentage of cache occupancy
611 system.cpu.dcache.ReadReq_hits::cpu.data 94753181 # number of ReadReq hits
612 system.cpu.dcache.ReadReq_hits::total 94753181 # number of ReadReq hits
613 system.cpu.dcache.WriteReq_hits::cpu.data 73501074 # number of WriteReq hits
614 system.cpu.dcache.WriteReq_hits::total 73501074 # number of WriteReq hits
615 system.cpu.dcache.demand_hits::cpu.data 168254255 # number of demand (read+write) hits
616 system.cpu.dcache.demand_hits::total 168254255 # number of demand (read+write) hits
617 system.cpu.dcache.overall_hits::cpu.data 168254255 # number of overall hits
618 system.cpu.dcache.overall_hits::total 168254255 # number of overall hits
619 system.cpu.dcache.ReadReq_misses::cpu.data 1308 # number of ReadReq misses
620 system.cpu.dcache.ReadReq_misses::total 1308 # number of ReadReq misses
621 system.cpu.dcache.WriteReq_misses::cpu.data 19655 # number of WriteReq misses
622 system.cpu.dcache.WriteReq_misses::total 19655 # number of WriteReq misses
623 system.cpu.dcache.demand_misses::cpu.data 20963 # number of demand (read+write) misses
624 system.cpu.dcache.demand_misses::total 20963 # number of demand (read+write) misses
625 system.cpu.dcache.overall_misses::cpu.data 20963 # number of overall misses
626 system.cpu.dcache.overall_misses::total 20963 # number of overall misses
627 system.cpu.dcache.ReadReq_miss_latency::cpu.data 88453749 # number of ReadReq miss cycles
628 system.cpu.dcache.ReadReq_miss_latency::total 88453749 # number of ReadReq miss cycles
629 system.cpu.dcache.WriteReq_miss_latency::cpu.data 1129220750 # number of WriteReq miss cycles
630 system.cpu.dcache.WriteReq_miss_latency::total 1129220750 # number of WriteReq miss cycles
631 system.cpu.dcache.demand_miss_latency::cpu.data 1217674499 # number of demand (read+write) miss cycles
632 system.cpu.dcache.demand_miss_latency::total 1217674499 # number of demand (read+write) miss cycles
633 system.cpu.dcache.overall_miss_latency::cpu.data 1217674499 # number of overall miss cycles
634 system.cpu.dcache.overall_miss_latency::total 1217674499 # number of overall miss cycles
635 system.cpu.dcache.ReadReq_accesses::cpu.data 94754489 # number of ReadReq accesses(hits+misses)
636 system.cpu.dcache.ReadReq_accesses::total 94754489 # number of ReadReq accesses(hits+misses)
637 system.cpu.dcache.WriteReq_accesses::cpu.data 73520729 # number of WriteReq accesses(hits+misses)
638 system.cpu.dcache.WriteReq_accesses::total 73520729 # number of WriteReq accesses(hits+misses)
639 system.cpu.dcache.demand_accesses::cpu.data 168275218 # number of demand (read+write) accesses
640 system.cpu.dcache.demand_accesses::total 168275218 # number of demand (read+write) accesses
641 system.cpu.dcache.overall_accesses::cpu.data 168275218 # number of overall (read+write) accesses
642 system.cpu.dcache.overall_accesses::total 168275218 # number of overall (read+write) accesses
643 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000014 # miss rate for ReadReq accesses
644 system.cpu.dcache.ReadReq_miss_rate::total 0.000014 # miss rate for ReadReq accesses
645 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000267 # miss rate for WriteReq accesses
646 system.cpu.dcache.WriteReq_miss_rate::total 0.000267 # miss rate for WriteReq accesses
647 system.cpu.dcache.demand_miss_rate::cpu.data 0.000125 # miss rate for demand accesses
648 system.cpu.dcache.demand_miss_rate::total 0.000125 # miss rate for demand accesses
649 system.cpu.dcache.overall_miss_rate::cpu.data 0.000125 # miss rate for overall accesses
650 system.cpu.dcache.overall_miss_rate::total 0.000125 # miss rate for overall accesses
651 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67625.190367 # average ReadReq miss latency
652 system.cpu.dcache.ReadReq_avg_miss_latency::total 67625.190367 # average ReadReq miss latency
653 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 57452.085983 # average WriteReq miss latency
654 system.cpu.dcache.WriteReq_avg_miss_latency::total 57452.085983 # average WriteReq miss latency
655 system.cpu.dcache.demand_avg_miss_latency::cpu.data 58086.843438 # average overall miss latency
656 system.cpu.dcache.demand_avg_miss_latency::total 58086.843438 # average overall miss latency
657 system.cpu.dcache.overall_avg_miss_latency::cpu.data 58086.843438 # average overall miss latency
658 system.cpu.dcache.overall_avg_miss_latency::total 58086.843438 # average overall miss latency
659 system.cpu.dcache.blocked_cycles::no_mshrs 33688 # number of cycles access was blocked
660 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
661 system.cpu.dcache.blocked::no_mshrs 584 # number of cycles access was blocked
662 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
663 system.cpu.dcache.avg_blocked_cycles::no_mshrs 57.684932 # average number of cycles each access was blocked
664 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
665 system.cpu.dcache.fast_writes 0 # number of fast writes performed
666 system.cpu.dcache.cache_copies 0 # number of cache copies performed
667 system.cpu.dcache.writebacks::writebacks 649 # number of writebacks
668 system.cpu.dcache.writebacks::total 649 # number of writebacks
669 system.cpu.dcache.ReadReq_mshr_hits::cpu.data 358 # number of ReadReq MSHR hits
670 system.cpu.dcache.ReadReq_mshr_hits::total 358 # number of ReadReq MSHR hits
671 system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16453 # number of WriteReq MSHR hits
672 system.cpu.dcache.WriteReq_mshr_hits::total 16453 # number of WriteReq MSHR hits
673 system.cpu.dcache.demand_mshr_hits::cpu.data 16811 # number of demand (read+write) MSHR hits
674 system.cpu.dcache.demand_mshr_hits::total 16811 # number of demand (read+write) MSHR hits
675 system.cpu.dcache.overall_mshr_hits::cpu.data 16811 # number of overall MSHR hits
676 system.cpu.dcache.overall_mshr_hits::total 16811 # number of overall MSHR hits
677 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 950 # number of ReadReq MSHR misses
678 system.cpu.dcache.ReadReq_mshr_misses::total 950 # number of ReadReq MSHR misses
679 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3202 # number of WriteReq MSHR misses
680 system.cpu.dcache.WriteReq_mshr_misses::total 3202 # number of WriteReq MSHR misses
681 system.cpu.dcache.demand_mshr_misses::cpu.data 4152 # number of demand (read+write) MSHR misses
682 system.cpu.dcache.demand_mshr_misses::total 4152 # number of demand (read+write) MSHR misses
683 system.cpu.dcache.overall_mshr_misses::cpu.data 4152 # number of overall MSHR misses
684 system.cpu.dcache.overall_mshr_misses::total 4152 # number of overall MSHR misses
685 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 64535001 # number of ReadReq MSHR miss cycles
686 system.cpu.dcache.ReadReq_mshr_miss_latency::total 64535001 # number of ReadReq MSHR miss cycles
687 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 230815000 # number of WriteReq MSHR miss cycles
688 system.cpu.dcache.WriteReq_mshr_miss_latency::total 230815000 # number of WriteReq MSHR miss cycles
689 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 295350001 # number of demand (read+write) MSHR miss cycles
690 system.cpu.dcache.demand_mshr_miss_latency::total 295350001 # number of demand (read+write) MSHR miss cycles
691 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 295350001 # number of overall MSHR miss cycles
692 system.cpu.dcache.overall_mshr_miss_latency::total 295350001 # number of overall MSHR miss cycles
693 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses
694 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses
695 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses
696 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000044 # mshr miss rate for WriteReq accesses
697 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for demand accesses
698 system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses
699 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses
700 system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses
701 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67931.580000 # average ReadReq mshr miss latency
702 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67931.580000 # average ReadReq mshr miss latency
703 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72084.634603 # average WriteReq mshr miss latency
704 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72084.634603 # average WriteReq mshr miss latency
705 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71134.393304 # average overall mshr miss latency
706 system.cpu.dcache.demand_avg_mshr_miss_latency::total 71134.393304 # average overall mshr miss latency
707 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71134.393304 # average overall mshr miss latency
708 system.cpu.dcache.overall_avg_mshr_miss_latency::total 71134.393304 # average overall mshr miss latency
709 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
711 ---------- End Simulation Statistics ----------
projects / gem5.git / blob