ca6ea576aa4645a8795ac0ad1eee66b8de030a7c
[gem5.git] / tests / long / se / 30.eon / ref / alpha / tru64 / simple-timing / config.ini
1 [root]
2 type=Root
3 children=system
4 eventq_index=0
5 full_system=false
6 sim_quantum=0
7 time_sync_enable=false
8 time_sync_period=100000000000
9 time_sync_spin_threshold=100000000
10
11 [system]
12 type=System
13 children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
14 boot_osflags=a
15 cache_line_size=64
16 clk_domain=system.clk_domain
17 eventq_index=0
18 init_param=0
19 kernel=
20 kernel_addr_check=true
21 load_addr_mask=1099511627775
22 load_offset=0
23 mem_mode=timing
24 mem_ranges=
25 memories=system.physmem
26 mmap_using_noreserve=false
27 num_work_ids=16
28 readfile=
29 symbolfile=
30 work_begin_ckpt_count=0
31 work_begin_cpu_id_exit=-1
32 work_begin_exit_count=0
33 work_cpus_ckpt_count=0
34 work_end_ckpt_count=0
35 work_end_exit_count=0
36 work_item_id=-1
37 system_port=system.membus.slave[0]
38
39 [system.clk_domain]
40 type=SrcClockDomain
41 clock=1000
42 domain_id=-1
43 eventq_index=0
44 init_perf_level=0
45 voltage_domain=system.voltage_domain
46
47 [system.cpu]
48 type=TimingSimpleCPU
49 children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
50 branchPred=Null
51 checker=Null
52 clk_domain=system.cpu_clk_domain
53 cpu_id=0
54 do_checkpoint_insts=true
55 do_quiesce=true
56 do_statistics_insts=true
57 dtb=system.cpu.dtb
58 eventq_index=0
59 function_trace=false
60 function_trace_start=0
61 interrupts=system.cpu.interrupts
62 isa=system.cpu.isa
63 itb=system.cpu.itb
64 max_insts_all_threads=0
65 max_insts_any_thread=0
66 max_loads_all_threads=0
67 max_loads_any_thread=0
68 numThreads=1
69 profile=0
70 progress_interval=0
71 simpoint_start_insts=
72 socket_id=0
73 switched_out=false
74 system=system
75 tracer=system.cpu.tracer
76 workload=system.cpu.workload
77 dcache_port=system.cpu.dcache.cpu_side
78 icache_port=system.cpu.icache.cpu_side
79
80 [system.cpu.dcache]
81 type=BaseCache
82 children=tags
83 addr_ranges=0:18446744073709551615
84 assoc=2
85 clk_domain=system.cpu_clk_domain
86 demand_mshr_reserve=1
87 eventq_index=0
88 forward_snoops=true
89 hit_latency=2
90 is_read_only=false
91 max_miss_count=0
92 mshrs=4
93 prefetch_on_access=false
94 prefetcher=Null
95 response_latency=2
96 sequential_access=false
97 size=262144
98 system=system
99 tags=system.cpu.dcache.tags
100 tgts_per_mshr=20
101 write_buffers=8
102 cpu_side=system.cpu.dcache_port
103 mem_side=system.cpu.toL2Bus.slave[1]
104
105 [system.cpu.dcache.tags]
106 type=LRU
107 assoc=2
108 block_size=64
109 clk_domain=system.cpu_clk_domain
110 eventq_index=0
111 hit_latency=2
112 sequential_access=false
113 size=262144
114
115 [system.cpu.dtb]
116 type=AlphaTLB
117 eventq_index=0
118 size=64
119
120 [system.cpu.icache]
121 type=BaseCache
122 children=tags
123 addr_ranges=0:18446744073709551615
124 assoc=2
125 clk_domain=system.cpu_clk_domain
126 demand_mshr_reserve=1
127 eventq_index=0
128 forward_snoops=true
129 hit_latency=2
130 is_read_only=true
131 max_miss_count=0
132 mshrs=4
133 prefetch_on_access=false
134 prefetcher=Null
135 response_latency=2
136 sequential_access=false
137 size=131072
138 system=system
139 tags=system.cpu.icache.tags
140 tgts_per_mshr=20
141 write_buffers=8
142 cpu_side=system.cpu.icache_port
143 mem_side=system.cpu.toL2Bus.slave[0]
144
145 [system.cpu.icache.tags]
146 type=LRU
147 assoc=2
148 block_size=64
149 clk_domain=system.cpu_clk_domain
150 eventq_index=0
151 hit_latency=2
152 sequential_access=false
153 size=131072
154
155 [system.cpu.interrupts]
156 type=AlphaInterrupts
157 eventq_index=0
158
159 [system.cpu.isa]
160 type=AlphaISA
161 eventq_index=0
162 system=system
163
164 [system.cpu.itb]
165 type=AlphaTLB
166 eventq_index=0
167 size=48
168
169 [system.cpu.l2cache]
170 type=BaseCache
171 children=tags
172 addr_ranges=0:18446744073709551615
173 assoc=8
174 clk_domain=system.cpu_clk_domain
175 demand_mshr_reserve=1
176 eventq_index=0
177 forward_snoops=true
178 hit_latency=20
179 is_read_only=false
180 max_miss_count=0
181 mshrs=20
182 prefetch_on_access=false
183 prefetcher=Null
184 response_latency=20
185 sequential_access=false
186 size=2097152
187 system=system
188 tags=system.cpu.l2cache.tags
189 tgts_per_mshr=12
190 write_buffers=8
191 cpu_side=system.cpu.toL2Bus.master[0]
192 mem_side=system.membus.slave[1]
193
194 [system.cpu.l2cache.tags]
195 type=LRU
196 assoc=8
197 block_size=64
198 clk_domain=system.cpu_clk_domain
199 eventq_index=0
200 hit_latency=20
201 sequential_access=false
202 size=2097152
203
204 [system.cpu.toL2Bus]
205 type=CoherentXBar
206 clk_domain=system.cpu_clk_domain
207 eventq_index=0
208 forward_latency=0
209 frontend_latency=1
210 response_latency=1
211 snoop_filter=Null
212 snoop_response_latency=1
213 system=system
214 use_default_range=false
215 width=32
216 master=system.cpu.l2cache.cpu_side
217 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
218
219 [system.cpu.tracer]
220 type=ExeTracer
221 eventq_index=0
222
223 [system.cpu.workload]
224 type=LiveProcess
225 cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
226 cwd=build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/simple-timing
227 drivers=
228 egid=100
229 env=
230 errout=cerr
231 euid=100
232 eventq_index=0
233 executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/eon
234 gid=100
235 input=cin
236 kvmInSE=false
237 max_stack_size=67108864
238 output=cout
239 pid=100
240 ppid=99
241 simpoint=0
242 system=system
243 uid=100
244 useArchPT=false
245
246 [system.cpu_clk_domain]
247 type=SrcClockDomain
248 clock=500
249 domain_id=-1
250 eventq_index=0
251 init_perf_level=0
252 voltage_domain=system.voltage_domain
253
254 [system.dvfs_handler]
255 type=DVFSHandler
256 domains=
257 enable=false
258 eventq_index=0
259 sys_clk_domain=system.clk_domain
260 transition_latency=100000000
261
262 [system.membus]
263 type=CoherentXBar
264 clk_domain=system.clk_domain
265 eventq_index=0
266 forward_latency=4
267 frontend_latency=3
268 response_latency=2
269 snoop_filter=Null
270 snoop_response_latency=4
271 system=system
272 use_default_range=false
273 width=16
274 master=system.physmem.port
275 slave=system.system_port system.cpu.l2cache.mem_side
276
277 [system.physmem]
278 type=SimpleMemory
279 bandwidth=73.000000
280 clk_domain=system.clk_domain
281 conf_table_reported=true
282 eventq_index=0
283 in_addr_map=true
284 latency=30000
285 latency_var=0
286 null=false
287 range=0:134217727
288 port=system.membus.master[0]
289
290 [system.voltage_domain]
291 type=VoltageDomain
292 eventq_index=0
293 voltage=1.000000
294