2 ---------- Begin Simulation Statistics ----------
3 final_tick 227445516000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
4 host_inst_rate 153700 # Simulator instruction rate (inst/s)
5 host_mem_usage 303376 # Number of bytes of host memory used
6 host_op_rate 196498 # Simulator op (including micro ops) rate (op/s)
7 host_seconds 1776.44 # Real time elapsed on the host
8 host_tick_rate 128034740 # Simulator tick rate (ticks/s)
9 sim_freq 1000000000000 # Frequency of simulated ticks
10 sim_insts 273037854 # Number of instructions simulated
11 sim_ops 349065592 # Number of ops (including micro ops) simulated
12 sim_seconds 0.227446 # Number of seconds simulated
13 sim_ticks 227445516000 # Number of ticks simulated
14 system.clk_domain.clock 1000 # Clock period in ticks
15 system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
16 system.cpu.branchPred.BTBHitPct 83.362247 # BTB Hit Percentage
17 system.cpu.branchPred.BTBHits 16723894 # Number of BTB hits
18 system.cpu.branchPred.BTBLookups 20061712 # Number of BTB lookups
19 system.cpu.branchPred.RASInCorrect 121 # Number of incorrect RAS predictions.
20 system.cpu.branchPred.condIncorrect 1671536 # Number of conditional branches incorrect
21 system.cpu.branchPred.condPredicted 21059526 # Number of conditional branches predicted
22 system.cpu.branchPred.lookups 35363260 # Number of BP lookups
23 system.cpu.branchPred.usedRAS 6617396 # Number of times the RAS was used to get a target.
24 system.cpu.committedInsts 273037854 # Number of instructions committed
25 system.cpu.committedOps 349065592 # Number of ops (including micro ops) committed
26 system.cpu.cpi 1.666037 # CPI: cycles per instruction
27 system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 10895 # number of LoadLockedReq accesses(hits+misses)
28 system.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses)
29 system.cpu.dcache.LoadLockedReq_hits::cpu.inst 10895 # number of LoadLockedReq hits
30 system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits
31 system.cpu.dcache.ReadReq_accesses::cpu.inst 95145110 # number of ReadReq accesses(hits+misses)
32 system.cpu.dcache.ReadReq_accesses::total 95145110 # number of ReadReq accesses(hits+misses)
33 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 61749.740048 # average ReadReq miss latency
34 system.cpu.dcache.ReadReq_avg_miss_latency::total 61749.740048 # average ReadReq miss latency
35 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 61620.734497 # average ReadReq mshr miss latency
36 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61620.734497 # average ReadReq mshr miss latency
37 system.cpu.dcache.ReadReq_hits::cpu.inst 95143025 # number of ReadReq hits
38 system.cpu.dcache.ReadReq_hits::total 95143025 # number of ReadReq hits
39 system.cpu.dcache.ReadReq_miss_latency::cpu.inst 128748208 # number of ReadReq miss cycles
40 system.cpu.dcache.ReadReq_miss_latency::total 128748208 # number of ReadReq miss cycles
41 system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.000022 # miss rate for ReadReq accesses
42 system.cpu.dcache.ReadReq_miss_rate::total 0.000022 # miss rate for ReadReq accesses
43 system.cpu.dcache.ReadReq_misses::cpu.inst 2085 # number of ReadReq misses
44 system.cpu.dcache.ReadReq_misses::total 2085 # number of ReadReq misses
45 system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 424 # number of ReadReq MSHR hits
46 system.cpu.dcache.ReadReq_mshr_hits::total 424 # number of ReadReq MSHR hits
47 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 102352040 # number of ReadReq MSHR miss cycles
48 system.cpu.dcache.ReadReq_mshr_miss_latency::total 102352040 # number of ReadReq MSHR miss cycles
49 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.000017 # mshr miss rate for ReadReq accesses
50 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000017 # mshr miss rate for ReadReq accesses
51 system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 1661 # number of ReadReq MSHR misses
52 system.cpu.dcache.ReadReq_mshr_misses::total 1661 # number of ReadReq MSHR misses
53 system.cpu.dcache.StoreCondReq_accesses::cpu.inst 10895 # number of StoreCondReq accesses(hits+misses)
54 system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses)
55 system.cpu.dcache.StoreCondReq_hits::cpu.inst 10895 # number of StoreCondReq hits
56 system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits
57 system.cpu.dcache.WriteReq_accesses::cpu.inst 82052677 # number of WriteReq accesses(hits+misses)
58 system.cpu.dcache.WriteReq_accesses::total 82052677 # number of WriteReq accesses(hits+misses)
59 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 68469.206380 # average WriteReq miss latency
60 system.cpu.dcache.WriteReq_avg_miss_latency::total 68469.206380 # average WriteReq miss latency
61 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 68654.108392 # average WriteReq mshr miss latency
62 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68654.108392 # average WriteReq mshr miss latency
63 system.cpu.dcache.WriteReq_hits::cpu.inst 82047473 # number of WriteReq hits
64 system.cpu.dcache.WriteReq_hits::total 82047473 # number of WriteReq hits
65 system.cpu.dcache.WriteReq_miss_latency::cpu.inst 356313750 # number of WriteReq miss cycles
66 system.cpu.dcache.WriteReq_miss_latency::total 356313750 # number of WriteReq miss cycles
67 system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.000063 # miss rate for WriteReq accesses
68 system.cpu.dcache.WriteReq_miss_rate::total 0.000063 # miss rate for WriteReq accesses
69 system.cpu.dcache.WriteReq_misses::cpu.inst 5204 # number of WriteReq misses
70 system.cpu.dcache.WriteReq_misses::total 5204 # number of WriteReq misses
71 system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 2344 # number of WriteReq MSHR hits
72 system.cpu.dcache.WriteReq_mshr_hits::total 2344 # number of WriteReq MSHR hits
73 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 196350750 # number of WriteReq MSHR miss cycles
74 system.cpu.dcache.WriteReq_mshr_miss_latency::total 196350750 # number of WriteReq MSHR miss cycles
75 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000035 # mshr miss rate for WriteReq accesses
76 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000035 # mshr miss rate for WriteReq accesses
77 system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 2860 # number of WriteReq MSHR misses
78 system.cpu.dcache.WriteReq_mshr_misses::total 2860 # number of WriteReq MSHR misses
79 system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
80 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
81 system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
82 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
83 system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
84 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
85 system.cpu.dcache.cache_copies 0 # number of cache copies performed
86 system.cpu.dcache.demand_accesses::cpu.inst 177197787 # number of demand (read+write) accesses
87 system.cpu.dcache.demand_accesses::total 177197787 # number of demand (read+write) accesses
88 system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66547.120044 # average overall miss latency
89 system.cpu.dcache.demand_avg_miss_latency::total 66547.120044 # average overall miss latency
90 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 66070.070781 # average overall mshr miss latency
91 system.cpu.dcache.demand_avg_mshr_miss_latency::total 66070.070781 # average overall mshr miss latency
92 system.cpu.dcache.demand_hits::cpu.inst 177190498 # number of demand (read+write) hits
93 system.cpu.dcache.demand_hits::total 177190498 # number of demand (read+write) hits
94 system.cpu.dcache.demand_miss_latency::cpu.inst 485061958 # number of demand (read+write) miss cycles
95 system.cpu.dcache.demand_miss_latency::total 485061958 # number of demand (read+write) miss cycles
96 system.cpu.dcache.demand_miss_rate::cpu.inst 0.000041 # miss rate for demand accesses
97 system.cpu.dcache.demand_miss_rate::total 0.000041 # miss rate for demand accesses
98 system.cpu.dcache.demand_misses::cpu.inst 7289 # number of demand (read+write) misses
99 system.cpu.dcache.demand_misses::total 7289 # number of demand (read+write) misses
100 system.cpu.dcache.demand_mshr_hits::cpu.inst 2768 # number of demand (read+write) MSHR hits
101 system.cpu.dcache.demand_mshr_hits::total 2768 # number of demand (read+write) MSHR hits
102 system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 298702790 # number of demand (read+write) MSHR miss cycles
103 system.cpu.dcache.demand_mshr_miss_latency::total 298702790 # number of demand (read+write) MSHR miss cycles
104 system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.000026 # mshr miss rate for demand accesses
105 system.cpu.dcache.demand_mshr_miss_rate::total 0.000026 # mshr miss rate for demand accesses
106 system.cpu.dcache.demand_mshr_misses::cpu.inst 4521 # number of demand (read+write) MSHR misses
107 system.cpu.dcache.demand_mshr_misses::total 4521 # number of demand (read+write) MSHR misses
108 system.cpu.dcache.fast_writes 0 # number of fast writes performed
109 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
110 system.cpu.dcache.overall_accesses::cpu.inst 177197787 # number of overall (read+write) accesses
111 system.cpu.dcache.overall_accesses::total 177197787 # number of overall (read+write) accesses
112 system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66547.120044 # average overall miss latency
113 system.cpu.dcache.overall_avg_miss_latency::total 66547.120044 # average overall miss latency
114 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 66070.070781 # average overall mshr miss latency
115 system.cpu.dcache.overall_avg_mshr_miss_latency::total 66070.070781 # average overall mshr miss latency
116 system.cpu.dcache.overall_hits::cpu.inst 177190498 # number of overall hits
117 system.cpu.dcache.overall_hits::total 177190498 # number of overall hits
118 system.cpu.dcache.overall_miss_latency::cpu.inst 485061958 # number of overall miss cycles
119 system.cpu.dcache.overall_miss_latency::total 485061958 # number of overall miss cycles
120 system.cpu.dcache.overall_miss_rate::cpu.inst 0.000041 # miss rate for overall accesses
121 system.cpu.dcache.overall_miss_rate::total 0.000041 # miss rate for overall accesses
122 system.cpu.dcache.overall_misses::cpu.inst 7289 # number of overall misses
123 system.cpu.dcache.overall_misses::total 7289 # number of overall misses
124 system.cpu.dcache.overall_mshr_hits::cpu.inst 2768 # number of overall MSHR hits
125 system.cpu.dcache.overall_mshr_hits::total 2768 # number of overall MSHR hits
126 system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 298702790 # number of overall MSHR miss cycles
127 system.cpu.dcache.overall_mshr_miss_latency::total 298702790 # number of overall MSHR miss cycles
128 system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.000026 # mshr miss rate for overall accesses
129 system.cpu.dcache.overall_mshr_miss_rate::total 0.000026 # mshr miss rate for overall accesses
130 system.cpu.dcache.overall_mshr_misses::cpu.inst 4521 # number of overall MSHR misses
131 system.cpu.dcache.overall_mshr_misses::total 4521 # number of overall MSHR misses
132 system.cpu.dcache.tags.age_task_id_blocks_1024::0 17 # Occupied blocks per task id
133 system.cpu.dcache.tags.age_task_id_blocks_1024::1 23 # Occupied blocks per task id
134 system.cpu.dcache.tags.age_task_id_blocks_1024::2 11 # Occupied blocks per task id
135 system.cpu.dcache.tags.age_task_id_blocks_1024::3 674 # Occupied blocks per task id
136 system.cpu.dcache.tags.age_task_id_blocks_1024::4 2436 # Occupied blocks per task id
137 system.cpu.dcache.tags.avg_refs 39197.586375 # Average number of references to valid blocks.
138 system.cpu.dcache.tags.data_accesses 354443675 # Number of data accesses
139 system.cpu.dcache.tags.occ_blocks::cpu.inst 3089.554835 # Average occupied blocks per requestor
140 system.cpu.dcache.tags.occ_percent::cpu.inst 0.754286 # Average percentage of cache occupancy
141 system.cpu.dcache.tags.occ_percent::total 0.754286 # Average percentage of cache occupancy
142 system.cpu.dcache.tags.occ_task_id_blocks::1024 3161 # Occupied blocks per task id
143 system.cpu.dcache.tags.occ_task_id_percent::1024 0.771729 # Percentage of cache occupancy per task id
144 system.cpu.dcache.tags.replacements 1360 # number of replacements
145 system.cpu.dcache.tags.sampled_refs 4521 # Sample count of references to valid blocks.
146 system.cpu.dcache.tags.tag_accesses 354443675 # Number of tag accesses
147 system.cpu.dcache.tags.tagsinuse 3089.554835 # Cycle average of tags in use
148 system.cpu.dcache.tags.total_refs 177212288 # Total number of references to valid blocks.
149 system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
150 system.cpu.dcache.writebacks::writebacks 1013 # number of writebacks
151 system.cpu.dcache.writebacks::total 1013 # number of writebacks
152 system.cpu.discardedOps 6932970 # Number of ops (including micro ops) which were discarded before commit
153 system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
154 system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
155 system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
156 system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
157 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
158 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
159 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
160 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
161 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
162 system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
163 system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
164 system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
165 system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
166 system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
167 system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
168 system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
169 system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
170 system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
171 system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
172 system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
173 system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
174 system.cpu.dtb.accesses 0 # DTB accesses
175 system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
176 system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
177 system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
178 system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
179 system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
180 system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
181 system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
182 system.cpu.dtb.hits 0 # DTB hits
183 system.cpu.dtb.inst_accesses 0 # ITB inst accesses
184 system.cpu.dtb.inst_hits 0 # ITB inst hits
185 system.cpu.dtb.inst_misses 0 # ITB inst misses
186 system.cpu.dtb.misses 0 # DTB misses
187 system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
188 system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
189 system.cpu.dtb.read_accesses 0 # DTB read accesses
190 system.cpu.dtb.read_hits 0 # DTB read hits
191 system.cpu.dtb.read_misses 0 # DTB read misses
192 system.cpu.dtb.write_accesses 0 # DTB write accesses
193 system.cpu.dtb.write_hits 0 # DTB write hits
194 system.cpu.dtb.write_misses 0 # DTB write misses
195 system.cpu.icache.ReadReq_accesses::cpu.inst 77471042 # number of ReadReq accesses(hits+misses)
196 system.cpu.icache.ReadReq_accesses::total 77471042 # number of ReadReq accesses(hits+misses)
197 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17858.870336 # average ReadReq miss latency
198 system.cpu.icache.ReadReq_avg_miss_latency::total 17858.870336 # average ReadReq miss latency
199 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15825.006083 # average ReadReq mshr miss latency
200 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15825.006083 # average ReadReq mshr miss latency
201 system.cpu.icache.ReadReq_hits::cpu.inst 77429612 # number of ReadReq hits
202 system.cpu.icache.ReadReq_hits::total 77429612 # number of ReadReq hits
203 system.cpu.icache.ReadReq_miss_latency::cpu.inst 739892998 # number of ReadReq miss cycles
204 system.cpu.icache.ReadReq_miss_latency::total 739892998 # number of ReadReq miss cycles
205 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000535 # miss rate for ReadReq accesses
206 system.cpu.icache.ReadReq_miss_rate::total 0.000535 # miss rate for ReadReq accesses
207 system.cpu.icache.ReadReq_misses::cpu.inst 41430 # number of ReadReq misses
208 system.cpu.icache.ReadReq_misses::total 41430 # number of ReadReq misses
209 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 655630002 # number of ReadReq MSHR miss cycles
210 system.cpu.icache.ReadReq_mshr_miss_latency::total 655630002 # number of ReadReq MSHR miss cycles
211 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000535 # mshr miss rate for ReadReq accesses
212 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000535 # mshr miss rate for ReadReq accesses
213 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 41430 # number of ReadReq MSHR misses
214 system.cpu.icache.ReadReq_mshr_misses::total 41430 # number of ReadReq MSHR misses
215 system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
216 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
217 system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
218 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
219 system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
220 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
221 system.cpu.icache.cache_copies 0 # number of cache copies performed
222 system.cpu.icache.demand_accesses::cpu.inst 77471042 # number of demand (read+write) accesses
223 system.cpu.icache.demand_accesses::total 77471042 # number of demand (read+write) accesses
224 system.cpu.icache.demand_avg_miss_latency::cpu.inst 17858.870336 # average overall miss latency
225 system.cpu.icache.demand_avg_miss_latency::total 17858.870336 # average overall miss latency
226 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15825.006083 # average overall mshr miss latency
227 system.cpu.icache.demand_avg_mshr_miss_latency::total 15825.006083 # average overall mshr miss latency
228 system.cpu.icache.demand_hits::cpu.inst 77429612 # number of demand (read+write) hits
229 system.cpu.icache.demand_hits::total 77429612 # number of demand (read+write) hits
230 system.cpu.icache.demand_miss_latency::cpu.inst 739892998 # number of demand (read+write) miss cycles
231 system.cpu.icache.demand_miss_latency::total 739892998 # number of demand (read+write) miss cycles
232 system.cpu.icache.demand_miss_rate::cpu.inst 0.000535 # miss rate for demand accesses
233 system.cpu.icache.demand_miss_rate::total 0.000535 # miss rate for demand accesses
234 system.cpu.icache.demand_misses::cpu.inst 41430 # number of demand (read+write) misses
235 system.cpu.icache.demand_misses::total 41430 # number of demand (read+write) misses
236 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 655630002 # number of demand (read+write) MSHR miss cycles
237 system.cpu.icache.demand_mshr_miss_latency::total 655630002 # number of demand (read+write) MSHR miss cycles
238 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000535 # mshr miss rate for demand accesses
239 system.cpu.icache.demand_mshr_miss_rate::total 0.000535 # mshr miss rate for demand accesses
240 system.cpu.icache.demand_mshr_misses::cpu.inst 41430 # number of demand (read+write) MSHR misses
241 system.cpu.icache.demand_mshr_misses::total 41430 # number of demand (read+write) MSHR misses
242 system.cpu.icache.fast_writes 0 # number of fast writes performed
243 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
244 system.cpu.icache.overall_accesses::cpu.inst 77471042 # number of overall (read+write) accesses
245 system.cpu.icache.overall_accesses::total 77471042 # number of overall (read+write) accesses
246 system.cpu.icache.overall_avg_miss_latency::cpu.inst 17858.870336 # average overall miss latency
247 system.cpu.icache.overall_avg_miss_latency::total 17858.870336 # average overall miss latency
248 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15825.006083 # average overall mshr miss latency
249 system.cpu.icache.overall_avg_mshr_miss_latency::total 15825.006083 # average overall mshr miss latency
250 system.cpu.icache.overall_hits::cpu.inst 77429612 # number of overall hits
251 system.cpu.icache.overall_hits::total 77429612 # number of overall hits
252 system.cpu.icache.overall_miss_latency::cpu.inst 739892998 # number of overall miss cycles
253 system.cpu.icache.overall_miss_latency::total 739892998 # number of overall miss cycles
254 system.cpu.icache.overall_miss_rate::cpu.inst 0.000535 # miss rate for overall accesses
255 system.cpu.icache.overall_miss_rate::total 0.000535 # miss rate for overall accesses
256 system.cpu.icache.overall_misses::cpu.inst 41430 # number of overall misses
257 system.cpu.icache.overall_misses::total 41430 # number of overall misses
258 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 655630002 # number of overall MSHR miss cycles
259 system.cpu.icache.overall_mshr_miss_latency::total 655630002 # number of overall MSHR miss cycles
260 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000535 # mshr miss rate for overall accesses
261 system.cpu.icache.overall_mshr_miss_rate::total 0.000535 # mshr miss rate for overall accesses
262 system.cpu.icache.overall_mshr_misses::cpu.inst 41430 # number of overall MSHR misses
263 system.cpu.icache.overall_mshr_misses::total 41430 # number of overall MSHR misses
264 system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id
265 system.cpu.icache.tags.age_task_id_blocks_1024::1 87 # Occupied blocks per task id
266 system.cpu.icache.tags.age_task_id_blocks_1024::2 33 # Occupied blocks per task id
267 system.cpu.icache.tags.age_task_id_blocks_1024::3 288 # Occupied blocks per task id
268 system.cpu.icache.tags.age_task_id_blocks_1024::4 1478 # Occupied blocks per task id
269 system.cpu.icache.tags.avg_refs 1868.971300 # Average number of references to valid blocks.
270 system.cpu.icache.tags.data_accesses 154983513 # Number of data accesses
271 system.cpu.icache.tags.occ_blocks::cpu.inst 1927.026996 # Average occupied blocks per requestor
272 system.cpu.icache.tags.occ_percent::cpu.inst 0.940931 # Average percentage of cache occupancy
273 system.cpu.icache.tags.occ_percent::total 0.940931 # Average percentage of cache occupancy
274 system.cpu.icache.tags.occ_task_id_blocks::1024 1941 # Occupied blocks per task id
275 system.cpu.icache.tags.occ_task_id_percent::1024 0.947754 # Percentage of cache occupancy per task id
276 system.cpu.icache.tags.replacements 39488 # number of replacements
277 system.cpu.icache.tags.sampled_refs 41429 # Sample count of references to valid blocks.
278 system.cpu.icache.tags.tag_accesses 154983513 # Number of tag accesses
279 system.cpu.icache.tags.tagsinuse 1927.026996 # Cycle average of tags in use
280 system.cpu.icache.tags.total_refs 77429612 # Total number of references to valid blocks.
281 system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
282 system.cpu.idleCycles 4029946 # Total number of cycles that the CPU has spent unscheduled due to idling
283 system.cpu.ipc 0.600227 # IPC: instructions per cycle
284 system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
285 system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
286 system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
287 system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
288 system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
289 system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
290 system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
291 system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
292 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
293 system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
294 system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
295 system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
296 system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
297 system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
298 system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
299 system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
300 system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
301 system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
302 system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
303 system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
304 system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
305 system.cpu.itb.accesses 0 # DTB accesses
306 system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
307 system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
308 system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
309 system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
310 system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
311 system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
312 system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
313 system.cpu.itb.hits 0 # DTB hits
314 system.cpu.itb.inst_accesses 0 # ITB inst accesses
315 system.cpu.itb.inst_hits 0 # ITB inst hits
316 system.cpu.itb.inst_misses 0 # ITB inst misses
317 system.cpu.itb.misses 0 # DTB misses
318 system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
319 system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
320 system.cpu.itb.read_accesses 0 # DTB read accesses
321 system.cpu.itb.read_hits 0 # DTB read hits
322 system.cpu.itb.read_misses 0 # DTB read misses
323 system.cpu.itb.write_accesses 0 # DTB write accesses
324 system.cpu.itb.write_hits 0 # DTB write hits
325 system.cpu.itb.write_misses 0 # DTB write misses
326 system.cpu.l2cache.ReadExReq_accesses::cpu.inst 2860 # number of ReadExReq accesses(hits+misses)
327 system.cpu.l2cache.ReadExReq_accesses::total 2860 # number of ReadExReq accesses(hits+misses)
328 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 67967.563291 # average ReadExReq miss latency
329 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67967.563291 # average ReadExReq miss latency
330 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 55399.173699 # average ReadExReq mshr miss latency
331 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55399.173699 # average ReadExReq mshr miss latency
332 system.cpu.l2cache.ReadExReq_hits::cpu.inst 16 # number of ReadExReq hits
333 system.cpu.l2cache.ReadExReq_hits::total 16 # number of ReadExReq hits
334 system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 193299750 # number of ReadExReq miss cycles
335 system.cpu.l2cache.ReadExReq_miss_latency::total 193299750 # number of ReadExReq miss cycles
336 system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.994406 # miss rate for ReadExReq accesses
337 system.cpu.l2cache.ReadExReq_miss_rate::total 0.994406 # miss rate for ReadExReq accesses
338 system.cpu.l2cache.ReadExReq_misses::cpu.inst 2844 # number of ReadExReq misses
339 system.cpu.l2cache.ReadExReq_misses::total 2844 # number of ReadExReq misses
340 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 157555250 # number of ReadExReq MSHR miss cycles
341 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 157555250 # number of ReadExReq MSHR miss cycles
342 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.994406 # mshr miss rate for ReadExReq accesses
343 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994406 # mshr miss rate for ReadExReq accesses
344 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 2844 # number of ReadExReq MSHR misses
345 system.cpu.l2cache.ReadExReq_mshr_misses::total 2844 # number of ReadExReq MSHR misses
346 system.cpu.l2cache.ReadReq_accesses::cpu.inst 43091 # number of ReadReq accesses(hits+misses)
347 system.cpu.l2cache.ReadReq_accesses::total 43091 # number of ReadReq accesses(hits+misses)
348 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68852.642487 # average ReadReq miss latency
349 system.cpu.l2cache.ReadReq_avg_miss_latency::total 68852.642487 # average ReadReq miss latency
350 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56391.699770 # average ReadReq mshr miss latency
351 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56391.699770 # average ReadReq mshr miss latency
352 system.cpu.l2cache.ReadReq_hits::cpu.inst 38266 # number of ReadReq hits
353 system.cpu.l2cache.ReadReq_hits::total 38266 # number of ReadReq hits
354 system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 332214000 # number of ReadReq miss cycles
355 system.cpu.l2cache.ReadReq_miss_latency::total 332214000 # number of ReadReq miss cycles
356 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.111972 # miss rate for ReadReq accesses
357 system.cpu.l2cache.ReadReq_miss_rate::total 0.111972 # miss rate for ReadReq accesses
358 system.cpu.l2cache.ReadReq_misses::cpu.inst 4825 # number of ReadReq misses
359 system.cpu.l2cache.ReadReq_misses::total 4825 # number of ReadReq misses
360 system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 42 # number of ReadReq MSHR hits
361 system.cpu.l2cache.ReadReq_mshr_hits::total 42 # number of ReadReq MSHR hits
362 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 269721500 # number of ReadReq MSHR miss cycles
363 system.cpu.l2cache.ReadReq_mshr_miss_latency::total 269721500 # number of ReadReq MSHR miss cycles
364 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.110998 # mshr miss rate for ReadReq accesses
365 system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.110998 # mshr miss rate for ReadReq accesses
366 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 4783 # number of ReadReq MSHR misses
367 system.cpu.l2cache.ReadReq_mshr_misses::total 4783 # number of ReadReq MSHR misses
368 system.cpu.l2cache.Writeback_accesses::writebacks 1013 # number of Writeback accesses(hits+misses)
369 system.cpu.l2cache.Writeback_accesses::total 1013 # number of Writeback accesses(hits+misses)
370 system.cpu.l2cache.Writeback_hits::writebacks 1013 # number of Writeback hits
371 system.cpu.l2cache.Writeback_hits::total 1013 # number of Writeback hits
372 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
373 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
374 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
375 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
376 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
377 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
378 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
379 system.cpu.l2cache.demand_accesses::cpu.inst 45951 # number of demand (read+write) accesses
380 system.cpu.l2cache.demand_accesses::total 45951 # number of demand (read+write) accesses
381 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68524.416482 # average overall miss latency
382 system.cpu.l2cache.demand_avg_miss_latency::total 68524.416482 # average overall miss latency
383 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56021.600892 # average overall mshr miss latency
384 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56021.600892 # average overall mshr miss latency
385 system.cpu.l2cache.demand_hits::cpu.inst 38282 # number of demand (read+write) hits
386 system.cpu.l2cache.demand_hits::total 38282 # number of demand (read+write) hits
387 system.cpu.l2cache.demand_miss_latency::cpu.inst 525513750 # number of demand (read+write) miss cycles
388 system.cpu.l2cache.demand_miss_latency::total 525513750 # number of demand (read+write) miss cycles
389 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.166895 # miss rate for demand accesses
390 system.cpu.l2cache.demand_miss_rate::total 0.166895 # miss rate for demand accesses
391 system.cpu.l2cache.demand_misses::cpu.inst 7669 # number of demand (read+write) misses
392 system.cpu.l2cache.demand_misses::total 7669 # number of demand (read+write) misses
393 system.cpu.l2cache.demand_mshr_hits::cpu.inst 42 # number of demand (read+write) MSHR hits
394 system.cpu.l2cache.demand_mshr_hits::total 42 # number of demand (read+write) MSHR hits
395 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 427276750 # number of demand (read+write) MSHR miss cycles
396 system.cpu.l2cache.demand_mshr_miss_latency::total 427276750 # number of demand (read+write) MSHR miss cycles
397 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.165981 # mshr miss rate for demand accesses
398 system.cpu.l2cache.demand_mshr_miss_rate::total 0.165981 # mshr miss rate for demand accesses
399 system.cpu.l2cache.demand_mshr_misses::cpu.inst 7627 # number of demand (read+write) MSHR misses
400 system.cpu.l2cache.demand_mshr_misses::total 7627 # number of demand (read+write) MSHR misses
401 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
402 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
403 system.cpu.l2cache.overall_accesses::cpu.inst 45951 # number of overall (read+write) accesses
404 system.cpu.l2cache.overall_accesses::total 45951 # number of overall (read+write) accesses
405 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68524.416482 # average overall miss latency
406 system.cpu.l2cache.overall_avg_miss_latency::total 68524.416482 # average overall miss latency
407 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56021.600892 # average overall mshr miss latency
408 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56021.600892 # average overall mshr miss latency
409 system.cpu.l2cache.overall_hits::cpu.inst 38282 # number of overall hits
410 system.cpu.l2cache.overall_hits::total 38282 # number of overall hits
411 system.cpu.l2cache.overall_miss_latency::cpu.inst 525513750 # number of overall miss cycles
412 system.cpu.l2cache.overall_miss_latency::total 525513750 # number of overall miss cycles
413 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.166895 # miss rate for overall accesses
414 system.cpu.l2cache.overall_miss_rate::total 0.166895 # miss rate for overall accesses
415 system.cpu.l2cache.overall_misses::cpu.inst 7669 # number of overall misses
416 system.cpu.l2cache.overall_misses::total 7669 # number of overall misses
417 system.cpu.l2cache.overall_mshr_hits::cpu.inst 42 # number of overall MSHR hits
418 system.cpu.l2cache.overall_mshr_hits::total 42 # number of overall MSHR hits
419 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 427276750 # number of overall MSHR miss cycles
420 system.cpu.l2cache.overall_mshr_miss_latency::total 427276750 # number of overall MSHR miss cycles
421 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.165981 # mshr miss rate for overall accesses
422 system.cpu.l2cache.overall_mshr_miss_rate::total 0.165981 # mshr miss rate for overall accesses
423 system.cpu.l2cache.overall_mshr_misses::cpu.inst 7627 # number of overall MSHR misses
424 system.cpu.l2cache.overall_mshr_misses::total 7627 # number of overall MSHR misses
425 system.cpu.l2cache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id
426 system.cpu.l2cache.tags.age_task_id_blocks_1024::1 43 # Occupied blocks per task id
427 system.cpu.l2cache.tags.age_task_id_blocks_1024::2 40 # Occupied blocks per task id
428 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1262 # Occupied blocks per task id
429 system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4305 # Occupied blocks per task id
430 system.cpu.l2cache.tags.avg_refs 6.727368 # Average number of references to valid blocks.
431 system.cpu.l2cache.tags.data_accesses 384272 # Number of data accesses
432 system.cpu.l2cache.tags.occ_blocks::writebacks 356.812936 # Average occupied blocks per requestor
433 system.cpu.l2cache.tags.occ_blocks::cpu.inst 3883.048925 # Average occupied blocks per requestor
434 system.cpu.l2cache.tags.occ_percent::writebacks 0.010889 # Average percentage of cache occupancy
435 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.118501 # Average percentage of cache occupancy
436 system.cpu.l2cache.tags.occ_percent::total 0.129390 # Average percentage of cache occupancy
437 system.cpu.l2cache.tags.occ_task_id_blocks::1024 5700 # Occupied blocks per task id
438 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.173950 # Percentage of cache occupancy per task id
439 system.cpu.l2cache.tags.replacements 0 # number of replacements
440 system.cpu.l2cache.tags.sampled_refs 5700 # Sample count of references to valid blocks.
441 system.cpu.l2cache.tags.tag_accesses 384272 # Number of tag accesses
442 system.cpu.l2cache.tags.tagsinuse 4239.861860 # Cycle average of tags in use
443 system.cpu.l2cache.tags.total_refs 38346 # Total number of references to valid blocks.
444 system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
445 system.cpu.numCycles 454891032 # number of cpu cycles simulated
446 system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
447 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
448 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
449 system.cpu.tickCycles 450861086 # Number of cycles that the CPU actually ticked
450 system.cpu.toL2Bus.data_through_bus 3005632 # Total data (bytes)
451 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 82859 # Packet count per connected master and slave (bytes)
452 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10055 # Packet count per connected master and slave (bytes)
453 system.cpu.toL2Bus.pkt_count::total 92914 # Packet count per connected master and slave (bytes)
454 system.cpu.toL2Bus.reqLayer0.occupancy 24495000 # Layer occupancy (ticks)
455 system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
456 system.cpu.toL2Bus.respLayer0.occupancy 62845998 # Layer occupancy (ticks)
457 system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
458 system.cpu.toL2Bus.respLayer1.occupancy 7514710 # Layer occupancy (ticks)
459 system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
460 system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
461 system.cpu.toL2Bus.throughput 13214734 # Throughput (bytes/s)
462 system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2651456 # Cumulative packet size per connected master and slave (bytes)
463 system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 354176 # Cumulative packet size per connected master and slave (bytes)
464 system.cpu.toL2Bus.tot_pkt_size::total 3005632 # Cumulative packet size per connected master and slave (bytes)
465 system.cpu.toL2Bus.trans_dist::ReadReq 43091 # Transaction distribution
466 system.cpu.toL2Bus.trans_dist::ReadResp 43090 # Transaction distribution
467 system.cpu.toL2Bus.trans_dist::Writeback 1013 # Transaction distribution
468 system.cpu.toL2Bus.trans_dist::ReadExReq 2860 # Transaction distribution
469 system.cpu.toL2Bus.trans_dist::ReadExResp 2860 # Transaction distribution
470 system.cpu.workload.num_syscalls 191 # Number of system calls
471 system.cpu_clk_domain.clock 500 # Clock period in ticks
472 system.membus.data_through_bus 488128 # Total data (bytes)
473 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 15254 # Packet count per connected master and slave (bytes)
474 system.membus.pkt_count::total 15254 # Packet count per connected master and slave (bytes)
475 system.membus.reqLayer0.occupancy 8910000 # Layer occupancy (ticks)
476 system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
477 system.membus.respLayer1.occupancy 71341750 # Layer occupancy (ticks)
478 system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
479 system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
480 system.membus.throughput 2146132 # Throughput (bytes/s)
481 system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 488128 # Cumulative packet size per connected master and slave (bytes)
482 system.membus.tot_pkt_size::total 488128 # Cumulative packet size per connected master and slave (bytes)
483 system.membus.trans_dist::ReadReq 4783 # Transaction distribution
484 system.membus.trans_dist::ReadResp 4783 # Transaction distribution
485 system.membus.trans_dist::ReadExReq 2844 # Transaction distribution
486 system.membus.trans_dist::ReadExResp 2844 # Transaction distribution
487 system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
488 system.physmem.avgGap 29821084.57 # Average gap between requests
489 system.physmem.avgMemAccLat 25580.41 # Average memory access latency per DRAM burst
490 system.physmem.avgQLat 6830.41 # Average queueing delay per DRAM burst
491 system.physmem.avgRdBW 2.15 # Average DRAM read bandwidth in MiByte/s
492 system.physmem.avgRdBWSys 2.15 # Average system read bandwidth in MiByte/s
493 system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing
494 system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
495 system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
496 system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
497 system.physmem.busUtil 0.02 # Data bus utilization in percentage
498 system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads
499 system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
500 system.physmem.bw_inst_read::cpu.inst 974721 # Instruction read bandwidth from this memory (bytes/s)
501 system.physmem.bw_inst_read::total 974721 # Instruction read bandwidth from this memory (bytes/s)
502 system.physmem.bw_read::cpu.inst 2146132 # Total read bandwidth from this memory (bytes/s)
503 system.physmem.bw_read::total 2146132 # Total read bandwidth from this memory (bytes/s)
504 system.physmem.bw_total::cpu.inst 2146132 # Total bandwidth to/from this memory (bytes/s)
505 system.physmem.bw_total::total 2146132 # Total bandwidth to/from this memory (bytes/s)
506 system.physmem.bytesPerActivate::samples 1544 # Bytes accessed per row activation
507 system.physmem.bytesPerActivate::mean 315.689119 # Bytes accessed per row activation
508 system.physmem.bytesPerActivate::gmean 184.950751 # Bytes accessed per row activation
509 system.physmem.bytesPerActivate::stdev 330.584238 # Bytes accessed per row activation
510 system.physmem.bytesPerActivate::0-127 593 38.41% 38.41% # Bytes accessed per row activation
511 system.physmem.bytesPerActivate::128-255 326 21.11% 59.52% # Bytes accessed per row activation
512 system.physmem.bytesPerActivate::256-383 172 11.14% 70.66% # Bytes accessed per row activation
513 system.physmem.bytesPerActivate::384-511 76 4.92% 75.58% # Bytes accessed per row activation
514 system.physmem.bytesPerActivate::512-639 71 4.60% 80.18% # Bytes accessed per row activation
515 system.physmem.bytesPerActivate::640-767 58 3.76% 83.94% # Bytes accessed per row activation
516 system.physmem.bytesPerActivate::768-895 38 2.46% 86.40% # Bytes accessed per row activation
517 system.physmem.bytesPerActivate::896-1023 28 1.81% 88.21% # Bytes accessed per row activation
518 system.physmem.bytesPerActivate::1024-1151 182 11.79% 100.00% # Bytes accessed per row activation
519 system.physmem.bytesPerActivate::total 1544 # Bytes accessed per row activation
520 system.physmem.bytesReadDRAM 488128 # Total number of bytes read from DRAM
521 system.physmem.bytesReadSys 488128 # Total read bytes from the system interface side
522 system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
523 system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
524 system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
525 system.physmem.bytes_inst_read::cpu.inst 221696 # Number of instructions bytes read from this memory
526 system.physmem.bytes_inst_read::total 221696 # Number of instructions bytes read from this memory
527 system.physmem.bytes_read::cpu.inst 488128 # Number of bytes read from this memory
528 system.physmem.bytes_read::total 488128 # Number of bytes read from this memory
529 system.physmem.memoryStateTime::IDLE 217468466000 # Time in different power states
530 system.physmem.memoryStateTime::REF 7594860000 # Time in different power states
531 system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
532 system.physmem.memoryStateTime::ACT 2381096500 # Time in different power states
533 system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
534 system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
535 system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
536 system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
537 system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
538 system.physmem.num_reads::cpu.inst 7627 # Number of read requests responded to by this memory
539 system.physmem.num_reads::total 7627 # Number of read requests responded to by this memory
540 system.physmem.pageHitRate 79.70 # Row buffer hit rate, read and write combined
541 system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
542 system.physmem.perBankRdBursts::0 637 # Per bank write bursts
543 system.physmem.perBankRdBursts::1 850 # Per bank write bursts
544 system.physmem.perBankRdBursts::2 633 # Per bank write bursts
545 system.physmem.perBankRdBursts::3 541 # Per bank write bursts
546 system.physmem.perBankRdBursts::4 470 # Per bank write bursts
547 system.physmem.perBankRdBursts::5 350 # Per bank write bursts
548 system.physmem.perBankRdBursts::6 175 # Per bank write bursts
549 system.physmem.perBankRdBursts::7 229 # Per bank write bursts
550 system.physmem.perBankRdBursts::8 210 # Per bank write bursts
551 system.physmem.perBankRdBursts::9 309 # Per bank write bursts
552 system.physmem.perBankRdBursts::10 346 # Per bank write bursts
553 system.physmem.perBankRdBursts::11 428 # Per bank write bursts
554 system.physmem.perBankRdBursts::12 552 # Per bank write bursts
555 system.physmem.perBankRdBursts::13 714 # Per bank write bursts
556 system.physmem.perBankRdBursts::14 639 # Per bank write bursts
557 system.physmem.perBankRdBursts::15 544 # Per bank write bursts
558 system.physmem.perBankWrBursts::0 0 # Per bank write bursts
559 system.physmem.perBankWrBursts::1 0 # Per bank write bursts
560 system.physmem.perBankWrBursts::2 0 # Per bank write bursts
561 system.physmem.perBankWrBursts::3 0 # Per bank write bursts
562 system.physmem.perBankWrBursts::4 0 # Per bank write bursts
563 system.physmem.perBankWrBursts::5 0 # Per bank write bursts
564 system.physmem.perBankWrBursts::6 0 # Per bank write bursts
565 system.physmem.perBankWrBursts::7 0 # Per bank write bursts
566 system.physmem.perBankWrBursts::8 0 # Per bank write bursts
567 system.physmem.perBankWrBursts::9 0 # Per bank write bursts
568 system.physmem.perBankWrBursts::10 0 # Per bank write bursts
569 system.physmem.perBankWrBursts::11 0 # Per bank write bursts
570 system.physmem.perBankWrBursts::12 0 # Per bank write bursts
571 system.physmem.perBankWrBursts::13 0 # Per bank write bursts
572 system.physmem.perBankWrBursts::14 0 # Per bank write bursts
573 system.physmem.perBankWrBursts::15 0 # Per bank write bursts
574 system.physmem.rdQLenPdf::0 6680 # What read queue length does an incoming req see
575 system.physmem.rdQLenPdf::1 887 # What read queue length does an incoming req see
576 system.physmem.rdQLenPdf::2 60 # What read queue length does an incoming req see
577 system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
578 system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
579 system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
580 system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
581 system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
582 system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
583 system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
584 system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
585 system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
586 system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
587 system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
588 system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
589 system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
590 system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
591 system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
592 system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
593 system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
594 system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
595 system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
596 system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
597 system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
598 system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
599 system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
600 system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
601 system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
602 system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
603 system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
604 system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
605 system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
606 system.physmem.readBursts 7627 # Number of DRAM read bursts, including those serviced by the write queue
607 system.physmem.readPktSize::0 0 # Read request sizes (log2)
608 system.physmem.readPktSize::1 0 # Read request sizes (log2)
609 system.physmem.readPktSize::2 0 # Read request sizes (log2)
610 system.physmem.readPktSize::3 0 # Read request sizes (log2)
611 system.physmem.readPktSize::4 0 # Read request sizes (log2)
612 system.physmem.readPktSize::5 0 # Read request sizes (log2)
613 system.physmem.readPktSize::6 7627 # Read request sizes (log2)
614 system.physmem.readReqs 7627 # Number of read requests accepted
615 system.physmem.readRowHitRate 79.70 # Row buffer hit rate for reads
616 system.physmem.readRowHits 6079 # Number of row buffer hits during reads
617 system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
618 system.physmem.totBusLat 38135000 # Total ticks spent in databus transfers
619 system.physmem.totGap 227445412000 # Total gap between requests
620 system.physmem.totMemAccLat 195101750 # Total ticks spent from burst creation until serviced by the DRAM
621 system.physmem.totQLat 52095500 # Total ticks spent queuing
622 system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
623 system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
624 system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
625 system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
626 system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
627 system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
628 system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
629 system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
630 system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
631 system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
632 system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
633 system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
634 system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
635 system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
636 system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
637 system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
638 system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
639 system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
640 system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
641 system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
642 system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
643 system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
644 system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
645 system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
646 system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
647 system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
648 system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
649 system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
650 system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
651 system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
652 system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
653 system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
654 system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
655 system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
656 system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
657 system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
658 system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
659 system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
660 system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
661 system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
662 system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
663 system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
664 system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
665 system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
666 system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
667 system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
668 system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
669 system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
670 system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
671 system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
672 system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
673 system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
674 system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
675 system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
676 system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
677 system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
678 system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
679 system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
680 system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
681 system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
682 system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
683 system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
684 system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
685 system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
686 system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
687 system.physmem.writePktSize::0 0 # Write request sizes (log2)
688 system.physmem.writePktSize::1 0 # Write request sizes (log2)
689 system.physmem.writePktSize::2 0 # Write request sizes (log2)
690 system.physmem.writePktSize::3 0 # Write request sizes (log2)
691 system.physmem.writePktSize::4 0 # Write request sizes (log2)
692 system.physmem.writePktSize::5 0 # Write request sizes (log2)
693 system.physmem.writePktSize::6 0 # Write request sizes (log2)
694 system.physmem.writeReqs 0 # Number of write requests accepted
695 system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
696 system.physmem.writeRowHits 0 # Number of row buffer hits during writes
697 system.voltage_domain.voltage 1 # Voltage in Volts
699 ---------- End Simulation Statistics ----------
projects / gem5.git / blob