tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini

   1 [root]
   2 type=Root
   3 children=system
   4 eventq_index=0
   5 full_system=false
   6 sim_quantum=0
   7 time_sync_enable=false
   8 time_sync_period=100000000000
   9 time_sync_spin_threshold=100000000
  10
  11 [system]
  12 type=System
  13 children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
  14 boot_osflags=a
  15 cache_line_size=64
  16 clk_domain=system.clk_domain
  17 eventq_index=0
  18 init_param=0
  19 kernel=
  20 kernel_addr_check=true
  21 load_addr_mask=1099511627775
  22 load_offset=0
  23 mem_mode=timing
  24 mem_ranges=
  25 memories=system.physmem
  26 num_work_ids=16
  27 readfile=
  28 symbolfile=
  29 work_begin_ckpt_count=0
  30 work_begin_cpu_id_exit=-1
  31 work_begin_exit_count=0
  32 work_cpus_ckpt_count=0
  33 work_end_ckpt_count=0
  34 work_end_exit_count=0
  35 work_item_id=-1
  36 system_port=system.membus.slave[0]
  37
  38 [system.clk_domain]
  39 type=SrcClockDomain
  40 clock=1000
  41 domain_id=-1
  42 eventq_index=0
  43 init_perf_level=0
  44 voltage_domain=system.voltage_domain
  45
  46 [system.cpu]
  47 type=DerivO3CPU
  48 children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload
  49 LFSTSize=1024
  50 LQEntries=32
  51 LSQCheckLoads=true
  52 LSQDepCheckShift=4
  53 SQEntries=32
  54 SSITSize=1024
  55 activity=0
  56 backComSize=5
  57 branchPred=system.cpu.branchPred
  58 cachePorts=200
  59 checker=Null
  60 clk_domain=system.cpu_clk_domain
  61 commitToDecodeDelay=1
  62 commitToFetchDelay=1
  63 commitToIEWDelay=1
  64 commitToRenameDelay=1
  65 commitWidth=8
  66 cpu_id=0
  67 decodeToFetchDelay=1
  68 decodeToRenameDelay=1
  69 decodeWidth=8
  70 dispatchWidth=8
  71 do_checkpoint_insts=true
  72 do_quiesce=true
  73 do_statistics_insts=true
  74 dstage2_mmu=system.cpu.dstage2_mmu
  75 dtb=system.cpu.dtb
  76 eventq_index=0
  77 fetchBufferSize=64
  78 fetchToDecodeDelay=1
  79 fetchTrapLatency=1
  80 fetchWidth=8
  81 forwardComSize=5
  82 fuPool=system.cpu.fuPool
  83 function_trace=false
  84 function_trace_start=0
  85 iewToCommitDelay=1
  86 iewToDecodeDelay=1
  87 iewToFetchDelay=1
  88 iewToRenameDelay=1
  89 interrupts=system.cpu.interrupts
  90 isa=system.cpu.isa
  91 issueToExecuteDelay=1
  92 issueWidth=8
  93 istage2_mmu=system.cpu.istage2_mmu
  94 itb=system.cpu.itb
  95 max_insts_all_threads=0
  96 max_insts_any_thread=0
  97 max_loads_all_threads=0
  98 max_loads_any_thread=0
  99 needsTSO=false
 100 numIQEntries=64
 101 numPhysCCRegs=0
 102 numPhysFloatRegs=256
 103 numPhysIntRegs=256
 104 numROBEntries=192
 105 numRobs=1
 106 numThreads=1
 107 profile=0
 108 progress_interval=0
 109 renameToDecodeDelay=1
 110 renameToFetchDelay=1
 111 renameToIEWDelay=2
 112 renameToROBDelay=1
 113 renameWidth=8
 114 simpoint_start_insts=
 115 smtCommitPolicy=RoundRobin
 116 smtFetchPolicy=SingleThread
 117 smtIQPolicy=Partitioned
 118 smtIQThreshold=100
 119 smtLSQPolicy=Partitioned
 120 smtLSQThreshold=100
 121 smtNumFetchingThreads=1
 122 smtROBPolicy=Partitioned
 123 smtROBThreshold=100
 124 socket_id=0
 125 squashWidth=8
 126 store_set_clear_period=250000
 127 switched_out=false
 128 system=system
 129 tracer=system.cpu.tracer
 130 trapLatency=13
 131 wbDepth=1
 132 wbWidth=8
 133 workload=system.cpu.workload
 134 dcache_port=system.cpu.dcache.cpu_side
 135 icache_port=system.cpu.icache.cpu_side
 136
 137 [system.cpu.branchPred]
 138 type=BranchPredictor
 139 BTBEntries=4096
 140 BTBTagSize=16
 141 RASSize=16
 142 choiceCtrBits=2
 143 choicePredictorSize=8192
 144 eventq_index=0
 145 globalCtrBits=2
 146 globalPredictorSize=8192
 147 instShiftAmt=2
 148 localCtrBits=2
 149 localHistoryTableSize=2048
 150 localPredictorSize=2048
 151 numThreads=1
 152 predType=tournament
 153
 154 [system.cpu.dcache]
 155 type=BaseCache
 156 children=tags
 157 addr_ranges=0:18446744073709551615
 158 assoc=2
 159 clk_domain=system.cpu_clk_domain
 160 eventq_index=0
 161 forward_snoops=true
 162 hit_latency=2
 163 is_top_level=true
 164 max_miss_count=0
 165 mshrs=4
 166 prefetch_on_access=false
 167 prefetcher=Null
 168 response_latency=2
 169 sequential_access=false
 170 size=262144
 171 system=system
 172 tags=system.cpu.dcache.tags
 173 tgts_per_mshr=20
 174 two_queue=false
 175 write_buffers=8
 176 cpu_side=system.cpu.dcache_port
 177 mem_side=system.cpu.toL2Bus.slave[1]
 178
 179 [system.cpu.dcache.tags]
 180 type=LRU
 181 assoc=2
 182 block_size=64
 183 clk_domain=system.cpu_clk_domain
 184 eventq_index=0
 185 hit_latency=2
 186 sequential_access=false
 187 size=262144
 188
 189 [system.cpu.dstage2_mmu]
 190 type=ArmStage2MMU
 191 children=stage2_tlb
 192 eventq_index=0
 193 stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
 194 tlb=system.cpu.dtb
 195
 196 [system.cpu.dstage2_mmu.stage2_tlb]
 197 type=ArmTLB
 198 children=walker
 199 eventq_index=0
 200 is_stage2=true
 201 size=32
 202 walker=system.cpu.dstage2_mmu.stage2_tlb.walker
 203
 204 [system.cpu.dstage2_mmu.stage2_tlb.walker]
 205 type=ArmTableWalker
 206 clk_domain=system.cpu_clk_domain
 207 eventq_index=0
 208 is_stage2=true
 209 num_squash_per_cycle=2
 210 sys=system
 211 port=system.cpu.toL2Bus.slave[5]
 212
 213 [system.cpu.dtb]
 214 type=ArmTLB
 215 children=walker
 216 eventq_index=0
 217 is_stage2=false
 218 size=64
 219 walker=system.cpu.dtb.walker
 220
 221 [system.cpu.dtb.walker]
 222 type=ArmTableWalker
 223 clk_domain=system.cpu_clk_domain
 224 eventq_index=0
 225 is_stage2=false
 226 num_squash_per_cycle=2
 227 sys=system
 228 port=system.cpu.toL2Bus.slave[3]
 229
 230 [system.cpu.fuPool]
 231 type=FUPool
 232 children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
 233 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
 234 eventq_index=0
 235
 236 [system.cpu.fuPool.FUList0]
 237 type=FUDesc
 238 children=opList
 239 count=6
 240 eventq_index=0
 241 opList=system.cpu.fuPool.FUList0.opList
 242
 243 [system.cpu.fuPool.FUList0.opList]
 244 type=OpDesc
 245 eventq_index=0
 246 issueLat=1
 247 opClass=IntAlu
 248 opLat=1
 249
 250 [system.cpu.fuPool.FUList1]
 251 type=FUDesc
 252 children=opList0 opList1
 253 count=2
 254 eventq_index=0
 255 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
 256
 257 [system.cpu.fuPool.FUList1.opList0]
 258 type=OpDesc
 259 eventq_index=0
 260 issueLat=1
 261 opClass=IntMult
 262 opLat=3
 263
 264 [system.cpu.fuPool.FUList1.opList1]
 265 type=OpDesc
 266 eventq_index=0
 267 issueLat=19
 268 opClass=IntDiv
 269 opLat=20
 270
 271 [system.cpu.fuPool.FUList2]
 272 type=FUDesc
 273 children=opList0 opList1 opList2
 274 count=4
 275 eventq_index=0
 276 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
 277
 278 [system.cpu.fuPool.FUList2.opList0]
 279 type=OpDesc
 280 eventq_index=0
 281 issueLat=1
 282 opClass=FloatAdd
 283 opLat=2
 284
 285 [system.cpu.fuPool.FUList2.opList1]
 286 type=OpDesc
 287 eventq_index=0
 288 issueLat=1
 289 opClass=FloatCmp
 290 opLat=2
 291
 292 [system.cpu.fuPool.FUList2.opList2]
 293 type=OpDesc
 294 eventq_index=0
 295 issueLat=1
 296 opClass=FloatCvt
 297 opLat=2
 298
 299 [system.cpu.fuPool.FUList3]
 300 type=FUDesc
 301 children=opList0 opList1 opList2
 302 count=2
 303 eventq_index=0
 304 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
 305
 306 [system.cpu.fuPool.FUList3.opList0]
 307 type=OpDesc
 308 eventq_index=0
 309 issueLat=1
 310 opClass=FloatMult
 311 opLat=4
 312
 313 [system.cpu.fuPool.FUList3.opList1]
 314 type=OpDesc
 315 eventq_index=0
 316 issueLat=12
 317 opClass=FloatDiv
 318 opLat=12
 319
 320 [system.cpu.fuPool.FUList3.opList2]
 321 type=OpDesc
 322 eventq_index=0
 323 issueLat=24
 324 opClass=FloatSqrt
 325 opLat=24
 326
 327 [system.cpu.fuPool.FUList4]
 328 type=FUDesc
 329 children=opList
 330 count=0
 331 eventq_index=0
 332 opList=system.cpu.fuPool.FUList4.opList
 333
 334 [system.cpu.fuPool.FUList4.opList]
 335 type=OpDesc
 336 eventq_index=0
 337 issueLat=1
 338 opClass=MemRead
 339 opLat=1
 340
 341 [system.cpu.fuPool.FUList5]
 342 type=FUDesc
 343 children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
 344 count=4
 345 eventq_index=0
 346 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
 347
 348 [system.cpu.fuPool.FUList5.opList00]
 349 type=OpDesc
 350 eventq_index=0
 351 issueLat=1
 352 opClass=SimdAdd
 353 opLat=1
 354
 355 [system.cpu.fuPool.FUList5.opList01]
 356 type=OpDesc
 357 eventq_index=0
 358 issueLat=1
 359 opClass=SimdAddAcc
 360 opLat=1
 361
 362 [system.cpu.fuPool.FUList5.opList02]
 363 type=OpDesc
 364 eventq_index=0
 365 issueLat=1
 366 opClass=SimdAlu
 367 opLat=1
 368
 369 [system.cpu.fuPool.FUList5.opList03]
 370 type=OpDesc
 371 eventq_index=0
 372 issueLat=1
 373 opClass=SimdCmp
 374 opLat=1
 375
 376 [system.cpu.fuPool.FUList5.opList04]
 377 type=OpDesc
 378 eventq_index=0
 379 issueLat=1
 380 opClass=SimdCvt
 381 opLat=1
 382
 383 [system.cpu.fuPool.FUList5.opList05]
 384 type=OpDesc
 385 eventq_index=0
 386 issueLat=1
 387 opClass=SimdMisc
 388 opLat=1
 389
 390 [system.cpu.fuPool.FUList5.opList06]
 391 type=OpDesc
 392 eventq_index=0
 393 issueLat=1
 394 opClass=SimdMult
 395 opLat=1
 396
 397 [system.cpu.fuPool.FUList5.opList07]
 398 type=OpDesc
 399 eventq_index=0
 400 issueLat=1
 401 opClass=SimdMultAcc
 402 opLat=1
 403
 404 [system.cpu.fuPool.FUList5.opList08]
 405 type=OpDesc
 406 eventq_index=0
 407 issueLat=1
 408 opClass=SimdShift
 409 opLat=1
 410
 411 [system.cpu.fuPool.FUList5.opList09]
 412 type=OpDesc
 413 eventq_index=0
 414 issueLat=1
 415 opClass=SimdShiftAcc
 416 opLat=1
 417
 418 [system.cpu.fuPool.FUList5.opList10]
 419 type=OpDesc
 420 eventq_index=0
 421 issueLat=1
 422 opClass=SimdSqrt
 423 opLat=1
 424
 425 [system.cpu.fuPool.FUList5.opList11]
 426 type=OpDesc
 427 eventq_index=0
 428 issueLat=1
 429 opClass=SimdFloatAdd
 430 opLat=1
 431
 432 [system.cpu.fuPool.FUList5.opList12]
 433 type=OpDesc
 434 eventq_index=0
 435 issueLat=1
 436 opClass=SimdFloatAlu
 437 opLat=1
 438
 439 [system.cpu.fuPool.FUList5.opList13]
 440 type=OpDesc
 441 eventq_index=0
 442 issueLat=1
 443 opClass=SimdFloatCmp
 444 opLat=1
 445
 446 [system.cpu.fuPool.FUList5.opList14]
 447 type=OpDesc
 448 eventq_index=0
 449 issueLat=1
 450 opClass=SimdFloatCvt
 451 opLat=1
 452
 453 [system.cpu.fuPool.FUList5.opList15]
 454 type=OpDesc
 455 eventq_index=0
 456 issueLat=1
 457 opClass=SimdFloatDiv
 458 opLat=1
 459
 460 [system.cpu.fuPool.FUList5.opList16]
 461 type=OpDesc
 462 eventq_index=0
 463 issueLat=1
 464 opClass=SimdFloatMisc
 465 opLat=1
 466
 467 [system.cpu.fuPool.FUList5.opList17]
 468 type=OpDesc
 469 eventq_index=0
 470 issueLat=1
 471 opClass=SimdFloatMult
 472 opLat=1
 473
 474 [system.cpu.fuPool.FUList5.opList18]
 475 type=OpDesc
 476 eventq_index=0
 477 issueLat=1
 478 opClass=SimdFloatMultAcc
 479 opLat=1
 480
 481 [system.cpu.fuPool.FUList5.opList19]
 482 type=OpDesc
 483 eventq_index=0
 484 issueLat=1
 485 opClass=SimdFloatSqrt
 486 opLat=1
 487
 488 [system.cpu.fuPool.FUList6]
 489 type=FUDesc
 490 children=opList
 491 count=0
 492 eventq_index=0
 493 opList=system.cpu.fuPool.FUList6.opList
 494
 495 [system.cpu.fuPool.FUList6.opList]
 496 type=OpDesc
 497 eventq_index=0
 498 issueLat=1
 499 opClass=MemWrite
 500 opLat=1
 501
 502 [system.cpu.fuPool.FUList7]
 503 type=FUDesc
 504 children=opList0 opList1
 505 count=4
 506 eventq_index=0
 507 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
 508
 509 [system.cpu.fuPool.FUList7.opList0]
 510 type=OpDesc
 511 eventq_index=0
 512 issueLat=1
 513 opClass=MemRead
 514 opLat=1
 515
 516 [system.cpu.fuPool.FUList7.opList1]
 517 type=OpDesc
 518 eventq_index=0
 519 issueLat=1
 520 opClass=MemWrite
 521 opLat=1
 522
 523 [system.cpu.fuPool.FUList8]
 524 type=FUDesc
 525 children=opList
 526 count=1
 527 eventq_index=0
 528 opList=system.cpu.fuPool.FUList8.opList
 529
 530 [system.cpu.fuPool.FUList8.opList]
 531 type=OpDesc
 532 eventq_index=0
 533 issueLat=3
 534 opClass=IprAccess
 535 opLat=3
 536
 537 [system.cpu.icache]
 538 type=BaseCache
 539 children=tags
 540 addr_ranges=0:18446744073709551615
 541 assoc=2
 542 clk_domain=system.cpu_clk_domain
 543 eventq_index=0
 544 forward_snoops=true
 545 hit_latency=2
 546 is_top_level=true
 547 max_miss_count=0
 548 mshrs=4
 549 prefetch_on_access=false
 550 prefetcher=Null
 551 response_latency=2
 552 sequential_access=false
 553 size=131072
 554 system=system
 555 tags=system.cpu.icache.tags
 556 tgts_per_mshr=20
 557 two_queue=false
 558 write_buffers=8
 559 cpu_side=system.cpu.icache_port
 560 mem_side=system.cpu.toL2Bus.slave[0]
 561
 562 [system.cpu.icache.tags]
 563 type=LRU
 564 assoc=2
 565 block_size=64
 566 clk_domain=system.cpu_clk_domain
 567 eventq_index=0
 568 hit_latency=2
 569 sequential_access=false
 570 size=131072
 571
 572 [system.cpu.interrupts]
 573 type=ArmInterrupts
 574 eventq_index=0
 575
 576 [system.cpu.isa]
 577 type=ArmISA
 578 eventq_index=0
 579 fpsid=1090793632
 580 id_aa64afr0_el1=0
 581 id_aa64afr1_el1=0
 582 id_aa64dfr0_el1=1052678
 583 id_aa64dfr1_el1=0
 584 id_aa64isar0_el1=0
 585 id_aa64isar1_el1=0
 586 id_aa64mmfr0_el1=15728642
 587 id_aa64mmfr1_el1=0
 588 id_aa64pfr0_el1=17
 589 id_aa64pfr1_el1=0
 590 id_isar0=34607377
 591 id_isar1=34677009
 592 id_isar2=555950401
 593 id_isar3=17899825
 594 id_isar4=268501314
 595 id_isar5=0
 596 id_mmfr0=270536963
 597 id_mmfr1=0
 598 id_mmfr2=19070976
 599 id_mmfr3=34611729
 600 id_pfr0=49
 601 id_pfr1=4113
 602 midr=1091551472
 603 system=system
 604
 605 [system.cpu.istage2_mmu]
 606 type=ArmStage2MMU
 607 children=stage2_tlb
 608 eventq_index=0
 609 stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
 610 tlb=system.cpu.itb
 611
 612 [system.cpu.istage2_mmu.stage2_tlb]
 613 type=ArmTLB
 614 children=walker
 615 eventq_index=0
 616 is_stage2=true
 617 size=32
 618 walker=system.cpu.istage2_mmu.stage2_tlb.walker
 619
 620 [system.cpu.istage2_mmu.stage2_tlb.walker]
 621 type=ArmTableWalker
 622 clk_domain=system.cpu_clk_domain
 623 eventq_index=0
 624 is_stage2=true
 625 num_squash_per_cycle=2
 626 sys=system
 627 port=system.cpu.toL2Bus.slave[4]
 628
 629 [system.cpu.itb]
 630 type=ArmTLB
 631 children=walker
 632 eventq_index=0
 633 is_stage2=false
 634 size=64
 635 walker=system.cpu.itb.walker
 636
 637 [system.cpu.itb.walker]
 638 type=ArmTableWalker
 639 clk_domain=system.cpu_clk_domain
 640 eventq_index=0
 641 is_stage2=false
 642 num_squash_per_cycle=2
 643 sys=system
 644 port=system.cpu.toL2Bus.slave[2]
 645
 646 [system.cpu.l2cache]
 647 type=BaseCache
 648 children=tags
 649 addr_ranges=0:18446744073709551615
 650 assoc=8
 651 clk_domain=system.cpu_clk_domain
 652 eventq_index=0
 653 forward_snoops=true
 654 hit_latency=20
 655 is_top_level=false
 656 max_miss_count=0
 657 mshrs=20
 658 prefetch_on_access=false
 659 prefetcher=Null
 660 response_latency=20
 661 sequential_access=false
 662 size=2097152
 663 system=system
 664 tags=system.cpu.l2cache.tags
 665 tgts_per_mshr=12
 666 two_queue=false
 667 write_buffers=8
 668 cpu_side=system.cpu.toL2Bus.master[0]
 669 mem_side=system.membus.slave[1]
 670
 671 [system.cpu.l2cache.tags]
 672 type=LRU
 673 assoc=8
 674 block_size=64
 675 clk_domain=system.cpu_clk_domain
 676 eventq_index=0
 677 hit_latency=20
 678 sequential_access=false
 679 size=2097152
 680
 681 [system.cpu.toL2Bus]
 682 type=CoherentBus
 683 clk_domain=system.cpu_clk_domain
 684 eventq_index=0
 685 header_cycles=1
 686 system=system
 687 use_default_range=false
 688 width=32
 689 master=system.cpu.l2cache.cpu_side
 690 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
 691
 692 [system.cpu.tracer]
 693 type=ExeTracer
 694 eventq_index=0
 695
 696 [system.cpu.workload]
 697 type=LiveProcess
 698 cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
 699 cwd=build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing
 700 egid=100
 701 env=
 702 errout=cerr
 703 euid=100
 704 eventq_index=0
 705 executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/eon
 706 gid=100
 707 input=cin
 708 max_stack_size=67108864
 709 output=cout
 710 pid=100
 711 ppid=99
 712 simpoint=0
 713 system=system
 714 uid=100
 715
 716 [system.cpu_clk_domain]
 717 type=SrcClockDomain
 718 clock=500
 719 domain_id=-1
 720 eventq_index=0
 721 init_perf_level=0
 722 voltage_domain=system.voltage_domain
 723
 724 [system.dvfs_handler]
 725 type=DVFSHandler
 726 domains=
 727 enable=false
 728 eventq_index=0
 729 sys_clk_domain=system.clk_domain
 730 transition_latency=100000000
 731
 732 [system.membus]
 733 type=CoherentBus
 734 clk_domain=system.clk_domain
 735 eventq_index=0
 736 header_cycles=1
 737 system=system
 738 use_default_range=false
 739 width=8
 740 master=system.physmem.port
 741 slave=system.system_port system.cpu.l2cache.mem_side
 742
 743 [system.physmem]
 744 type=DRAMCtrl
 745 activation_limit=4
 746 addr_mapping=RoRaBaChCo
 747 banks_per_rank=8
 748 burst_length=8
 749 channels=1
 750 clk_domain=system.clk_domain
 751 conf_table_reported=true
 752 device_bus_width=8
 753 device_rowbuffer_size=1024
 754 devices_per_rank=8
 755 eventq_index=0
 756 in_addr_map=true
 757 max_accesses_per_row=16
 758 mem_sched_policy=frfcfs
 759 min_writes_per_switch=16
 760 null=false
 761 page_policy=open_adaptive
 762 range=0:134217727
 763 ranks_per_channel=2
 764 read_buffer_size=32
 765 static_backend_latency=10000
 766 static_frontend_latency=10000
 767 tBURST=5000
 768 tCK=1250
 769 tCL=13750
 770 tRAS=35000
 771 tRCD=13750
 772 tREFI=7800000
 773 tRFC=260000
 774 tRP=13750
 775 tRRD=6000
 776 tRTP=7500
 777 tRTW=2500
 778 tWR=15000
 779 tWTR=7500
 780 tXAW=30000
 781 write_buffer_size=64
 782 write_high_thresh_perc=85
 783 write_low_thresh_perc=50
 784 port=system.membus.master[0]
 785
 786 [system.voltage_domain]
 787 type=VoltageDomain
 788 eventq_index=0
 789 voltage=1.000000
 790