tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini

   1 [root]
   2 type=Root
   3 children=system
   4 full_system=false
   5 time_sync_enable=false
   6 time_sync_period=100000000000
   7 time_sync_spin_threshold=100000000
   8
   9 [system]
  10 type=System
  11 children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
  12 boot_osflags=a
  13 cache_line_size=64
  14 clk_domain=system.clk_domain
  15 init_param=0
  16 kernel=
  17 load_addr_mask=1099511627775
  18 mem_mode=timing
  19 mem_ranges=
  20 memories=system.physmem
  21 num_work_ids=16
  22 readfile=
  23 symbolfile=
  24 work_begin_ckpt_count=0
  25 work_begin_cpu_id_exit=-1
  26 work_begin_exit_count=0
  27 work_cpus_ckpt_count=0
  28 work_end_ckpt_count=0
  29 work_end_exit_count=0
  30 work_item_id=-1
  31 system_port=system.membus.slave[0]
  32
  33 [system.clk_domain]
  34 type=SrcClockDomain
  35 clock=1000
  36 voltage_domain=system.voltage_domain
  37
  38 [system.cpu]
  39 type=DerivO3CPU
  40 children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
  41 LFSTSize=1024
  42 LQEntries=32
  43 LSQCheckLoads=true
  44 LSQDepCheckShift=4
  45 SQEntries=32
  46 SSITSize=1024
  47 activity=0
  48 backComSize=5
  49 branchPred=system.cpu.branchPred
  50 cachePorts=200
  51 checker=Null
  52 clk_domain=system.cpu_clk_domain
  53 commitToDecodeDelay=1
  54 commitToFetchDelay=1
  55 commitToIEWDelay=1
  56 commitToRenameDelay=1
  57 commitWidth=8
  58 cpu_id=0
  59 decodeToFetchDelay=1
  60 decodeToRenameDelay=1
  61 decodeWidth=8
  62 dispatchWidth=8
  63 do_checkpoint_insts=true
  64 do_quiesce=true
  65 do_statistics_insts=true
  66 dtb=system.cpu.dtb
  67 fetchToDecodeDelay=1
  68 fetchTrapLatency=1
  69 fetchWidth=8
  70 forwardComSize=5
  71 fuPool=system.cpu.fuPool
  72 function_trace=false
  73 function_trace_start=0
  74 iewToCommitDelay=1
  75 iewToDecodeDelay=1
  76 iewToFetchDelay=1
  77 iewToRenameDelay=1
  78 interrupts=system.cpu.interrupts
  79 isa=system.cpu.isa
  80 issueToExecuteDelay=1
  81 issueWidth=8
  82 itb=system.cpu.itb
  83 max_insts_all_threads=0
  84 max_insts_any_thread=0
  85 max_loads_all_threads=0
  86 max_loads_any_thread=0
  87 needsTSO=false
  88 numIQEntries=64
  89 numPhysFloatRegs=256
  90 numPhysIntRegs=256
  91 numROBEntries=192
  92 numRobs=1
  93 numThreads=1
  94 profile=0
  95 progress_interval=0
  96 renameToDecodeDelay=1
  97 renameToFetchDelay=1
  98 renameToIEWDelay=2
  99 renameToROBDelay=1
 100 renameWidth=8
 101 simpoint_start_insts=
 102 smtCommitPolicy=RoundRobin
 103 smtFetchPolicy=SingleThread
 104 smtIQPolicy=Partitioned
 105 smtIQThreshold=100
 106 smtLSQPolicy=Partitioned
 107 smtLSQThreshold=100
 108 smtNumFetchingThreads=1
 109 smtROBPolicy=Partitioned
 110 smtROBThreshold=100
 111 squashWidth=8
 112 store_set_clear_period=250000
 113 switched_out=false
 114 system=system
 115 tracer=system.cpu.tracer
 116 trapLatency=13
 117 wbDepth=1
 118 wbWidth=8
 119 workload=system.cpu.workload
 120 dcache_port=system.cpu.dcache.cpu_side
 121 icache_port=system.cpu.icache.cpu_side
 122
 123 [system.cpu.branchPred]
 124 type=BranchPredictor
 125 BTBEntries=4096
 126 BTBTagSize=16
 127 RASSize=16
 128 choiceCtrBits=2
 129 choicePredictorSize=8192
 130 globalCtrBits=2
 131 globalPredictorSize=8192
 132 instShiftAmt=2
 133 localCtrBits=2
 134 localHistoryTableSize=2048
 135 localPredictorSize=2048
 136 numThreads=1
 137 predType=tournament
 138
 139 [system.cpu.dcache]
 140 type=BaseCache
 141 children=tags
 142 addr_ranges=0:18446744073709551615
 143 assoc=2
 144 clk_domain=system.cpu_clk_domain
 145 forward_snoops=true
 146 hit_latency=2
 147 is_top_level=true
 148 max_miss_count=0
 149 mshrs=4
 150 prefetch_on_access=false
 151 prefetcher=Null
 152 response_latency=2
 153 size=262144
 154 system=system
 155 tags=system.cpu.dcache.tags
 156 tgts_per_mshr=20
 157 two_queue=false
 158 write_buffers=8
 159 cpu_side=system.cpu.dcache_port
 160 mem_side=system.cpu.toL2Bus.slave[1]
 161
 162 [system.cpu.dcache.tags]
 163 type=LRU
 164 assoc=2
 165 block_size=64
 166 clk_domain=system.cpu_clk_domain
 167 hit_latency=2
 168 size=262144
 169
 170 [system.cpu.dtb]
 171 type=ArmTLB
 172 children=walker
 173 size=64
 174 walker=system.cpu.dtb.walker
 175
 176 [system.cpu.dtb.walker]
 177 type=ArmTableWalker
 178 clk_domain=system.cpu_clk_domain
 179 num_squash_per_cycle=2
 180 sys=system
 181 port=system.cpu.toL2Bus.slave[3]
 182
 183 [system.cpu.fuPool]
 184 type=FUPool
 185 children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
 186 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
 187
 188 [system.cpu.fuPool.FUList0]
 189 type=FUDesc
 190 children=opList
 191 count=6
 192 opList=system.cpu.fuPool.FUList0.opList
 193
 194 [system.cpu.fuPool.FUList0.opList]
 195 type=OpDesc
 196 issueLat=1
 197 opClass=IntAlu
 198 opLat=1
 199
 200 [system.cpu.fuPool.FUList1]
 201 type=FUDesc
 202 children=opList0 opList1
 203 count=2
 204 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
 205
 206 [system.cpu.fuPool.FUList1.opList0]
 207 type=OpDesc
 208 issueLat=1
 209 opClass=IntMult
 210 opLat=3
 211
 212 [system.cpu.fuPool.FUList1.opList1]
 213 type=OpDesc
 214 issueLat=19
 215 opClass=IntDiv
 216 opLat=20
 217
 218 [system.cpu.fuPool.FUList2]
 219 type=FUDesc
 220 children=opList0 opList1 opList2
 221 count=4
 222 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
 223
 224 [system.cpu.fuPool.FUList2.opList0]
 225 type=OpDesc
 226 issueLat=1
 227 opClass=FloatAdd
 228 opLat=2
 229
 230 [system.cpu.fuPool.FUList2.opList1]
 231 type=OpDesc
 232 issueLat=1
 233 opClass=FloatCmp
 234 opLat=2
 235
 236 [system.cpu.fuPool.FUList2.opList2]
 237 type=OpDesc
 238 issueLat=1
 239 opClass=FloatCvt
 240 opLat=2
 241
 242 [system.cpu.fuPool.FUList3]
 243 type=FUDesc
 244 children=opList0 opList1 opList2
 245 count=2
 246 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
 247
 248 [system.cpu.fuPool.FUList3.opList0]
 249 type=OpDesc
 250 issueLat=1
 251 opClass=FloatMult
 252 opLat=4
 253
 254 [system.cpu.fuPool.FUList3.opList1]
 255 type=OpDesc
 256 issueLat=12
 257 opClass=FloatDiv
 258 opLat=12
 259
 260 [system.cpu.fuPool.FUList3.opList2]
 261 type=OpDesc
 262 issueLat=24
 263 opClass=FloatSqrt
 264 opLat=24
 265
 266 [system.cpu.fuPool.FUList4]
 267 type=FUDesc
 268 children=opList
 269 count=0
 270 opList=system.cpu.fuPool.FUList4.opList
 271
 272 [system.cpu.fuPool.FUList4.opList]
 273 type=OpDesc
 274 issueLat=1
 275 opClass=MemRead
 276 opLat=1
 277
 278 [system.cpu.fuPool.FUList5]
 279 type=FUDesc
 280 children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
 281 count=4
 282 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
 283
 284 [system.cpu.fuPool.FUList5.opList00]
 285 type=OpDesc
 286 issueLat=1
 287 opClass=SimdAdd
 288 opLat=1
 289
 290 [system.cpu.fuPool.FUList5.opList01]
 291 type=OpDesc
 292 issueLat=1
 293 opClass=SimdAddAcc
 294 opLat=1
 295
 296 [system.cpu.fuPool.FUList5.opList02]
 297 type=OpDesc
 298 issueLat=1
 299 opClass=SimdAlu
 300 opLat=1
 301
 302 [system.cpu.fuPool.FUList5.opList03]
 303 type=OpDesc
 304 issueLat=1
 305 opClass=SimdCmp
 306 opLat=1
 307
 308 [system.cpu.fuPool.FUList5.opList04]
 309 type=OpDesc
 310 issueLat=1
 311 opClass=SimdCvt
 312 opLat=1
 313
 314 [system.cpu.fuPool.FUList5.opList05]
 315 type=OpDesc
 316 issueLat=1
 317 opClass=SimdMisc
 318 opLat=1
 319
 320 [system.cpu.fuPool.FUList5.opList06]
 321 type=OpDesc
 322 issueLat=1
 323 opClass=SimdMult
 324 opLat=1
 325
 326 [system.cpu.fuPool.FUList5.opList07]
 327 type=OpDesc
 328 issueLat=1
 329 opClass=SimdMultAcc
 330 opLat=1
 331
 332 [system.cpu.fuPool.FUList5.opList08]
 333 type=OpDesc
 334 issueLat=1
 335 opClass=SimdShift
 336 opLat=1
 337
 338 [system.cpu.fuPool.FUList5.opList09]
 339 type=OpDesc
 340 issueLat=1
 341 opClass=SimdShiftAcc
 342 opLat=1
 343
 344 [system.cpu.fuPool.FUList5.opList10]
 345 type=OpDesc
 346 issueLat=1
 347 opClass=SimdSqrt
 348 opLat=1
 349
 350 [system.cpu.fuPool.FUList5.opList11]
 351 type=OpDesc
 352 issueLat=1
 353 opClass=SimdFloatAdd
 354 opLat=1
 355
 356 [system.cpu.fuPool.FUList5.opList12]
 357 type=OpDesc
 358 issueLat=1
 359 opClass=SimdFloatAlu
 360 opLat=1
 361
 362 [system.cpu.fuPool.FUList5.opList13]
 363 type=OpDesc
 364 issueLat=1
 365 opClass=SimdFloatCmp
 366 opLat=1
 367
 368 [system.cpu.fuPool.FUList5.opList14]
 369 type=OpDesc
 370 issueLat=1
 371 opClass=SimdFloatCvt
 372 opLat=1
 373
 374 [system.cpu.fuPool.FUList5.opList15]
 375 type=OpDesc
 376 issueLat=1
 377 opClass=SimdFloatDiv
 378 opLat=1
 379
 380 [system.cpu.fuPool.FUList5.opList16]
 381 type=OpDesc
 382 issueLat=1
 383 opClass=SimdFloatMisc
 384 opLat=1
 385
 386 [system.cpu.fuPool.FUList5.opList17]
 387 type=OpDesc
 388 issueLat=1
 389 opClass=SimdFloatMult
 390 opLat=1
 391
 392 [system.cpu.fuPool.FUList5.opList18]
 393 type=OpDesc
 394 issueLat=1
 395 opClass=SimdFloatMultAcc
 396 opLat=1
 397
 398 [system.cpu.fuPool.FUList5.opList19]
 399 type=OpDesc
 400 issueLat=1
 401 opClass=SimdFloatSqrt
 402 opLat=1
 403
 404 [system.cpu.fuPool.FUList6]
 405 type=FUDesc
 406 children=opList
 407 count=0
 408 opList=system.cpu.fuPool.FUList6.opList
 409
 410 [system.cpu.fuPool.FUList6.opList]
 411 type=OpDesc
 412 issueLat=1
 413 opClass=MemWrite
 414 opLat=1
 415
 416 [system.cpu.fuPool.FUList7]
 417 type=FUDesc
 418 children=opList0 opList1
 419 count=4
 420 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
 421
 422 [system.cpu.fuPool.FUList7.opList0]
 423 type=OpDesc
 424 issueLat=1
 425 opClass=MemRead
 426 opLat=1
 427
 428 [system.cpu.fuPool.FUList7.opList1]
 429 type=OpDesc
 430 issueLat=1
 431 opClass=MemWrite
 432 opLat=1
 433
 434 [system.cpu.fuPool.FUList8]
 435 type=FUDesc
 436 children=opList
 437 count=1
 438 opList=system.cpu.fuPool.FUList8.opList
 439
 440 [system.cpu.fuPool.FUList8.opList]
 441 type=OpDesc
 442 issueLat=3
 443 opClass=IprAccess
 444 opLat=3
 445
 446 [system.cpu.icache]
 447 type=BaseCache
 448 children=tags
 449 addr_ranges=0:18446744073709551615
 450 assoc=2
 451 clk_domain=system.cpu_clk_domain
 452 forward_snoops=true
 453 hit_latency=2
 454 is_top_level=true
 455 max_miss_count=0
 456 mshrs=4
 457 prefetch_on_access=false
 458 prefetcher=Null
 459 response_latency=2
 460 size=131072
 461 system=system
 462 tags=system.cpu.icache.tags
 463 tgts_per_mshr=20
 464 two_queue=false
 465 write_buffers=8
 466 cpu_side=system.cpu.icache_port
 467 mem_side=system.cpu.toL2Bus.slave[0]
 468
 469 [system.cpu.icache.tags]
 470 type=LRU
 471 assoc=2
 472 block_size=64
 473 clk_domain=system.cpu_clk_domain
 474 hit_latency=2
 475 size=131072
 476
 477 [system.cpu.interrupts]
 478 type=ArmInterrupts
 479
 480 [system.cpu.isa]
 481 type=ArmISA
 482 fpsid=1090793632
 483 id_isar0=34607377
 484 id_isar1=34677009
 485 id_isar2=555950401
 486 id_isar3=17899825
 487 id_isar4=268501314
 488 id_isar5=0
 489 id_mmfr0=3
 490 id_mmfr1=0
 491 id_mmfr2=19070976
 492 id_mmfr3=4027589137
 493 id_pfr0=49
 494 id_pfr1=1
 495 midr=890224640
 496
 497 [system.cpu.itb]
 498 type=ArmTLB
 499 children=walker
 500 size=64
 501 walker=system.cpu.itb.walker
 502
 503 [system.cpu.itb.walker]
 504 type=ArmTableWalker
 505 clk_domain=system.cpu_clk_domain
 506 num_squash_per_cycle=2
 507 sys=system
 508 port=system.cpu.toL2Bus.slave[2]
 509
 510 [system.cpu.l2cache]
 511 type=BaseCache
 512 children=tags
 513 addr_ranges=0:18446744073709551615
 514 assoc=8
 515 clk_domain=system.cpu_clk_domain
 516 forward_snoops=true
 517 hit_latency=20
 518 is_top_level=false
 519 max_miss_count=0
 520 mshrs=20
 521 prefetch_on_access=false
 522 prefetcher=Null
 523 response_latency=20
 524 size=2097152
 525 system=system
 526 tags=system.cpu.l2cache.tags
 527 tgts_per_mshr=12
 528 two_queue=false
 529 write_buffers=8
 530 cpu_side=system.cpu.toL2Bus.master[0]
 531 mem_side=system.membus.slave[1]
 532
 533 [system.cpu.l2cache.tags]
 534 type=LRU
 535 assoc=8
 536 block_size=64
 537 clk_domain=system.cpu_clk_domain
 538 hit_latency=20
 539 size=2097152
 540
 541 [system.cpu.toL2Bus]
 542 type=CoherentBus
 543 clk_domain=system.cpu_clk_domain
 544 header_cycles=1
 545 system=system
 546 use_default_range=false
 547 width=32
 548 master=system.cpu.l2cache.cpu_side
 549 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
 550
 551 [system.cpu.tracer]
 552 type=ExeTracer
 553
 554 [system.cpu.workload]
 555 type=LiveProcess
 556 cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
 557 cwd=build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing
 558 egid=100
 559 env=
 560 errout=cerr
 561 euid=100
 562 executable=/dist/m5/cpu2000/binaries/arm/linux/eon
 563 gid=100
 564 input=cin
 565 max_stack_size=67108864
 566 output=cout
 567 pid=100
 568 ppid=99
 569 simpoint=0
 570 system=system
 571 uid=100
 572
 573 [system.cpu_clk_domain]
 574 type=SrcClockDomain
 575 clock=500
 576 voltage_domain=system.voltage_domain
 577
 578 [system.membus]
 579 type=CoherentBus
 580 clk_domain=system.clk_domain
 581 header_cycles=1
 582 system=system
 583 use_default_range=false
 584 width=8
 585 master=system.physmem.port
 586 slave=system.system_port system.cpu.l2cache.mem_side
 587
 588 [system.physmem]
 589 type=SimpleDRAM
 590 activation_limit=4
 591 addr_mapping=RaBaChCo
 592 banks_per_rank=8
 593 burst_length=8
 594 channels=1
 595 clk_domain=system.clk_domain
 596 conf_table_reported=true
 597 device_bus_width=8
 598 device_rowbuffer_size=1024
 599 devices_per_rank=8
 600 in_addr_map=true
 601 mem_sched_policy=frfcfs
 602 null=false
 603 page_policy=open
 604 range=0:134217727
 605 ranks_per_channel=2
 606 read_buffer_size=32
 607 static_backend_latency=10000
 608 static_frontend_latency=10000
 609 tBURST=5000
 610 tCL=13750
 611 tRCD=13750
 612 tREFI=7800000
 613 tRFC=300000
 614 tRP=13750
 615 tWTR=7500
 616 tXAW=40000
 617 write_buffer_size=32
 618 write_thresh_perc=70
 619 port=system.membus.master[0]
 620
 621 [system.voltage_domain]
 622 type=VoltageDomain
 623 voltage=1.000000
 624