2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.068340 # Number of seconds simulated
4 sim_ticks 68340072000 # Number of ticks simulated
5 final_tick 68340072000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 97727 # Simulator instruction rate (inst/s)
8 host_op_rate 124939 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 24460648 # Simulator tick rate (ticks/s)
10 host_mem_usage 254748 # Number of bytes of host memory used
11 host_seconds 2793.88 # Real time elapsed on the host
12 sim_insts 273036725 # Number of instructions simulated
13 sim_ops 349064449 # Number of ops (including micro ops) simulated
14 system.physmem.bytes_read::cpu.inst 193856 # Number of bytes read from this memory
15 system.physmem.bytes_read::cpu.data 272320 # Number of bytes read from this memory
16 system.physmem.bytes_read::total 466176 # Number of bytes read from this memory
17 system.physmem.bytes_inst_read::cpu.inst 193856 # Number of instructions bytes read from this memory
18 system.physmem.bytes_inst_read::total 193856 # Number of instructions bytes read from this memory
19 system.physmem.num_reads::cpu.inst 3029 # Number of read requests responded to by this memory
20 system.physmem.num_reads::cpu.data 4255 # Number of read requests responded to by this memory
21 system.physmem.num_reads::total 7284 # Number of read requests responded to by this memory
22 system.physmem.bw_read::cpu.inst 2836637 # Total read bandwidth from this memory (bytes/s)
23 system.physmem.bw_read::cpu.data 3984778 # Total read bandwidth from this memory (bytes/s)
24 system.physmem.bw_read::total 6821415 # Total read bandwidth from this memory (bytes/s)
25 system.physmem.bw_inst_read::cpu.inst 2836637 # Instruction read bandwidth from this memory (bytes/s)
26 system.physmem.bw_inst_read::total 2836637 # Instruction read bandwidth from this memory (bytes/s)
27 system.physmem.bw_total::cpu.inst 2836637 # Total bandwidth to/from this memory (bytes/s)
28 system.physmem.bw_total::cpu.data 3984778 # Total bandwidth to/from this memory (bytes/s)
29 system.physmem.bw_total::total 6821415 # Total bandwidth to/from this memory (bytes/s)
30 system.physmem.readReqs 7284 # Total number of read requests seen
31 system.physmem.writeReqs 0 # Total number of write requests seen
32 system.physmem.cpureqs 7289 # Reqs generatd by CPU via cache - shady
33 system.physmem.bytesRead 466176 # Total number of bytes read from memory
34 system.physmem.bytesWritten 0 # Total number of bytes written to memory
35 system.physmem.bytesConsumedRd 466176 # bytesRead derated as per pkt->getSize()
36 system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
37 system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
38 system.physmem.neitherReadNorWrite 5 # Reqs where no action is needed
39 system.physmem.perBankRdReqs::0 605 # Track reads on a per bank basis
40 system.physmem.perBankRdReqs::1 803 # Track reads on a per bank basis
41 system.physmem.perBankRdReqs::2 607 # Track reads on a per bank basis
42 system.physmem.perBankRdReqs::3 525 # Track reads on a per bank basis
43 system.physmem.perBankRdReqs::4 442 # Track reads on a per bank basis
44 system.physmem.perBankRdReqs::5 354 # Track reads on a per bank basis
45 system.physmem.perBankRdReqs::6 161 # Track reads on a per bank basis
46 system.physmem.perBankRdReqs::7 219 # Track reads on a per bank basis
47 system.physmem.perBankRdReqs::8 210 # Track reads on a per bank basis
48 system.physmem.perBankRdReqs::9 288 # Track reads on a per bank basis
49 system.physmem.perBankRdReqs::10 325 # Track reads on a per bank basis
50 system.physmem.perBankRdReqs::11 414 # Track reads on a per bank basis
51 system.physmem.perBankRdReqs::12 530 # Track reads on a per bank basis
52 system.physmem.perBankRdReqs::13 686 # Track reads on a per bank basis
53 system.physmem.perBankRdReqs::14 611 # Track reads on a per bank basis
54 system.physmem.perBankRdReqs::15 504 # Track reads on a per bank basis
55 system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
56 system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
57 system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
58 system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
59 system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
60 system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
61 system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
62 system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
63 system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
64 system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
65 system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
66 system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
67 system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
68 system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
69 system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
70 system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
71 system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
72 system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
73 system.physmem.totGap 68339875000 # Total gap between requests
74 system.physmem.readPktSize::0 0 # Categorize read packet sizes
75 system.physmem.readPktSize::1 0 # Categorize read packet sizes
76 system.physmem.readPktSize::2 0 # Categorize read packet sizes
77 system.physmem.readPktSize::3 0 # Categorize read packet sizes
78 system.physmem.readPktSize::4 0 # Categorize read packet sizes
79 system.physmem.readPktSize::5 0 # Categorize read packet sizes
80 system.physmem.readPktSize::6 7284 # Categorize read packet sizes
81 system.physmem.writePktSize::0 0 # Categorize write packet sizes
82 system.physmem.writePktSize::1 0 # Categorize write packet sizes
83 system.physmem.writePktSize::2 0 # Categorize write packet sizes
84 system.physmem.writePktSize::3 0 # Categorize write packet sizes
85 system.physmem.writePktSize::4 0 # Categorize write packet sizes
86 system.physmem.writePktSize::5 0 # Categorize write packet sizes
87 system.physmem.writePktSize::6 0 # Categorize write packet sizes
88 system.physmem.rdQLenPdf::0 4420 # What read queue length does an incoming req see
89 system.physmem.rdQLenPdf::1 2077 # What read queue length does an incoming req see
90 system.physmem.rdQLenPdf::2 561 # What read queue length does an incoming req see
91 system.physmem.rdQLenPdf::3 165 # What read queue length does an incoming req see
92 system.physmem.rdQLenPdf::4 60 # What read queue length does an incoming req see
93 system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
94 system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
95 system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
96 system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
97 system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
98 system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
99 system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
100 system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
101 system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
102 system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
103 system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
104 system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
105 system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
106 system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
107 system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
108 system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
109 system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
110 system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
111 system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
112 system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
113 system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
114 system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
115 system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
116 system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
117 system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
118 system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
119 system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
120 system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
121 system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
122 system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
123 system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
124 system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
125 system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
126 system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
127 system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
128 system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
129 system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
130 system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
131 system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
132 system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
133 system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
134 system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
135 system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
136 system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
137 system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
138 system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
139 system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
140 system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
141 system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
142 system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
143 system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
144 system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
145 system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
146 system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
147 system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
148 system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
149 system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
150 system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
151 system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
152 system.physmem.bytesPerActivate::samples 717 # Bytes accessed per row activation
153 system.physmem.bytesPerActivate::mean 639.642957 # Bytes accessed per row activation
154 system.physmem.bytesPerActivate::gmean 236.501213 # Bytes accessed per row activation
155 system.physmem.bytesPerActivate::stdev 1328.325684 # Bytes accessed per row activation
156 system.physmem.bytesPerActivate::64-65 231 32.22% 32.22% # Bytes accessed per row activation
157 system.physmem.bytesPerActivate::128-129 96 13.39% 45.61% # Bytes accessed per row activation
158 system.physmem.bytesPerActivate::192-193 63 8.79% 54.39% # Bytes accessed per row activation
159 system.physmem.bytesPerActivate::256-257 56 7.81% 62.20% # Bytes accessed per row activation
160 system.physmem.bytesPerActivate::320-321 30 4.18% 66.39% # Bytes accessed per row activation
161 system.physmem.bytesPerActivate::384-385 30 4.18% 70.57% # Bytes accessed per row activation
162 system.physmem.bytesPerActivate::448-449 16 2.23% 72.80% # Bytes accessed per row activation
163 system.physmem.bytesPerActivate::512-513 21 2.93% 75.73% # Bytes accessed per row activation
164 system.physmem.bytesPerActivate::576-577 13 1.81% 77.55% # Bytes accessed per row activation
165 system.physmem.bytesPerActivate::640-641 17 2.37% 79.92% # Bytes accessed per row activation
166 system.physmem.bytesPerActivate::704-705 8 1.12% 81.03% # Bytes accessed per row activation
167 system.physmem.bytesPerActivate::768-769 12 1.67% 82.71% # Bytes accessed per row activation
168 system.physmem.bytesPerActivate::832-833 3 0.42% 83.12% # Bytes accessed per row activation
169 system.physmem.bytesPerActivate::896-897 9 1.26% 84.38% # Bytes accessed per row activation
170 system.physmem.bytesPerActivate::960-961 5 0.70% 85.08% # Bytes accessed per row activation
171 system.physmem.bytesPerActivate::1024-1025 7 0.98% 86.05% # Bytes accessed per row activation
172 system.physmem.bytesPerActivate::1088-1089 5 0.70% 86.75% # Bytes accessed per row activation
173 system.physmem.bytesPerActivate::1152-1153 5 0.70% 87.45% # Bytes accessed per row activation
174 system.physmem.bytesPerActivate::1216-1217 4 0.56% 88.01% # Bytes accessed per row activation
175 system.physmem.bytesPerActivate::1280-1281 4 0.56% 88.56% # Bytes accessed per row activation
176 system.physmem.bytesPerActivate::1344-1345 2 0.28% 88.84% # Bytes accessed per row activation
177 system.physmem.bytesPerActivate::1408-1409 4 0.56% 89.40% # Bytes accessed per row activation
178 system.physmem.bytesPerActivate::1472-1473 3 0.42% 89.82% # Bytes accessed per row activation
179 system.physmem.bytesPerActivate::1600-1601 4 0.56% 90.38% # Bytes accessed per row activation
180 system.physmem.bytesPerActivate::1664-1665 4 0.56% 90.93% # Bytes accessed per row activation
181 system.physmem.bytesPerActivate::1728-1729 2 0.28% 91.21% # Bytes accessed per row activation
182 system.physmem.bytesPerActivate::1792-1793 2 0.28% 91.49% # Bytes accessed per row activation
183 system.physmem.bytesPerActivate::1856-1857 2 0.28% 91.77% # Bytes accessed per row activation
184 system.physmem.bytesPerActivate::1920-1921 2 0.28% 92.05% # Bytes accessed per row activation
185 system.physmem.bytesPerActivate::1984-1985 2 0.28% 92.33% # Bytes accessed per row activation
186 system.physmem.bytesPerActivate::2048-2049 2 0.28% 92.61% # Bytes accessed per row activation
187 system.physmem.bytesPerActivate::2112-2113 3 0.42% 93.03% # Bytes accessed per row activation
188 system.physmem.bytesPerActivate::2176-2177 3 0.42% 93.44% # Bytes accessed per row activation
189 system.physmem.bytesPerActivate::2240-2241 1 0.14% 93.58% # Bytes accessed per row activation
190 system.physmem.bytesPerActivate::2304-2305 2 0.28% 93.86% # Bytes accessed per row activation
191 system.physmem.bytesPerActivate::2368-2369 2 0.28% 94.14% # Bytes accessed per row activation
192 system.physmem.bytesPerActivate::2432-2433 1 0.14% 94.28% # Bytes accessed per row activation
193 system.physmem.bytesPerActivate::2560-2561 2 0.28% 94.56% # Bytes accessed per row activation
194 system.physmem.bytesPerActivate::2624-2625 1 0.14% 94.70% # Bytes accessed per row activation
195 system.physmem.bytesPerActivate::2688-2689 2 0.28% 94.98% # Bytes accessed per row activation
196 system.physmem.bytesPerActivate::2816-2817 2 0.28% 95.26% # Bytes accessed per row activation
197 system.physmem.bytesPerActivate::2880-2881 1 0.14% 95.40% # Bytes accessed per row activation
198 system.physmem.bytesPerActivate::3072-3073 3 0.42% 95.82% # Bytes accessed per row activation
199 system.physmem.bytesPerActivate::3136-3137 1 0.14% 95.96% # Bytes accessed per row activation
200 system.physmem.bytesPerActivate::3200-3201 1 0.14% 96.09% # Bytes accessed per row activation
201 system.physmem.bytesPerActivate::3264-3265 1 0.14% 96.23% # Bytes accessed per row activation
202 system.physmem.bytesPerActivate::3328-3329 1 0.14% 96.37% # Bytes accessed per row activation
203 system.physmem.bytesPerActivate::3520-3521 1 0.14% 96.51% # Bytes accessed per row activation
204 system.physmem.bytesPerActivate::3584-3585 1 0.14% 96.65% # Bytes accessed per row activation
205 system.physmem.bytesPerActivate::3712-3713 1 0.14% 96.79% # Bytes accessed per row activation
206 system.physmem.bytesPerActivate::3776-3777 1 0.14% 96.93% # Bytes accessed per row activation
207 system.physmem.bytesPerActivate::4608-4609 1 0.14% 97.07% # Bytes accessed per row activation
208 system.physmem.bytesPerActivate::4800-4801 1 0.14% 97.21% # Bytes accessed per row activation
209 system.physmem.bytesPerActivate::4864-4865 2 0.28% 97.49% # Bytes accessed per row activation
210 system.physmem.bytesPerActivate::5632-5633 1 0.14% 97.63% # Bytes accessed per row activation
211 system.physmem.bytesPerActivate::5952-5953 1 0.14% 97.77% # Bytes accessed per row activation
212 system.physmem.bytesPerActivate::6080-6081 1 0.14% 97.91% # Bytes accessed per row activation
213 system.physmem.bytesPerActivate::6656-6657 1 0.14% 98.05% # Bytes accessed per row activation
214 system.physmem.bytesPerActivate::6912-6913 2 0.28% 98.33% # Bytes accessed per row activation
215 system.physmem.bytesPerActivate::8128-8129 2 0.28% 98.61% # Bytes accessed per row activation
216 system.physmem.bytesPerActivate::8192-8193 10 1.39% 100.00% # Bytes accessed per row activation
217 system.physmem.bytesPerActivate::total 717 # Bytes accessed per row activation
218 system.physmem.totQLat 39275000 # Total cycles spent in queuing delays
219 system.physmem.totMemAccLat 171092500 # Sum of mem lat for all requests
220 system.physmem.totBusLat 36420000 # Total cycles spent in databus access
221 system.physmem.totBankLat 95397500 # Total cycles spent in bank access
222 system.physmem.avgQLat 5391.95 # Average queueing delay per request
223 system.physmem.avgBankLat 13096.86 # Average bank access latency per request
224 system.physmem.avgBusLat 5000.00 # Average bus latency per request
225 system.physmem.avgMemAccLat 23488.81 # Average memory access latency
226 system.physmem.avgRdBW 6.82 # Average achieved read bandwidth in MB/s
227 system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
228 system.physmem.avgConsumedRdBW 6.82 # Average consumed read bandwidth in MB/s
229 system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
230 system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
231 system.physmem.busUtil 0.05 # Data bus utilization in percentage
232 system.physmem.avgRdQLen 0.00 # Average read queue length over time
233 system.physmem.avgWrQLen 0.00 # Average write queue length over time
234 system.physmem.readRowHits 6567 # Number of row buffer hits during reads
235 system.physmem.writeRowHits 0 # Number of row buffer hits during writes
236 system.physmem.readRowHitRate 90.16 # Row buffer hit rate for reads
237 system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
238 system.physmem.avgGap 9382190.42 # Average gap between requests
239 system.membus.throughput 6821415 # Throughput (bytes/s)
240 system.membus.trans_dist::ReadReq 4461 # Transaction distribution
241 system.membus.trans_dist::ReadResp 4461 # Transaction distribution
242 system.membus.trans_dist::UpgradeReq 5 # Transaction distribution
243 system.membus.trans_dist::UpgradeResp 5 # Transaction distribution
244 system.membus.trans_dist::ReadExReq 2823 # Transaction distribution
245 system.membus.trans_dist::ReadExResp 2823 # Transaction distribution
246 system.membus.pkt_count_system.cpu.l2cache.mem_side 14578 # Packet count per connected master and slave (bytes)
247 system.membus.pkt_count 14578 # Packet count per connected master and slave (bytes)
248 system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 466176 # Cumulative packet size per connected master and slave (bytes)
249 system.membus.tot_pkt_size 466176 # Cumulative packet size per connected master and slave (bytes)
250 system.membus.data_through_bus 466176 # Total data (bytes)
251 system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
252 system.membus.reqLayer0.occupancy 8863500 # Layer occupancy (ticks)
253 system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
254 system.membus.respLayer1.occupancy 67994996 # Layer occupancy (ticks)
255 system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
256 system.cpu.branchPred.lookups 35386289 # Number of BP lookups
257 system.cpu.branchPred.condPredicted 21204879 # Number of conditional branches predicted
258 system.cpu.branchPred.condIncorrect 1638532 # Number of conditional branches incorrect
259 system.cpu.branchPred.BTBLookups 19153921 # Number of BTB lookups
260 system.cpu.branchPred.BTBHits 16759106 # Number of BTB hits
261 system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
262 system.cpu.branchPred.BTBHitPct 87.496999 # BTB Hit Percentage
263 system.cpu.branchPred.usedRAS 6781793 # Number of times the RAS was used to get a target.
264 system.cpu.branchPred.RASInCorrect 8488 # Number of incorrect RAS predictions.
265 system.cpu.dtb.inst_hits 0 # ITB inst hits
266 system.cpu.dtb.inst_misses 0 # ITB inst misses
267 system.cpu.dtb.read_hits 0 # DTB read hits
268 system.cpu.dtb.read_misses 0 # DTB read misses
269 system.cpu.dtb.write_hits 0 # DTB write hits
270 system.cpu.dtb.write_misses 0 # DTB write misses
271 system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
272 system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
273 system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
274 system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
275 system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
276 system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
277 system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
278 system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
279 system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
280 system.cpu.dtb.read_accesses 0 # DTB read accesses
281 system.cpu.dtb.write_accesses 0 # DTB write accesses
282 system.cpu.dtb.inst_accesses 0 # ITB inst accesses
283 system.cpu.dtb.hits 0 # DTB hits
284 system.cpu.dtb.misses 0 # DTB misses
285 system.cpu.dtb.accesses 0 # DTB accesses
286 system.cpu.itb.inst_hits 0 # ITB inst hits
287 system.cpu.itb.inst_misses 0 # ITB inst misses
288 system.cpu.itb.read_hits 0 # DTB read hits
289 system.cpu.itb.read_misses 0 # DTB read misses
290 system.cpu.itb.write_hits 0 # DTB write hits
291 system.cpu.itb.write_misses 0 # DTB write misses
292 system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
293 system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
294 system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
295 system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
296 system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
297 system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
298 system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
299 system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
300 system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
301 system.cpu.itb.read_accesses 0 # DTB read accesses
302 system.cpu.itb.write_accesses 0 # DTB write accesses
303 system.cpu.itb.inst_accesses 0 # ITB inst accesses
304 system.cpu.itb.hits 0 # DTB hits
305 system.cpu.itb.misses 0 # DTB misses
306 system.cpu.itb.accesses 0 # DTB accesses
307 system.cpu.workload.num_syscalls 191 # Number of system calls
308 system.cpu.numCycles 136680145 # number of cpu cycles simulated
309 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
310 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
311 system.cpu.fetch.icacheStallCycles 38911514 # Number of cycles fetch is stalled on an Icache miss
312 system.cpu.fetch.Insts 317585001 # Number of instructions fetch has processed
313 system.cpu.fetch.Branches 35386289 # Number of branches that fetch encountered
314 system.cpu.fetch.predictedBranches 23540899 # Number of branches that fetch has predicted taken
315 system.cpu.fetch.Cycles 70801219 # Number of cycles fetch has run and was not squashing or blocked
316 system.cpu.fetch.SquashCycles 6795871 # Number of cycles fetch has spent squashing
317 system.cpu.fetch.BlockedCycles 21500027 # Number of cycles fetch has spent blocked
318 system.cpu.fetch.MiscStallCycles 100 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
319 system.cpu.fetch.PendingTrapStallCycles 1484 # Number of stall cycles due to pending traps
320 system.cpu.fetch.IcacheWaitRetryStallCycles 53 # Number of stall cycles due to full MSHR
321 system.cpu.fetch.CacheLines 37522622 # Number of cache lines fetched
322 system.cpu.fetch.IcacheSquashes 503492 # Number of outstanding Icache misses that were squashed
323 system.cpu.fetch.rateDist::samples 136360129 # Number of instructions fetched each cycle (Total)
324 system.cpu.fetch.rateDist::mean 2.984944 # Number of instructions fetched each cycle (Total)
325 system.cpu.fetch.rateDist::stdev 3.454705 # Number of instructions fetched each cycle (Total)
326 system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
327 system.cpu.fetch.rateDist::0 66188924 48.54% 48.54% # Number of instructions fetched each cycle (Total)
328 system.cpu.fetch.rateDist::1 6771554 4.97% 53.51% # Number of instructions fetched each cycle (Total)
329 system.cpu.fetch.rateDist::2 5692762 4.17% 57.68% # Number of instructions fetched each cycle (Total)
330 system.cpu.fetch.rateDist::3 6083969 4.46% 62.14% # Number of instructions fetched each cycle (Total)
331 system.cpu.fetch.rateDist::4 4907326 3.60% 65.74% # Number of instructions fetched each cycle (Total)
332 system.cpu.fetch.rateDist::5 4077145 2.99% 68.73% # Number of instructions fetched each cycle (Total)
333 system.cpu.fetch.rateDist::6 3184432 2.34% 71.07% # Number of instructions fetched each cycle (Total)
334 system.cpu.fetch.rateDist::7 4135342 3.03% 74.10% # Number of instructions fetched each cycle (Total)
335 system.cpu.fetch.rateDist::8 35318675 25.90% 100.00% # Number of instructions fetched each cycle (Total)
336 system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
337 system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
338 system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
339 system.cpu.fetch.rateDist::total 136360129 # Number of instructions fetched each cycle (Total)
340 system.cpu.fetch.branchRate 0.258899 # Number of branch fetches per cycle
341 system.cpu.fetch.rate 2.323564 # Number of inst fetches per cycle
342 system.cpu.decode.IdleCycles 45414780 # Number of cycles decode is idle
343 system.cpu.decode.BlockedCycles 16659439 # Number of cycles decode is blocked
344 system.cpu.decode.RunCycles 66663560 # Number of cycles decode is running
345 system.cpu.decode.UnblockCycles 2545187 # Number of cycles decode is unblocking
346 system.cpu.decode.SquashCycles 5077163 # Number of cycles decode is squashing
347 system.cpu.decode.BranchResolved 7331349 # Number of times decode resolved a branch
348 system.cpu.decode.BranchMispred 68935 # Number of times decode detected a branch misprediction
349 system.cpu.decode.DecodedInsts 401047467 # Number of instructions handled by decode
350 system.cpu.decode.SquashedInsts 212517 # Number of squashed instructions handled by decode
351 system.cpu.rename.SquashCycles 5077163 # Number of cycles rename is squashing
352 system.cpu.rename.IdleCycles 50947779 # Number of cycles rename is idle
353 system.cpu.rename.BlockCycles 1931381 # Number of cycles rename is blocking
354 system.cpu.rename.serializeStallCycles 327570 # count of cycles rename stalled for serializing inst
355 system.cpu.rename.RunCycles 63615860 # Number of cycles rename is running
356 system.cpu.rename.UnblockCycles 14460376 # Number of cycles rename is unblocking
357 system.cpu.rename.RenamedInsts 393522571 # Number of instructions processed by rename
358 system.cpu.rename.ROBFullEvents 45 # Number of times rename has blocked due to ROB full
359 system.cpu.rename.IQFullEvents 1660698 # Number of times rename has blocked due to IQ full
360 system.cpu.rename.LSQFullEvents 10177766 # Number of times rename has blocked due to LSQ full
361 system.cpu.rename.FullRegisterEvents 1066 # Number of times there has been no free registers
362 system.cpu.rename.RenamedOperands 432139045 # Number of destination operands rename has renamed
363 system.cpu.rename.RenameLookups 2330040462 # Number of register rename lookups that rename has made
364 system.cpu.rename.int_rename_lookups 1257112117 # Number of integer rename lookups
365 system.cpu.rename.fp_rename_lookups 1072928345 # Number of floating rename lookups
366 system.cpu.rename.CommittedMaps 384566193 # Number of HB maps that are committed
367 system.cpu.rename.UndoneMaps 47572852 # Number of HB maps that are undone due to squashing
368 system.cpu.rename.serializingInsts 11802 # count of serializing insts renamed
369 system.cpu.rename.tempSerializingInsts 11801 # count of temporary serializing insts renamed
370 system.cpu.rename.skidInsts 36468583 # count of insts added to the skid buffer
371 system.cpu.memDep0.insertedLoads 103474945 # Number of loads inserted to the mem dependence unit.
372 system.cpu.memDep0.insertedStores 91276854 # Number of stores inserted to the mem dependence unit.
373 system.cpu.memDep0.conflictingLoads 4259608 # Number of conflicting loads.
374 system.cpu.memDep0.conflictingStores 5261316 # Number of conflicting stores.
375 system.cpu.iq.iqInstsAdded 384098955 # Number of instructions added to the IQ (excludes non-spec)
376 system.cpu.iq.iqNonSpecInstsAdded 22768 # Number of non-speculative instructions added to the IQ
377 system.cpu.iq.iqInstsIssued 373971213 # Number of instructions issued
378 system.cpu.iq.iqSquashedInstsIssued 1208914 # Number of squashed instructions issued
379 system.cpu.iq.iqSquashedInstsExamined 34303040 # Number of squashed instructions iterated over during squash; mainly for profiling
380 system.cpu.iq.iqSquashedOperandsExamined 86231470 # Number of squashed operands that are examined and possibly removed from graph
381 system.cpu.iq.iqSquashedNonSpecRemoved 648 # Number of squashed non-spec instructions that were removed
382 system.cpu.iq.issued_per_cycle::samples 136360129 # Number of insts issued each cycle
383 system.cpu.iq.issued_per_cycle::mean 2.742526 # Number of insts issued each cycle
384 system.cpu.iq.issued_per_cycle::stdev 2.023578 # Number of insts issued each cycle
385 system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
386 system.cpu.iq.issued_per_cycle::0 24894566 18.26% 18.26% # Number of insts issued each cycle
387 system.cpu.iq.issued_per_cycle::1 19912259 14.60% 32.86% # Number of insts issued each cycle
388 system.cpu.iq.issued_per_cycle::2 20562905 15.08% 47.94% # Number of insts issued each cycle
389 system.cpu.iq.issued_per_cycle::3 18156426 13.32% 61.25% # Number of insts issued each cycle
390 system.cpu.iq.issued_per_cycle::4 24028186 17.62% 78.88% # Number of insts issued each cycle
391 system.cpu.iq.issued_per_cycle::5 15708589 11.52% 90.40% # Number of insts issued each cycle
392 system.cpu.iq.issued_per_cycle::6 8792760 6.45% 96.84% # Number of insts issued each cycle
393 system.cpu.iq.issued_per_cycle::7 3383887 2.48% 99.32% # Number of insts issued each cycle
394 system.cpu.iq.issued_per_cycle::8 920551 0.68% 100.00% # Number of insts issued each cycle
395 system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
396 system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
397 system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
398 system.cpu.iq.issued_per_cycle::total 136360129 # Number of insts issued each cycle
399 system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
400 system.cpu.iq.fu_full::IntAlu 8941 0.05% 0.05% # attempts to use FU when none available
401 system.cpu.iq.fu_full::IntMult 4699 0.03% 0.08% # attempts to use FU when none available
402 system.cpu.iq.fu_full::IntDiv 0 0.00% 0.08% # attempts to use FU when none available
403 system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.08% # attempts to use FU when none available
404 system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.08% # attempts to use FU when none available
405 system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.08% # attempts to use FU when none available
406 system.cpu.iq.fu_full::FloatMult 0 0.00% 0.08% # attempts to use FU when none available
407 system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.08% # attempts to use FU when none available
408 system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.08% # attempts to use FU when none available
409 system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.08% # attempts to use FU when none available
410 system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.08% # attempts to use FU when none available
411 system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.08% # attempts to use FU when none available
412 system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.08% # attempts to use FU when none available
413 system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.08% # attempts to use FU when none available
414 system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.08% # attempts to use FU when none available
415 system.cpu.iq.fu_full::SimdMult 0 0.00% 0.08% # attempts to use FU when none available
416 system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.08% # attempts to use FU when none available
417 system.cpu.iq.fu_full::SimdShift 0 0.00% 0.08% # attempts to use FU when none available
418 system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.08% # attempts to use FU when none available
419 system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.08% # attempts to use FU when none available
420 system.cpu.iq.fu_full::SimdFloatAdd 46063 0.26% 0.34% # attempts to use FU when none available
421 system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.34% # attempts to use FU when none available
422 system.cpu.iq.fu_full::SimdFloatCmp 7630 0.04% 0.38% # attempts to use FU when none available
423 system.cpu.iq.fu_full::SimdFloatCvt 434 0.00% 0.38% # attempts to use FU when none available
424 system.cpu.iq.fu_full::SimdFloatDiv 2 0.00% 0.38% # attempts to use FU when none available
425 system.cpu.iq.fu_full::SimdFloatMisc 190949 1.08% 1.46% # attempts to use FU when none available
426 system.cpu.iq.fu_full::SimdFloatMult 4204 0.02% 1.48% # attempts to use FU when none available
427 system.cpu.iq.fu_full::SimdFloatMultAcc 241086 1.36% 2.84% # attempts to use FU when none available
428 system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.84% # attempts to use FU when none available
429 system.cpu.iq.fu_full::MemRead 9286535 52.36% 55.20% # attempts to use FU when none available
430 system.cpu.iq.fu_full::MemWrite 7946359 44.80% 100.00% # attempts to use FU when none available
431 system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
432 system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
433 system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
434 system.cpu.iq.FU_type_0::IntAlu 126344065 33.78% 33.78% # Type of FU issued
435 system.cpu.iq.FU_type_0::IntMult 2175771 0.58% 34.37% # Type of FU issued
436 system.cpu.iq.FU_type_0::IntDiv 0 0.00% 34.37% # Type of FU issued
437 system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 34.37% # Type of FU issued
438 system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 34.37% # Type of FU issued
439 system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 34.37% # Type of FU issued
440 system.cpu.iq.FU_type_0::FloatMult 0 0.00% 34.37% # Type of FU issued
441 system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 34.37% # Type of FU issued
442 system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 34.37% # Type of FU issued
443 system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 34.37% # Type of FU issued
444 system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 34.37% # Type of FU issued
445 system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 34.37% # Type of FU issued
446 system.cpu.iq.FU_type_0::SimdCmp 2 0.00% 34.37% # Type of FU issued
447 system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 34.37% # Type of FU issued
448 system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 34.37% # Type of FU issued
449 system.cpu.iq.FU_type_0::SimdMult 0 0.00% 34.37% # Type of FU issued
450 system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 34.37% # Type of FU issued
451 system.cpu.iq.FU_type_0::SimdShift 0 0.00% 34.37% # Type of FU issued
452 system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 34.37% # Type of FU issued
453 system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 34.37% # Type of FU issued
454 system.cpu.iq.FU_type_0::SimdFloatAdd 6778681 1.81% 36.18% # Type of FU issued
455 system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 36.18% # Type of FU issued
456 system.cpu.iq.FU_type_0::SimdFloatCmp 8473226 2.27% 38.44% # Type of FU issued
457 system.cpu.iq.FU_type_0::SimdFloatCvt 3428816 0.92% 39.36% # Type of FU issued
458 system.cpu.iq.FU_type_0::SimdFloatDiv 1595959 0.43% 39.79% # Type of FU issued
459 system.cpu.iq.FU_type_0::SimdFloatMisc 20861053 5.58% 45.37% # Type of FU issued
460 system.cpu.iq.FU_type_0::SimdFloatMult 7172627 1.92% 47.28% # Type of FU issued
461 system.cpu.iq.FU_type_0::SimdFloatMultAcc 7127553 1.91% 49.19% # Type of FU issued
462 system.cpu.iq.FU_type_0::SimdFloatSqrt 175287 0.05% 49.24% # Type of FU issued
463 system.cpu.iq.FU_type_0::MemRead 101561380 27.16% 76.39% # Type of FU issued
464 system.cpu.iq.FU_type_0::MemWrite 88276793 23.61% 100.00% # Type of FU issued
465 system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
466 system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
467 system.cpu.iq.FU_type_0::total 373971213 # Type of FU issued
468 system.cpu.iq.rate 2.736105 # Inst issue rate
469 system.cpu.iq.fu_busy_cnt 17736902 # FU busy when requested
470 system.cpu.iq.fu_busy_rate 0.047429 # FU busy rate (busy events/executed inst)
471 system.cpu.iq.int_inst_queue_reads 653872242 # Number of integer instruction queue reads
472 system.cpu.iq.int_inst_queue_writes 288125780 # Number of integer instruction queue writes
473 system.cpu.iq.int_inst_queue_wakeup_accesses 249960786 # Number of integer instruction queue wakeup accesses
474 system.cpu.iq.fp_inst_queue_reads 249376129 # Number of floating instruction queue reads
475 system.cpu.iq.fp_inst_queue_writes 130313231 # Number of floating instruction queue writes
476 system.cpu.iq.fp_inst_queue_wakeup_accesses 118044740 # Number of floating instruction queue wakeup accesses
477 system.cpu.iq.int_alu_accesses 263109864 # Number of integer alu accesses
478 system.cpu.iq.fp_alu_accesses 128598251 # Number of floating point alu accesses
479 system.cpu.iew.lsq.thread0.forwLoads 11095244 # Number of loads that had data forwarded from stores
480 system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
481 system.cpu.iew.lsq.thread0.squashedLoads 8826197 # Number of loads squashed
482 system.cpu.iew.lsq.thread0.ignoredResponses 108953 # Number of memory responses ignored because the instruction is squashed
483 system.cpu.iew.lsq.thread0.memOrderViolation 14410 # Number of memory ordering violations
484 system.cpu.iew.lsq.thread0.squashedStores 8901271 # Number of stores squashed
485 system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
486 system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
487 system.cpu.iew.lsq.thread0.rescheduledLoads 178209 # Number of loads that were rescheduled
488 system.cpu.iew.lsq.thread0.cacheBlocked 1806 # Number of times an access to memory failed due to the cache being blocked
489 system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
490 system.cpu.iew.iewSquashCycles 5077163 # Number of cycles IEW is squashing
491 system.cpu.iew.iewBlockCycles 281172 # Number of cycles IEW is blocking
492 system.cpu.iew.iewUnblockCycles 37033 # Number of cycles IEW is unblocking
493 system.cpu.iew.iewDispatchedInsts 384123288 # Number of instructions dispatched to IQ
494 system.cpu.iew.iewDispSquashedInsts 853132 # Number of squashed instructions skipped by dispatch
495 system.cpu.iew.iewDispLoadInsts 103474945 # Number of dispatched load instructions
496 system.cpu.iew.iewDispStoreInsts 91276854 # Number of dispatched store instructions
497 system.cpu.iew.iewDispNonSpecInsts 11734 # Number of dispatched non-speculative instructions
498 system.cpu.iew.iewIQFullEvents 343 # Number of times the IQ has become full, causing a stall
499 system.cpu.iew.iewLSQFullEvents 352 # Number of times the LSQ has become full, causing a stall
500 system.cpu.iew.memOrderViolationEvents 14410 # Number of memory order violations
501 system.cpu.iew.predictedTakenIncorrect 1275078 # Number of branches that were predicted taken incorrectly
502 system.cpu.iew.predictedNotTakenIncorrect 370888 # Number of branches that were predicted not taken incorrectly
503 system.cpu.iew.branchMispredicts 1645966 # Number of branch mispredicts detected at execute
504 system.cpu.iew.iewExecutedInsts 370028321 # Number of executed instructions
505 system.cpu.iew.iewExecLoadInsts 100269572 # Number of load instructions executed
506 system.cpu.iew.iewExecSquashedInsts 3942892 # Number of squashed instructions skipped in execute
507 system.cpu.iew.exec_swp 0 # number of swp insts executed
508 system.cpu.iew.exec_nop 1565 # number of nop insts executed
509 system.cpu.iew.exec_refs 187470029 # number of memory reference insts executed
510 system.cpu.iew.exec_branches 32001457 # Number of branches executed
511 system.cpu.iew.exec_stores 87200457 # Number of stores executed
512 system.cpu.iew.exec_rate 2.707257 # Inst execution rate
513 system.cpu.iew.wb_sent 368660932 # cumulative count of insts sent to commit
514 system.cpu.iew.wb_count 368005526 # cumulative count of insts written-back
515 system.cpu.iew.wb_producers 182984682 # num instructions producing a value
516 system.cpu.iew.wb_consumers 363667286 # num instructions consuming a value
517 system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
518 system.cpu.iew.wb_rate 2.692458 # insts written-back per cycle
519 system.cpu.iew.wb_fanout 0.503165 # average fanout of values written-back
520 system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
521 system.cpu.commit.commitSquashedInsts 35058333 # The number of squashed insts skipped by commit
522 system.cpu.commit.commitNonSpecStalls 22120 # The number of times commit has been forced to stall to communicate backwards
523 system.cpu.commit.branchMispredicts 1569963 # The number of times a branch was mispredicted
524 system.cpu.commit.committed_per_cycle::samples 131282966 # Number of insts commited each cycle
525 system.cpu.commit.committed_per_cycle::mean 2.658875 # Number of insts commited each cycle
526 system.cpu.commit.committed_per_cycle::stdev 2.659705 # Number of insts commited each cycle
527 system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
528 system.cpu.commit.committed_per_cycle::0 34515611 26.29% 26.29% # Number of insts commited each cycle
529 system.cpu.commit.committed_per_cycle::1 28430867 21.66% 47.95% # Number of insts commited each cycle
530 system.cpu.commit.committed_per_cycle::2 13310132 10.14% 58.09% # Number of insts commited each cycle
531 system.cpu.commit.committed_per_cycle::3 11454615 8.73% 66.81% # Number of insts commited each cycle
532 system.cpu.commit.committed_per_cycle::4 13758236 10.48% 77.29% # Number of insts commited each cycle
533 system.cpu.commit.committed_per_cycle::5 7411224 5.65% 82.94% # Number of insts commited each cycle
534 system.cpu.commit.committed_per_cycle::6 3878786 2.95% 85.89% # Number of insts commited each cycle
535 system.cpu.commit.committed_per_cycle::7 3899655 2.97% 88.86% # Number of insts commited each cycle
536 system.cpu.commit.committed_per_cycle::8 14623840 11.14% 100.00% # Number of insts commited each cycle
537 system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
538 system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
539 system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
540 system.cpu.commit.committed_per_cycle::total 131282966 # Number of insts commited each cycle
541 system.cpu.commit.committedInsts 273037337 # Number of instructions committed
542 system.cpu.commit.committedOps 349065061 # Number of ops (including micro ops) committed
543 system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
544 system.cpu.commit.refs 177024331 # Number of memory references committed
545 system.cpu.commit.loads 94648748 # Number of loads committed
546 system.cpu.commit.membars 11033 # Number of memory barriers committed
547 system.cpu.commit.branches 30563497 # Number of branches committed
548 system.cpu.commit.fp_insts 114216705 # Number of committed floating point instructions.
549 system.cpu.commit.int_insts 279584611 # Number of committed integer instructions.
550 system.cpu.commit.function_calls 6225112 # Number of function calls committed.
551 system.cpu.commit.bw_lim_events 14623840 # number cycles where commit BW limit reached
552 system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
553 system.cpu.rob.rob_reads 500779997 # The number of ROB reads
554 system.cpu.rob.rob_writes 773327958 # The number of ROB writes
555 system.cpu.timesIdled 6728 # Number of times that the entire CPU went into an idle state and unscheduled itself
556 system.cpu.idleCycles 320016 # Total number of cycles that the CPU has spent unscheduled due to idling
557 system.cpu.committedInsts 273036725 # Number of Instructions Simulated
558 system.cpu.committedOps 349064449 # Number of Ops (including micro ops) Simulated
559 system.cpu.committedInsts_total 273036725 # Number of Instructions Simulated
560 system.cpu.cpi 0.500593 # CPI: Cycles Per Instruction
561 system.cpu.cpi_total 0.500593 # CPI: Total CPI of All Threads
562 system.cpu.ipc 1.997633 # IPC: Instructions Per Cycle
563 system.cpu.ipc_total 1.997633 # IPC: Total IPC of All Threads
564 system.cpu.int_regfile_reads 1768864956 # number of integer regfile reads
565 system.cpu.int_regfile_writes 232856502 # number of integer regfile writes
566 system.cpu.fp_regfile_reads 188105910 # number of floating regfile reads
567 system.cpu.fp_regfile_writes 132495512 # number of floating regfile writes
568 system.cpu.misc_regfile_reads 566780330 # number of misc regfile reads
569 system.cpu.misc_regfile_writes 34421755 # number of misc regfile writes
570 system.cpu.toL2Bus.throughput 20129917 # Throughput (bytes/s)
571 system.cpu.toL2Bus.trans_dist::ReadReq 17615 # Transaction distribution
572 system.cpu.toL2Bus.trans_dist::ReadResp 17615 # Transaction distribution
573 system.cpu.toL2Bus.trans_dist::Writeback 1040 # Transaction distribution
574 system.cpu.toL2Bus.trans_dist::UpgradeReq 5 # Transaction distribution
575 system.cpu.toL2Bus.trans_dist::UpgradeResp 5 # Transaction distribution
576 system.cpu.toL2Bus.trans_dist::ReadExReq 2840 # Transaction distribution
577 system.cpu.toL2Bus.trans_dist::ReadExResp 2840 # Transaction distribution
578 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 31680 # Packet count per connected master and slave (bytes)
579 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 10272 # Packet count per connected master and slave (bytes)
580 system.cpu.toL2Bus.pkt_count 41952 # Packet count per connected master and slave (bytes)
581 system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 1013504 # Cumulative packet size per connected master and slave (bytes)
582 system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 361664 # Cumulative packet size per connected master and slave (bytes)
583 system.cpu.toL2Bus.tot_pkt_size 1375168 # Cumulative packet size per connected master and slave (bytes)
584 system.cpu.toL2Bus.data_through_bus 1375168 # Total data (bytes)
585 system.cpu.toL2Bus.snoop_data_through_bus 512 # Total snoop data (bytes)
586 system.cpu.toL2Bus.reqLayer0.occupancy 11790000 # Layer occupancy (ticks)
587 system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
588 system.cpu.toL2Bus.respLayer0.occupancy 23771988 # Layer occupancy (ticks)
589 system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
590 system.cpu.toL2Bus.respLayer1.occupancy 6938461 # Layer occupancy (ticks)
591 system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
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595 system.cpu.icache.sampled_refs 15840 # Sample count of references to valid blocks.
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598 system.cpu.icache.occ_blocks::cpu.inst 1844.969918 # Average occupied blocks per requestor
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602 system.cpu.icache.ReadReq_hits::total 37505309 # number of ReadReq hits
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608 system.cpu.icache.ReadReq_misses::total 17311 # number of ReadReq misses
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614 system.cpu.icache.ReadReq_miss_latency::total 438177497 # number of ReadReq miss cycles
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616 system.cpu.icache.demand_miss_latency::total 438177497 # number of demand (read+write) miss cycles
617 system.cpu.icache.overall_miss_latency::cpu.inst 438177497 # number of overall miss cycles
618 system.cpu.icache.overall_miss_latency::total 438177497 # number of overall miss cycles
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628 system.cpu.icache.demand_miss_rate::total 0.000461 # miss rate for demand accesses
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635 system.cpu.icache.overall_avg_miss_latency::cpu.inst 25312.084628 # average overall miss latency
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652 system.cpu.icache.ReadReq_mshr_misses::total 15844 # number of ReadReq MSHR misses
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662 system.cpu.icache.overall_mshr_miss_latency::total 350210509 # number of overall MSHR miss cycles
663 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000422 # mshr miss rate for ReadReq accesses
664 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000422 # mshr miss rate for ReadReq accesses
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666 system.cpu.icache.demand_mshr_miss_rate::total 0.000422 # mshr miss rate for demand accesses
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668 system.cpu.icache.overall_mshr_miss_rate::total 0.000422 # mshr miss rate for overall accesses
669 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22103.667571 # average ReadReq mshr miss latency
670 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22103.667571 # average ReadReq mshr miss latency
671 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22103.667571 # average overall mshr miss latency
672 system.cpu.icache.demand_avg_mshr_miss_latency::total 22103.667571 # average overall mshr miss latency
673 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22103.667571 # average overall mshr miss latency
674 system.cpu.icache.overall_avg_mshr_miss_latency::total 22103.667571 # average overall mshr miss latency
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679 system.cpu.l2cache.sampled_refs 5388 # Sample count of references to valid blocks.
680 system.cpu.l2cache.avg_refs 2.448033 # Average number of references to valid blocks.
681 system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
682 system.cpu.l2cache.occ_blocks::writebacks 380.401816 # Average occupied blocks per requestor
683 system.cpu.l2cache.occ_blocks::cpu.inst 2774.612860 # Average occupied blocks per requestor
684 system.cpu.l2cache.occ_blocks::cpu.data 780.466052 # Average occupied blocks per requestor
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691 system.cpu.l2cache.ReadReq_hits::total 13095 # number of ReadReq hits
692 system.cpu.l2cache.Writeback_hits::writebacks 1040 # number of Writeback hits
693 system.cpu.l2cache.Writeback_hits::total 1040 # number of Writeback hits
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724 system.cpu.l2cache.overall_miss_latency::cpu.data 290236000 # number of overall miss cycles
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728 system.cpu.l2cache.ReadReq_accesses::total 17607 # number of ReadReq accesses(hits+misses)
729 system.cpu.l2cache.Writeback_accesses::writebacks 1040 # number of Writeback accesses(hits+misses)
730 system.cpu.l2cache.Writeback_accesses::total 1040 # number of Writeback accesses(hits+misses)
731 system.cpu.l2cache.UpgradeReq_accesses::cpu.data 5 # number of UpgradeReq accesses(hits+misses)
732 system.cpu.l2cache.UpgradeReq_accesses::total 5 # number of UpgradeReq accesses(hits+misses)
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745 system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses
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747 system.cpu.l2cache.ReadExReq_miss_rate::total 0.994014 # miss rate for ReadExReq accesses
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751 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.192031 # miss rate for overall accesses
752 system.cpu.l2cache.overall_miss_rate::cpu.data 0.931251 # miss rate for overall accesses
753 system.cpu.l2cache.overall_miss_rate::total 0.358732 # miss rate for overall accesses
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755 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 69068.660775 # average ReadReq miss latency
756 system.cpu.l2cache.ReadReq_avg_miss_latency::total 68257.867908 # average ReadReq miss latency
757 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 66821.112292 # average ReadExReq miss latency
758 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66821.112292 # average ReadExReq miss latency
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761 system.cpu.l2cache.demand_avg_miss_latency::total 67704.907975 # average overall miss latency
762 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67865.669188 # average overall miss latency
763 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 67591.057289 # average overall miss latency
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770 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
771 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
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775 system.cpu.l2cache.ReadReq_mshr_hits::total 51 # number of ReadReq MSHR hits
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779 system.cpu.l2cache.overall_mshr_hits::cpu.inst 12 # number of overall MSHR hits
780 system.cpu.l2cache.overall_mshr_hits::cpu.data 39 # number of overall MSHR hits
781 system.cpu.l2cache.overall_mshr_hits::total 51 # number of overall MSHR hits
782 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3029 # number of ReadReq MSHR misses
783 system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1432 # number of ReadReq MSHR misses
784 system.cpu.l2cache.ReadReq_mshr_misses::total 4461 # number of ReadReq MSHR misses
785 system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 5 # number of UpgradeReq MSHR misses
786 system.cpu.l2cache.UpgradeReq_mshr_misses::total 5 # number of UpgradeReq MSHR misses
787 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2823 # number of ReadExReq MSHR misses
788 system.cpu.l2cache.ReadExReq_mshr_misses::total 2823 # number of ReadExReq MSHR misses
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792 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3029 # number of overall MSHR misses
793 system.cpu.l2cache.overall_mshr_misses::cpu.data 4255 # number of overall MSHR misses
794 system.cpu.l2cache.overall_mshr_misses::total 7284 # number of overall MSHR misses
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796 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 81472500 # number of ReadReq MSHR miss cycles
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798 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 51504 # number of UpgradeReq MSHR miss cycles
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801 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 153947250 # number of ReadExReq MSHR miss cycles
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805 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 168121750 # number of overall MSHR miss cycles
806 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 235419750 # number of overall MSHR miss cycles
807 system.cpu.l2cache.overall_mshr_miss_latency::total 403541500 # number of overall MSHR miss cycles
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809 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.808583 # mshr miss rate for ReadReq accesses
810 system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.253365 # mshr miss rate for ReadReq accesses
811 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses
812 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
813 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994014 # mshr miss rate for ReadExReq accesses
814 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994014 # mshr miss rate for ReadExReq accesses
815 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.191273 # mshr miss rate for demand accesses
816 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.922793 # mshr miss rate for demand accesses
817 system.cpu.l2cache.demand_mshr_miss_rate::total 0.356238 # mshr miss rate for demand accesses
818 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.191273 # mshr miss rate for overall accesses
819 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.922793 # mshr miss rate for overall accesses
820 system.cpu.l2cache.overall_mshr_miss_rate::total 0.356238 # mshr miss rate for overall accesses
821 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55504.044239 # average ReadReq mshr miss latency
822 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 56894.203911 # average ReadReq mshr miss latency
823 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55950.291414 # average ReadReq mshr miss latency
824 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10300.800000 # average UpgradeReq mshr miss latency
825 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10300.800000 # average UpgradeReq mshr miss latency
826 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54533.209352 # average ReadExReq mshr miss latency
827 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54533.209352 # average ReadExReq mshr miss latency
828 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55504.044239 # average overall mshr miss latency
829 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 55327.790834 # average overall mshr miss latency
830 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55401.084569 # average overall mshr miss latency
831 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55504.044239 # average overall mshr miss latency
832 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 55327.790834 # average overall mshr miss latency
833 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55401.084569 # average overall mshr miss latency
834 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
835 system.cpu.dcache.replacements 1417 # number of replacements
836 system.cpu.dcache.tagsinuse 3105.227160 # Cycle average of tags in use
837 system.cpu.dcache.total_refs 170865642 # Total number of references to valid blocks.
838 system.cpu.dcache.sampled_refs 4611 # Sample count of references to valid blocks.
839 system.cpu.dcache.avg_refs 37056.092388 # Average number of references to valid blocks.
840 system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
841 system.cpu.dcache.occ_blocks::cpu.data 3105.227160 # Average occupied blocks per requestor
842 system.cpu.dcache.occ_percent::cpu.data 0.758112 # Average percentage of cache occupancy
843 system.cpu.dcache.occ_percent::total 0.758112 # Average percentage of cache occupancy
844 system.cpu.dcache.ReadReq_hits::cpu.data 88812489 # number of ReadReq hits
845 system.cpu.dcache.ReadReq_hits::total 88812489 # number of ReadReq hits
846 system.cpu.dcache.WriteReq_hits::cpu.data 82031226 # number of WriteReq hits
847 system.cpu.dcache.WriteReq_hits::total 82031226 # number of WriteReq hits
848 system.cpu.dcache.LoadLockedReq_hits::cpu.data 11012 # number of LoadLockedReq hits
849 system.cpu.dcache.LoadLockedReq_hits::total 11012 # number of LoadLockedReq hits
850 system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits
851 system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits
852 system.cpu.dcache.demand_hits::cpu.data 170843715 # number of demand (read+write) hits
853 system.cpu.dcache.demand_hits::total 170843715 # number of demand (read+write) hits
854 system.cpu.dcache.overall_hits::cpu.data 170843715 # number of overall hits
855 system.cpu.dcache.overall_hits::total 170843715 # number of overall hits
856 system.cpu.dcache.ReadReq_misses::cpu.data 3995 # number of ReadReq misses
857 system.cpu.dcache.ReadReq_misses::total 3995 # number of ReadReq misses
858 system.cpu.dcache.WriteReq_misses::cpu.data 21439 # number of WriteReq misses
859 system.cpu.dcache.WriteReq_misses::total 21439 # number of WriteReq misses
860 system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses
861 system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses
862 system.cpu.dcache.demand_misses::cpu.data 25434 # number of demand (read+write) misses
863 system.cpu.dcache.demand_misses::total 25434 # number of demand (read+write) misses
864 system.cpu.dcache.overall_misses::cpu.data 25434 # number of overall misses
865 system.cpu.dcache.overall_misses::total 25434 # number of overall misses
866 system.cpu.dcache.ReadReq_miss_latency::cpu.data 218203000 # number of ReadReq miss cycles
867 system.cpu.dcache.ReadReq_miss_latency::total 218203000 # number of ReadReq miss cycles
868 system.cpu.dcache.WriteReq_miss_latency::cpu.data 1190820596 # number of WriteReq miss cycles
869 system.cpu.dcache.WriteReq_miss_latency::total 1190820596 # number of WriteReq miss cycles
870 system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 155000 # number of LoadLockedReq miss cycles
871 system.cpu.dcache.LoadLockedReq_miss_latency::total 155000 # number of LoadLockedReq miss cycles
872 system.cpu.dcache.demand_miss_latency::cpu.data 1409023596 # number of demand (read+write) miss cycles
873 system.cpu.dcache.demand_miss_latency::total 1409023596 # number of demand (read+write) miss cycles
874 system.cpu.dcache.overall_miss_latency::cpu.data 1409023596 # number of overall miss cycles
875 system.cpu.dcache.overall_miss_latency::total 1409023596 # number of overall miss cycles
876 system.cpu.dcache.ReadReq_accesses::cpu.data 88816484 # number of ReadReq accesses(hits+misses)
877 system.cpu.dcache.ReadReq_accesses::total 88816484 # number of ReadReq accesses(hits+misses)
878 system.cpu.dcache.WriteReq_accesses::cpu.data 82052665 # number of WriteReq accesses(hits+misses)
879 system.cpu.dcache.WriteReq_accesses::total 82052665 # number of WriteReq accesses(hits+misses)
880 system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11014 # number of LoadLockedReq accesses(hits+misses)
881 system.cpu.dcache.LoadLockedReq_accesses::total 11014 # number of LoadLockedReq accesses(hits+misses)
882 system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses)
883 system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses)
884 system.cpu.dcache.demand_accesses::cpu.data 170869149 # number of demand (read+write) accesses
885 system.cpu.dcache.demand_accesses::total 170869149 # number of demand (read+write) accesses
886 system.cpu.dcache.overall_accesses::cpu.data 170869149 # number of overall (read+write) accesses
887 system.cpu.dcache.overall_accesses::total 170869149 # number of overall (read+write) accesses
888 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000045 # miss rate for ReadReq accesses
889 system.cpu.dcache.ReadReq_miss_rate::total 0.000045 # miss rate for ReadReq accesses
890 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000261 # miss rate for WriteReq accesses
891 system.cpu.dcache.WriteReq_miss_rate::total 0.000261 # miss rate for WriteReq accesses
892 system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000182 # miss rate for LoadLockedReq accesses
893 system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000182 # miss rate for LoadLockedReq accesses
894 system.cpu.dcache.demand_miss_rate::cpu.data 0.000149 # miss rate for demand accesses
895 system.cpu.dcache.demand_miss_rate::total 0.000149 # miss rate for demand accesses
896 system.cpu.dcache.overall_miss_rate::cpu.data 0.000149 # miss rate for overall accesses
897 system.cpu.dcache.overall_miss_rate::total 0.000149 # miss rate for overall accesses
898 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54619.023780 # average ReadReq miss latency
899 system.cpu.dcache.ReadReq_avg_miss_latency::total 54619.023780 # average ReadReq miss latency
900 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55544.596110 # average WriteReq miss latency
901 system.cpu.dcache.WriteReq_avg_miss_latency::total 55544.596110 # average WriteReq miss latency
902 system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 77500 # average LoadLockedReq miss latency
903 system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 77500 # average LoadLockedReq miss latency
904 system.cpu.dcache.demand_avg_miss_latency::cpu.data 55399.213494 # average overall miss latency
905 system.cpu.dcache.demand_avg_miss_latency::total 55399.213494 # average overall miss latency
906 system.cpu.dcache.overall_avg_miss_latency::cpu.data 55399.213494 # average overall miss latency
907 system.cpu.dcache.overall_avg_miss_latency::total 55399.213494 # average overall miss latency
908 system.cpu.dcache.blocked_cycles::no_mshrs 24937 # number of cycles access was blocked
909 system.cpu.dcache.blocked_cycles::no_targets 1182 # number of cycles access was blocked
910 system.cpu.dcache.blocked::no_mshrs 461 # number of cycles access was blocked
911 system.cpu.dcache.blocked::no_targets 13 # number of cycles access was blocked
912 system.cpu.dcache.avg_blocked_cycles::no_mshrs 54.093275 # average number of cycles each access was blocked
913 system.cpu.dcache.avg_blocked_cycles::no_targets 90.923077 # average number of cycles each access was blocked
914 system.cpu.dcache.fast_writes 0 # number of fast writes performed
915 system.cpu.dcache.cache_copies 0 # number of cache copies performed
916 system.cpu.dcache.writebacks::writebacks 1040 # number of writebacks
917 system.cpu.dcache.writebacks::total 1040 # number of writebacks
918 system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2223 # number of ReadReq MSHR hits
919 system.cpu.dcache.ReadReq_mshr_hits::total 2223 # number of ReadReq MSHR hits
920 system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18595 # number of WriteReq MSHR hits
921 system.cpu.dcache.WriteReq_mshr_hits::total 18595 # number of WriteReq MSHR hits
922 system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits
923 system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits
924 system.cpu.dcache.demand_mshr_hits::cpu.data 20818 # number of demand (read+write) MSHR hits
925 system.cpu.dcache.demand_mshr_hits::total 20818 # number of demand (read+write) MSHR hits
926 system.cpu.dcache.overall_mshr_hits::cpu.data 20818 # number of overall MSHR hits
927 system.cpu.dcache.overall_mshr_hits::total 20818 # number of overall MSHR hits
928 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1772 # number of ReadReq MSHR misses
929 system.cpu.dcache.ReadReq_mshr_misses::total 1772 # number of ReadReq MSHR misses
930 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2844 # number of WriteReq MSHR misses
931 system.cpu.dcache.WriteReq_mshr_misses::total 2844 # number of WriteReq MSHR misses
932 system.cpu.dcache.demand_mshr_misses::cpu.data 4616 # number of demand (read+write) MSHR misses
933 system.cpu.dcache.demand_mshr_misses::total 4616 # number of demand (read+write) MSHR misses
934 system.cpu.dcache.overall_mshr_misses::cpu.data 4616 # number of overall MSHR misses
935 system.cpu.dcache.overall_mshr_misses::total 4616 # number of overall MSHR misses
936 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 106478039 # number of ReadReq MSHR miss cycles
937 system.cpu.dcache.ReadReq_mshr_miss_latency::total 106478039 # number of ReadReq MSHR miss cycles
938 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 191753000 # number of WriteReq MSHR miss cycles
939 system.cpu.dcache.WriteReq_mshr_miss_latency::total 191753000 # number of WriteReq MSHR miss cycles
940 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 298231039 # number of demand (read+write) MSHR miss cycles
941 system.cpu.dcache.demand_mshr_miss_latency::total 298231039 # number of demand (read+write) MSHR miss cycles
942 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 298231039 # number of overall MSHR miss cycles
943 system.cpu.dcache.overall_mshr_miss_latency::total 298231039 # number of overall MSHR miss cycles
944 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000020 # mshr miss rate for ReadReq accesses
945 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000020 # mshr miss rate for ReadReq accesses
946 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses
947 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000035 # mshr miss rate for WriteReq accesses
948 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for demand accesses
949 system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses
950 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses
951 system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses
952 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 60089.186795 # average ReadReq mshr miss latency
953 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 60089.186795 # average ReadReq mshr miss latency
954 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 67423.699015 # average WriteReq mshr miss latency
955 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67423.699015 # average WriteReq mshr miss latency
956 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 64608.110702 # average overall mshr miss latency
957 system.cpu.dcache.demand_avg_mshr_miss_latency::total 64608.110702 # average overall mshr miss latency
958 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 64608.110702 # average overall mshr miss latency
959 system.cpu.dcache.overall_avg_mshr_miss_latency::total 64608.110702 # average overall mshr miss latency
960 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
962 ---------- End Simulation Statistics ----------
projects / gem5.git / blob