2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.068510 # Number of seconds simulated
4 sim_ticks 68509635500 # Number of ticks simulated
5 final_tick 68509635500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 157844 # Simulator instruction rate (inst/s)
8 host_op_rate 201796 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 39605771 # Simulator tick rate (ticks/s)
10 host_mem_usage 257252 # Number of bytes of host memory used
11 host_seconds 1729.79 # Real time elapsed on the host
12 sim_insts 273036725 # Number of instructions simulated
13 sim_ops 349064449 # Number of ops (including micro ops) simulated
14 system.voltage_domain.voltage 1 # Voltage in Volts
15 system.clk_domain.clock 1000 # Clock period in ticks
16 system.physmem.bytes_read::cpu.inst 194560 # Number of bytes read from this memory
17 system.physmem.bytes_read::cpu.data 272384 # Number of bytes read from this memory
18 system.physmem.bytes_read::total 466944 # Number of bytes read from this memory
19 system.physmem.bytes_inst_read::cpu.inst 194560 # Number of instructions bytes read from this memory
20 system.physmem.bytes_inst_read::total 194560 # Number of instructions bytes read from this memory
21 system.physmem.num_reads::cpu.inst 3040 # Number of read requests responded to by this memory
22 system.physmem.num_reads::cpu.data 4256 # Number of read requests responded to by this memory
23 system.physmem.num_reads::total 7296 # Number of read requests responded to by this memory
24 system.physmem.bw_read::cpu.inst 2839892 # Total read bandwidth from this memory (bytes/s)
25 system.physmem.bw_read::cpu.data 3975849 # Total read bandwidth from this memory (bytes/s)
26 system.physmem.bw_read::total 6815742 # Total read bandwidth from this memory (bytes/s)
27 system.physmem.bw_inst_read::cpu.inst 2839892 # Instruction read bandwidth from this memory (bytes/s)
28 system.physmem.bw_inst_read::total 2839892 # Instruction read bandwidth from this memory (bytes/s)
29 system.physmem.bw_total::cpu.inst 2839892 # Total bandwidth to/from this memory (bytes/s)
30 system.physmem.bw_total::cpu.data 3975849 # Total bandwidth to/from this memory (bytes/s)
31 system.physmem.bw_total::total 6815742 # Total bandwidth to/from this memory (bytes/s)
32 system.physmem.readReqs 7296 # Number of read requests accepted
33 system.physmem.writeReqs 0 # Number of write requests accepted
34 system.physmem.readBursts 7296 # Number of DRAM read bursts, including those serviced by the write queue
35 system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
36 system.physmem.bytesReadDRAM 466944 # Total number of bytes read from DRAM
37 system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
38 system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
39 system.physmem.bytesReadSys 466944 # Total read bytes from the system interface side
40 system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
41 system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
42 system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
43 system.physmem.neitherReadNorWriteReqs 2 # Number of requests that are neither read nor write
44 system.physmem.perBankRdBursts::0 607 # Per bank write bursts
45 system.physmem.perBankRdBursts::1 801 # Per bank write bursts
46 system.physmem.perBankRdBursts::2 608 # Per bank write bursts
47 system.physmem.perBankRdBursts::3 526 # Per bank write bursts
48 system.physmem.perBankRdBursts::4 444 # Per bank write bursts
49 system.physmem.perBankRdBursts::5 356 # Per bank write bursts
50 system.physmem.perBankRdBursts::6 162 # Per bank write bursts
51 system.physmem.perBankRdBursts::7 220 # Per bank write bursts
52 system.physmem.perBankRdBursts::8 207 # Per bank write bursts
53 system.physmem.perBankRdBursts::9 294 # Per bank write bursts
54 system.physmem.perBankRdBursts::10 324 # Per bank write bursts
55 system.physmem.perBankRdBursts::11 416 # Per bank write bursts
56 system.physmem.perBankRdBursts::12 529 # Per bank write bursts
57 system.physmem.perBankRdBursts::13 687 # Per bank write bursts
58 system.physmem.perBankRdBursts::14 611 # Per bank write bursts
59 system.physmem.perBankRdBursts::15 504 # Per bank write bursts
60 system.physmem.perBankWrBursts::0 0 # Per bank write bursts
61 system.physmem.perBankWrBursts::1 0 # Per bank write bursts
62 system.physmem.perBankWrBursts::2 0 # Per bank write bursts
63 system.physmem.perBankWrBursts::3 0 # Per bank write bursts
64 system.physmem.perBankWrBursts::4 0 # Per bank write bursts
65 system.physmem.perBankWrBursts::5 0 # Per bank write bursts
66 system.physmem.perBankWrBursts::6 0 # Per bank write bursts
67 system.physmem.perBankWrBursts::7 0 # Per bank write bursts
68 system.physmem.perBankWrBursts::8 0 # Per bank write bursts
69 system.physmem.perBankWrBursts::9 0 # Per bank write bursts
70 system.physmem.perBankWrBursts::10 0 # Per bank write bursts
71 system.physmem.perBankWrBursts::11 0 # Per bank write bursts
72 system.physmem.perBankWrBursts::12 0 # Per bank write bursts
73 system.physmem.perBankWrBursts::13 0 # Per bank write bursts
74 system.physmem.perBankWrBursts::14 0 # Per bank write bursts
75 system.physmem.perBankWrBursts::15 0 # Per bank write bursts
76 system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
77 system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
78 system.physmem.totGap 68509447000 # Total gap between requests
79 system.physmem.readPktSize::0 0 # Read request sizes (log2)
80 system.physmem.readPktSize::1 0 # Read request sizes (log2)
81 system.physmem.readPktSize::2 0 # Read request sizes (log2)
82 system.physmem.readPktSize::3 0 # Read request sizes (log2)
83 system.physmem.readPktSize::4 0 # Read request sizes (log2)
84 system.physmem.readPktSize::5 0 # Read request sizes (log2)
85 system.physmem.readPktSize::6 7296 # Read request sizes (log2)
86 system.physmem.writePktSize::0 0 # Write request sizes (log2)
87 system.physmem.writePktSize::1 0 # Write request sizes (log2)
88 system.physmem.writePktSize::2 0 # Write request sizes (log2)
89 system.physmem.writePktSize::3 0 # Write request sizes (log2)
90 system.physmem.writePktSize::4 0 # Write request sizes (log2)
91 system.physmem.writePktSize::5 0 # Write request sizes (log2)
92 system.physmem.writePktSize::6 0 # Write request sizes (log2)
93 system.physmem.rdQLenPdf::0 4378 # What read queue length does an incoming req see
94 system.physmem.rdQLenPdf::1 2103 # What read queue length does an incoming req see
95 system.physmem.rdQLenPdf::2 570 # What read queue length does an incoming req see
96 system.physmem.rdQLenPdf::3 177 # What read queue length does an incoming req see
97 system.physmem.rdQLenPdf::4 67 # What read queue length does an incoming req see
98 system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
99 system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
100 system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
101 system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
102 system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
103 system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
104 system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
105 system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
106 system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
107 system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
108 system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
109 system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
110 system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
111 system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
112 system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
113 system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
114 system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
115 system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
116 system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
117 system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
118 system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
119 system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
120 system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
121 system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
122 system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
123 system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
124 system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
125 system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
126 system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
127 system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
128 system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
129 system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
130 system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
131 system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
132 system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
133 system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
134 system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
135 system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
136 system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
137 system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
138 system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
139 system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
140 system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
141 system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
142 system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
143 system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
144 system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
145 system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
146 system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
147 system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
148 system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
149 system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
150 system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
151 system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
152 system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
153 system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
154 system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
155 system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
156 system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
157 system.physmem.bytesPerActivate::samples 1278 # Bytes accessed per row activation
158 system.physmem.bytesPerActivate::mean 364.419405 # Bytes accessed per row activation
159 system.physmem.bytesPerActivate::gmean 165.521659 # Bytes accessed per row activation
160 system.physmem.bytesPerActivate::stdev 755.556461 # Bytes accessed per row activation
161 system.physmem.bytesPerActivate::64-65 528 41.31% 41.31% # Bytes accessed per row activation
162 system.physmem.bytesPerActivate::128-129 217 16.98% 58.29% # Bytes accessed per row activation
163 system.physmem.bytesPerActivate::192-193 132 10.33% 68.62% # Bytes accessed per row activation
164 system.physmem.bytesPerActivate::256-257 73 5.71% 74.33% # Bytes accessed per row activation
165 system.physmem.bytesPerActivate::320-321 38 2.97% 77.31% # Bytes accessed per row activation
166 system.physmem.bytesPerActivate::384-385 36 2.82% 80.13% # Bytes accessed per row activation
167 system.physmem.bytesPerActivate::448-449 30 2.35% 82.47% # Bytes accessed per row activation
168 system.physmem.bytesPerActivate::512-513 40 3.13% 85.60% # Bytes accessed per row activation
169 system.physmem.bytesPerActivate::576-577 15 1.17% 86.78% # Bytes accessed per row activation
170 system.physmem.bytesPerActivate::640-641 24 1.88% 88.65% # Bytes accessed per row activation
171 system.physmem.bytesPerActivate::704-705 7 0.55% 89.20% # Bytes accessed per row activation
172 system.physmem.bytesPerActivate::768-769 13 1.02% 90.22% # Bytes accessed per row activation
173 system.physmem.bytesPerActivate::832-833 4 0.31% 90.53% # Bytes accessed per row activation
174 system.physmem.bytesPerActivate::896-897 10 0.78% 91.31% # Bytes accessed per row activation
175 system.physmem.bytesPerActivate::960-961 5 0.39% 91.71% # Bytes accessed per row activation
176 system.physmem.bytesPerActivate::1024-1025 6 0.47% 92.18% # Bytes accessed per row activation
177 system.physmem.bytesPerActivate::1088-1089 7 0.55% 92.72% # Bytes accessed per row activation
178 system.physmem.bytesPerActivate::1152-1153 7 0.55% 93.27% # Bytes accessed per row activation
179 system.physmem.bytesPerActivate::1216-1217 3 0.23% 93.51% # Bytes accessed per row activation
180 system.physmem.bytesPerActivate::1280-1281 4 0.31% 93.82% # Bytes accessed per row activation
181 system.physmem.bytesPerActivate::1344-1345 3 0.23% 94.05% # Bytes accessed per row activation
182 system.physmem.bytesPerActivate::1408-1409 6 0.47% 94.52% # Bytes accessed per row activation
183 system.physmem.bytesPerActivate::1472-1473 5 0.39% 94.91% # Bytes accessed per row activation
184 system.physmem.bytesPerActivate::1536-1537 5 0.39% 95.31% # Bytes accessed per row activation
185 system.physmem.bytesPerActivate::1600-1601 2 0.16% 95.46% # Bytes accessed per row activation
186 system.physmem.bytesPerActivate::1664-1665 5 0.39% 95.85% # Bytes accessed per row activation
187 system.physmem.bytesPerActivate::1728-1729 4 0.31% 96.17% # Bytes accessed per row activation
188 system.physmem.bytesPerActivate::1792-1793 2 0.16% 96.32% # Bytes accessed per row activation
189 system.physmem.bytesPerActivate::1920-1921 2 0.16% 96.48% # Bytes accessed per row activation
190 system.physmem.bytesPerActivate::2048-2049 3 0.23% 96.71% # Bytes accessed per row activation
191 system.physmem.bytesPerActivate::2112-2113 4 0.31% 97.03% # Bytes accessed per row activation
192 system.physmem.bytesPerActivate::2176-2177 2 0.16% 97.18% # Bytes accessed per row activation
193 system.physmem.bytesPerActivate::2240-2241 1 0.08% 97.26% # Bytes accessed per row activation
194 system.physmem.bytesPerActivate::2304-2305 1 0.08% 97.34% # Bytes accessed per row activation
195 system.physmem.bytesPerActivate::2368-2369 2 0.16% 97.50% # Bytes accessed per row activation
196 system.physmem.bytesPerActivate::2432-2433 1 0.08% 97.57% # Bytes accessed per row activation
197 system.physmem.bytesPerActivate::2560-2561 2 0.16% 97.73% # Bytes accessed per row activation
198 system.physmem.bytesPerActivate::2624-2625 1 0.08% 97.81% # Bytes accessed per row activation
199 system.physmem.bytesPerActivate::2752-2753 1 0.08% 97.89% # Bytes accessed per row activation
200 system.physmem.bytesPerActivate::2816-2817 1 0.08% 97.97% # Bytes accessed per row activation
201 system.physmem.bytesPerActivate::2880-2881 2 0.16% 98.12% # Bytes accessed per row activation
202 system.physmem.bytesPerActivate::2944-2945 1 0.08% 98.20% # Bytes accessed per row activation
203 system.physmem.bytesPerActivate::3008-3009 2 0.16% 98.36% # Bytes accessed per row activation
204 system.physmem.bytesPerActivate::3136-3137 2 0.16% 98.51% # Bytes accessed per row activation
205 system.physmem.bytesPerActivate::3200-3201 2 0.16% 98.67% # Bytes accessed per row activation
206 system.physmem.bytesPerActivate::3328-3329 1 0.08% 98.75% # Bytes accessed per row activation
207 system.physmem.bytesPerActivate::3584-3585 2 0.16% 98.90% # Bytes accessed per row activation
208 system.physmem.bytesPerActivate::3712-3713 1 0.08% 98.98% # Bytes accessed per row activation
209 system.physmem.bytesPerActivate::4032-4033 1 0.08% 99.06% # Bytes accessed per row activation
210 system.physmem.bytesPerActivate::4096-4097 1 0.08% 99.14% # Bytes accessed per row activation
211 system.physmem.bytesPerActivate::4160-4161 1 0.08% 99.22% # Bytes accessed per row activation
212 system.physmem.bytesPerActivate::4608-4609 3 0.23% 99.45% # Bytes accessed per row activation
213 system.physmem.bytesPerActivate::4736-4737 1 0.08% 99.53% # Bytes accessed per row activation
214 system.physmem.bytesPerActivate::6464-6465 1 0.08% 99.61% # Bytes accessed per row activation
215 system.physmem.bytesPerActivate::6528-6529 1 0.08% 99.69% # Bytes accessed per row activation
216 system.physmem.bytesPerActivate::6912-6913 1 0.08% 99.77% # Bytes accessed per row activation
217 system.physmem.bytesPerActivate::7552-7553 1 0.08% 99.84% # Bytes accessed per row activation
218 system.physmem.bytesPerActivate::8192-8193 2 0.16% 100.00% # Bytes accessed per row activation
219 system.physmem.bytesPerActivate::total 1278 # Bytes accessed per row activation
220 system.physmem.totQLat 61296000 # Total ticks spent queuing
221 system.physmem.totMemAccLat 197202250 # Total ticks spent from burst creation until serviced by the DRAM
222 system.physmem.totBusLat 36480000 # Total ticks spent in databus transfers
223 system.physmem.totBankLat 99426250 # Total ticks spent accessing banks
224 system.physmem.avgQLat 8401.32 # Average queueing delay per DRAM burst
225 system.physmem.avgBankLat 13627.50 # Average bank access latency per DRAM burst
226 system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
227 system.physmem.avgMemAccLat 27028.82 # Average memory access latency per DRAM burst
228 system.physmem.avgRdBW 6.82 # Average DRAM read bandwidth in MiByte/s
229 system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
230 system.physmem.avgRdBWSys 6.82 # Average system read bandwidth in MiByte/s
231 system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
232 system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
233 system.physmem.busUtil 0.05 # Data bus utilization in percentage
234 system.physmem.busUtilRead 0.05 # Data bus utilization in percentage for reads
235 system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
236 system.physmem.avgRdQLen 0.00 # Average read queue length when enqueuing
237 system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
238 system.physmem.readRowHits 6018 # Number of row buffer hits during reads
239 system.physmem.writeRowHits 0 # Number of row buffer hits during writes
240 system.physmem.readRowHitRate 82.48 # Row buffer hit rate for reads
241 system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
242 system.physmem.avgGap 9390000.96 # Average gap between requests
243 system.physmem.pageHitRate 82.48 # Row buffer hit rate, read and write combined
244 system.physmem.prechargeAllPercent 1.14 # Percentage of time for which DRAM has all the banks in precharge state
245 system.membus.throughput 6815742 # Throughput (bytes/s)
246 system.membus.trans_dist::ReadReq 4471 # Transaction distribution
247 system.membus.trans_dist::ReadResp 4471 # Transaction distribution
248 system.membus.trans_dist::UpgradeReq 2 # Transaction distribution
249 system.membus.trans_dist::UpgradeResp 2 # Transaction distribution
250 system.membus.trans_dist::ReadExReq 2825 # Transaction distribution
251 system.membus.trans_dist::ReadExResp 2825 # Transaction distribution
252 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14596 # Packet count per connected master and slave (bytes)
253 system.membus.pkt_count::total 14596 # Packet count per connected master and slave (bytes)
254 system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 466944 # Cumulative packet size per connected master and slave (bytes)
255 system.membus.tot_pkt_size::total 466944 # Cumulative packet size per connected master and slave (bytes)
256 system.membus.data_through_bus 466944 # Total data (bytes)
257 system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
258 system.membus.reqLayer0.occupancy 8937500 # Layer occupancy (ticks)
259 system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
260 system.membus.respLayer1.occupancy 67899498 # Layer occupancy (ticks)
261 system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
262 system.cpu_clk_domain.clock 500 # Clock period in ticks
263 system.cpu.branchPred.lookups 35425567 # Number of BP lookups
264 system.cpu.branchPred.condPredicted 21222314 # Number of conditional branches predicted
265 system.cpu.branchPred.condIncorrect 1660593 # Number of conditional branches incorrect
266 system.cpu.branchPred.BTBLookups 19605313 # Number of BTB lookups
267 system.cpu.branchPred.BTBHits 16823422 # Number of BTB hits
268 system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
269 system.cpu.branchPred.BTBHitPct 85.810525 # BTB Hit Percentage
270 system.cpu.branchPred.usedRAS 6781780 # Number of times the RAS was used to get a target.
271 system.cpu.branchPred.RASInCorrect 8434 # Number of incorrect RAS predictions.
272 system.cpu.dtb.inst_hits 0 # ITB inst hits
273 system.cpu.dtb.inst_misses 0 # ITB inst misses
274 system.cpu.dtb.read_hits 0 # DTB read hits
275 system.cpu.dtb.read_misses 0 # DTB read misses
276 system.cpu.dtb.write_hits 0 # DTB write hits
277 system.cpu.dtb.write_misses 0 # DTB write misses
278 system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
279 system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
280 system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
281 system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
282 system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
283 system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
284 system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
285 system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
286 system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
287 system.cpu.dtb.read_accesses 0 # DTB read accesses
288 system.cpu.dtb.write_accesses 0 # DTB write accesses
289 system.cpu.dtb.inst_accesses 0 # ITB inst accesses
290 system.cpu.dtb.hits 0 # DTB hits
291 system.cpu.dtb.misses 0 # DTB misses
292 system.cpu.dtb.accesses 0 # DTB accesses
293 system.cpu.itb.inst_hits 0 # ITB inst hits
294 system.cpu.itb.inst_misses 0 # ITB inst misses
295 system.cpu.itb.read_hits 0 # DTB read hits
296 system.cpu.itb.read_misses 0 # DTB read misses
297 system.cpu.itb.write_hits 0 # DTB write hits
298 system.cpu.itb.write_misses 0 # DTB write misses
299 system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
300 system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
301 system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
302 system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
303 system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
304 system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
305 system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
306 system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
307 system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
308 system.cpu.itb.read_accesses 0 # DTB read accesses
309 system.cpu.itb.write_accesses 0 # DTB write accesses
310 system.cpu.itb.inst_accesses 0 # ITB inst accesses
311 system.cpu.itb.hits 0 # DTB hits
312 system.cpu.itb.misses 0 # DTB misses
313 system.cpu.itb.accesses 0 # DTB accesses
314 system.cpu.workload.num_syscalls 191 # Number of system calls
315 system.cpu.numCycles 137019272 # number of cpu cycles simulated
316 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
317 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
318 system.cpu.fetch.icacheStallCycles 39008530 # Number of cycles fetch is stalled on an Icache miss
319 system.cpu.fetch.Insts 318058207 # Number of instructions fetch has processed
320 system.cpu.fetch.Branches 35425567 # Number of branches that fetch encountered
321 system.cpu.fetch.predictedBranches 23605202 # Number of branches that fetch has predicted taken
322 system.cpu.fetch.Cycles 70950828 # Number of cycles fetch has run and was not squashing or blocked
323 system.cpu.fetch.SquashCycles 6887573 # Number of cycles fetch has spent squashing
324 system.cpu.fetch.BlockedCycles 21494775 # Number of cycles fetch has spent blocked
325 system.cpu.fetch.MiscStallCycles 105 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
326 system.cpu.fetch.PendingTrapStallCycles 1573 # Number of stall cycles due to pending traps
327 system.cpu.fetch.IcacheWaitRetryStallCycles 61 # Number of stall cycles due to full MSHR
328 system.cpu.fetch.CacheLines 37609299 # Number of cache lines fetched
329 system.cpu.fetch.IcacheSquashes 515132 # Number of outstanding Icache misses that were squashed
330 system.cpu.fetch.rateDist::samples 136671204 # Number of instructions fetched each cycle (Total)
331 system.cpu.fetch.rateDist::mean 2.983776 # Number of instructions fetched each cycle (Total)
332 system.cpu.fetch.rateDist::stdev 3.454359 # Number of instructions fetched each cycle (Total)
333 system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
334 system.cpu.fetch.rateDist::0 66353464 48.55% 48.55% # Number of instructions fetched each cycle (Total)
335 system.cpu.fetch.rateDist::1 6794042 4.97% 53.52% # Number of instructions fetched each cycle (Total)
336 system.cpu.fetch.rateDist::2 5704725 4.17% 57.69% # Number of instructions fetched each cycle (Total)
337 system.cpu.fetch.rateDist::3 6102503 4.47% 62.16% # Number of instructions fetched each cycle (Total)
338 system.cpu.fetch.rateDist::4 4920388 3.60% 65.76% # Number of instructions fetched each cycle (Total)
339 system.cpu.fetch.rateDist::5 4084365 2.99% 68.75% # Number of instructions fetched each cycle (Total)
340 system.cpu.fetch.rateDist::6 3186134 2.33% 71.08% # Number of instructions fetched each cycle (Total)
341 system.cpu.fetch.rateDist::7 4139625 3.03% 74.11% # Number of instructions fetched each cycle (Total)
342 system.cpu.fetch.rateDist::8 35385958 25.89% 100.00% # Number of instructions fetched each cycle (Total)
343 system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
344 system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
345 system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
346 system.cpu.fetch.rateDist::total 136671204 # Number of instructions fetched each cycle (Total)
347 system.cpu.fetch.branchRate 0.258544 # Number of branch fetches per cycle
348 system.cpu.fetch.rate 2.321266 # Number of inst fetches per cycle
349 system.cpu.decode.IdleCycles 45524127 # Number of cycles decode is idle
350 system.cpu.decode.BlockedCycles 16648036 # Number of cycles decode is blocked
351 system.cpu.decode.RunCycles 66820925 # Number of cycles decode is running
352 system.cpu.decode.UnblockCycles 2531461 # Number of cycles decode is unblocking
353 system.cpu.decode.SquashCycles 5146655 # Number of cycles decode is squashing
354 system.cpu.decode.BranchResolved 7342433 # Number of times decode resolved a branch
355 system.cpu.decode.BranchMispred 69027 # Number of times decode detected a branch misprediction
356 system.cpu.decode.DecodedInsts 401839978 # Number of instructions handled by decode
357 system.cpu.decode.SquashedInsts 214083 # Number of squashed instructions handled by decode
358 system.cpu.rename.SquashCycles 5146655 # Number of cycles rename is squashing
359 system.cpu.rename.IdleCycles 51074305 # Number of cycles rename is idle
360 system.cpu.rename.BlockCycles 1910036 # Number of cycles rename is blocking
361 system.cpu.rename.serializeStallCycles 332499 # count of cycles rename stalled for serializing inst
362 system.cpu.rename.RunCycles 63741314 # Number of cycles rename is running
363 system.cpu.rename.UnblockCycles 14466395 # Number of cycles rename is unblocking
364 system.cpu.rename.RenamedInsts 394244633 # Number of instructions processed by rename
365 system.cpu.rename.ROBFullEvents 55 # Number of times rename has blocked due to ROB full
366 system.cpu.rename.IQFullEvents 1658642 # Number of times rename has blocked due to IQ full
367 system.cpu.rename.LSQFullEvents 10186296 # Number of times rename has blocked due to LSQ full
368 system.cpu.rename.FullRegisterEvents 1132 # Number of times there has been no free registers
369 system.cpu.rename.RenamedOperands 432779208 # Number of destination operands rename has renamed
370 system.cpu.rename.RenameLookups 2333721873 # Number of register rename lookups that rename has made
371 system.cpu.rename.int_rename_lookups 1575557795 # Number of integer rename lookups
372 system.cpu.rename.fp_rename_lookups 200430073 # Number of floating rename lookups
373 system.cpu.rename.CommittedMaps 384566193 # Number of HB maps that are committed
374 system.cpu.rename.UndoneMaps 48213015 # Number of HB maps that are undone due to squashing
375 system.cpu.rename.serializingInsts 11816 # count of serializing insts renamed
376 system.cpu.rename.tempSerializingInsts 11815 # count of temporary serializing insts renamed
377 system.cpu.rename.skidInsts 36510705 # count of insts added to the skid buffer
378 system.cpu.memDep0.insertedLoads 103606610 # Number of loads inserted to the mem dependence unit.
379 system.cpu.memDep0.insertedStores 91402094 # Number of stores inserted to the mem dependence unit.
380 system.cpu.memDep0.conflictingLoads 4304684 # Number of conflicting loads.
381 system.cpu.memDep0.conflictingStores 5331956 # Number of conflicting stores.
382 system.cpu.iq.iqInstsAdded 384603029 # Number of instructions added to the IQ (excludes non-spec)
383 system.cpu.iq.iqNonSpecInstsAdded 22794 # Number of non-speculative instructions added to the IQ
384 system.cpu.iq.iqInstsIssued 374241110 # Number of instructions issued
385 system.cpu.iq.iqSquashedInstsIssued 1211414 # Number of squashed instructions issued
386 system.cpu.iq.iqSquashedInstsExamined 34812310 # Number of squashed instructions iterated over during squash; mainly for profiling
387 system.cpu.iq.iqSquashedOperandsExamined 87759919 # Number of squashed operands that are examined and possibly removed from graph
388 system.cpu.iq.iqSquashedNonSpecRemoved 674 # Number of squashed non-spec instructions that were removed
389 system.cpu.iq.issued_per_cycle::samples 136671204 # Number of insts issued each cycle
390 system.cpu.iq.issued_per_cycle::mean 2.738259 # Number of insts issued each cycle
391 system.cpu.iq.issued_per_cycle::stdev 2.024772 # Number of insts issued each cycle
392 system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
393 system.cpu.iq.issued_per_cycle::0 25129949 18.39% 18.39% # Number of insts issued each cycle
394 system.cpu.iq.issued_per_cycle::1 19927179 14.58% 32.97% # Number of insts issued each cycle
395 system.cpu.iq.issued_per_cycle::2 20562891 15.05% 48.01% # Number of insts issued each cycle
396 system.cpu.iq.issued_per_cycle::3 18173263 13.30% 61.31% # Number of insts issued each cycle
397 system.cpu.iq.issued_per_cycle::4 24036101 17.59% 78.90% # Number of insts issued each cycle
398 system.cpu.iq.issued_per_cycle::5 15736190 11.51% 90.41% # Number of insts issued each cycle
399 system.cpu.iq.issued_per_cycle::6 8814920 6.45% 96.86% # Number of insts issued each cycle
400 system.cpu.iq.issued_per_cycle::7 3372202 2.47% 99.33% # Number of insts issued each cycle
401 system.cpu.iq.issued_per_cycle::8 918509 0.67% 100.00% # Number of insts issued each cycle
402 system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
403 system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
404 system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
405 system.cpu.iq.issued_per_cycle::total 136671204 # Number of insts issued each cycle
406 system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
407 system.cpu.iq.fu_full::IntAlu 8708 0.05% 0.05% # attempts to use FU when none available
408 system.cpu.iq.fu_full::IntMult 4694 0.03% 0.08% # attempts to use FU when none available
409 system.cpu.iq.fu_full::IntDiv 0 0.00% 0.08% # attempts to use FU when none available
410 system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.08% # attempts to use FU when none available
411 system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.08% # attempts to use FU when none available
412 system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.08% # attempts to use FU when none available
413 system.cpu.iq.fu_full::FloatMult 0 0.00% 0.08% # attempts to use FU when none available
414 system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.08% # attempts to use FU when none available
415 system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.08% # attempts to use FU when none available
416 system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.08% # attempts to use FU when none available
417 system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.08% # attempts to use FU when none available
418 system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.08% # attempts to use FU when none available
419 system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.08% # attempts to use FU when none available
420 system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.08% # attempts to use FU when none available
421 system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.08% # attempts to use FU when none available
422 system.cpu.iq.fu_full::SimdMult 0 0.00% 0.08% # attempts to use FU when none available
423 system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.08% # attempts to use FU when none available
424 system.cpu.iq.fu_full::SimdShift 0 0.00% 0.08% # attempts to use FU when none available
425 system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.08% # attempts to use FU when none available
426 system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.08% # attempts to use FU when none available
427 system.cpu.iq.fu_full::SimdFloatAdd 46360 0.26% 0.34% # attempts to use FU when none available
428 system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.34% # attempts to use FU when none available
429 system.cpu.iq.fu_full::SimdFloatCmp 7648 0.04% 0.38% # attempts to use FU when none available
430 system.cpu.iq.fu_full::SimdFloatCvt 433 0.00% 0.38% # attempts to use FU when none available
431 system.cpu.iq.fu_full::SimdFloatDiv 2 0.00% 0.38% # attempts to use FU when none available
432 system.cpu.iq.fu_full::SimdFloatMisc 190801 1.08% 1.46% # attempts to use FU when none available
433 system.cpu.iq.fu_full::SimdFloatMult 4328 0.02% 1.48% # attempts to use FU when none available
434 system.cpu.iq.fu_full::SimdFloatMultAcc 241338 1.36% 2.85% # attempts to use FU when none available
435 system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.85% # attempts to use FU when none available
436 system.cpu.iq.fu_full::MemRead 9265240 52.28% 55.13% # attempts to use FU when none available
437 system.cpu.iq.fu_full::MemWrite 7952555 44.87% 100.00% # attempts to use FU when none available
438 system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
439 system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
440 system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
441 system.cpu.iq.FU_type_0::IntAlu 126474576 33.79% 33.79% # Type of FU issued
442 system.cpu.iq.FU_type_0::IntMult 2175710 0.58% 34.38% # Type of FU issued
443 system.cpu.iq.FU_type_0::IntDiv 0 0.00% 34.38% # Type of FU issued
444 system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 34.38% # Type of FU issued
445 system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 34.38% # Type of FU issued
446 system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 34.38% # Type of FU issued
447 system.cpu.iq.FU_type_0::FloatMult 0 0.00% 34.38% # Type of FU issued
448 system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 34.38% # Type of FU issued
449 system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 34.38% # Type of FU issued
450 system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 34.38% # Type of FU issued
451 system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 34.38% # Type of FU issued
452 system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 34.38% # Type of FU issued
453 system.cpu.iq.FU_type_0::SimdCmp 3 0.00% 34.38% # Type of FU issued
454 system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 34.38% # Type of FU issued
455 system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 34.38% # Type of FU issued
456 system.cpu.iq.FU_type_0::SimdMult 0 0.00% 34.38% # Type of FU issued
457 system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 34.38% # Type of FU issued
458 system.cpu.iq.FU_type_0::SimdShift 0 0.00% 34.38% # Type of FU issued
459 system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 34.38% # Type of FU issued
460 system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 34.38% # Type of FU issued
461 system.cpu.iq.FU_type_0::SimdFloatAdd 6781686 1.81% 36.19% # Type of FU issued
462 system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 36.19% # Type of FU issued
463 system.cpu.iq.FU_type_0::SimdFloatCmp 8476200 2.26% 38.45% # Type of FU issued
464 system.cpu.iq.FU_type_0::SimdFloatCvt 3430464 0.92% 39.37% # Type of FU issued
465 system.cpu.iq.FU_type_0::SimdFloatDiv 1596092 0.43% 39.80% # Type of FU issued
466 system.cpu.iq.FU_type_0::SimdFloatMisc 20867035 5.58% 45.37% # Type of FU issued
467 system.cpu.iq.FU_type_0::SimdFloatMult 7174148 1.92% 47.29% # Type of FU issued
468 system.cpu.iq.FU_type_0::SimdFloatMultAcc 7130628 1.91% 49.19% # Type of FU issued
469 system.cpu.iq.FU_type_0::SimdFloatSqrt 175287 0.05% 49.24% # Type of FU issued
470 system.cpu.iq.FU_type_0::MemRead 101661693 27.16% 76.41% # Type of FU issued
471 system.cpu.iq.FU_type_0::MemWrite 88297588 23.59% 100.00% # Type of FU issued
472 system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
473 system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
474 system.cpu.iq.FU_type_0::total 374241110 # Type of FU issued
475 system.cpu.iq.rate 2.731303 # Inst issue rate
476 system.cpu.iq.fu_busy_cnt 17722107 # FU busy when requested
477 system.cpu.iq.fu_busy_rate 0.047355 # FU busy rate (busy events/executed inst)
478 system.cpu.iq.int_inst_queue_reads 654665747 # Number of integer instruction queue reads
479 system.cpu.iq.int_inst_queue_writes 289075917 # Number of integer instruction queue writes
480 system.cpu.iq.int_inst_queue_wakeup_accesses 250124446 # Number of integer instruction queue wakeup accesses
481 system.cpu.iq.fp_inst_queue_reads 249421198 # Number of floating instruction queue reads
482 system.cpu.iq.fp_inst_queue_writes 130376340 # Number of floating instruction queue writes
483 system.cpu.iq.fp_inst_queue_wakeup_accesses 118073548 # Number of floating instruction queue wakeup accesses
484 system.cpu.iq.int_alu_accesses 263342959 # Number of integer alu accesses
485 system.cpu.iq.fp_alu_accesses 128620258 # Number of floating point alu accesses
486 system.cpu.iew.lsq.thread0.forwLoads 11085750 # Number of loads that had data forwarded from stores
487 system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
488 system.cpu.iew.lsq.thread0.squashedLoads 8957862 # Number of loads squashed
489 system.cpu.iew.lsq.thread0.ignoredResponses 109225 # Number of memory responses ignored because the instruction is squashed
490 system.cpu.iew.lsq.thread0.memOrderViolation 14255 # Number of memory ordering violations
491 system.cpu.iew.lsq.thread0.squashedStores 9026511 # Number of stores squashed
492 system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
493 system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
494 system.cpu.iew.lsq.thread0.rescheduledLoads 173986 # Number of loads that were rescheduled
495 system.cpu.iew.lsq.thread0.cacheBlocked 1905 # Number of times an access to memory failed due to the cache being blocked
496 system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
497 system.cpu.iew.iewSquashCycles 5146655 # Number of cycles IEW is squashing
498 system.cpu.iew.iewBlockCycles 274797 # Number of cycles IEW is blocking
499 system.cpu.iew.iewUnblockCycles 35672 # Number of cycles IEW is unblocking
500 system.cpu.iew.iewDispatchedInsts 384627381 # Number of instructions dispatched to IQ
501 system.cpu.iew.iewDispSquashedInsts 873173 # Number of squashed instructions skipped by dispatch
502 system.cpu.iew.iewDispLoadInsts 103606610 # Number of dispatched load instructions
503 system.cpu.iew.iewDispStoreInsts 91402094 # Number of dispatched store instructions
504 system.cpu.iew.iewDispNonSpecInsts 11760 # Number of dispatched non-speculative instructions
505 system.cpu.iew.iewIQFullEvents 340 # Number of times the IQ has become full, causing a stall
506 system.cpu.iew.iewLSQFullEvents 365 # Number of times the LSQ has become full, causing a stall
507 system.cpu.iew.memOrderViolationEvents 14255 # Number of memory order violations
508 system.cpu.iew.predictedTakenIncorrect 1300817 # Number of branches that were predicted taken incorrectly
509 system.cpu.iew.predictedNotTakenIncorrect 370830 # Number of branches that were predicted not taken incorrectly
510 system.cpu.iew.branchMispredicts 1671647 # Number of branch mispredicts detected at execute
511 system.cpu.iew.iewExecutedInsts 370280641 # Number of executed instructions
512 system.cpu.iew.iewExecLoadInsts 100372061 # Number of load instructions executed
513 system.cpu.iew.iewExecSquashedInsts 3960469 # Number of squashed instructions skipped in execute
514 system.cpu.iew.exec_swp 0 # number of swp insts executed
515 system.cpu.iew.exec_nop 1558 # number of nop insts executed
516 system.cpu.iew.exec_refs 187586293 # number of memory reference insts executed
517 system.cpu.iew.exec_branches 32011507 # Number of branches executed
518 system.cpu.iew.exec_stores 87214232 # Number of stores executed
519 system.cpu.iew.exec_rate 2.702398 # Inst execution rate
520 system.cpu.iew.wb_sent 368867964 # cumulative count of insts sent to commit
521 system.cpu.iew.wb_count 368197994 # cumulative count of insts written-back
522 system.cpu.iew.wb_producers 183086265 # num instructions producing a value
523 system.cpu.iew.wb_consumers 363871713 # num instructions consuming a value
524 system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
525 system.cpu.iew.wb_rate 2.687199 # insts written-back per cycle
526 system.cpu.iew.wb_fanout 0.503162 # average fanout of values written-back
527 system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
528 system.cpu.commit.commitSquashedInsts 35562440 # The number of squashed insts skipped by commit
529 system.cpu.commit.commitNonSpecStalls 22120 # The number of times commit has been forced to stall to communicate backwards
530 system.cpu.commit.branchMispredicts 1591916 # The number of times a branch was mispredicted
531 system.cpu.commit.committed_per_cycle::samples 131524549 # Number of insts commited each cycle
532 system.cpu.commit.committed_per_cycle::mean 2.653992 # Number of insts commited each cycle
533 system.cpu.commit.committed_per_cycle::stdev 2.659233 # Number of insts commited each cycle
534 system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
535 system.cpu.commit.committed_per_cycle::0 34720675 26.40% 26.40% # Number of insts commited each cycle
536 system.cpu.commit.committed_per_cycle::1 28457654 21.64% 48.04% # Number of insts commited each cycle
537 system.cpu.commit.committed_per_cycle::2 13339371 10.14% 58.18% # Number of insts commited each cycle
538 system.cpu.commit.committed_per_cycle::3 11431101 8.69% 66.87% # Number of insts commited each cycle
539 system.cpu.commit.committed_per_cycle::4 13773309 10.47% 77.34% # Number of insts commited each cycle
540 system.cpu.commit.committed_per_cycle::5 7413510 5.64% 82.98% # Number of insts commited each cycle
541 system.cpu.commit.committed_per_cycle::6 3874860 2.95% 85.92% # Number of insts commited each cycle
542 system.cpu.commit.committed_per_cycle::7 3887136 2.96% 88.88% # Number of insts commited each cycle
543 system.cpu.commit.committed_per_cycle::8 14626933 11.12% 100.00% # Number of insts commited each cycle
544 system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
545 system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
546 system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
547 system.cpu.commit.committed_per_cycle::total 131524549 # Number of insts commited each cycle
548 system.cpu.commit.committedInsts 273037337 # Number of instructions committed
549 system.cpu.commit.committedOps 349065061 # Number of ops (including micro ops) committed
550 system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
551 system.cpu.commit.refs 177024331 # Number of memory references committed
552 system.cpu.commit.loads 94648748 # Number of loads committed
553 system.cpu.commit.membars 11033 # Number of memory barriers committed
554 system.cpu.commit.branches 30563497 # Number of branches committed
555 system.cpu.commit.fp_insts 114216705 # Number of committed floating point instructions.
556 system.cpu.commit.int_insts 279584611 # Number of committed integer instructions.
557 system.cpu.commit.function_calls 6225112 # Number of function calls committed.
558 system.cpu.commit.bw_lim_events 14626933 # number cycles where commit BW limit reached
559 system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
560 system.cpu.rob.rob_reads 501522594 # The number of ROB reads
561 system.cpu.rob.rob_writes 774405807 # The number of ROB writes
562 system.cpu.timesIdled 6645 # Number of times that the entire CPU went into an idle state and unscheduled itself
563 system.cpu.idleCycles 348068 # Total number of cycles that the CPU has spent unscheduled due to idling
564 system.cpu.committedInsts 273036725 # Number of Instructions Simulated
565 system.cpu.committedOps 349064449 # Number of Ops (including micro ops) Simulated
566 system.cpu.committedInsts_total 273036725 # Number of Instructions Simulated
567 system.cpu.cpi 0.501835 # CPI: Cycles Per Instruction
568 system.cpu.cpi_total 0.501835 # CPI: Total CPI of All Threads
569 system.cpu.ipc 1.992688 # IPC: Instructions Per Cycle
570 system.cpu.ipc_total 1.992688 # IPC: Total IPC of All Threads
571 system.cpu.int_regfile_reads 1769988396 # number of integer regfile reads
572 system.cpu.int_regfile_writes 233047297 # number of integer regfile writes
573 system.cpu.fp_regfile_reads 188164665 # number of floating regfile reads
574 system.cpu.fp_regfile_writes 132532739 # number of floating regfile writes
575 system.cpu.misc_regfile_reads 566941334 # number of misc regfile reads
576 system.cpu.misc_regfile_writes 34421755 # number of misc regfile writes
577 system.cpu.toL2Bus.throughput 20093174 # Throughput (bytes/s)
578 system.cpu.toL2Bus.trans_dist::ReadReq 17631 # Transaction distribution
579 system.cpu.toL2Bus.trans_dist::ReadResp 17631 # Transaction distribution
580 system.cpu.toL2Bus.trans_dist::Writeback 1036 # Transaction distribution
581 system.cpu.toL2Bus.trans_dist::UpgradeReq 2 # Transaction distribution
582 system.cpu.toL2Bus.trans_dist::UpgradeResp 2 # Transaction distribution
583 system.cpu.toL2Bus.trans_dist::ReadExReq 2842 # Transaction distribution
584 system.cpu.toL2Bus.trans_dist::ReadExResp 2842 # Transaction distribution
585 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 31714 # Packet count per connected master and slave (bytes)
586 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10268 # Packet count per connected master and slave (bytes)
587 system.cpu.toL2Bus.pkt_count::total 41982 # Packet count per connected master and slave (bytes)
588 system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1014720 # Cumulative packet size per connected master and slave (bytes)
589 system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 361600 # Cumulative packet size per connected master and slave (bytes)
590 system.cpu.toL2Bus.tot_pkt_size::total 1376320 # Cumulative packet size per connected master and slave (bytes)
591 system.cpu.toL2Bus.data_through_bus 1376320 # Total data (bytes)
592 system.cpu.toL2Bus.snoop_data_through_bus 256 # Total snoop data (bytes)
593 system.cpu.toL2Bus.reqLayer0.occupancy 11791500 # Layer occupancy (ticks)
594 system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
595 system.cpu.toL2Bus.respLayer0.occupancy 24322738 # Layer occupancy (ticks)
596 system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
597 system.cpu.toL2Bus.respLayer1.occupancy 7408962 # Layer occupancy (ticks)
598 system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
599 system.cpu.icache.tags.replacements 13968 # number of replacements
600 system.cpu.icache.tags.tagsinuse 1848.251388 # Cycle average of tags in use
601 system.cpu.icache.tags.total_refs 37591948 # Total number of references to valid blocks.
602 system.cpu.icache.tags.sampled_refs 15858 # Sample count of references to valid blocks.
603 system.cpu.icache.tags.avg_refs 2370.535250 # Average number of references to valid blocks.
604 system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
605 system.cpu.icache.tags.occ_blocks::cpu.inst 1848.251388 # Average occupied blocks per requestor
606 system.cpu.icache.tags.occ_percent::cpu.inst 0.902466 # Average percentage of cache occupancy
607 system.cpu.icache.tags.occ_percent::total 0.902466 # Average percentage of cache occupancy
608 system.cpu.icache.tags.occ_task_id_blocks::1024 1890 # Occupied blocks per task id
609 system.cpu.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id
610 system.cpu.icache.tags.age_task_id_blocks_1024::1 95 # Occupied blocks per task id
611 system.cpu.icache.tags.age_task_id_blocks_1024::2 206 # Occupied blocks per task id
612 system.cpu.icache.tags.age_task_id_blocks_1024::3 9 # Occupied blocks per task id
613 system.cpu.icache.tags.age_task_id_blocks_1024::4 1526 # Occupied blocks per task id
614 system.cpu.icache.tags.occ_task_id_percent::1024 0.922852 # Percentage of cache occupancy per task id
615 system.cpu.icache.tags.tag_accesses 75234453 # Number of tag accesses
616 system.cpu.icache.tags.data_accesses 75234453 # Number of data accesses
617 system.cpu.icache.ReadReq_hits::cpu.inst 37591948 # number of ReadReq hits
618 system.cpu.icache.ReadReq_hits::total 37591948 # number of ReadReq hits
619 system.cpu.icache.demand_hits::cpu.inst 37591948 # number of demand (read+write) hits
620 system.cpu.icache.demand_hits::total 37591948 # number of demand (read+write) hits
621 system.cpu.icache.overall_hits::cpu.inst 37591948 # number of overall hits
622 system.cpu.icache.overall_hits::total 37591948 # number of overall hits
623 system.cpu.icache.ReadReq_misses::cpu.inst 17349 # number of ReadReq misses
624 system.cpu.icache.ReadReq_misses::total 17349 # number of ReadReq misses
625 system.cpu.icache.demand_misses::cpu.inst 17349 # number of demand (read+write) misses
626 system.cpu.icache.demand_misses::total 17349 # number of demand (read+write) misses
627 system.cpu.icache.overall_misses::cpu.inst 17349 # number of overall misses
628 system.cpu.icache.overall_misses::total 17349 # number of overall misses
629 system.cpu.icache.ReadReq_miss_latency::cpu.inst 451171984 # number of ReadReq miss cycles
630 system.cpu.icache.ReadReq_miss_latency::total 451171984 # number of ReadReq miss cycles
631 system.cpu.icache.demand_miss_latency::cpu.inst 451171984 # number of demand (read+write) miss cycles
632 system.cpu.icache.demand_miss_latency::total 451171984 # number of demand (read+write) miss cycles
633 system.cpu.icache.overall_miss_latency::cpu.inst 451171984 # number of overall miss cycles
634 system.cpu.icache.overall_miss_latency::total 451171984 # number of overall miss cycles
635 system.cpu.icache.ReadReq_accesses::cpu.inst 37609297 # number of ReadReq accesses(hits+misses)
636 system.cpu.icache.ReadReq_accesses::total 37609297 # number of ReadReq accesses(hits+misses)
637 system.cpu.icache.demand_accesses::cpu.inst 37609297 # number of demand (read+write) accesses
638 system.cpu.icache.demand_accesses::total 37609297 # number of demand (read+write) accesses
639 system.cpu.icache.overall_accesses::cpu.inst 37609297 # number of overall (read+write) accesses
640 system.cpu.icache.overall_accesses::total 37609297 # number of overall (read+write) accesses
641 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000461 # miss rate for ReadReq accesses
642 system.cpu.icache.ReadReq_miss_rate::total 0.000461 # miss rate for ReadReq accesses
643 system.cpu.icache.demand_miss_rate::cpu.inst 0.000461 # miss rate for demand accesses
644 system.cpu.icache.demand_miss_rate::total 0.000461 # miss rate for demand accesses
645 system.cpu.icache.overall_miss_rate::cpu.inst 0.000461 # miss rate for overall accesses
646 system.cpu.icache.overall_miss_rate::total 0.000461 # miss rate for overall accesses
647 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 26005.647818 # average ReadReq miss latency
648 system.cpu.icache.ReadReq_avg_miss_latency::total 26005.647818 # average ReadReq miss latency
649 system.cpu.icache.demand_avg_miss_latency::cpu.inst 26005.647818 # average overall miss latency
650 system.cpu.icache.demand_avg_miss_latency::total 26005.647818 # average overall miss latency
651 system.cpu.icache.overall_avg_miss_latency::cpu.inst 26005.647818 # average overall miss latency
652 system.cpu.icache.overall_avg_miss_latency::total 26005.647818 # average overall miss latency
653 system.cpu.icache.blocked_cycles::no_mshrs 2002 # number of cycles access was blocked
654 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
655 system.cpu.icache.blocked::no_mshrs 23 # number of cycles access was blocked
656 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
657 system.cpu.icache.avg_blocked_cycles::no_mshrs 87.043478 # average number of cycles each access was blocked
658 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
659 system.cpu.icache.fast_writes 0 # number of fast writes performed
660 system.cpu.icache.cache_copies 0 # number of cache copies performed
661 system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1490 # number of ReadReq MSHR hits
662 system.cpu.icache.ReadReq_mshr_hits::total 1490 # number of ReadReq MSHR hits
663 system.cpu.icache.demand_mshr_hits::cpu.inst 1490 # number of demand (read+write) MSHR hits
664 system.cpu.icache.demand_mshr_hits::total 1490 # number of demand (read+write) MSHR hits
665 system.cpu.icache.overall_mshr_hits::cpu.inst 1490 # number of overall MSHR hits
666 system.cpu.icache.overall_mshr_hits::total 1490 # number of overall MSHR hits
667 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15859 # number of ReadReq MSHR misses
668 system.cpu.icache.ReadReq_mshr_misses::total 15859 # number of ReadReq MSHR misses
669 system.cpu.icache.demand_mshr_misses::cpu.inst 15859 # number of demand (read+write) MSHR misses
670 system.cpu.icache.demand_mshr_misses::total 15859 # number of demand (read+write) MSHR misses
671 system.cpu.icache.overall_mshr_misses::cpu.inst 15859 # number of overall MSHR misses
672 system.cpu.icache.overall_mshr_misses::total 15859 # number of overall MSHR misses
673 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 359132259 # number of ReadReq MSHR miss cycles
674 system.cpu.icache.ReadReq_mshr_miss_latency::total 359132259 # number of ReadReq MSHR miss cycles
675 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 359132259 # number of demand (read+write) MSHR miss cycles
676 system.cpu.icache.demand_mshr_miss_latency::total 359132259 # number of demand (read+write) MSHR miss cycles
677 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 359132259 # number of overall MSHR miss cycles
678 system.cpu.icache.overall_mshr_miss_latency::total 359132259 # number of overall MSHR miss cycles
679 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000422 # mshr miss rate for ReadReq accesses
680 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000422 # mshr miss rate for ReadReq accesses
681 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000422 # mshr miss rate for demand accesses
682 system.cpu.icache.demand_mshr_miss_rate::total 0.000422 # mshr miss rate for demand accesses
683 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000422 # mshr miss rate for overall accesses
684 system.cpu.icache.overall_mshr_miss_rate::total 0.000422 # mshr miss rate for overall accesses
685 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22645.328142 # average ReadReq mshr miss latency
686 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22645.328142 # average ReadReq mshr miss latency
687 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22645.328142 # average overall mshr miss latency
688 system.cpu.icache.demand_avg_mshr_miss_latency::total 22645.328142 # average overall mshr miss latency
689 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22645.328142 # average overall mshr miss latency
690 system.cpu.icache.overall_avg_mshr_miss_latency::total 22645.328142 # average overall mshr miss latency
691 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
692 system.cpu.l2cache.tags.replacements 0 # number of replacements
693 system.cpu.l2cache.tags.tagsinuse 3941.799565 # Cycle average of tags in use
694 system.cpu.l2cache.tags.total_refs 13198 # Total number of references to valid blocks.
695 system.cpu.l2cache.tags.sampled_refs 5394 # Sample count of references to valid blocks.
696 system.cpu.l2cache.tags.avg_refs 2.446793 # Average number of references to valid blocks.
697 system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
698 system.cpu.l2cache.tags.occ_blocks::writebacks 379.005926 # Average occupied blocks per requestor
699 system.cpu.l2cache.tags.occ_blocks::cpu.inst 2786.464306 # Average occupied blocks per requestor
700 system.cpu.l2cache.tags.occ_blocks::cpu.data 776.329333 # Average occupied blocks per requestor
701 system.cpu.l2cache.tags.occ_percent::writebacks 0.011566 # Average percentage of cache occupancy
702 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.085036 # Average percentage of cache occupancy
703 system.cpu.l2cache.tags.occ_percent::cpu.data 0.023692 # Average percentage of cache occupancy
704 system.cpu.l2cache.tags.occ_percent::total 0.120294 # Average percentage of cache occupancy
705 system.cpu.l2cache.tags.occ_task_id_blocks::1024 5394 # Occupied blocks per task id
706 system.cpu.l2cache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id
707 system.cpu.l2cache.tags.age_task_id_blocks_1024::1 71 # Occupied blocks per task id
708 system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1235 # Occupied blocks per task id
709 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 11 # Occupied blocks per task id
710 system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4014 # Occupied blocks per task id
711 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.164612 # Percentage of cache occupancy per task id
712 system.cpu.l2cache.tags.tag_accesses 180292 # Number of tag accesses
713 system.cpu.l2cache.tags.data_accesses 180292 # Number of data accesses
714 system.cpu.l2cache.ReadReq_hits::cpu.inst 12803 # number of ReadReq hits
715 system.cpu.l2cache.ReadReq_hits::cpu.data 301 # number of ReadReq hits
716 system.cpu.l2cache.ReadReq_hits::total 13104 # number of ReadReq hits
717 system.cpu.l2cache.Writeback_hits::writebacks 1036 # number of Writeback hits
718 system.cpu.l2cache.Writeback_hits::total 1036 # number of Writeback hits
719 system.cpu.l2cache.ReadExReq_hits::cpu.data 17 # number of ReadExReq hits
720 system.cpu.l2cache.ReadExReq_hits::total 17 # number of ReadExReq hits
721 system.cpu.l2cache.demand_hits::cpu.inst 12803 # number of demand (read+write) hits
722 system.cpu.l2cache.demand_hits::cpu.data 318 # number of demand (read+write) hits
723 system.cpu.l2cache.demand_hits::total 13121 # number of demand (read+write) hits
724 system.cpu.l2cache.overall_hits::cpu.inst 12803 # number of overall hits
725 system.cpu.l2cache.overall_hits::cpu.data 318 # number of overall hits
726 system.cpu.l2cache.overall_hits::total 13121 # number of overall hits
727 system.cpu.l2cache.ReadReq_misses::cpu.inst 3052 # number of ReadReq misses
728 system.cpu.l2cache.ReadReq_misses::cpu.data 1471 # number of ReadReq misses
729 system.cpu.l2cache.ReadReq_misses::total 4523 # number of ReadReq misses
730 system.cpu.l2cache.UpgradeReq_misses::cpu.data 2 # number of UpgradeReq misses
731 system.cpu.l2cache.UpgradeReq_misses::total 2 # number of UpgradeReq misses
732 system.cpu.l2cache.ReadExReq_misses::cpu.data 2825 # number of ReadExReq misses
733 system.cpu.l2cache.ReadExReq_misses::total 2825 # number of ReadExReq misses
734 system.cpu.l2cache.demand_misses::cpu.inst 3052 # number of demand (read+write) misses
735 system.cpu.l2cache.demand_misses::cpu.data 4296 # number of demand (read+write) misses
736 system.cpu.l2cache.demand_misses::total 7348 # number of demand (read+write) misses
737 system.cpu.l2cache.overall_misses::cpu.inst 3052 # number of overall misses
738 system.cpu.l2cache.overall_misses::cpu.data 4296 # number of overall misses
739 system.cpu.l2cache.overall_misses::total 7348 # number of overall misses
740 system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 215204250 # number of ReadReq miss cycles
741 system.cpu.l2cache.ReadReq_miss_latency::cpu.data 109433000 # number of ReadReq miss cycles
742 system.cpu.l2cache.ReadReq_miss_latency::total 324637250 # number of ReadReq miss cycles
743 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 200213000 # number of ReadExReq miss cycles
744 system.cpu.l2cache.ReadExReq_miss_latency::total 200213000 # number of ReadExReq miss cycles
745 system.cpu.l2cache.demand_miss_latency::cpu.inst 215204250 # number of demand (read+write) miss cycles
746 system.cpu.l2cache.demand_miss_latency::cpu.data 309646000 # number of demand (read+write) miss cycles
747 system.cpu.l2cache.demand_miss_latency::total 524850250 # number of demand (read+write) miss cycles
748 system.cpu.l2cache.overall_miss_latency::cpu.inst 215204250 # number of overall miss cycles
749 system.cpu.l2cache.overall_miss_latency::cpu.data 309646000 # number of overall miss cycles
750 system.cpu.l2cache.overall_miss_latency::total 524850250 # number of overall miss cycles
751 system.cpu.l2cache.ReadReq_accesses::cpu.inst 15855 # number of ReadReq accesses(hits+misses)
752 system.cpu.l2cache.ReadReq_accesses::cpu.data 1772 # number of ReadReq accesses(hits+misses)
753 system.cpu.l2cache.ReadReq_accesses::total 17627 # number of ReadReq accesses(hits+misses)
754 system.cpu.l2cache.Writeback_accesses::writebacks 1036 # number of Writeback accesses(hits+misses)
755 system.cpu.l2cache.Writeback_accesses::total 1036 # number of Writeback accesses(hits+misses)
756 system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2 # number of UpgradeReq accesses(hits+misses)
757 system.cpu.l2cache.UpgradeReq_accesses::total 2 # number of UpgradeReq accesses(hits+misses)
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772 system.cpu.l2cache.ReadExReq_miss_rate::total 0.994018 # miss rate for ReadExReq accesses
773 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.192494 # miss rate for demand accesses
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775 system.cpu.l2cache.demand_miss_rate::total 0.358982 # miss rate for demand accesses
776 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.192494 # miss rate for overall accesses
777 system.cpu.l2cache.overall_miss_rate::cpu.data 0.931079 # miss rate for overall accesses
778 system.cpu.l2cache.overall_miss_rate::total 0.358982 # miss rate for overall accesses
779 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70512.532765 # average ReadReq miss latency
780 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74393.609789 # average ReadReq miss latency
781 system.cpu.l2cache.ReadReq_avg_miss_latency::total 71774.762326 # average ReadReq miss latency
782 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70871.858407 # average ReadExReq miss latency
783 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70871.858407 # average ReadExReq miss latency
784 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70512.532765 # average overall miss latency
785 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72077.746741 # average overall miss latency
786 system.cpu.l2cache.demand_avg_miss_latency::total 71427.633370 # average overall miss latency
787 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70512.532765 # average overall miss latency
788 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72077.746741 # average overall miss latency
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791 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
792 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
793 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
794 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
795 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
796 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
797 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
798 system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 12 # number of ReadReq MSHR hits
799 system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 40 # number of ReadReq MSHR hits
800 system.cpu.l2cache.ReadReq_mshr_hits::total 52 # number of ReadReq MSHR hits
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804 system.cpu.l2cache.overall_mshr_hits::cpu.inst 12 # number of overall MSHR hits
805 system.cpu.l2cache.overall_mshr_hits::cpu.data 40 # number of overall MSHR hits
806 system.cpu.l2cache.overall_mshr_hits::total 52 # number of overall MSHR hits
807 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3040 # number of ReadReq MSHR misses
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810 system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2 # number of UpgradeReq MSHR misses
811 system.cpu.l2cache.UpgradeReq_mshr_misses::total 2 # number of UpgradeReq MSHR misses
812 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2825 # number of ReadExReq MSHR misses
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818 system.cpu.l2cache.overall_mshr_misses::cpu.data 4256 # number of overall MSHR misses
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823 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 20002 # number of UpgradeReq MSHR miss cycles
824 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 20002 # number of UpgradeReq MSHR miss cycles
825 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 165233500 # number of ReadExReq MSHR miss cycles
826 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 165233500 # number of ReadExReq MSHR miss cycles
827 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 176370000 # number of demand (read+write) MSHR miss cycles
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834 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.807562 # mshr miss rate for ReadReq accesses
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836 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses
837 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
838 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994018 # mshr miss rate for ReadExReq accesses
839 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994018 # mshr miss rate for ReadExReq accesses
840 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.191738 # mshr miss rate for demand accesses
841 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.922410 # mshr miss rate for demand accesses
842 system.cpu.l2cache.demand_mshr_miss_rate::total 0.356441 # mshr miss rate for demand accesses
843 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.191738 # mshr miss rate for overall accesses
844 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.922410 # mshr miss rate for overall accesses
845 system.cpu.l2cache.overall_mshr_miss_rate::total 0.356441 # mshr miss rate for overall accesses
846 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58016.447368 # average ReadReq mshr miss latency
847 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62114.605171 # average ReadReq mshr miss latency
848 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59328.114516 # average ReadReq mshr miss latency
849 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency
850 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency
851 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58489.734513 # average ReadExReq mshr miss latency
852 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58489.734513 # average ReadExReq mshr miss latency
853 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58016.447368 # average overall mshr miss latency
854 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59708.529135 # average overall mshr miss latency
855 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59003.495066 # average overall mshr miss latency
856 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58016.447368 # average overall mshr miss latency
857 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59708.529135 # average overall mshr miss latency
858 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59003.495066 # average overall mshr miss latency
859 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
860 system.cpu.dcache.tags.replacements 1417 # number of replacements
861 system.cpu.dcache.tags.tagsinuse 3102.941006 # Cycle average of tags in use
862 system.cpu.dcache.tags.total_refs 170982340 # Total number of references to valid blocks.
863 system.cpu.dcache.tags.sampled_refs 4614 # Sample count of references to valid blocks.
864 system.cpu.dcache.tags.avg_refs 37057.290854 # Average number of references to valid blocks.
865 system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
866 system.cpu.dcache.tags.occ_blocks::cpu.data 3102.941006 # Average occupied blocks per requestor
867 system.cpu.dcache.tags.occ_percent::cpu.data 0.757554 # Average percentage of cache occupancy
868 system.cpu.dcache.tags.occ_percent::total 0.757554 # Average percentage of cache occupancy
869 system.cpu.dcache.tags.occ_task_id_blocks::1024 3197 # Occupied blocks per task id
870 system.cpu.dcache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id
871 system.cpu.dcache.tags.age_task_id_blocks_1024::1 32 # Occupied blocks per task id
872 system.cpu.dcache.tags.age_task_id_blocks_1024::2 684 # Occupied blocks per task id
873 system.cpu.dcache.tags.age_task_id_blocks_1024::3 11 # Occupied blocks per task id
874 system.cpu.dcache.tags.age_task_id_blocks_1024::4 2446 # Occupied blocks per task id
875 system.cpu.dcache.tags.occ_task_id_percent::1024 0.780518 # Percentage of cache occupancy per task id
876 system.cpu.dcache.tags.tag_accesses 342019754 # Number of tag accesses
877 system.cpu.dcache.tags.data_accesses 342019754 # Number of data accesses
878 system.cpu.dcache.ReadReq_hits::cpu.data 88929043 # number of ReadReq hits
879 system.cpu.dcache.ReadReq_hits::total 88929043 # number of ReadReq hits
880 system.cpu.dcache.WriteReq_hits::cpu.data 82031381 # number of WriteReq hits
881 system.cpu.dcache.WriteReq_hits::total 82031381 # number of WriteReq hits
882 system.cpu.dcache.LoadLockedReq_hits::cpu.data 11009 # number of LoadLockedReq hits
883 system.cpu.dcache.LoadLockedReq_hits::total 11009 # number of LoadLockedReq hits
884 system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits
885 system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits
886 system.cpu.dcache.demand_hits::cpu.data 170960424 # number of demand (read+write) hits
887 system.cpu.dcache.demand_hits::total 170960424 # number of demand (read+write) hits
888 system.cpu.dcache.overall_hits::cpu.data 170960424 # number of overall hits
889 system.cpu.dcache.overall_hits::total 170960424 # number of overall hits
890 system.cpu.dcache.ReadReq_misses::cpu.data 3956 # number of ReadReq misses
891 system.cpu.dcache.ReadReq_misses::total 3956 # number of ReadReq misses
892 system.cpu.dcache.WriteReq_misses::cpu.data 21284 # number of WriteReq misses
893 system.cpu.dcache.WriteReq_misses::total 21284 # number of WriteReq misses
894 system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses
895 system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses
896 system.cpu.dcache.demand_misses::cpu.data 25240 # number of demand (read+write) misses
897 system.cpu.dcache.demand_misses::total 25240 # number of demand (read+write) misses
898 system.cpu.dcache.overall_misses::cpu.data 25240 # number of overall misses
899 system.cpu.dcache.overall_misses::total 25240 # number of overall misses
900 system.cpu.dcache.ReadReq_miss_latency::cpu.data 235586955 # number of ReadReq miss cycles
901 system.cpu.dcache.ReadReq_miss_latency::total 235586955 # number of ReadReq miss cycles
902 system.cpu.dcache.WriteReq_miss_latency::cpu.data 1260992389 # number of WriteReq miss cycles
903 system.cpu.dcache.WriteReq_miss_latency::total 1260992389 # number of WriteReq miss cycles
904 system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 170250 # number of LoadLockedReq miss cycles
905 system.cpu.dcache.LoadLockedReq_miss_latency::total 170250 # number of LoadLockedReq miss cycles
906 system.cpu.dcache.demand_miss_latency::cpu.data 1496579344 # number of demand (read+write) miss cycles
907 system.cpu.dcache.demand_miss_latency::total 1496579344 # number of demand (read+write) miss cycles
908 system.cpu.dcache.overall_miss_latency::cpu.data 1496579344 # number of overall miss cycles
909 system.cpu.dcache.overall_miss_latency::total 1496579344 # number of overall miss cycles
910 system.cpu.dcache.ReadReq_accesses::cpu.data 88932999 # number of ReadReq accesses(hits+misses)
911 system.cpu.dcache.ReadReq_accesses::total 88932999 # number of ReadReq accesses(hits+misses)
912 system.cpu.dcache.WriteReq_accesses::cpu.data 82052665 # number of WriteReq accesses(hits+misses)
913 system.cpu.dcache.WriteReq_accesses::total 82052665 # number of WriteReq accesses(hits+misses)
914 system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11011 # number of LoadLockedReq accesses(hits+misses)
915 system.cpu.dcache.LoadLockedReq_accesses::total 11011 # number of LoadLockedReq accesses(hits+misses)
916 system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses)
917 system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses)
918 system.cpu.dcache.demand_accesses::cpu.data 170985664 # number of demand (read+write) accesses
919 system.cpu.dcache.demand_accesses::total 170985664 # number of demand (read+write) accesses
920 system.cpu.dcache.overall_accesses::cpu.data 170985664 # number of overall (read+write) accesses
921 system.cpu.dcache.overall_accesses::total 170985664 # number of overall (read+write) accesses
922 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000044 # miss rate for ReadReq accesses
923 system.cpu.dcache.ReadReq_miss_rate::total 0.000044 # miss rate for ReadReq accesses
924 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000259 # miss rate for WriteReq accesses
925 system.cpu.dcache.WriteReq_miss_rate::total 0.000259 # miss rate for WriteReq accesses
926 system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000182 # miss rate for LoadLockedReq accesses
927 system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000182 # miss rate for LoadLockedReq accesses
928 system.cpu.dcache.demand_miss_rate::cpu.data 0.000148 # miss rate for demand accesses
929 system.cpu.dcache.demand_miss_rate::total 0.000148 # miss rate for demand accesses
930 system.cpu.dcache.overall_miss_rate::cpu.data 0.000148 # miss rate for overall accesses
931 system.cpu.dcache.overall_miss_rate::total 0.000148 # miss rate for overall accesses
932 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59551.808645 # average ReadReq miss latency
933 system.cpu.dcache.ReadReq_avg_miss_latency::total 59551.808645 # average ReadReq miss latency
934 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59246.024666 # average WriteReq miss latency
935 system.cpu.dcache.WriteReq_avg_miss_latency::total 59246.024666 # average WriteReq miss latency
936 system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 85125 # average LoadLockedReq miss latency
937 system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 85125 # average LoadLockedReq miss latency
938 system.cpu.dcache.demand_avg_miss_latency::cpu.data 59293.951823 # average overall miss latency
939 system.cpu.dcache.demand_avg_miss_latency::total 59293.951823 # average overall miss latency
940 system.cpu.dcache.overall_avg_miss_latency::cpu.data 59293.951823 # average overall miss latency
941 system.cpu.dcache.overall_avg_miss_latency::total 59293.951823 # average overall miss latency
942 system.cpu.dcache.blocked_cycles::no_mshrs 28312 # number of cycles access was blocked
943 system.cpu.dcache.blocked_cycles::no_targets 1224 # number of cycles access was blocked
944 system.cpu.dcache.blocked::no_mshrs 411 # number of cycles access was blocked
945 system.cpu.dcache.blocked::no_targets 12 # number of cycles access was blocked
946 system.cpu.dcache.avg_blocked_cycles::no_mshrs 68.885645 # average number of cycles each access was blocked
947 system.cpu.dcache.avg_blocked_cycles::no_targets 102 # average number of cycles each access was blocked
948 system.cpu.dcache.fast_writes 0 # number of fast writes performed
949 system.cpu.dcache.cache_copies 0 # number of cache copies performed
950 system.cpu.dcache.writebacks::writebacks 1036 # number of writebacks
951 system.cpu.dcache.writebacks::total 1036 # number of writebacks
952 system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2182 # number of ReadReq MSHR hits
953 system.cpu.dcache.ReadReq_mshr_hits::total 2182 # number of ReadReq MSHR hits
954 system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18442 # number of WriteReq MSHR hits
955 system.cpu.dcache.WriteReq_mshr_hits::total 18442 # number of WriteReq MSHR hits
956 system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits
957 system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits
958 system.cpu.dcache.demand_mshr_hits::cpu.data 20624 # number of demand (read+write) MSHR hits
959 system.cpu.dcache.demand_mshr_hits::total 20624 # number of demand (read+write) MSHR hits
960 system.cpu.dcache.overall_mshr_hits::cpu.data 20624 # number of overall MSHR hits
961 system.cpu.dcache.overall_mshr_hits::total 20624 # number of overall MSHR hits
962 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1774 # number of ReadReq MSHR misses
963 system.cpu.dcache.ReadReq_mshr_misses::total 1774 # number of ReadReq MSHR misses
964 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2842 # number of WriteReq MSHR misses
965 system.cpu.dcache.WriteReq_mshr_misses::total 2842 # number of WriteReq MSHR misses
966 system.cpu.dcache.demand_mshr_misses::cpu.data 4616 # number of demand (read+write) MSHR misses
967 system.cpu.dcache.demand_mshr_misses::total 4616 # number of demand (read+write) MSHR misses
968 system.cpu.dcache.overall_mshr_misses::cpu.data 4616 # number of overall MSHR misses
969 system.cpu.dcache.overall_mshr_misses::total 4616 # number of overall MSHR misses
970 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 114384040 # number of ReadReq MSHR miss cycles
971 system.cpu.dcache.ReadReq_mshr_miss_latency::total 114384040 # number of ReadReq MSHR miss cycles
972 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 203208498 # number of WriteReq MSHR miss cycles
973 system.cpu.dcache.WriteReq_mshr_miss_latency::total 203208498 # number of WriteReq MSHR miss cycles
974 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 317592538 # number of demand (read+write) MSHR miss cycles
975 system.cpu.dcache.demand_mshr_miss_latency::total 317592538 # number of demand (read+write) MSHR miss cycles
976 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 317592538 # number of overall MSHR miss cycles
977 system.cpu.dcache.overall_mshr_miss_latency::total 317592538 # number of overall MSHR miss cycles
978 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000020 # mshr miss rate for ReadReq accesses
979 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000020 # mshr miss rate for ReadReq accesses
980 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses
981 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000035 # mshr miss rate for WriteReq accesses
982 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for demand accesses
983 system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses
984 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses
985 system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses
986 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 64478.038331 # average ReadReq mshr miss latency
987 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 64478.038331 # average ReadReq mshr miss latency
988 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71501.934553 # average WriteReq mshr miss latency
989 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71501.934553 # average WriteReq mshr miss latency
990 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68802.542894 # average overall mshr miss latency
991 system.cpu.dcache.demand_avg_mshr_miss_latency::total 68802.542894 # average overall mshr miss latency
992 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68802.542894 # average overall mshr miss latency
993 system.cpu.dcache.overall_avg_mshr_miss_latency::total 68802.542894 # average overall mshr miss latency
994 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
996 ---------- End Simulation Statistics ----------
projects / gem5.git / blob